Power semiconductor element, power conversion device including the same, and method for manufacturing power semiconductor element
The power semiconductor device addresses the issue of cell pitch reduction and electric field concentration by using a second conductivity type well below the trench gate, improving breakdown voltage and reliability without high-energy ion implantation.
Patent Information
- Application Number
- JP2025007605
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-04-19
- Filing Date
- 2025-01-20
- Publication Date
- 2025-10-30
AI Technical Summary
The challenge in power semiconductor devices is to prevent a reduction in cell pitch due to lateral straggling while avoiding electric field concentration at the corners of the trench, which can lead to gate insulating film breakdown.
A power semiconductor device design that includes a second conductivity type well disposed below the trench gate to disperse the electric field, formed without high-energy ion implantation, and with a higher doping concentration than the ion implantation region, allowing for deeper formation and vertical alignment with the trench gate.
This design prevents pitch reduction and disperses the electric field, enhancing breakdown voltage and gate reliability, reducing threshold voltage, and increasing current density.
Smart Images
Figure 2025164684000001_ABST
Abstract
Description
[Technical Field]
[0001] The embodiments relate to a power semiconductor element, a power semiconductor module, a power conversion device, and a manufacturing method thereof. [Background technology]
[0002] Power semiconductors are one of the key elements that determine the efficiency, speed, durability, and reliability of power electronic systems.
[0003] Recently, with the development of the power electronics industry, the conventional silicon ((Silicon)Si) power semiconductors have reached their physical limits, and research into WBG (Wide Bandgap) power semiconductors such as silicon carbide ((Silicon Carbide)SiC) and gallium nitride ((Galium Nitride)GaN) is being actively conducted to replace them.
[0004] WBG power semiconductor elements have approximately three times the band gap energy of Si power semiconductor elements, which gives them the following characteristics: low intrinsic carrier concentration, high dielectric breakdown field (approximately 4 to 20 times), high thermal conductivity (approximately 3 to 13 times), and large electron saturation velocity (approximately 2 to 2.5 times).
[0005] These characteristics allow them to operate in high-temperature, high-voltage environments, and they have high switching speeds and low switching losses. Among these, gallium nitride (GaN) power semiconductor elements can be used in low-voltage systems, while silicon carbide (SiC) power semiconductor elements are suitable for high-voltage systems.
[0006] Conventional SiC MOSFET power semiconductors are generally referred to as VDMOSFETs, which stand for vertical diffused structure, or simply as double-diffused structure DMOSFETs. SiC MOSFETs can also be classified into planar MOSFETs and trench MOSFETs depending on the channel direction.
[0007] Among these, the trench MOSFET has a structure in which a channel is formed on the sidewall of a trench, and therefore a gate insulating film is formed on the sidewall of the trench and a gate electrode is formed in the trench.
[0008] SiC MOSFETs have high on-resistance due to low channel mobility and large channel resistance, so trench MOSFETs have been proposed to reduce this. Trench MOSFETs have the advantage of increasing channel density by forming a channel on the trench sidewall.
[0009] However, trench MOSFETs have a larger electric field in the trench gate oxide, which has a shorter drift distance than the P-base (P-well), and the electric field is concentrated especially at the trench edge, which causes early breakdown of the gate oxide and reduces BV (Breakdown voltage).
[0010] For example, in the case of SiC trench MOSFETs, the breakdown field strength is 10 times that of silicon (Si), so SiC semiconductor devices are used under conditions where a voltage nearly 10 times that of Si devices is applied. As a result, the gate insulating film formed inside the trench is also subjected to an electric field 10 times stronger than that of silicon devices, which creates the problem of the gate insulating film easily breaking down at the corners of the trench.
[0011] Internal technology is researching a process to form a p-type well (P-base) deeper than the gate trench to prevent electric field concentration at the trench corners, but forming such a deep p-type well poses a problem as the ion implantation energy required exceeds that of conventional processes.
[0012] Furthermore, high energy ion implantation can cause severe ion implantation outside the target area, which can lead to a problem of reduced cell pitch due to difficulty in controlling lateral straggling. Summary of the Invention [Problem to be solved by the invention]
[0013] One of the technical challenges of the power semiconductor device according to the embodiment, the power conversion device including the same, and the method for manufacturing the power semiconductor device is to prevent the problem of a reduction in cell pitch due to lateral straggling while preventing electric field concentration at the corners of the trench.
[0014] The technical problems of the embodiments are not limited to those described in this section, but include those that can be understood from the description of the invention. [Means for solving the problem]
[0015] A power semiconductor device according to an embodiment may include a substrate, a first epitaxial layer of a first conductivity type disposed on the substrate, a second epitaxial layer of a first conductivity type disposed on the first epitaxial layer of the first conductivity type, a well of a second conductivity type partially formed in the second epitaxial layer of the first conductivity type, an ion-implanted region of a second conductivity type and a source region located above the well of the second conductivity type, a source electrode disposed on the source region, a gate insulating layer formed in a trench region in which the ion-implanted region of the second conductivity type and a portion of the second epitaxial layer of the first conductivity type are removed, a trench gate disposed on the gate insulating layer, an interlayer insulating layer disposed on the trench gate, and a gate electrode electrically connected to the trench gate.
[0016] The second epilayer of the first conductivity type may include a 2-1 epilayer of the first conductivity type disposed on the first epilayer of the first conductivity type, and a 2-2 epilayer of the first conductivity type disposed on the 2-1 epilayer of the first conductivity type.
[0017] The well of the second conductivity type is formed partially in the second epitaxial layer of the first conductivity type.
[0018] The gate insulating layer may contact an upper surface of the second conductivity type well.
[0019] The trench gate is arranged to be aligned above and below the second conductive type well.
[0020] The well of the second conductivity type may be disposed lower than the trench gate.
[0021] The power semiconductor device according to the embodiment includes a substrate 110, a first conductivity type first epitaxial layer 111 disposed on the substrate 110, a first conductivity type second-1 epitaxial layer 112a disposed on the first conductivity type first epitaxial layer 111, a first conductivity type second-2 epitaxial layer 112b disposed on the first conductivity type second-1 epitaxial layer 112a, a second conductivity type well 121 partially formed in the first conductivity type second-1 epitaxial layer 112a, and a second conductivity type ion implantation layer 122 disposed above the second conductivity type well 121. The semiconductor device may include an ion implantation region 122 and a source region 115, a source electrode 142 disposed on the source region 115, a gate insulating layer 131 formed in a trench region T where a portion of the second conductive type ion implantation region 122 and the first conductive type 2-2 epitaxial layer 112b have been removed, a trench gate 132 disposed on the gate insulating layer 131, an interlayer insulating layer 150 disposed on the trench gate 132, and a gate electrode electrically connected to the trench gate 132.
[0022] The top surface of the second conductive type well 121 may be at the same level as or lower than the first conductive type 2-1 epitaxial layer 112a.
[0023] The doping concentration of the second conductivity type well 121 formed in the first conductivity type 2-1 epitaxial layer 112a may be higher than the doping concentration of the second conductivity type ion implantation region 122.
[0024] A power conversion device according to an embodiment may include any one of the power semiconductor elements.
[0025] The method for manufacturing a power semiconductor device according to the embodiment includes the steps of growing a first epitaxial layer 111 of a first conductivity type on a substrate 110, growing a second epitaxial layer 112a of a first conductivity type on the first epitaxial layer 111 of the first conductivity type, implanting ions into the second epitaxial layer 112a of the first conductivity type to partially form a well 121 of a second conductivity type, growing a second epitaxial layer 112b of a first conductivity type on the second epitaxial layer 112a of the first conductivity type, and implanting ions into the second epitaxial layer 112b of the first conductivity type. The method may include the steps of: implanting ions to form a second conductive type ion implantation region 122 and a source region 115; removing the second conductive type ion implantation region 122 and a portion of the first conductive type 2-2 epitaxial layer 112b to form a trench region T; forming a gate insulating layer 131 and a trench gate 132 in the trench region; forming an interlayer insulating layer 150 on the trench gate 132; and forming a gate electrode electrically connected to the trench gate 132.
[0026] The top surface of the second conductive type well 121 may be at the same level as or lower than the first conductive type 2-1 epitaxial layer 112a.
[0027] The doping concentration of the second conductivity type well 121 formed in the first conductivity type 2-1 epitaxial layer 112a may be higher than the doping concentration of the second conductivity type ion implantation region 122.
[0028] In forming the trench region T by removing a portion of the second conductive type ion implantation region 122 and the first conductive type 2-2 epitaxial layer 112b, a portion of the second conductive type well 121 may be exposed.
[0029] The gate insulating layer 131 may be in contact with the second conductive type well 121 .
[0030] The hard mask pattern for forming the trench region may correspond to an open region of the hard mask pattern for ion implantation for forming the second conductive type well 121.
[0031] The trench region is arranged to be aligned vertically with the second conductive type well 121 .
[0032] The trench gate 132 and the second conductive well 121 are vertically aligned. [Effects of the Invention]
[0033] According to the power semiconductor device, the power converter including the same, and the method for manufacturing the power semiconductor device according to the embodiment, the second conductivity type well 121 is disposed below the trench gate 132 to disperse an electric field concentrated at the bottom corner of the trench gate. If the electric field at the bottom corner of the trench gate cannot be dispersed, the breakdown voltage may be significantly reduced or problems may occur with gate reliability, resulting in a shortened lifespan of the semiconductor device.
[0034] In addition, according to the embodiment, the second conductivity type well 121 is formed without using high-energy ion implantation, thereby preventing the problem of pitch reduction due to lateral straggling of dopants, and the second conductivity type well 121 is formed in a region deeper than the trench, thereby enabling the dispersion of the electric field concentrated at the bottom corner of the gate trench, thereby providing the technical effect of preventing breakdown of the gate insulating layer.
[0035] In addition, in the embodiment, the doping concentration of the second conductivity type well 121 formed on the first conductivity type 2-1 epitaxial layer 112a may be higher than the doping concentration of the second conductivity type ion implantation region 122. For example, according to the embodiment, there is a technical effect that the doping concentration of the second conductivity type well 121 formed below the trench gate 132 can be abruptly changed from the doping concentration of the second conductivity type ion implantation region 122 formed adjacent to the trench gate 132.
[0036] For example, the doping concentration of the second conductivity type well 121 is 2×10 17 ~2×10 19 / cm 3 The doping concentration of the second conductivity type ion implantation region 122 may be 1×10 16 ~1×10 17 / cm 3 It may be, but is not limited to this.
[0037] According to the embodiment, the doping concentration of the second conductive type well 121 formed below the trench gate 132 is higher than the doping concentration of the second conductive type ion implantation region 122, which has the effect of expanding a depletion layer toward the substrate 110, thereby providing a technical effect of increasing the breakdown voltage. Also, according to the embodiment, the doping concentration of the second conductive type ion implantation region 122 formed around the trench gate 132 is lower than the doping concentration of the second conductive type well 121, which provides a combined technical effect of reducing the threshold voltage and increasing the current density.
[0038] The technical effects of the embodiments are not limited to those described in this section, but include those that can be understood from the description of the invention. [Brief explanation of the drawings]
[0039] [Figure 1] FIG. 1 is a diagram illustrating a configuration example of a power conversion device 1000 according to an embodiment. [Figure 2] FIG. 2 is a cross-sectional view of a power semiconductor device 100 according to an embodiment. [Figure 3] FIG. 3 is a cross-sectional view of a power semiconductor device 100 according to an embodiment. [Figure 4] FIG. 4 is a cross-sectional view illustrating a manufacturing process of the power semiconductor element 100 according to the embodiment. [Figure 5] FIG. 5 is a cross-sectional view illustrating a manufacturing process of the power semiconductor element 100 according to the embodiment. [Figure 6] FIG. 6 is a cross-sectional view illustrating a manufacturing process of the power semiconductor element 100 according to the embodiment. [Figure 7] FIG. 7 is a cross-sectional view illustrating a manufacturing process of the power semiconductor element 100 according to the embodiment. [Figure 8] FIG. 8 is a cross-sectional view illustrating a manufacturing process of the power semiconductor element 100 according to the embodiment. [Figure 9] FIG. 9 is a cross-sectional view illustrating a manufacturing process of the power semiconductor element 100 according to the embodiment. [Figure 10] FIG. 10 is a cross-sectional view illustrating a manufacturing process of the power semiconductor element 100 according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION
[0040] Hereinafter, the invention according to the embodiment for solving the above problems will be described in more detail with reference to the drawings.
[0041] The suffixes "module" and "section" used in the following description for components are given merely to facilitate the preparation of the specification and do not themselves have any particular significance or role. Therefore, the terms "module" and "section" can be used interchangeably.
[0042] Terms including ordinal numbers such as first, second, etc. may be used to describe various components, but the components are not limited by the terms. The terms are used only to distinguish one component from another.
[0043] The singular expression includes the plural expression unless the context clearly indicates otherwise.
[0044] In this application, the use of terms such as "comprises," "has," or "has" is intended to specify the presence of any feature, number, step, operation, component, part, or combination thereof set forth in the specification, but is to be understood as not precluding the possible presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.
[0045] (Example) FIG. 1 is a diagram illustrating a configuration example of a power conversion device 1000 according to an embodiment.
[0046] The power conversion device 1000 according to the embodiment can receive DC power from a battery or a fuel cell, convert it into AC power, and supply the AC power to a predetermined load. For example, the power conversion device 1000 according to the embodiment can include an inverter, receive DC power from a battery, convert it into three-phase AC power, and supply it to a motor M, which can provide power to an electric vehicle, a fuel cell vehicle, etc.
[0047] The power converter 1000 according to the embodiment may include a power semiconductor device 100. The power semiconductor device 100 may be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but is not limited thereto, and may include an IGBT (Insulated Gate Bipolar Transistor).
[0048] For example, the power conversion device 1000 may include a plurality of power semiconductor devices 100a, 100b, 100c, 100d, 100e, and 100f, and may include a plurality of diodes (not shown). Each of the plurality of diodes may be included in the power semiconductor devices 100a, 100b, 100c, 100d, 100e, and 100f in the form of an internal diode, but is not limited thereto and may be separately disposed.
[0049] The embodiment can convert DC power into AC power by controlling the on / off of the plurality of power semiconductor elements 100a to 100f. For example, the power conversion device 1000 according to the embodiment can supply positive polarity power to the motor M by turning on the first power semiconductor element 100a and turning off the second power semiconductor element 100b during a first time interval of one cycle, and supply negative polarity power to the motor M by turning off the first power semiconductor element 100a and turning on the second power semiconductor element 100b during a second time interval of one cycle.
[0050] In the embodiment, a group of power semiconductor devices arranged in series on the high-voltage line and low-voltage line on the input side may be called an arm. For example, the first power semiconductor device 100a and the second power semiconductor device 100b may form a first arm, the third power semiconductor device 100c and the fourth power semiconductor device 100d may form a second arm, and the fifth power semiconductor device 100e and the sixth power semiconductor device 100f may form a third arm.
[0051] In each arm, the upper and lower power semiconductor devices are controlled so as not to be turned on at the same time. For example, in the first arm, the first power semiconductor device 100a and the second power semiconductor device 100b are not turned on at the same time but can be turned on and off alternately.
[0052] A high voltage is applied to each of the power semiconductor elements 100a-100f when the elements are turned off. For example, when the first power semiconductor element 100a is turned on and the second power semiconductor element 100b is turned off, the input voltage is applied to the second power semiconductor element 100b as is. The voltage input to the second power semiconductor element 100b is a relatively high voltage, and the withstand voltage of each of the power semiconductor elements 100a-100f is designed to be high so that it can withstand such a high voltage.
[0053] Each of the power semiconductor elements 100a to 100f can conduct a high current when it is turned on. The motor M is driven by a relatively high current, and this high current is supplied to the motor M through the power semiconductors that are turned on.
[0054] A high voltage applied to each of the power semiconductor elements 100a-100f may induce high switching loss. A high current passing through the power semiconductor elements 100a-100f may induce high conduction loss. To dissipate heat generated by such loss, the power semiconductor elements 100a-100f may be packaged in a power semiconductor module including a heat dissipation means.
[0055] The power semiconductor device 100 of the embodiment may be a silicon carbide (SiC) power semiconductor device, which can operate in a high temperature and high voltage environment and has a high switching speed and low switching loss.
[0056] Meanwhile, the power conversion device 1000 according to the embodiment may include a plurality of power semiconductor modules.
[0057] For example, the plurality of power semiconductor elements 100a to 100f shown in FIG. 1 may be packaged in one power semiconductor module, or the power semiconductor elements constituting each arm may be packaged in one power semiconductor module.
[0058] For example, the first power semiconductor element 100a, the second power semiconductor element 100b, the third power semiconductor element 100c, the fourth power semiconductor element 100d, the fifth power semiconductor element 100e, and the sixth power semiconductor element 100f shown in FIG. 1 may be packaged into one power semiconductor module.
[0059] In addition, there may be additional power semiconductor elements arranged in parallel with each of the power semiconductor elements 100a to 100f to increase the current capacity. In this case, the number of power semiconductor elements included in the power semiconductor module may be more than six.
[0060] The power converter 1000 according to the embodiment may include diode-type power semiconductor elements in addition to the transistor-type power semiconductor elements 100a to 100f. For example, a first diode (not shown) may be arranged in parallel with the first power semiconductor element 100a, and a second diode (not shown) may be arranged in parallel with the second power semiconductor element 100b. These diodes may also be packaged together in one power semiconductor module. Alternatively, the diodes may be arranged in the form of internal diodes in each power semiconductor element.
[0061] Next, the power semiconductor elements that make up each arm may be packaged into one power semiconductor module.
[0062] For example, the first power semiconductor element 100a and the second power semiconductor element 100b that constitute the first arm may be packaged in a first power semiconductor module, the third power semiconductor element 100c and the fourth power semiconductor element 100d that constitute the second arm may be packaged in a second power semiconductor module, and the fifth power semiconductor element 100e and the sixth power semiconductor element 100f that constitute the third arm may be packaged in a third power semiconductor module.
[0063] In addition, additional power semiconductor elements may be arranged in parallel with each of the power semiconductor elements 100a-100f to increase current capacity. In this case, the number of power semiconductor elements included in each power semiconductor module may be more than two. Each arm may also include a diode-type power semiconductor element (not shown) in addition to the transistor-type power semiconductor elements 100a-100f, and such a diode may also be packaged together in one power semiconductor module. The diode may also be arranged in the form of an internal diode in each power semiconductor element.
[0064] Next, FIG. 2 is a cross-sectional view of one of the power semiconductor devices 100 according to the embodiment.
[0065] The power semiconductor device 100 according to the embodiment may include a source electrode 142 and a gate electrode 175 disposed on a predetermined semiconductor epitaxial layer 120 , and a drain electrode 105 disposed on a lower side of the semiconductor epitaxial layer 120 .
[0066] In the MOSFET configuration, the source electrode 142 or the gate electrode 175 may include an Al-based metal, and the drain electrode 105 may include, but is not limited to, Ti / Ni / Ag metal including a Ti layer, a Ni layer, or an Ag layer, NiV / Ag, V (vanadium) / Ni / Ag, or the like.
[0067] One of the technical challenges of the embodiment is to prevent the problem of a reduction in cell pitch due to lateral straggling while preventing electric field concentration at the corners of the trench.
[0068] A power semiconductor device 100 according to an embodiment for solving the above technical problems will be described below.
[0069] FIG. 3 is a cross-sectional view of a power semiconductor device 100 according to an embodiment.
[0070] First, referring to FIG. 3, the power semiconductor device 100 according to the embodiment may include at least one of a drain electrode 105, a substrate 110, a first conductive type first epitaxial layer 111, a first conductive type second epitaxial layer 112, a second conductive type well 121, a second conductive type ion implantation region 122, a first conductive type source region 115, a source contact region 141, a second conductive type contact region 123, a source electrode 142, a gate insulating layer 131, a gate 132, and an interlayer insulating layer 150.
[0071] The first conductive type second epitaxial layer 112 may include a first conductive type 2-1 epitaxial layer 112a and a first conductive type 2-2 epitaxial layer 112b.
[0072] The first conductivity type may be N-type and the second conductivity type may be P-type, but is not limited thereto. The substrate 110, the first conductivity type first epitaxial layer 111, and the first conductivity type second epitaxial layer 112 may include, but are not limited to, SiC (Silicon Carbide).
[0073] Specifically, the power semiconductor device 100 according to the embodiment may include a substrate 110, a first epitaxial layer 111 of a first conductivity type disposed on the substrate 110, a second epitaxial layer 112a of a first conductivity type disposed on the first epitaxial layer 111 of the first conductivity type, and a second epitaxial layer 112b of a first conductivity type disposed on the second epitaxial layer 112a of the first conductivity type.
[0074] The embodiment may also include a well 121 of a second conductivity type formed in the 2-1 epitaxial layer 112a of the first conductivity type.
[0075] The top surface of the second conductive type well 121 may be at the same level as or lower than the first conductive type 2-1 epitaxial layer 112a.
[0076] The embodiment may also include a second conductivity type ion implantation region 122 located above the second conductivity type well 121, a source region 115 arranged on the second conductivity type ion implantation region 122, and a second conductivity type contact region 123.
[0077] The embodiment may also include a source electrode 142 disposed on the source region 115 and the second conductivity type contact region 123, a gate insulating layer 131 formed on the bottom and sidewalls of a trench region T (see FIG. 8) in which a portion of the second conductivity type ion implantation region 122 and the first conductivity type 2-2 epitaxial layer 112b has been removed, a gate 132 disposed on the gate insulating layer 131, an interlayer insulating layer 150 disposed on the trench gate 132, and a gate electrode (not shown) electrically connected to the trench gate 132.
[0078] According to the power semiconductor device, the power conversion device including the same, and the method for manufacturing the power semiconductor device according to the embodiment, the second conductivity type well 121 is disposed below the trench gate 132 to disperse an electric field concentrated at the bottom corner of the trench gate. If the electric field at the bottom corner of the trench gate cannot be dispersed, the breakdown voltage may be significantly reduced or problems may occur with gate reliability, resulting in a shortened lifespan of the semiconductor device.
[0079] In addition, according to the embodiment, the second conductivity type well 121 is formed without using high-energy ion implantation, thereby preventing the problem of pitch reduction due to lateral straggling of dopants. In addition, by forming the second conductivity type well 121 in a region deeper than the trench, it is possible to disperse the electric field concentrated at the bottom corner of the gate trench, thereby providing the technical effect of preventing breakdown of the gate insulating layer.
[0080] On the other hand, conventional techniques require the introduction of expensive specialized equipment for high-energy ion implantation, and despite this specialized equipment, yields are low and there is a problem of pitch reduction due to the difficulty of controlling lateral straggling, which occurs severely in high-energy ion implantation.
[0081] Lateral straggling refers to the unintentional increase in ion implantation in the lateral direction, and when lateral straggling occurs, the electron movement width becomes narrower, resulting in an increase in Ron.
[0082] Furthermore, in the conventional technology, if a subsequent thermal oxidation process is performed on the trench sidewall after ion implantation on the trench sidewall, unexpectedly grown oxide may occur in terms of thickness and characteristics, which may affect Vth, Ron, gate oxide lifetime, etc.
[0083] In addition, in the embodiment, the doping concentration of the second conductivity type well 121 formed on the first conductivity type 2-1 epitaxial layer 112a may be higher than the doping concentration of the second conductivity type ion implantation region 122. For example, according to the embodiment, there is a technical effect that the doping concentration of the second conductivity type well 121 formed below the trench gate 132 can be abruptly changed from the doping concentration of the second conductivity type ion implantation region 122 formed adjacent to the trench gate 132.
[0084] For example, the doping concentration of the second conductivity type well 121 is 2×10 17 ~2×10 19 / cm 3 The doping concentration of the second conductivity type ion implantation region 122 may be 1×10 16 ~1×10 17 / cm 3 It may be, but is not limited to this.
[0085] According to the embodiment, the doping concentration of the second conductive type well 121 formed below the trench gate 132 is higher than the doping concentration of the second conductive type ion implantation region 122, which has the effect of expanding a depletion layer toward the substrate 110, thereby providing a technical effect of increasing the breakdown voltage. Also, according to the embodiment, the doping concentration of the second conductive type ion implantation region 122 formed around the trench gate 132 is lower than the doping concentration of the second conductive type well 121, which provides a combined technical effect of reducing the threshold voltage and increasing the current density.
[0086] Hereinafter, a manufacturing process of the power semiconductor device 100 according to the embodiment shown in FIG. 3 will be described with reference to FIGS.
[0087] 4, a first conductivity type first epitaxial layer 111 and a first conductivity type 2-1 epitaxial layer 112a may be sequentially grown on a substrate 110. The first conductivity type first epitaxial layer 111 may include a first conductivity type buffer layer (not shown) and a first conductivity type drift layer (not shown).
[0088] The substrate 110, the first conductive type first epitaxial layer 111, and the 2-1 epitaxial layer 112a may include, but are not limited to, 4H—SiC material. For example, the substrate 110, the first conductive type first epitaxial layer 111, and the 2-1 epitaxial layer 112a may include 3C—SiC or 6H—SiC.
[0089] Next, a well 121 of a second conductivity type can be formed in the 2-1 epitaxial layer 112a of the first conductivity type by ion implantation.
[0090] For example, the second conductive type well 121 may be formed by forming a first hard mask pattern (not shown) and then performing ion implantation using the first hard mask pattern as an ion implantation mask. The second conductive type well 121 may be, but is not limited to, a P-type body. The first hard mask pattern may include, but is not limited to, a polysilicon pattern and an oxide pattern.
[0091] The second conductivity type well 121 may be ion-implanted with a P-type dopant, such as Al or boron, but is not limited thereto.
[0092] According to the embodiment, the second conductivity type well 121 is formed in the first conductivity type 2-1 epitaxial layer 112a without using high energy ion implantation, thereby preventing the problem of pitch reduction due to lateral straggling of dopants. In addition, by forming the second conductivity type well 121 in a region deeper than the trench, it is possible to disperse the electric field concentrated at the bottom corner of the gate trench, thereby providing the technical effect of preventing breakdown of the gate insulating layer.
[0093] Next, referring to FIG. 5, a second epitaxial layer 112b of the first conductivity type may be regrown on the first epitaxial layer 112a of the first conductivity type.
[0094] According to this embodiment, the second conductivity type well 121 is formed on the first conductivity type 2-1 epitaxial layer 112a without using high energy ion implantation, thereby preventing the problem of pitch reduction due to lateral straggling of dopants and forming the second conductivity type well 121 in a region deeper than the trench gate 132 to be formed later. This allows for the dispersion of an electric field concentrated at the bottom corner of the gate trench, thereby providing a technical effect of preventing breakdown of the gate insulating layer.
[0095] Next, referring to FIG. 6, a second conductivity type ion implantation region 122 can be formed by implanting ions such as Al or boron into the first conductivity type 2-2 epitaxial layer 112b.
[0096] In the embodiment, the doping concentration of the second conductivity type well 121 formed in the first conductivity type 2-1 epitaxial layer 112 a may be higher than the doping concentration of the second conductivity type ion implantation region 122 .
[0097] For example, according to the embodiment, there is a technical effect that the doping concentration of the second conductive type well 121 formed under the trench gate 132 changes abruptly from the doping concentration of the second conductive type ion implantation region 122 formed adjacent to the trench gate 132.
[0098] For example, the doping concentration of the second conductivity type well 121 is 2×10 17 ~2×10 19 / cm 3 The doping concentration of the second conductivity type ion implantation region 122 may be 1×10 16 ~1×10 17 / cm 3 It may be, but is not limited to this.
[0099] According to the embodiment, the doping concentration of the second conductive type well 121 formed below the trench gate 132 is higher than the doping concentration of the second conductive type ion implantation region 122, which has the effect of expanding the depletion layer toward the substrate 110, resulting in a technical effect of increasing the breakdown voltage.
[0100] In addition, according to the embodiment, the doping concentration of the second conductive type ion implantation region 122 formed around the trench gate 132 is formed lower than the doping concentration of the second conductive type well 121, thereby providing the combined technical effects of reducing the threshold voltage and increasing the current density.
[0101] 7, a second hard mask pattern (not shown) may be used as an ion implantation mask to implant ions into the second conductivity type ion implantation region 122 to form the first conductivity type source region 115. For example, about 1×10 ions of an N-type dopant, such as nitrogen or phosphorus, may be implanted into the second conductivity type ion implantation region 122 to form the first conductivity type source region 115. 18 cm -3 ~Approx. 7×10 19 cm -3 The first conductivity type source region 115 can be formed by ion implantation at a concentration of 1000 .mu.m or more by a self-alignment method.
[0102] In addition, a second conductive type contact region 123 may be formed using a third hard mask pattern (not shown) as an ion implantation mask. The second conductive type contact region 123 may function to maintain the zero potential of the second conductive type ion implantation region 122 and may function as a body diode.
[0103] Next, referring to FIG. 8, a trench region T can be formed by partially removing the first conductivity type source region 115, the second conductivity type ion implantation region 122, and the first conductivity type 2-2 epitaxial layer 112b using a fourth hard mask pattern (not shown) as an etching mask.
[0104] The fourth hard mask pattern may be an inverted pattern of the first hard mask pattern.
[0105] For example, the fourth hard mask pattern for forming the trench region T may correspond to an open region of the first hard mask pattern for ion implantation.
[0106] As a result, in this embodiment, the trench region T is formed to be aligned on the second conductivity type well 121, and the trench gate 132 and the second conductivity type well 121 formed later are aligned vertically.
[0107] Next, referring to FIG. 9, a gate insulating layer 131 may be formed in the trench region T, and a trench gate 132 may be formed on the gate insulating layer 131.
[0108] According to the embodiment, the second conductive type well 121 is disposed below the trench gate 132 to disperse the electric field concentrated at the bottom corner of the gate trench.
[0109] In particular, according to the embodiment, the second conductivity type well 121 is formed without using high-energy ion implantation, which prevents the problem of pitch reduction due to lateral straggling of dopants. In addition, the second conductivity type well 121 can be formed in a region deeper than the trench, which allows for the dispersion of the electric field concentrated at the bottom corner of the gate trench, thereby providing the technical effect of preventing breakdown of the gate insulating layer.
[0110] The gate insulating layer 131 may be, but is not limited to, a thermal oxide film or a deposited oxide film using LPCVD, etc. The trench gate 132 may be, but is not limited to, polysilicon.
[0111] Thereafter, the source contact 141 can be formed. For example, the source contact 141 can be formed using Ti or Ni, but is not limited thereto.
[0112] Also, the drain electrode 105 can be formed on the substrate 110 using Ti / Al.
[0113] Next, referring to FIG. 10, an interlayer insulating layer 150 may be formed on the trench gate 132 and the gate insulating layer 131, and a source electrode 142 and a gate electrode (not shown) may be formed on the interlayer insulating layer 150 and the source contact 141.
[0114] The interlayer insulating layer 150 may be formed of an oxide film or a nitride film, but is not limited thereto.
[0115] The source electrode 142 may be made of, but is not limited to, Al, etc. The source electrode 142 may further include a barrier metal layer.
[0116] According to the power semiconductor device, the power conversion device including the same, and the method for manufacturing the power semiconductor device according to the embodiment, the second conductivity type well 121 is disposed below the trench gate 132 to disperse an electric field concentrated at the bottom corner of the trench gate. If the electric field at the bottom corner of the trench gate cannot be dispersed, the breakdown voltage may be significantly reduced or problems may occur with gate reliability, resulting in a shortened lifespan of the semiconductor device.
[0117] In addition, according to the embodiment, the second conductivity type well 121 is formed without using high-energy ion implantation, thereby preventing the problem of pitch reduction due to lateral straggling of dopants, and the second conductivity type well 121 is formed in a region deeper than the trench, thereby enabling the dispersion of the electric field concentrated at the bottom corner of the gate trench, thereby providing the technical effect of preventing breakdown of the gate insulating layer.
[0118] In addition, in the embodiment, the doping concentration of the second conductivity type well 121 formed on the first conductivity type 2-1 epitaxial layer 112a may be higher than the doping concentration of the second conductivity type ion implantation region 122. For example, according to the embodiment, there is a technical effect that the doping concentration of the second conductivity type well 121 formed below the trench gate 132 can be abruptly changed from the doping concentration of the second conductivity type ion implantation region 122 formed adjacent to the trench gate 132.
[0119] For example, the doping concentration of the second conductivity type well 121 is 2×10 17 ~2×10 19 / cm 3 The doping concentration of the second conductivity type ion implantation region 122 may be 1×10 16 ~1×10 17 / cm 3 It may be, but is not limited to this.
[0120] According to the embodiment, the doping concentration of the second conductive type well 121 formed below the trench gate 132 is higher than the doping concentration of the second conductive type ion implantation region 122, which has the effect of expanding a depletion layer toward the substrate 110, thereby providing a technical effect of increasing the breakdown voltage. Also, according to the embodiment, the doping concentration of the second conductive type ion implantation region 122 formed around the trench gate 132 is lower than the doping concentration of the second conductive type well 121, which provides a combined technical effect of reducing the threshold voltage and increasing the current density.
[0121] Although the present invention has been described above with reference to an embodiment, it will be readily apparent to those skilled in the art that the present invention can be modified and changed in various ways without departing from the spirit and scope of the present invention as set forth in the claims below.
Claims
1. A substrate; a first epitaxial layer of a first conductivity type disposed on the substrate; a second-first epitaxial layer of a first conductivity type disposed on the first epitaxial layer of the first conductivity type; a second-second epitaxial layer of the first conductivity type disposed on the second-first epitaxial layer of the first conductivity type; a well of a second conductivity type partially formed in the second-1 epitaxial layer of the first conductivity type; a second conductivity type ion implantation region and a source region located above the second conductivity type well; a source electrode disposed over the source region; a gate insulating layer formed in a trench region in which the second conductivity type ion implantation region and a portion of the first conductivity type second-2 epitaxial layer are removed; a trench gate disposed on the gate insulating layer; an interlayer insulating layer disposed on the trench gate; a gate electrode electrically connected to the trench gate.
2. 2. The power semiconductor device according to claim 1, wherein an upper surface of the second conductivity type well is at the same level as or lower than the first conductivity type 2-1 epitaxial layer.
3. 2. The power semiconductor device according to claim 1, wherein the doping concentration of the second conductivity type well formed in the first conductivity type 2-1 epitaxial layer is higher than the doping concentration of the second conductivity type ion implantation region.
4. A power conversion device comprising the power semiconductor device according to claim 1 .
5. growing a first epitaxial layer of a first conductivity type on a substrate; growing a second epitaxial layer of a first conductivity type on the first epitaxial layer of the first conductivity type; partially forming a well of a second conductivity type by implanting ions into the second-1 epitaxial layer of the first conductivity type; growing a second epitaxial layer of the first conductivity type on the second epitaxial layer of the first conductivity type; implanting ions into the second-2 epitaxial layer of the first conductivity type to form a second conductivity type ion implantation region and a source region; forming a trench region by removing a portion of the second conductivity type ion implantation region and the first conductivity type second-2 epitaxial layer; forming a gate insulating layer and a trench gate in the trench region; forming an interlayer insulating layer on the trench gate; forming a gate electrode electrically connected to the trench gate.
6. 6. The method of claim 5, wherein an upper surface of the second conductivity type well is at the same level as or lower than the first conductivity type 2-1 epitaxial layer.
7. 6. The method for manufacturing a power semiconductor element according to claim 5, wherein a doping concentration of the well of the second conductivity type formed in the 2-1 epitaxial layer of the first conductivity type is higher than a doping concentration of the ion implantation region of the second conductivity type.
8. 6. The method of claim 5, wherein a portion of the second conductivity type well is exposed in the step of forming the trench region by removing a portion of the second conductivity type ion implantation region and the first conductivity type 2-2 epitaxial layer.
9. The method for manufacturing a power semiconductor device according to claim 5 , wherein the gate insulating layer is in contact with the well of the second conductivity type.
10. 6. The method of claim 5, wherein the hard mask pattern for forming the trench region corresponds to an open region of the hard mask pattern for ion implantation for forming the second conductivity type well.