Semiconductor die and method for manufacturing the same

Abstract

To provide a passivation system used for SiC semiconductors.SOLUTION: A semiconductor die (1) comprises a silicon carbide (SiC) semiconductor body (11), and a passivation system (40) on a first side (11.1) of the SiC semiconductor body (11). The passivation system (40) includes an inorganic passivation layer system (45), and an organic layer (41) on the inorganic passivation layer system (45). A side edge (45.i) of the inorganic passivation layer system (45) is disposed on the SiC semiconductor body (11). The inorganic passivation layer system (45) is recessed laterally beneath the organic layer (41), and the side edge (45.i) of the inorganic passivation layer system (45) is covered by the organic layer (41).SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor die that includes a semiconductor body. [Background technology]

[0002] In an embodiment of this application, the semiconductor body is made of, for example, silicon carbide (SiC), which has a relatively wide bandgap compared to silicon. This may be interesting, for example, for power semiconductor devices in high voltage and / or high current applications. Device structures having one or more load terminals, for example, transistor structures having source and drain terminals, may be formed within the semiconductor body. Metallization may be formed on the semiconductor body for wiring and contacting the device structures. Summary of the Invention

[0003] The embodiments of the present application are directed to advantageous semiconductor dies.

[0004] The semiconductor die may include a silicon carbide (SiC) semiconductor body, an insulating layer, and a passivation system having an inorganic passivation layer system. The insulating layer is disposed on a first side of the SiC semiconductor body, and the passivation system is disposed on the insulating layer (with local metallization disposed therebetween). The insulating layer has an outer side edge on the first side of the SiC semiconductor body, for example, offset laterally inward from a side edge of the SiC semiconductor body. In one embodiment, the outer side edge of the inorganic passivation layer system is disposed on the insulating layer, for example, offset laterally inward from the outer side edge of the insulating layer.

[0005] In other words, the inorganic passivation layer system does not extend to the first side of the SiC semiconductor body, but terminates on the insulating layer. Thus, for example, at least in the edge termination region of the side edge of the SiC semiconductor body, an interface between the SiC semiconductor body and the insulating layer may be provided, rather than an interface between the inorganic passivation layer system and the SiC semiconductor body. For example, given possible SiC oxidation caused or driven by humidity and electric fields in this region, such an insulating layer and / or the interface between the SiC semiconductor body and the insulating layer may not be as critical.

[0006] The insulating layer may include one or more silicon oxide layers (see details below) and may be less susceptible to delamination or crack propagation / penetration than inorganic passivation layer systems, which may include, for example, silicon nitride layers (see details below). Laterally protruding insulating layers can reduce mechanical stress through localized cracking, for example, in the case of mechanical stress resulting from side or underlying SiC oxidation, which can reduce the risk of inward crack or delamination propagation. Simply put, cracking or localized chipping of an outwardly protruding insulating layer can reduce the risk of inward cracking / delamination (toward the active area). Alternatively or additionally, interfaces such as silicon oxide / SiC may have a reduced risk of delamination.

[0007] Further embodiments and features are provided in the claims and throughout this disclosure. Thus, individual features are disclosed independently of any particular claim category, and the disclosure relates not only to apparatus and device aspects, but also to method and use aspects. For example, if a die manufactured by a particular method is described, this also discloses the corresponding manufacturing process, and vice versa.

[0008] Generally, a SiC semiconductor body may include a SiC semiconductor substrate, e.g., in combination with one or more epitaxial SiC layers thereon. The side of the top epitaxial SiC layer facing away from the SiC substrate may be the "first side" of the SiC semiconductor body. Conversely, the side of the SiC substrate facing away from the one or more epitaxial SiC layers may be the "second side" of the SiC semiconductor body.

[0009] Generally, when referring to the disposition of a layer or a side edge of a layer "on" another layer or entity, e.g., on a SiC semiconductor body, this does not necessarily mean disposition directly adjacent to this layer or entity. In other words, additional layers may be disposed in between. See further details below regarding the disposition of an inorganic passivation layer system on an insulating layer. Alternatively, disposition "on" can refer to disposition "directly on," e.g., an outer side edge of an insulating layer may be disposed directly on a first side of the SiC semiconductor body.

[0010] In one embodiment, the outer lateral edge of the inorganic passivation layer system is offset laterally inward from the outer lateral edge of the insulating layer by at least 1 μm. Further lower limits are, for example, at least 2 μm or 2.5 μm. Possible upper limits are, for example, at most 50 μm, 30 μm, or 20 μm. In particular, each distance can be taken as, for example, the smallest lateral distance between the lateral edge of the inorganic passivation layer system and the outer lateral edge of the insulating layer in a cross-sectional plane perpendicular to the lateral edge of the inorganic passivation layer system. Generally, when referring to a "cross-sectional plane," this can refer to a vertical cross-section parallel to the vertical direction and perpendicular to the lateral direction. For example, the extension of the SiC semiconductor body in the vertical direction can be smaller than its extension in the lateral direction.

[0011] In one embodiment, the outer side edge of the insulating layer is laterally disposed between the side edge of the SiC semiconductor body and the active area. In other words, the outer side edge of the insulating layer may be disposed in an edge termination region, where device structures may be formed within the SiC semiconductor body. See further details below.

[0012] Near the side edges of the SiC semiconductor body, there may be an electric field, e.g., arising from a back surface potential that can reach from the back surface (second side) to the front surface (first side) at the side edges of the SiC semiconductor body, which may cause or drive an oxidation process. The "outer side edge" of the insulating layer or inorganic passivation layer system may face the side edge of the SiC semiconductor body (while the inner edge may face the active area).

[0013] Each outer side edge may be, for example, the outermost side edge of an insulating layer or inorganic passivation layer or system (e.g., no other elements of the insulating layer or inorganic passivation layer system are disposed further outward). Generally, "outer" or "outermost" refers to a lateral position relative to a respective side edge of the SiC semiconductor body, i.e., near or closest to this side edge. Elements discussed with respect to their relative position are, for example, disposed on the same side of the active area of ​​the die, i.e., on the same side edge of the SiC semiconductor body. Thus, similar structures may be disposed on other side edges of the SiC semiconductor body, but this is not required.

[0014] In the active area, a device structure may be formed within the SiC semiconductor body. The device structure may include, for example, a first load terminal disposed on a first side of the SiC semiconductor body. Additionally, the device structure may include, for example, a second load terminal on a second, vertically opposite side of the SiC semiconductor body. The device structure may be, for example, a FET having a source terminal / region and a drain terminal / region within the SiC semiconductor body (e.g., a source region on a first side of the SiC semiconductor body and a drain region on a second side thereof). In other words, a load pad within the metallization may be a source pad connected to the source terminal of the device structure.

[0015] In addition to the source and drain regions, the device may include a body region to which the gate electrode is capacitively coupled. Additionally, a drift region, for example, made of the same doping type as the drain region but less concentrated than the drain region, may be disposed between the body and drain regions. The source and drain regions, and the drift region, if present, may be made of a first doping type, and the body region may be made of a second doping type. In the illustrated embodiment, the first doping type is n-type and the second doping type is p-type.

[0016] In one embodiment, regardless of the specific device type in the active area, the insulating layer can include an oxide layer. The oxide layer can be, for example, an undoped silicate glass (USG) layer, for example, when the device formed in the active area of ​​the die is a diode. Alternatively, the oxide layer can be a phosphosilicate glass (PSG) layer or a borophosphosilicate glass (BPSG) layer (e.g., a BPSG layer having a boron content of 0.5 wt.% (mass percentage)). In other words, the insulating layer can include a doped oxide layer, for example, in addition to an undoped oxide layer. The insulating layer can have a total thickness of, for example, at least 0.3 μm, e.g., at least 0.5 μm, and / or at most 3 μm.

[0017] In particular, the insulating layer may include an undoped oxide layer (e.g., a TEOS layer), which is referred to in the exemplary embodiments as a "second oxide layer." Alternatively or additionally, the insulating layer may include a doped oxide layer (e.g., a BPSG layer), which is referred to in the exemplary embodiments as a "third oxide layer." Optionally, the insulating layer may include an additional oxide layer, e.g., below the second and / or third oxide layers, which is referred to in the exemplary embodiments as a "first oxide layer." The first oxide layer, if present, may be, e.g., a gate oxide layer, the same layer forming a gate dielectric, e.g., in the active area.

[0018] In one embodiment, the insulating layer includes a first, second, and third oxide layer. For example, the second oxide layer may be disposed directly on the first oxide layer, and / or the third oxide layer may be disposed directly on the second oxide layer. In other examples, additional oxide layers may be disposed between the first and second oxide layers and / or between the second and third oxide layers. In alternative embodiments, the insulating layer includes only the first and third oxide layers (e.g., no second oxide layer), e.g., the third oxide layer is disposed directly on the first oxide layer.

[0019] For example, the third oxide layer may have a thickness of, for example, at least 0.2 μm, for example, at least 0.4 μm, and / or at most 2 μm, for example, at most 1.2 μm. The second oxide layer, if present, may have a thickness of, for example, at least 0.1 μm, for example, at least 0.15 μm, and / or at most 0.8 μm, for example, at most 0.6 μm. The first oxide layer, if present, may have a thickness of, for example, at least 30 nm, 50 nm, 70 nm, or 80 nm, with possible upper limits being, for example, at most 250 nm, 200 nm, or 150 nm.

[0020] In one embodiment, the inorganic passivation layer system includes a silicon nitride layer. Optionally, the inorganic passivation layer system may additionally include a silicon oxide layer. The silicon nitride layer may be disposed below or above the silicon oxide layer. In one embodiment, the silicon oxide layer is disposed on a first silicon nitride layer, and the second silicon nitride layer is disposed on the silicon oxide layer, e.g., the silicon oxide layer is disposed directly on the first silicon nitride layer, and / or the second silicon nitride layer is disposed directly on the silicon oxide layer. For example, the first silicon nitride layer may be thinner than the silicon oxide layer and / or the second silicon nitride layer. Regardless of these geometric details, the silicon oxide layer may be an undoped silicon oxide layer (e.g., undoped silicon glass (USG)).

[0021] Regardless of the details of the additional layer stack or materials, the bottom layer of the inorganic passivation layer system can be a silicon nitride layer, e.g., the first silicon nitride layer in the above terminology. The bottom layer of the inorganic passivation layer system, e.g., the silicon nitride layer, can be disposed directly on the insulating layer or with an additional layer therebetween. In other words, an additional layer, e.g., an aluminum oxide layer or a (thin) silicon nitride layer, can be disposed between the inorganic passivation layer system and the insulating layer, as discussed in further detail below. For example, only an aluminum oxide layer can be disposed between the inorganic passivation layer system and the first side of the SiC semiconductor body. The additional layer can function, for example, as an adhesion promoter layer and / or an etch stop layer. The additional layer can have a thickness of, for example, 30 nm, 20 nm, or 15 nm or less, with possible lower limits being, for example, 3 nm or 5 nm. In other words, to summarize, a placement "on" can mean a relatively small distance, for example 100 nm, 50 nm, 30 nm, 20 nm, or 15 nm or less, or a placement "directly on."

[0022] In one embodiment, the passivation system includes an organic layer (e.g., an imide layer). The organic layer disposed on the inorganic passivation layer system may be disposed directly on the inorganic passivation layer system or may be disposed with an additional layer, such as an aluminum oxide layer, in between. Optionally, the outer lateral edges of the organic layer may be laterally flush with the outer lateral edges of the inorganic passivation layer system. In this case, the organic layer may be used, for example, as a mask for structuring the inorganic passivation layer system during manufacturing and may remain intact on the inorganic passivation layer system in the prefabricated die.

[0023] In alternative embodiments, the organic layer extends further outward, covering the outer lateral edges of the inorganic passivation layer system. The organic layer may have its outer lateral edges on the insulating layer, i.e., laterally between the outer lateral edges of the insulating layer and the outer lateral edges of the inorganic passivation layer system. By way of example, the outer lateral edges of the inorganic passivation layer system may be recessed laterally below the organic layer by at least 1 μm, with further lower limits being, for example, at least 2 μm or 2.5 μm. Possible upper limits are, for example, at most 50 μm, 30 μm, or 20 μm.

[0024] In an alternative embodiment, the organic layer extends further outward, covering the outer side edges of the insulating layer. In other words, the organic layer has its outer side edges on the SiC semiconductor body. The organic layer extending further outward can, for example, reduce or slow SiC oxidation, for example, by slowing the propagation of moisture to the interface / first side of the SiC semiconductor body. As discussed above, SiC oxidation can introduce mechanical stresses and potentially lead to a risk of delamination. Extending the organic layer (e.g., an imide layer) above the outer side edges of the insulating layer can at least slow SiC oxidation in this geometrically critical location.

[0025] Generally speaking, embodiments of the present application aim to provide an organic layer having a lateral, outer overlap on, i.e., covering, the side edges of an inorganic layer.

[0026] In one embodiment, the outer side edges of the insulating layer are recessed laterally below the organic layer by at least 1 μm, with further lower limits such as at least 2 μm or 2.5 μm. Possible upper limits are, for example, up to 50 μm, 30 μm, or 20 μm.

[0027] In one embodiment, the organic layer has a thickness of at least 1 μm, with further lower limits such as at least 2 μm, 3 μm, 4 μm, or 5 μm. Possible upper limits can be, for example, 50 μm, 40 μm, 30 μm, or 25 μm or less.

[0028] In one embodiment, the organic layer is an imide layer. The imide may be, for example, a photosensitive polyimide precursor.

[0029] In one embodiment, an electric field reduction structure is formed in the SiC semiconductor body. The electric field reduction structure may be laterally disposed between the active area and the side edge of the SiC semiconductor body. The electric field reduction structure can lower or reduce the electric field extending from the back surface to the first side, for example, reducing the electric field toward the active area where the device structure is located. The electric field reduction structure may include a doping well embedded with multiple laterally offset doping rings. For example, when viewed in a vertical cross section perpendicular to the side edge of the SiC semiconductor body, the doped rings may be arranged contiguously. When viewed in a vertical plan view, the doped rings may form nested rings, one within the other. The doping well may have a second doping type, and the doped rings may also have, for example, a second doping type. As described above, the load region, or regions of the device structure in the active area, for example, the source and drain regions, may have a first doping type.

[0030] Regardless of these details, the inorganic passivation layer system can cover the electric field reduction structure in a vertically upward direction. In other words, the outer side edge of the inorganic passivation layer system can be located, for example, at the same side as the outer side edge of the electric field reduction structure or further outward than the outer side edge of the electric field reduction structure when viewed in a vertical cross section perpendicular to the side edge of the inorganic passivation layer system. Alternatively or in addition, the inner side edge of the inorganic passivation layer system can be located, for example, at the same side as the inner side edge of the electric field reduction structure or further inward than the inner side edge of the electric field reduction structure when viewed in a vertical cross section perpendicular to the side edge of the inorganic passivation layer system.

[0031] In one embodiment, the semiconductor die includes a metallization on the first side of the SiC semiconductor body, and the insulating layer described above is disposed, for example, between the SiC semiconductor body and the metallization. In the case of a FET formed in the semiconductor body, the load pad can be, for example, a source pad (see above for details). The metallization can include at least one of copper and aluminum. The metallization can include a copper layer or copper layer system, for example, a bath-deposited copper layer system. Alternatively or additionally, the metallization can include an aluminum layer, for example, a sputter-deposited aluminum layer. The aluminum layer can be, for example, Al or AlCu with a copper content of less than 5 wt.%. A Ti / TiN and / or NiAl layer or layer stack can be disposed below the aluminum layer. For example, a layer stack including only a Ti / TiN layer and a NiAl layer can be disposed.

[0032] In one embodiment, the metallization comprises an aluminum layer (e.g., Al or AlCu) with a total thickness of at least 1.5 μm, 2.5 μm, or 3 μm, with possible upper limits, for example, up to 10 μm, 7 μm, or 5 μm. In alternative embodiments, the metallization comprises a copper layer system (e.g., bath deposited) with a total thickness of at least 3 μm, 5 μm, or 7 μm, with possible upper limits, for example, up to 20 μm, 15 μm, or 12 μm.

[0033] The passivation system can cover the side edges of the load pad, for example, extending to the side and reaching above the load pad. For example, in the case of a load pad made of a copper layer system, the inorganic passivation layer system can extend over the load pad and cover the outer side edges of the load pad. Alternatively, for example, in the case of a load pad made of an aluminum layer, the inorganic passivation layer system can be arranged on the side of the load pad, with the inner side edges of the inorganic passivation layer system being arranged, for example, at a distance of at least 1 μm and / or at most 50 μm, e.g., at least 3 μm and / or at most 10 μm, from the outer side edges of the metallization. However, even if the inorganic passivation layer system is arranged on the side of the load pad, the organic layer can still reach onto the load pad. Therefore, regardless of whether only the organic layer and / or the inorganic passivation layer system reaches onto the load pad, the passivation system can have openings in the load pad, for example, for later contact in a package or other mounting structure.

[0034] At the outer side edges of the load pad, whether made of aluminum or copper, the insulating layer may be disposed below the load pad and the passivation system may be disposed above the load pad (e.g., when viewed in a vertical cross section perpendicular to the outer side edges of the load pad). In other words, the load pad or metallization may, in certain areas, be disposed vertically between the insulating layer and the passivation system (e.g., an organic layer and / or an inorganic passivation layer system). In further outer areas, the passivation system may be disposed on the insulating layer without any metallization in between (e.g., other than one or more locations where runners are formed). In this further outer area, the inorganic passivation layer system may be disposed at a relatively small distance from the insulating layer, e.g., 100 nm, 50 nm, 30 nm, 20 nm, or 15 nm or less, or may be disposed "directly on" the insulating layer. See the above description for details.

[0035] When viewed in a cross-sectional plane perpendicular to the side edges of the load pad, the inorganic passivation layer system that extends onto the load pad may have an inner lateral edge on the load pad. Generally, the organic layer may be flush with the inner lateral edge of the inorganic passivation layer system on the load pad. However, in one embodiment, the organic layer extends further inward than the inorganic passivation layer system, i.e., laterally inwardly covering the inner lateral edge of the inorganic passivation layer system.

[0036] In one embodiment, the inorganic passivation layer system extends uninterrupted, i.e., without interruptions, between the side edges of the load pad and the inner side edges of the inorganic passivation layer system when viewed in a cross-sectional plane perpendicular to the side edges of the load pad. Alternatively, the inorganic passivation layer system may be provided with interruptions on the load pad, for example, on side locations between the side edges of the load pad and the inner side edges of the inorganic passivation layer system. Regardless of whether the inorganic passivation layer system is provided with interruptions, the organic layer may extend uninterrupted, i.e., without interruptions, between the opening in the load pad and the side edges of the load pad (and further outward toward the side edges of the SiC semiconductor body).

[0037] In one embodiment, the metallization in the area of ​​the load pad is stepped. Laterally outside the step, e.g., closer to the side edge of the SiC semiconductor body or die, the load pad has a first thickness t1. Laterally inside the step, e.g., at a greater distance from the side edge of the SiC semiconductor body or die, the load pad has a second thickness t2, where t1 is smaller than t2. In other words, the load pad has a smaller thickness t1 at the edge of the load pad and a larger thickness at the center of the load pad. The latter may be advantageous, for example, in terms of thermal management or mounting and bonding; the smaller thickness at the edge may, for example, reduce the topology of a passivation system extending over the load pad.

[0038] In one embodiment, the inner side position x2 along which the passivation system extends is located laterally outward of the step. In other words, the passivation system extends laterally over the load pad when viewed in the cross-sectional plane, but terminates at the edge region of the load pad, where the load pad has a thickness t1. When viewed in the cross-sectional plane, the passivation system covers the side edges of the load pad but not the step.

[0039] In one embodiment, the metallization includes a copper layer. The copper layer may be part of a copper layer system that may include, for example, a sputter-deposited copper layer and one or more bath-deposited copper layers thereon. In one embodiment, the metallization includes a first bath-deposited copper layer and a second bath-deposited copper layer deposited on the first bath-deposited copper layer, where the second bath-deposited copper layer may be structured relative to the first bath-deposited copper layer. In other words, the second bath-deposited copper layer may form a step portion of the load pad.

[0040] To structure the second bath-deposited copper layer, a mask can be applied to the first bath-deposited copper layer before the second bath-deposited copper layer is deposited. Steps in the load pad can be formed at the side edges of the second bath-deposited copper layer, with the side edges of the second bath-deposited copper layer being displaced inward relative to the side edges of the first bath-deposited copper layer. Alternatively, however, one or more copper layers can be sputter-deposited regardless of whether a bath-deposited copper layer system is subsequently applied. In other words, one or more sputter-deposited copper layers can be combined with bath-deposited copper layers, or the entire copper metallization can be sputter-deposited. Also, in the case of sputter-deposited copper metallization, the upper copper layer can be structured relative to the underlying copper layer to form a step.

[0041] In summary, all copper layers of the metallization, whether sputter-deposited and / or bath-deposited, can have a thickness of at least 3 μm, with further lower limits of, for example, 5 μm or 7 μm. For example, the upper limit can be 25 μm or 20 μm. A barrier layer system (e.g., including a Ti / TiN layer) can be arranged below the lowest copper layer, e.g., a sputter-deposited copper layer, in the metallization. An adhesion promoter layer can be provided above the insulating layer and / or below the organic layer, e.g., vertically between the insulating layer and the organic layer. The adhesion promoter layer can have a thickness of at least 10 μm and / or up to 100 μm, with further upper limits of, for example, up to 70 μm or 50 μm. The adhesion promoter layer can also be an inorganic layer, e.g., a silicon nitride layer. Compared to inorganic passivation layer systems, the adhesion promoter layer can extend further inward and / or outward, for example, when viewed in a vertical cross section perpendicular to the outer lateral edge of the insulating layer.

[0042] If an inorganic passivation layer system is formed on an insulating layer, the adhesion promoter layer can be disposed vertically between the insulating layer and the inorganic passivation layer system. If a metallization (e.g., a load pad) extends on the insulating layer, the adhesion promoter layer can cover at least a portion of the metallization / load pad (e.g., disposed vertically between the load pad / metallization and the organic layer). Laterally and inwardly on the metallization / load pad, the adhesion promoter layer can extend, for example, to the extent that the passivation system extends, for example, to the opening where the organic layer is on the load pad / metallization.

[0043] A method for manufacturing a semiconductor die includes: I) forming an insulating layer on a first side of a silicon carbide (SiC) semiconductor body such that an outer side edge of the insulating layer is disposed on the SiC semiconductor body; II) forming an inorganic passivation layer system on the insulating layer such that an outer side edge of the inorganic passivation layer system is disposed on the insulating layer and is offset laterally inward from the outer side edge of the insulating layer; may include:

[0044] In one embodiment, step II) comprises: i) depositing an inorganic passivation layer system on a first side of a SiC semiconductor body; ii) etching the inorganic passivation layer system in order to locally define outer lateral edges of the inorganic passivation layer system; Includes.

[0045] In step ii), a mask can be deposited on the inorganic passivation layer system, which can be locally etched where there are openings in the mask, for example on the insulating layer and / or on the load pads formed in the metallization. Regardless of these details, after the inorganic passivation layer system has been locally etched, the mask can be removed, for example before forming the organic layer in step II).

[0046] Any of these methods or method steps may be applied to the manufacture of semiconductor dies as described above.

[0047] In the following, the semiconductor die and the manufacturing method will be described in further detail by exemplary embodiments, in which the individual features can also be associated in different combinations. [Brief explanation of the drawings]

[0048] [Figure 1] 1 shows a cross-sectional view of a semiconductor die comprising a SiC semiconductor body and a passivation system. [Figure 2] 1 shows a more detailed view of a passivation system on a SiC semiconductor body. [Figure 3] 1 shows a schematic cross section of a device formed in an active area of ​​a semiconductor die. [Figures 4a-4e] 1 illustrates different steps in manufacturing a semiconductor die with a passivation system comprising an inorganic passivation layer system and an organic layer. [Figure 5]1 shows a detailed view of one embodiment of a passivation system on a SiC semiconductor body. [Figure 6] Several manufacturing steps are summarized in a flow diagram. [Figure 7] 1 shows a cross-sectional view of a semiconductor die comprising a SiC semiconductor body, an insulating layer, and a passivation system. [Figures 8a-8e] 1A-1D show schematic cross-sectional views of different embodiments of a SiC semiconductor body with an insulating layer and a passivation system; [Figure 9] Several manufacturing steps are summarized in a flow diagram. [Figure 10] 1 shows a cross-sectional view of a semiconductor die comprising a SiC semiconductor body and a passivation system. DETAILED DESCRIPTION OF THE INVENTION

[0049] 1 illustrates a vertical cross section of a portion of a semiconductor die 1. The semiconductor die 1 comprises a silicon carbide (SiC) semiconductor body 11. An insulating layer 90 is disposed on a first side 11.1 of the SiC semiconductor body 11. Furthermore, a metallization 30 including a barrier layer system 130 is formed on the SiC semiconductor body 11. Disposed on the barrier layer system 130 is a copper layer system 230, which in the illustrated embodiment includes a sputter-deposited copper layer 231 and a bath-deposited copper layer system 235 having a first bath-deposited copper layer 235a and a second bath-deposited copper layer 235b.

[0050] Specifically, the cross-sectional view of FIG. 1 is located at a side edge 1.1 of die 1, with an inactive area 1b laterally disposed between side edge 1.1 of die 1 and active area 1a, shown on the right side of FIG. 1. In active area 1a, a transistor device cell may be disposed (see details below). In active area 1a, load pads 31, such as source pads connected to source terminals of devices or device cells, may be formed within metallization 30. In inactive area 1b, gate runners 32 and / or source runners 33 may be formed within metallization 30, each extending along active area 1a.

[0051] A passivation system 40 is disposed on the metallization 30. In the illustrated embodiment, the passivation system 40 comprises an inorganic passivation layer system 45 and an organic layer 41 (e.g., an imide layer 42) of the inorganic passivation layer system 45. As will be discussed in more detail with reference to Figure 4e, an additional adhesion promoter layer may be disposed in between (not shown here).

[0052] The inorganic passivation layer system 45 shown in the figure includes a first silicon nitride layer 45.1, an undoped silicon oxide layer 45.2 directly on the first silicon nitride layer 45.1, and a second silicon nitride layer 45.3 directly on the undoped silicon oxide layer 45.2. The passivation system 40 covers the gate runners 32 and the source runners 33, and also covers an insulating layer 90 made of a doped oxide (e.g., borophosphosilicate glass (BPSG)). In the illustrated embodiment, an aluminum oxide layer 340 (shown only as a line in FIG. 1) is disposed below the inorganic passivation layer system 45, i.e., above the insulating layer 90 and above the metallization 30.

[0053] The cross-sectional plane of Figure 1 lies perpendicular to the side edge 31.1 of the load pad 31. The passivation system 40 extends between an outer side position x1 beside the load pad and an inner side position x2 located on the load pad 31 (i.e. covering the side edge 31.1 of the load pad 31). In the illustrated embodiment, an interruption 60 is provided in at least one layer 41, 42, 45.1-45.3 of the passivation system 40. In this case, the interruption 60 completely intersects the inorganic passivation layer system 45. The interruption 60 extends laterally between the side edge 31.1 of the load pad 31 and the inner side position x2 at the interruption position x1. i will be placed in.

[0054] 2 shows a more detailed view of the lateral edges 45.i of the inorganic passivation layer system 45 arranged on the SiC semiconductor body 11, with the cross-sectional plane lying perpendicular to the lateral edges 45.i. The lateral edges 45.i of the inorganic passivation layer system 45 are offset inward from the lateral edges 11.i of the SiC semiconductor body 11. The organic layer 41 (e.g., the imide layer 42 in the illustrated embodiment) extends further outward, covering the lateral edges 45.i of the inorganic passivation layer system 45. Thus, the outer lateral edges 41.i of the organic layer 41 are positioned further outward than the lateral edges 45.i of the inorganic passivation layer system 45, i.e., closer to the lateral edges 11.i of the SiC semiconductor body 11.

[0055] In the illustrated embodiment, the inorganic passivation layer system 45, i.e. the first silicon nitride layer 45.1 and the organic layer 41, respectively, are arranged directly on the first side 11.1 of the SiC semiconductor body 11. That is, the inorganic passivation layer system 45 is arranged laterally outside the insulating layer 90, and the organic layer 41 is arranged laterally outside the lateral edge 45.i of the inorganic passivation layer system. However, alternatively, an additional layer, such as, for example, an aluminum oxide layer, may be arranged in between (see FIG. 5 for illustration).

[0056] 3 shows a possible device 200 and device structure 20 formed within the active area 1a of die 1, for example, below load pad 31 (see FIG. 1 for comparison). In the SiC semiconductor body 11, in the illustrated embodiment, load terminal 21 is formed on a first side 11.1, which is a source region 22. On a vertically opposite second side 11.2, a drain region 27 is located, a body region 23 is disposed below source region 22, and a drift region 24 is located between body region 23 and drain region 27.

[0057] A gate region 25, including a gate electrode 25.1 and a gate dielectric 25.2 that capacitively couples the gate electrode 25.1 to the body region 23, is disposed within the trench 26. Through a voltage applied to the gate electrode 25.1, channel formation in the body region 23 and the resulting current flow between the source region 22 and the drain region 25 can be controlled. The device 200 may include multiple device cells 201 connected in parallel.

[0058] 4a-4e show several steps for manufacturing a semiconductor die having a semiconductor body, a metallization, and a passivation system. In FIG. 4a, an insulating layer 90 has already been deposited on a first side 11.1 of the semiconductor body 11, forming the metallization 30. On top of the metallization 30, an aluminum oxide layer 230 has been deposited (shown only as lines), followed by a silicon nitride layer 45.1 and a silicon oxide layer 45.2.

[0059] As shown in FIG. 4b, the silicon oxide layer 45.2 may be etched (not shown in detail here) before being covered with a second silicon nitride layer 45.3. In FIG. 4b, the inorganic passivation layer system 45 is deposited but not yet structured. Therefore, a mask 145 is provided on the inorganic passivation layer system 45. The mask 145 has openings 160 that define where interruptions in the inorganic passivation layer system 45 will be etched. Furthermore, the mask 145 defines the inner and outer side edges of the inorganic passivation layer system 45, i.e., where the inorganic passivation layer system 45 will open over the load pad 31.

[0060] 4c shows the inorganic passivation layer system 45 after the etching step, i.e. after the interruptions 60 have been etched into the inorganic passivation layer system 45 and after the side edges 45.i of the inorganic passivation layer system 45 have been defined. For example, applying an anisotropic etching step may leave inorganic layers 81.1, 81.2, e.g. a stack 80 of inorganic layers 81.1, 81.2, on the side surfaces 71 of the step 70.

[0061] In the next step, shown in Figure 4d, an organic layer 41 (in the illustrated embodiment an imide layer 42) is deposited on the structured inorganic passivation layer system 45. For structuring the organic layer 41, a mask 141 is formed on the organic layer 41. The mask 141 defines the lateral edges 41.i of the organic layer 41 and openings 140. See Figure 4e for an explanation. In this process step, the organic layer 41 is etched and the mask is removed from the organic layer 41.

[0062] Figure 5 shows a detailed view of a side edge 11.i of the SiC semiconductor body 11. The embodiment shown in Figure 5 differs from the embodiment shown in Figure 2 in that the inorganic passivation layer system 45 and the organic layer 41 (e.g., the imide layer 42) are not disposed directly on the first side 11.1 of the SiC semiconductor body 11 laterally outside the insulating layer 90. Instead, an adhesion promoter or etch stop layer 290, which in the illustrated example is an aluminum oxide layer, is disposed therebetween.

[0063] 6 summarizes several manufacturing steps in a flow diagram. Forming an inorganic passivation layer system on a first side of a SiC semiconductor body (600) can include depositing an inorganic passivation layer system on the first side (601), which is then locally etched (602) to define lateral edges of the inorganic passivation layer system. An organic layer can then be formed (610), for example, by depositing an organic layer (611) and locally etching the organic layer (612) to define openings and lateral edges.

[0064] Figure 7 shows an embodiment that differs in some respects from that discussed with reference to Figure 1. In this case, too, an insulating layer 90, a metallization 30, and a passivation system 40 are arranged on a first side 11.1 of a SiC semiconductor body 11 (see above for further details). In contrast to Figure 1, the outer side edges 45.i of the inorganic passivation layer system 45 are not arranged beside the insulating layer 90, but rather on the insulating layer 90. As a result, portions 90a of the insulating layer 90 that are beside the outer side edges 45.i of the inorganic passivation layer system 45, i.e., between the outer side edges 45.i of the inorganic passivation layer system 45 and the outer side edges 90.i of the insulating layer 90, are not covered by the inorganic passivation layer system 45.

[0065] The organic layer 41 (e.g., the imide layer 42) extends further outward than the inorganic passivation layer system 45 and the insulating layer 90, i.e., in the direction toward the outer side edge 1.1 of the die 1. The organic layer 41 (e.g., the imide layer 42) covers the outer side edges 45.i of the inorganic passivation layer system 45 and the outer side edges 90.i of the insulating layer 90.

[0066] The embodiment shown in FIG. 8a essentially corresponds to the embodiment of FIG. 7, with FIG. 8a showing a smaller portion of die 1. An insulating layer 90 is disposed on (e.g., directly on) first side 11.1 of SiC semiconductor body 11. In the illustrated example, insulating layer 90 includes a first oxide layer 91, a second oxide layer 92, and a third oxide layer 93, where first oxide layer 91 and second oxide layer 92 are undoped and third oxide layer 93 is doped. In particular, third oxide layer 93 may be a BPSG layer, second oxide layer 92 may be a TEOS (tetraethoxysilane) layer, and first oxide layer 91 may be a gate oxide layer or may function as a gate dielectric, for example, in the active area of ​​die 1.

[0067] Regardless of these details, the insulating layer 90 has an outer side edge 90.i on the first side 11.1 of the SiC semiconductor body 11, the outer side edge 90.i being offset inwardly from the outer side edge 11.1 of the SiC semiconductor body 11. Furthermore, a passivation system 40 including an inorganic passivation layer system 45 is disposed on the insulating layer 90, for example, directly on the insulating layer 90 or with an aluminum oxide layer (not shown here) therebetween. For example, as shown in FIGS. 1, 2, 4, 5, and 7, metallization can be disposed between the insulating layer 90 and the inorganic passivation layer system 45 in other portions of the die 1 (e.g., where gate and / or source runners are formed and / or at the side edges of load pads).

[0068] 8a, the inorganic passivation layer system 45 includes a first silicon nitride layer 45.1, an undoped silicon oxide layer 45.2 directly on the first silicon nitride layer 45.1, and a second silicon nitride layer 45.3 directly on the undoped silicon oxide layer 45.2. Regardless of the details of this layer stack, the inorganic passivation layer system 45 has outer side edges 45.i that reside on the insulating layer 90. In other words, the outer side edges 45.i of the inorganic passivation layer system 45 are offset inwardly from the outer side edges 90.i of the insulating layer 90, which in turn are offset inwardly from the side edges 11.i of the SiC semiconductor body 11.

[0069] In addition to the inorganic passivation layer system 45, the passivation system 40 of Figure 8a includes an organic layer 41 (e.g., an imide layer 42). In this embodiment, the organic layer 41 covers the outer side edges 45.i of the inorganic passivation layer system 45 and the outer side edges 90.i of the insulating layer 90. That is, the inorganic passivation layer system 45 also extends further outward than the insulating layer 90. The outer side edges 41.i of the organic layer 41 are disposed on the first side 11.1 of the SiC semiconductor body 11, for example, directly or with an aluminum oxide layer therebetween.

[0070] In the embodiment shown in Figure 8b, the insulating layer 90 and the inorganic passivation layer system 45 are arranged as discussed with reference to Figure 8a. However, this embodiment differs in that, with regard to the extension of the organic layer 41, the outer lateral edges 41.i of the organic layer 41 are not arranged outside the outer lateral edges 90.i of the insulating layer 90, but are laterally flush with the outer lateral edges 45.i of the inorganic passivation layer system 45. During production, the organic layer 41 can be used, for example, as an etching mask for structuring the inorganic passivation layer system 45 and can remain intact on the inorganic passivation layer system 45 in the already-fabricated die.

[0071] In the embodiment shown in Figure 8c, the organic layer 41 extends further outward than the inorganic passivation layer system 45, the latter being structured, for example, with another mask that is removed before the deposition of the organic layer 41. In contrast to Figure 8a, the outer lateral edges 41.i of the organic layer 41 are offset inward from the outer lateral edges 90.i of the insulating layer 90. The lateral edges 41.i are arranged laterally between the outer lateral edges 90.i of the insulating layer 90 and the outer lateral edges 45.i of the inorganic passivation layer system 45.

[0072] 8d shows a further embodiment, in which the passivation system 40 comprises an inorganic passivation layer system 45 but no organic layers. The outer side edges 45.i of the inorganic passivation layer system 45 are arranged on the insulating layer 90. See above.

[0073] Figure 8e shows another embodiment in which the passivation system 40 corresponds to the embodiment shown in Figure 8d. However, Figure 8e also shows an electric field reduction structure 360 ​​formed in the SiC semiconductor body 11. The electric field reduction structure 360 ​​includes a doping well 365 embedded with a plurality of laterally offset doping rings 366, such that the doping concentration decreases gradually towards the side edges 11.i of the SiC semiconductor body 11.

[0074] As mentioned above, the outer side edges 45.i of the inorganic passivation layer system 45 are disposed on the insulating layer 90, i.e., offset laterally inward from the outer side edges 90.i of the insulating layer 90. The inorganic passivation layer system 45 thus still vertically covers the field-reducing structure 360. In the illustrated embodiment, the outer side edges 45.i of the inorganic passivation layer system 45 are disposed further outward than the outer side edges 360.i of the field-generating structure 360.

[0075] The electric field reduction structure 360 ​​shown in Figure 8e can be implemented in any of the embodiments shown in Figures 8a to 8d, i.e., in combination with an organic layer 41 (e.g., an imide layer 42), as well as regardless of where the outer side edge 41.i of the organic layer 41 is located.

[0076] 9 summarizes some manufacturing steps in a flow diagram. After forming an insulating layer on a first side of a SiC semiconductor body (700), an inorganic passivation layer system 45 can be formed (710) (with metallization optionally formed therebetween). Forming the inorganic passivation layer system (710) can include depositing the inorganic passivation layer system on the first side of the SiC semiconductor body (711) and locally etching the inorganic passivation layer system (712) to define outer side edges.

[0077] FIG. 10 shows the semiconductor die 1 in vertical cross section. An insulating layer 90 is disposed on a first side 11.1 of the SiC semiconductor body 11. In the illustrated example, the insulating layer 90 includes a first oxide layer 91, which is an undoped oxide, for example, formed as a gate oxide layer. The insulating layer 90 further includes a third oxide layer 93, which may be a silicon glass layer (e.g., a USG, PSG, or BPSG layer). In contrast to the above embodiment, no second oxide layer is disposed between the first oxide layer 91 and the third oxide layer 93. In other words, the third oxide layer 93 is disposed, for example, directly on the first oxide layer 91.

[0078] The inorganic passivation layer system 45 shown in FIG. 10 includes a first silicon nitride layer 45.1 disposed on an adhesion promoter layer 245. The adhesion promoter layer 245 may also be a silicon nitride layer and have a thickness of, for example, 10-100 μm. The adhesion promoter layer 245 extends below and further laterally beside the first silicon nitride layer 45.1 to, for example, enhance adhesion of the organic layer 41 onto the insulating layer 90 and / or metallization 30. Apart from the first silicon nitride layer 45.1, the inorganic passivation layer system 45 shown in the figure does not include any additional layers.

[0079] The outer lateral edges 45.i of the inorganic passivation layer system 45 are disposed on the insulating layer 90. As discussed in detail for the embodiment of Fig. 8c, the outer lateral edges 41.i of the organic layer 41 are also disposed on the insulating layer 90, i.e., laterally disposed between the outer lateral edges 90.i of the insulating layer 90 and the outer lateral edges 45.i of the inorganic passivation layer system 45. In the example of Fig. 10, the first lateral distance d1 between the outer lateral edges 90.i of the insulating layer 90 and the outer lateral edges 41.i of the inorganic layer 41 is 1 to 20 µm (e.g., 3 to 10 µm), and the second lateral distance d2 between the outer lateral edges 41.i of the organic layer 41 and the outer lateral edges 45.i of the inorganic passivation layer system 45 is also 1 to 20 µm (e.g., 3 to 10 µm).

[0080] An electric field reduction structure 360 ​​is disposed in the SiC semiconductor body 11. The electric field reduction structure 360 ​​includes a doping well 365 embedded with a plurality of laterally stacked doping rings 366. In the illustrated embodiment, the doping well 365 and the doping rings 366 have a second doping type, which may be p-type.

[0081] The inorganic passivation layer system 45 covers the electric field reduction structure 360 ​​in a vertically upward direction. The outer lateral edges 360.i of the electric field reduction structure 360 ​​are arranged laterally inward of the outer lateral edges 45.i of the inorganic passivation layer system 45, and the inner lateral edges 360.ii of the electric field reduction structure are arranged laterally outward of the inner lateral edges 45.ii of the inorganic passivation layer system 45. In the illustrated embodiment, a third lateral distance d3 between the outer lateral edges 45.i and the outer lateral edges 360.i is 10 to 40 μm (e.g., 20 to 30 μm), and a fourth lateral distance d4 between the outer lateral edges 90.i and the outer lateral edges 360.i is 20 to 50 μm (e.g., 30 to 40 μm). The fifth lateral distance d5 between the inner side edge 45.ii and the inner side end 360.ii is 1 to 20 μm (e.g., 3 to 10 μm), and the sixth lateral distance d6 between the inner side edge 45.ii and the metallization 30 is 1 to 20 μm (e.g., 3 to 10 μm).

[0082] The metallization 30 shown in FIG. 10 includes a barrier layer system 130 having, for example, a first layer 131 and a second layer 132. The first layer 131 and / or the second layer 132 may each include at least one of Ti, TiN, Ta, TaN, TiW, W, or NiAl. An aluminum or copper layer 330, for example made of AlCu in the embodiment of FIG. 10, is disposed on the barrier layer system 130. A layer stack 340 including one or more layers (e.g., a first layer 341 and a second layer 342) is disposed on the aluminum or copper layer 330. The first layer 341 and / or the second layer 342 may each include at least one of Pd, NiP, Au, or Ag.

Claims

1. a silicon carbide (SiC) semiconductor body (11); an insulating layer (90) on a first side (11.1) of the SiC semiconductor body (11); a passivation system (40) on said insulating layer (90); Equipped with the passivation system (40) comprises an inorganic passivation layer system (45); the insulating layer (90) has outer side edges (90.i) on the SiC semiconductor body (11); The semiconductor die (1), wherein outer side edges (45.i) of the inorganic passivation layer system (45) are disposed on the insulating layer (90) and are offset laterally inward from the outer side edges (90.i) of the insulating layer (90).

2. 2. The semiconductor die (1) of claim 1, wherein the outer side edges (45.i) of the inorganic passivation layer system (45) are offset laterally inward from the outer side edges (90.i) of the insulating layer (90) by at least 1 μm and / or by at most 50 μm.

3. 2. The semiconductor die (1) of claim 1, wherein the outer side edges (90.i) of the insulating layer (90) are disposed between the side edges (11.i) of the SiC semiconductor body (11) and the active area (1a) of the semiconductor die (1).

4. The semiconductor die (1) of claim 1, wherein the insulating layer (90) comprises a silicon oxide layer (91, 92, 93).

5. The semiconductor die (1) of claim 4, wherein the insulating layer (90) comprises an undoped oxide layer (91, 92) and / or a doped oxide layer (93).

6. The semiconductor die (1) of claim 1, wherein the insulating layer (90) has a total thickness of at least 0.3 μm and / or at most 3 μm.

7. The semiconductor die (1) of claim 1, wherein the inorganic passivation layer system (45) comprises a silicon nitride layer (45.1, 45.3).

8. The semiconductor die (1) of claim 1, wherein the passivation system (40) comprises an organic layer (41) on the inorganic passivation layer system (45).

9. 9. The semiconductor die (1) of claim 8, wherein the outer side edges (45.i) of the inorganic passivation layer system (45) are covered by the organic layer (41), the organic layer (41) having outer side edges (41.i) on the insulating layer (90).

10. 10. The semiconductor die (1) of claim 9, wherein the outer side edges (45.i) of the inorganic passivation layer system (45) are laterally recessed by at least 1 μm below the organic layer (41).

11. 9. The semiconductor die (1) of claim 8, wherein the outer side edges (45.i) of the inorganic passivation layer system (45) and the outer side edges (90.i) of the insulating layer (90) are covered by the organic layer (41), the organic layer (41) having outer side edges (41.i) on the SiC semiconductor body (11).

12. 12. The semiconductor die (1) of claim 11, wherein the outer side edges (90.i) of the insulating layer (90) are laterally recessed below the organic layer by at least 1 μm.

13. 2. The semiconductor die (1) of claim 1, wherein an electric field reduction structure (360) is formed in the SiC semiconductor body (11), and the inorganic passivation layer system (45) covers the electric field reduction structure (360) in a vertically upward direction.

14. I) forming an insulating layer (90) on a first side (11.1) of a silicon carbide (SiC) semiconductor body (11), such that an outer side edge (90.i) of the insulating layer (90) is disposed on the SiC semiconductor body (11); II) forming (710) an inorganic passivation layer system (45) on said insulating layer (90), such that outer side edges (45.i) of said inorganic passivation layer (45) are disposed on said insulating layer (90) and are offset laterally inward from said outer side edges (90.1) of said insulating layer (90); A method for forming a semiconductor die (1), comprising:

15. Step II) is i) depositing (711) the inorganic passivation layer system (45) on the first side (11.1) of the SiC semiconductor body (11); ii) etching (712) said inorganic passivation layer system (45) to locally define said outer lateral edges (45.i) of said inorganic passivation layer system (45); 15. The method of claim 14, comprising:

16. 15. A method according to claim 14 for manufacturing a semiconductor die (1) according to any one of claims 1 to 13.

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