Semiconductor die and method for manufacturing the same

Abstract

To provide a semiconductor die and a method for manufacturing the same which reduce the risk of delamination of a passivation system.SOLUTION: A semiconductor die 1 comprises: a metallization 30 on a first side of a SiC semiconductor body 10 where a load pad 31 is formed; and a passivation system 40 having an opening above the load pad 31 on the metallization. In a cross-sectional plane perpendicular to a side edge 31.1 of the load pad 31, the passivation system 40 extends between an outer side position x1 located beside the load pad 31 and an inner side position x2 located inside the load pad 31. At an interruption position xi between the side edge 31.1 of the load pad 31 and the inner side position x2, the passivation system 40 has an interruption 60 in at least one of layers 41, 42 and 45.1-45.3.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor die that includes a semiconductor body. [Background technology]

[0002] In an embodiment of this application, the semiconductor body is made of, for example, silicon carbide (SiC), which has a relatively wide bandgap compared to silicon. This may be interesting, for example, for power semiconductor devices in high voltage and / or high current applications. Device structures having one or more load terminals, for example, transistor structures having source and drain terminals, may be formed within the semiconductor body. Metallization may be formed on the semiconductor body for wiring and contacting the device structures. Summary of the Invention

[0003] The embodiments of the present application are directed to advantageous semiconductor dies.

[0004] In one embodiment, a semiconductor die having a semiconductor body includes a metallization on which a load pad is formed. A passivation system is provided on the metallization, the passivation system having an opening in the load pad (e.g., for later contact in a package or other mounting structure). When viewed in vertical cross section, the passivation system may extend between an outer side location x1 beside the load pad (e.g., at or near a side edge of the die) and an inner side location x2 on the load pad. In one embodiment, an interruption may be provided at an interruption location x1 between the side edge of the load pad and the inner side location x2, e.g., when viewed in vertical cross section. i and provided in at least one layer of the passivation system above the load pad, in other words, the interruption is arranged laterally outside the opening in the passivation system, but may still be arranged above the load pad.

[0005] The interruptions can, for example, reduce stress propagation and, as a result, the risk of delamination, for example, of inorganic / hard passivation layers of the passivation system. Mechanical stresses can increase with increasing metal area, with particularly high stress values ​​occurring at the corners and / or side edges of the load pad. Interruptions located in the load pad, i.e., laterally located between the opening in the passivation system and the side edge of the load pad, can reduce the stress level in the passivation system there. The interruptions are, for example, smaller than the openings in the passivation system in the load pad. When viewed in a cross-sectional plane, the openings can have a width of, for example, at least 0.2 mm, 0.5 mm, or 1 mm (possible upper limits are several millimeters or even centimeters), while the interruptions can, for example, have a width of several micrometers or even tens of micrometers.

[0006] Further embodiments and features are provided in the claims and throughout this disclosure. Thus, individual features are disclosed independently of specific claim categories, and the disclosure relates not only to apparatus and device aspects, but also to method and use aspects. For example, if a die manufactured by a particular method is described, this also discloses the corresponding manufacturing process, and vice versa. Generally speaking, embodiments of the present application are directed to providing a disruption in at least one layer of a passivation system, for example, on a load pad.

[0007] A load pad formed in the metallization can be connected to a load terminal of a device structure in the semiconductor body. The load terminal connected to the load pad can be a first load terminal disposed on a first side of the semiconductor body, and the device structure can include a second load terminal, for example, on a vertically opposite second side of the semiconductor body. The device structure can be, for example, a FET having a source terminal / region and a drain terminal / region within the semiconductor body (e.g., a source region on a first side of the semiconductor body and a drain region on a second side thereof). In other words, the load pad in the metallization can be a source pad connected to the source terminal of the device structure.

[0008] In addition to the source and drain regions, the device may include a body region to which the gate electrode is capacitively coupled. Additionally, a drift region, for example, made of the same doping type as the drain region but less concentrated than the drain region, may be disposed between the body and drain regions. The source and drain regions, and the drift region, if present, may be made of a first doping type, and the body region may be made of a second doping type. In the illustrated embodiment, the first doping type is n-type and the second doping type is p-type.

[0009] When referring to a "vertical cross section," this may refer to a cross-sectional plane perpendicular to the side edge of the load pad. This "side edge" may be, for example, the outer edge of the top surface of the metallization. This top surface faces away from the semiconductor body. The inner side edge of the passivation system may be, for example, located laterally inward of the same top surface, i.e., side edge, of the metallization.

[0010] As viewed in a vertical top view, the interruptions may be, for example, slots (e.g., surrounding an angle with the side edge of the load pad or extending parallel to the side edge). The slots may extend partially or completely around the load pad. When viewed in a cross-sectional plane, at least one layer of the passivation system may provide a single interruption or multiple interruptions between the side edge of the load pad and an interior side location on the load pad. In other words, as viewed in a vertical top view, a single slot or multiple slots may be disposed between each side edge of the load pad and the opening.

[0011] A passivation system "on" a metallization is not necessarily disposed directly on the metallization, i.e., it is not necessarily directly adjacent to the metallization. In other words, an additional layer, such as an adhesion promoter layer, e.g., an aluminum oxide layer, may be disposed in between. The adhesion promoter layer can enhance the adhesion of the passivation system to the metallization, e.g., the adhesion of an inorganic passivation layer system or stack to a copper layer of the metallization.

[0012] The semiconductor body may include a semiconductor substrate, for example, in combination with one or more epitaxial layers thereon. Generally, the semiconductor body may be a silicon (Si) or gallium nitride (GaN) semiconductor body, although embodiments of the present application relate to semiconductor dies having silicon carbide (SiC) semiconductor bodies. This allows for high voltages during operation of the device or device structure, and therefore the aforementioned delamination issues may be particularly relevant.

[0013] In one embodiment, the passivation system comprises an inorganic passivation layer system and an organic layer on the inorganic passivation layer system. The "inorganic passivation layer system" can be a single inorganic layer or a stack of inorganic layers. Essentially, the "at least one layer" in which the interruptions are provided can be an organic layer, for example, a cured imide can induce certain mechanical stresses and the interruptions can allow stress relaxation in the imide.

[0014] However, in one embodiment, the interruptions are provided at least in the inorganic passivation layer system. In other words, the interruptions are provided in at least one inorganic layer of the inorganic passivation layer system, for example a single inorganic layer or a stack of inorganic layers. In general, the interruptions may be combined with interrupted organic / imide layers, and the interruptions, when viewed in a cross-sectional plane, intersect at least one inorganic layer and also the organic / imide layer.

[0015] However, in one embodiment, the organic layer is not interrupted at the interruption location (e.g., fills the interruption in the inorganic passivation layer system). In other words, the interruption only intersects with at least one inorganic layer (e.g., intersects with the inorganic layer stack) when viewed in a cross-sectional plane, and the organic layer covers the interruption. The organic layer (e.g., an imide layer) can fill the interruption when viewed in a cross-sectional plane, which can, for example, reduce the risk of residue at the interruption.

[0016] In one embodiment, the inorganic passivation layer system includes a silicon nitride layer and a silicon oxide layer. The silicon nitride layer can be disposed under or over the silicon oxide layer. In one embodiment, the silicon oxide layer is disposed on a first silicon nitride layer, and the second silicon nitride layer is disposed on the silicon oxide layer, e.g., the silicon oxide layer is disposed directly on the first silicon nitride layer, and / or the second silicon nitride layer is disposed directly on the silicon oxide layer. For example, the first silicon nitride layer may be thinner than the silicon oxide layer and / or the second silicon nitride layer. Regardless of these geometric details, the silicon oxide layer may be an undoped silicon oxide layer (e.g., undoped silicon glass (USG)).

[0017] As described above, a passivation system, which may include an inorganic passivation layer system and an organic layer thereon, is disposed on the metallization. An insulating layer may be disposed below the metallization, for example, between the metallization and the SiC semiconductor body. The insulating layer may function as an interlayer dielectric. For example, it may define a contact structure between the metallization and the semiconductor body. The insulating layer may include an oxide layer, for example, a borophosphosilicate glass (BPSG) layer. In other words, the insulating layer may include a doped oxide layer in addition to, for example, an undoped oxide layer. The insulating layer may have a total thickness, for example, of at least 0.5 μm and / or at most 3 μm.

[0018] In one embodiment, the organic layer is an imide layer. The imide can be, for example, a photosensitive polyimide precursor. The organic layer (e.g., an imide layer) can have a thickness of at least 1 μm, with further lower limits being, for example, at least 2 μm, 3 μm, 4 μm, or 5 μm. Possible upper limits can be, for example, 50 μm, 40 μm, 30 μm, or 25 μm or less.

[0019] In one embodiment, an adhesion promoter layer is disposed on the inorganic passivation layer system below the organic layer. In other words, the organic layer is not disposed directly on the inorganic passivation layer system, but is disposed with the adhesion promoter layer in between. The adhesion promoter layer may be disposed directly on the inorganic passivation layer system and / or the organic layer may be disposed directly on the adhesion promoter layer. In other words, the adhesion promoter layer may be disposed directly on the top inorganic layer of the passivation layer system, for example, a silicon nitride layer.

[0020] An adhesion promoter layer between the inorganic passivation layer system and the organic layer is also disclosed, regardless of the interruption in the passivation system. Thus, a semiconductor die is disclosed that includes a semiconductor body, a metallization on a first side of the semiconductor body, an inorganic passivation layer system on the metallization, an adhesion promoter layer on the inorganic passivation layer system, and an organic layer on the adhesion promoter layer. For possible embodiments and additional features, e.g., in terms of materials, thicknesses, etc., please refer to the entire disclosure.

[0021] An adhesion promoter layer on an inorganic passivation layer system can also provide uniform adhesion properties, for example, compared to the interface on a metallization that may be provided with an adhesion promoter layer. See details below. Whether or not combined with interruptions, the adhesion promoter layer can have a thickness of, for example, up to 30 nm, with further upper limits being, for example, 20 nm or 15 nm. A possible lower limit for the thickness of the adhesion promoter layer can be 5 nm.

[0022] In one embodiment, the adhesion promoter layer is an aluminum oxide layer. Optionally, the adhesion promoter layer may also be deposited on the metallization, where it may have, for example, a protective function. See details below.

[0023] In one embodiment, the interruptions in at least one layer of the passivation layer system are spaced laterally inwardly by at least 1 μm from the lateral edge of the load pad when viewed in the cross-sectional plane and / or spaced laterally outwardly by at least 1 μm from the inner lateral position at which the passivation system extends on the load pad. Further lower limits can be at least 2 μm or 3 μm, possible upper limits being, for example, up to 50 μm, 30 μm or 20 μm.

[0024] Generally, "outer" or "outermost" may refer to a lateral position relative to a respective lateral edge of the semiconductor body, i.e., may mean near or closest to this lateral edge. When viewed in vertical cross section, at least one layer in which an interruption is provided may have an outer portion laterally outside the interruption and an inner portion laterally inside the interruption (but still outside the active area). In other words, when viewed in vertical cross section, each layer (e.g., inorganic or organic layer) intersected by the interruption may extend on both sides of the interruption. Generally, elements discussed in terms of relative position are located, for example, on the same side of the active area of ​​the die, i.e., on the same lateral edge of the semiconductor body. Thus, similar structures may be located on other lateral edges of the semiconductor body, but this is not required. Generally, when a passivation system includes an inorganic passivation layer system and an organic layer, the outer lateral edges of the inorganic passivation layer system and the organic layer can be coplanar (at the outer lateral position) when viewed in vertical cross section, and / or the inner lateral edges of the inorganic passivation layer system and the organic layer can be coplanar (at the inner lateral position) when viewed in vertical cross section. Alternatively, when the layers of the passivation system extend further outward and / or inward, the outer lateral positions are located at the outer lateral edges of the further outwardly extending layers, and / or the inner lateral positions are located at the inner lateral edges of the further inwardly extending layers. For example, the outer lateral positions can be located at the outer lateral edges of the organic layers, and / or the inner lateral positions can be located at the inner lateral edges of the organic layers.

[0025] In one embodiment, the interruptions have a width of at least 0.5 μm, with further lower limits such as at least 1 μm, 2 μm, 3 μm, 4 μm, or 5 μm. Alternatively or additionally, possible upper limits can be up to 50 μm, 40 μm, or 30 μm. The width of the interruptions can be taken in the cross-sectional plane, for example, at the lower end or bottom of the interruptions (e.g., at the lowest inorganic layer where the interruptions intersect).

[0026] In one embodiment, the metallization in the area of ​​the load pad is stepped. Laterally outside the step, e.g., closer to the side edge of the semiconductor body or die, the load pad has a first thickness t1. Laterally inside the step, e.g., at a greater distance from the side edge of the semiconductor body or die, the load pad has a second thickness t2, where t1 is smaller than t2. In other words, the load pad has a smaller thickness t1 at the edge of the load pad and a larger thickness at the center of the load pad. The latter may be advantageous, for example, in terms of thermal management or mounting and bonding; the smaller thickness at the edge may, for example, reduce the topology of a passivation system extending over the load pad.

[0027] In one embodiment, the inner side position x2 along which the passivation system extends is located laterally outward of the step. In other words, the passivation system extends laterally over the load pad when viewed in the cross-sectional plane, but terminates at the edge region of the load pad, where the load pad has a thickness t1. When viewed in the cross-sectional plane, the passivation system covers the side edges of the load pad but not the step.

[0028] In one embodiment, an inorganic layer or inorganic layer stack covers the side of the step in the load pad. The inorganic layer can be a silicon nitride layer and / or a silicon oxide layer (or the inorganic layer stack can include a silicon nitride layer and / or a silicon oxide layer). Regardless of the specific material, covering the side can, for example, reduce the risk of under-etching or protect the interface between, for example, a first copper layer and a second copper layer, depending on, for example, the metallization stack or structure. See further details below. Even if the electric field resulting from the backside potential reaching the first side of the lateral edge of the semiconductor body is reduced in the edge termination area or structure, a residual electric field strength can remain on the load pad, which can be important, for example, from the perspective of migration or diffusion processes.

[0029] Side surfaces covered with an inorganic layer or layer stack are also disclosed, regardless of the interruption in the passivation system. In other words, a semiconductor die is disclosed, comprising: a semiconductor body; and a metallization on a first side of the semiconductor body, the metallization forming a load pad, the metallization in the area of ​​the load pad forming a step, the load pad having a first thickness t1 on a lateral outer side of the step and a second thickness t2 on a lateral inner side of the step, t1 being smaller than t2, and the inorganic layer or inorganic layer stack covering the side surfaces of the step. For possible embodiments and additional features, please see the entire disclosure.

[0030] In one embodiment, the metallization includes a copper layer. The copper layer may be part of a copper layer system that may include, for example, a sputter-deposited copper layer and one or more bath-deposited copper layers thereon. The "bath-deposited" copper layer may be, for example, an electrochemically deposited copper layer, i.e., an ECD layer (although electroless deposition is generally also conceivable). In one embodiment, the metallization includes a first bath-deposited copper layer and a second bath-deposited copper layer deposited on the first bath-deposited copper layer, where the second bath-deposited copper layer may be structured relative to the first bath-deposited copper layer. In other words, the second bath-deposited copper layer may form a step portion of the load pad.

[0031] To structure the second bath-deposited copper layer, a mask can be applied to the first bath-deposited copper layer before the second bath-deposited copper layer is deposited. Steps in the load pad can be formed at the side edges of the second bath-deposited copper layer, with the side edges of the second bath-deposited copper layer being displaced inward relative to the side edges of the first bath-deposited copper layer. Alternatively, however, one or more copper layers can be sputter-deposited regardless of whether a bath-deposited copper layer system is subsequently applied. In other words, one or more sputter-deposited copper layers can be combined with bath-deposited copper layers, or the entire copper metallization can be sputter-deposited. Also, in the case of sputter-deposited copper metallization, the upper copper layer can be structured relative to the underlying copper layer to form a step.

[0032] In summary, all copper layers of the metallization, whether sputter-deposited and / or bath-deposited, can have a thickness of, for example, at least 3 μm, with further lower limits of, for example, 5 μm or 7 μm. For example, the upper limit can be 25 μm or 20 μm. Beneath the bottom copper layer, e.g., a sputter-deposited copper layer, a barrier layer system of the metallization can be arranged (e.g., including a Ti / TiN layer).

[0033] In one embodiment, runners, e.g., conductor lines extending beside the load pads (e.g., parallel to the side edges of the load pads and / or the side edges of the die), are formed on the metallization beside the load pads. The runners may be gate runners electrically connected to one or more gate electrodes (e.g., corresponding gate electrodes of each device cell in the active area). Alternatively, the runners may be source runners, e.g., electrically connected to corresponding source terminals of each device cell in the active area. In one embodiment, gate runners and source runners are formed beside the load pads. For example, the source runners are laterally outside the gate runners.

[0034] In one embodiment, a method for manufacturing a semiconductor die includes: I) forming a device structure having a load terminal within a semiconductor body; II) forming a metallization having a load pad on a first side of the semiconductor body; III) forming a passivation system on the metallization, the passivation system having an opening on the load pad, and an interruption at an interruption position x between a side edge of the load pad and the opening; i forming a passivation system in at least one layer; Includes.

[0035] For possible embodiments and details, please refer to the entire disclosure.

[0036] In one embodiment, step III) comprises: i) forming an inorganic passivation layer system; ii) forming an organic layer (e.g., an imide layer) on the inorganic passivation layer system.

[0037] In one embodiment, the interruption comprises: - providing a mask on the inorganic passivation layer system after step i), - etching the interruptions defined by the mask into the inorganic passivation layer system; The inorganic passivation layer system is formed by

[0038] The mask can be structured to define interruptions, for example, to have openings that are etched into the underlying inorganic passivation layer system. In addition to defining one or more interruptions, the mask can define inner and / or outer lateral edges of the inorganic passivation layer system, for example, when viewed in a cross-sectional plane. Regardless of these details, the mask that defines the interruptions in the etching step can be removed before forming the organic layer (e.g., an imide layer) in step ii).

[0039] Alternatively, in embodiments relating to a passivation system without interruptions, an organic layer (e.g., an imide layer) of the passivation system can be used, for example, as an etching mask to define the inner and / or outer lateral edges of the inorganic passivation layer system and can remain on the inorganic passivation layer system after the etching step.

[0040] In one embodiment, a method for manufacturing a semiconductor die includes: a) forming a metallization having a load pad on a first side of a semiconductor body; b) forming an inorganic passivation layer system on the metallization, the inorganic passivation layer system having openings over the load pads; c) after step b), forming a protective layer within the opening of the load pad.

[0041] For additional embodiments and features, see the entire disclosure.

[0042] The protective layer can have a thickness of up to 30 nm, with further upper limits being, for example, 20 nm or 15 nm. Providing a relatively thin protective layer can have advantages, for example, in subsequent attachment or bonding processes, for example, allowing contact formation to wires or clips (even in the case of an electrically insulating protective layer). A possible lower limit for the thickness of the protective layer can be, for example, 3 nm or 5 nm.

[0043] The protective layer can reduce or prevent dissolution and washing away of atoms or particles of the metallization, e.g., copper, in later manufacturing steps, e.g., during the back end of the line assembly (e.g., when rinsing with solvents or acids (e.g., CHO)). More generally, the protective layer can provide protection against process-induced oxidation, e.g., in later manufacturing steps. Depositing a protective layer after the inorganic passivation layer system has been deposited and structured (e.g., locally etched from the load pad), e.g., in the case of the stepped load pads described above, can also ensure a homogenous protective layer over the openings of the load pads.

[0044] Furthermore, the same layer that serves as a protective layer in the opening of the load pad may also serve as an adhesion promoter layer on the inorganic passivation layer system below the organic layer. See above for details. In one embodiment, the protective layer formed in step c) is an aluminum oxide layer. In any case, the protective layer may be deposited in the opening of the load pad and, in one embodiment, is simultaneously deposited on the inorganic passivation layer system.

[0045] In one embodiment, before forming the protective layer in step c), a temporary protective layer present on the metallization is removed from the load pad in the opening. The temporary protective layer may also be an aluminum oxide layer, e.g., having a thickness of 3 nm to 30 nm. It may remain on the metallization beside the opening, i.e., under the inorganic passivation layer system, e.g., to improve adhesion of the inorganic passivation layer system to the metallization.

[0046] Any of the above methods or method steps can be applied to the fabrication of the above semiconductor die, for example, with or without interruptions in the passivation system, with or without steps and step coverage in the load pad, and / or with or without an adhesion promoter layer on the inorganic passivation layer system below the organic layer.

[0047] In the following, the semiconductor die and the manufacturing method will be described in further detail by exemplary embodiments, in which the individual features can also be associated in different combinations. [Brief explanation of the drawings]

[0048] [Figure 1] 1 shows a cross-sectional view of a semiconductor die comprising a semiconductor body, a metallization, and a passivation system on the metallization. [Figure 2] 1 shows a more detailed view of the passivation system on the load pads in the metallization. [Figure 3] 2 shows a schematic cross section of a device formed in the active area of ​​a die. [Figure 4a] 1 illustrates steps for manufacturing a semiconductor die with a passivation system that includes an inorganic passivation layer system and an organic layer. [Figure 4b] 4 illustrates another step in manufacturing a semiconductor die with a passivation system that includes an inorganic passivation layer system and an organic layer. [Figure 4c]4 illustrates another step in manufacturing a semiconductor die with a passivation system that includes an inorganic passivation layer system and an organic layer. [Figure 4d] 4 illustrates another step in manufacturing a semiconductor die with a passivation system that includes an inorganic passivation layer system and an organic layer. [Figure 4e] 4 illustrates another step in manufacturing a semiconductor die with a passivation system that includes an inorganic passivation layer system and an organic layer. [Figure 5] Figures a and b show a flow diagram summarizing some of the manufacturing steps. DETAILED DESCRIPTION OF THE INVENTION

[0049] 1 illustrates a vertical cross section of a portion of a semiconductor die 1. The semiconductor die 1 comprises a semiconductor body 10, which in the illustrated embodiment is a silicon carbide (SIC) semiconductor body 11. An insulating layer 90 is disposed on a first side 10.1 of the semiconductor body 10. Furthermore, a metallization 30 including a barrier layer system 130 is formed on the semiconductor body 10. Disposed on the barrier layer system 130 is a copper layer system 230, which in the illustrated embodiment includes a sputter-deposited copper layer 231 and a bath-deposited copper layer system 235 having a first bath-deposited copper layer 235a and a second bath-deposited copper layer 235b.

[0050] Specifically, the cross-sectional view of FIG. 1 is located at a side edge 1.1 of die 1, with an inactive area 1b laterally disposed between side edge 1.1 of die 1 and active area 1a, shown on the right side of FIG. 1. In active area 1a, a transistor device cell may be disposed (see details below). In active area 1a, load pads 31, such as source pads connected to source terminals of devices or device cells, may be formed within metallization 30. In inactive area 1b, gate runners 32 and / or source runners 33 may be formed within metallization 30, each extending along active area 1a.

[0051] A passivation system 40 is disposed on the metallization 30. In the illustrated embodiment, the passivation system 40 comprises an inorganic passivation layer system 45 and an organic layer 41 (e.g., an imide layer 42) of the inorganic passivation layer system 45. As will be discussed in more detail with reference to Figure 4e, an additional adhesion promoter layer may be disposed in between (not shown here).

[0052] The inorganic passivation layer system 45 shown in the figure includes a first silicon nitride layer 45.1, an undoped silicon oxide layer 45.2 directly on the first silicon nitride layer 45.1, and a second silicon nitride layer 45.3 directly on the undoped silicon oxide layer 45.2. The passivation system 40 covers the gate runners 32 and the source runners 33, and also covers an insulating layer 90 made of a doped oxide (e.g., borophosphosilicate glass (BPSG)). In the illustrated embodiment, an aluminum oxide layer 340 (shown only as a line in FIG. 1) is disposed below the inorganic passivation layer system 40, i.e., above the insulating layer 90 and also above the metallization 30.

[0053] The cross-sectional plane of Figure 1 lies perpendicular to the side edge 31.1 of the load pad 31. The passivation system 40 extends between an outer side position x1 beside the load pad and an inner side position x2 located on the load pad 31 (i.e. covering the side edge 31.1 of the load pad 31). In the illustrated embodiment, an interruption 60 is provided in at least one layer 41, 42, 45.1-45.3 of the passivation system 40. In this case, the interruption 60 completely intersects the inorganic passivation layer system 45. The interruption 60 extends laterally between the side edge 31.1 of the load pad 31 and the inner side position x2 at the interruption position x1. i will be placed in.

[0054] The organic layer 41 (for example, the imide layer 42) is cut off at the position x i2. At the bottom of the interruption 60 in the inorganic passivation layer system 45, the organic layer 41 or the imide layer 42 can be located directly on the aluminum oxide layer 340 covering the metallization 30. In the illustrated embodiment, one single interruption 60 is provided in the passivation system 40, i.e., in the inorganic passivation layer system 45, but in practice several interruptions may be provided, offset to one another, between the side edge 31.1 and the inner side position x2 of the load pad 31.

[0055] The lateral distance d between the lateral edge 31.1 of the load pad 31 and the inner lateral position x2 can be, for example, at least 100 μm or 200 μm (the upper limit can be a few millimeters, or for example, up to 1 mm). In the detailed view of FIG. 2, reference is made to the distance d between the lateral edge 31.1 of the load pad 31 and the inner lateral position x2. The interruption position x1 is located within this distance d. For illustration purposes, in absolute value, the distance d can be several hundred micrometers, and the interruption 60 can have a width w of a few micrometers or tens of micrometers.

[0056] A step 70 is formed in the load pad 31. Laterally outside the step 70, the load pad 31 has a first thickness t1, and laterally inside the step 70, a greater thickness t2. In the illustrated embodiment, the step 70 is formed by a second bath-deposited copper layer 235b that is structured relative to the first bath-deposited copper layer 235a, i.e., offset inward (away from the side edge 1.1 of the die 1). The passivation system 40 extends over the load pad 31 but terminates on the first bath-deposited copper layer 235a, with an inner side position x2 located laterally outside the step 70.

[0057] In the illustrated embodiment, the side surface 71 of the step portion faces laterally outward and is covered with inorganic layers 81.1, 81.2 (e.g., a stack 80 of inorganic layers 81.1, 81.2). The inorganic layers 81.1, 81.2, or inorganic layer stack 80, may be disposed directly on the side surface 71, or, as shown in FIG. 2, may be disposed directly on the metallization 30 and on an aluminum oxide layer 340 (represented only as lines) that also extends on the side surface 71. The first inorganic layer 81.1 disposed directly on the aluminum oxide layer 340 may be a silicon nitride layer, and a second inorganic layer 81.2, which is a silicon oxide layer (e.g., USG), is disposed on the first inorganic layer 81.1.

[0058] 3 shows a possible device 200 and device structure 20 formed within the active area 1a of die 1, e.g., beneath load pad 31 (see FIG. 1 for comparison). In a semiconductor body 10, e.g., a SiC semiconductor body 11, a load terminal 21 is formed on a first side 10.1, which in the illustrated embodiment is a source region 22. On a perpendicularly opposite second side 10.2, a drain region 27 is located, a body region 23 is disposed beneath the source region 22, and a drift region 24 is located between the body region 23 and the drain region 27.

[0059] A gate region 25, including a gate electrode 25.1 and a gate dielectric 25.2 that capacitively couples the gate electrode 25.1 to the body region 23, is disposed within the trench 26. Through a voltage applied to the gate electrode 25.1, channel formation within the body region 23 and the resulting current flow between the source region 22 and the drain region 27 can be controlled. The device 200 may include multiple device cells 201 connected in parallel.

[0060] 4a-4e illustrate several steps for manufacturing a semiconductor die having a semiconductor body, a metallization, and a passivation system. In FIG. 4a, an insulating layer 90 has already been deposited on a first side 10.1 of the semiconductor body 10, forming the metallization 30. On top of the metallization 30, an aluminum oxide layer 230 has been deposited (shown only as lines), followed by a silicon nitride layer 45.1 and a silicon oxide layer 45.2.

[0061] As shown in FIG. 4b, the silicon oxide layer 45.2 may be etched (not shown in detail here) before being covered with a second silicon nitride layer 45.3. In FIG. 4b, the inorganic passivation layer system 45 is deposited but not yet structured. Therefore, a mask 145 is provided on the inorganic passivation layer system 45. The mask 145 has openings 160 that define where interruptions in the inorganic passivation layer system 45 will be etched. Furthermore, the mask 145 defines the inner and outer side edges of the inorganic passivation layer system 45, i.e., where the inorganic passivation layer system 45 will open over the load pad 31.

[0062] 4c shows the inorganic passivation layer system 45 after the etching step, i.e. after the interruption 60 has been etched into the inorganic passivation layer system 45. The mask has already been removed. For example, applying an anisotropic etching step can leave inorganic layers 81.1, 81.2 on the side surfaces 71 of the step 80.

[0063] 4d shows the die 1 after an organic layer 41 (e.g., an imide layer 42) has been deposited, structured, and cured. The organic layer 41 or the imide layer 42 defines an opening 140 for the load pad 31.

[0064] FIG. 4e shows an additional process variant that can be applied before the deposition of the organic layer 41 or the imide layer 42, i.e., before the situation shown in FIG. 4d. As shown in FIG. 4e, an adhesion promoter layer 350, e.g., an aluminum oxide layer 351, can be deposited on the inorganic passivation layer system 45. Above the load pad 31, the inorganic passivation layer system 45 has an opening 341. Therefore, before the deposition of the adhesion promoter layer 350, the aluminum oxide layer 340, e.g., a temporary protective layer 345, can be removed. Regardless of whether the aluminum oxide layer 340 has been removed in the opening 341, the adhesion promoter layer 350, e.g., the aluminum oxide layer 351, can function as a protective layer 355 there. In other words, the same layer can function as an adhesion promoter on the inorganic passivation layer system 45 and as a protective layer where the passivation is opened to expose the metallization.

[0065] Figure 5a summarizes several manufacturing steps in a flow diagram. After forming device structures in a semiconductor body (400), metallization can be formed on the semiconductor body (401). For example, a passivation system can be formed on the metallization (402) by forming an inorganic passivation system (402.1), providing a mask on the inorganic passivation layer system (402.2), etching interruptions in the inorganic passivation layer system (402.3), and then forming an organic layer on the inorganic passivation layer system (402.4).

[0066] Figure 5b summarizes some manufacturing steps in a flow diagram. After forming a metallization on the semiconductor body (401) and forming an inorganic passivation layer system on the metallization (402.1), a protective layer can be formed in the openings in the inorganic passivation layer system on the load pads (411). Optionally, the temporary protective layer can be removed beforehand (410).

Claims

1. a semiconductor body (10) having a device structure (20) formed therein, the device structure having a load terminal (21); a metallization (30) on a first side (10.1) of the semiconductor body (10), the metallization (30) having a load pad (31) formed thereon; a passivation system (40) on said metallization (30), said passivation system (40) having openings (140) on said load pads (31); Equipped with The passivation system (40) is arranged at an outer side position x lateral to the side of the load pad (31) when viewed in a cross-sectional plane perpendicular to the side edge (31.1) of the load pad (31). １ and an inner side position x on the load pad (31) ２ and extending between The side edge (31.1) of the load pad (31) and the inner side position x ２ Interruption position x between ｉ and wherein at least one layer (41, 42, 45.1 to 45.3) of said passivation system (40) is provided with an interruption (60).

2. The semiconductor die (1) of claim 1, wherein the passivation system (40) comprises an inorganic passivation layer system (45) and an organic layer (41) on the inorganic passivation layer system (45).

3. The semiconductor die (1) of claim 2, wherein the interruptions (60) are provided in at least the inorganic passivation layer system (45).

4. The organic layer (41) is ｉ 4. The semiconductor die (1) of claim 3, wherein the inorganic passivation layer system (45) is not interrupted by a metal oxide, filling the interruptions (60) in the inorganic passivation layer system (45).

5. The semiconductor die (1) of claim 2, wherein the interruptions (60) are provided in at least the organic layer (41).

6. The semiconductor die (1) according to claim 2, wherein the inorganic passivation layer system (45) comprises a silicon nitride layer (45.1, 45.3) and a silicon oxide layer (45.2).

7. The semiconductor die (1) of claim 2, wherein the organic layer (41) is an imide layer (42).

8. The semiconductor die (1) of claim 2, wherein an adhesion promoter layer (350) is disposed on the inorganic passivation layer system (45) and below the organic layer (41).

9. The semiconductor die (1) of claim 8, wherein the adhesion promoter layer (350) is made of aluminum oxide and / or has a thickness of at most 30 nm.

10. The interruptions (60) are located at the side edges (31.1) and at the inner side positions x of the load pad (31), respectively. ２ and the distance d is at least 10% of the distance between the side edge (31.1) of the load pad (30) and the inner side position x ２ 2. The semiconductor die (1) of claim 1, wherein the cross-sectional plane is taken between

11. The semiconductor die (1) according to claim 1, wherein the interruptions (60) have a width of at least 0.5 μm and / or at most 50 μm.

12. A step (70) is formed in the metallization (30) in the area of ​​the load pad (31), and the load pad (31) has a first thickness t laterally outside the step (70). １ and a second thickness t ２ and t １ is ２ The semiconductor die (1) of claim 1, wherein the die (1) is smaller than

13. The inner side position x along which the passivation system (40) extends ２ is the thickness t １ 13. The semiconductor die (1) of claim 12, wherein the die (1) is disposed laterally outward of the step portion (70) having the

14. The semiconductor die (1) according to claim 12, wherein an inorganic layer (81.1, 81.2) or layer stack (80) covers the side surfaces (71) of the step portion (70).

15. The semiconductor die (1) of claim 1, wherein the metallization (30) comprises a copper layer (231, 235a, 235b).

16. 2. The semiconductor die (1) of claim 1, wherein runners (32, 33) are formed in the metallization (30) on the sides of the load pads (31), and the passivation system (40) is uninterrupted above the runners (32, 33).

17. I) forming a device structure (20) having a load terminal (21) in a semiconductor body (10) (400); II) forming (401) a metallization (30) having a load pad (31) on a first side (10.1) of said semiconductor body (10); III) forming (402) a passivation system (40) on the metallization (30), the passivation system (40) having an opening (140) on the load pad (31), and an interruption (60) at a position x between the side edge (31.1) of the load pad (31) and the opening (140); ｉ forming (402), wherein at least one layer of the passivation system (40) is provided; A method for manufacturing a semiconductor die (1), comprising:

18. Step III) i) forming (402.1) an inorganic passivation layer system (45); ii) forming (402.4) an organic layer (41) on said inorganic passivation layer system (45); 18. The method of claim 17, comprising:

19. The interrupted portion (60) is - after step iii), providing (402.2) a mask (145) on said inorganic passivation layer system (45) with openings (160) defining said interruptions (60), - etching (402.3) said interruptions (60) defined by said mask (145) into said inorganic passivation layer system (45); 20. The method of claim 18, wherein the inorganic passivation layer system (45) is formed by

20. 20. The method of claim 19, wherein after etching the interruptions (60) the mask (145) is removed before forming the organic layer (41) in step ii).

21. a) forming (401) a metallization (30) having a load pad (31) on a first side (10.1) of a semiconductor body (10); b) forming (402.1) an inorganic passivation layer system (45) on said metallization (30), said inorganic passivation layer system (45) having openings (341) above said load pads (31); c) after step b), forming a protective layer (355) in said opening (341) on said load pad (31) with a thickness of up to 30 nm; A method for manufacturing a semiconductor die (1), comprising:

22. 22. The method of claim 21, wherein the protective layer (355) is an aluminum oxide layer.

23. 22. The method of claim 21, wherein a temporary protective layer (345) present on the metallization (30) is removed (410) from the load pad (31) in the opening (140) before step c).

24. 18. A method according to claim 17 for manufacturing a semiconductor die (1) according to any one of claims 1 to 16.

25. 22. A method according to claim 21 for manufacturing a semiconductor die (1) according to any one of claims 1 to 16.

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