Multilayer printed wiring board and method of manufacturing multilayer printed wiring board

Abstract

To provide a multilayer printed wiring board capable of improving the adhesive strength between a conductor circuit and a resin insulation layer and also capable of preventing a decrease in insulation resistance between adjacent conductor circuits.SOLUTION: A multilayer printed wiring board includes: a first resin insulation layer; a first conductor circuit which is formed on the first resin insulation layer; a second resin insulation layer which is formed on the first resin insulation layer and the first conductor circuit and in which an opening reaching the first conductor circuit is formed; a second conductor circuit which is formed on the second resin insulation layer; and a via conductor which is formed in the opening to connect the first conductor circuit and the second conductor circuit. A metal layer containing Al is formed on upper faces of the first and second conductor circuits and on an upper face of the via conductor, while the metal layer is not formed on side faces of the first and second conductor circuits and on a side face of the via conductor.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] The present invention relates to a multilayer printed wiring board and a method for manufacturing the same, and more particularly to a multilayer printed wiring board having a metal film for adhering a conductor circuit to a resin insulating layer, the metal film being formed only on the top surface of the conductor layer, and a method for manufacturing the same. [Background technology]

[0002] Multilayer printed wiring boards have been proposed in which conductor circuits and interlayer resin insulation layers are alternately stacked. The conductor circuits, made of copper or other materials, that make up such multilayer printed wiring boards have poor adhesion to the interlayer resin insulation layers. In response to this, multilayer printed wiring boards have been proposed in which a predetermined metal film is formed on the surface of the conductor circuit, a coating made of a coupling agent is formed on this metal film, and at least a portion of the bottom of the via conductor is directly connected to the conductor circuit. Such multilayer printed wiring boards are characterized by being able to maintain the electrical properties of the conductor circuit and the via conductor while ensuring adhesion between the conductor circuit and the interlayer resin insulation layer.

[0003] Fig. 3 is a schematic cross-sectional view showing an example of an embodiment of such a multilayer printed wiring board. As shown in Fig. 3, the multilayer printed wiring board includes a conductor circuit 114 on an interlayer resin insulating layer 112a and a via conductor 117 that connects the conductor circuit 114 on the interlayer insulating layer 112a to a component mounting pad 107. Furthermore, a conductor circuit coating layer 115 having a coating made of a metal layer containing Sn and a silane coupling agent is formed on the surface of the via conductor 117 of the multilayer printed wiring board. Here, the conductor circuit coating layer 115 is formed on the side surface and upper surface of the via conductor 117 so as to cover the surface of the via conductor 117 (Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 5033192 specification Summary of the Invention [Problem to be solved by the invention]

[0005] In the technology disclosed in Patent Document 1, interlayer resin insulating layer 112a is exposed when conductor circuit coating layer 115 having a metal layer containing Sn and a coating made of a silane coupling agent is formed on the surface of via conductor 117. Therefore, there is a possibility that the metal layer constituting conductor circuit coating layer 115 may precipitate on interlayer resin insulating layer 112a where conductor circuit 114 is exposed. As a result, a multilayer printed wiring board in which a metal layer constituting the conductor circuit coating layer 115 is deposited on the interlayer resin insulation layer 112a has the problem that the insulation resistance between adjacent conductor circuits 114 decreases due to the influence of the metal layer. Furthermore, in the multilayer printed wiring board disclosed in Patent Document 1, conductor circuit coating layer 115 cannot follow deformation due to expansion of interlayer resin insulation layer 112a. As a result, this multilayer printed wiring board has the problem that conductor circuit 114 is easily peeled off from interlayer resin insulation layer 112a. From this technical perspective, the technical object of the present invention is to provide a multilayer printed wiring board that can improve the adhesive strength between the conductor circuit and the resin insulation layer and prevent a decrease in insulation resistance between adjacent conductor circuits. [Means for solving the problem]

[0006] A multilayer printed wiring board according to the present invention is a multilayer printed wiring board comprising: a first resin insulating layer; a first conductive circuit formed on the first resin insulating layer; a second resin insulating layer formed on the first resin insulating layer and the first conductive circuit, the second resin insulating layer having an opening reaching the first conductive circuit; a second conductive circuit formed on the second resin insulating layer; and a via conductor formed in the opening for connecting the first conductive circuit and the second conductive circuit, A metal layer containing Al is formed only on the top surface of the first conductive circuit, the top surface of the second conductive circuit, and the top surface of the via conductor, and the metal layer is not formed on the side surface of the first conductive circuit, the side surface of the second conductive circuit, or the side surface of the via conductor.

[0007] a first resin insulating layer; a first conductive circuit on the first resin insulating layer; forming a plurality of plating resists on the first resin insulating layer that are exposed after the first conductive circuit is formed, thereby forming a plating resist recess; forming a metal layer containing Al only on the upper surface of the first conductive circuit that is exposed from the plating resist recess; removing the plating resist from the first resin insulating layer after forming the metal layer containing Al; forming a second resin insulating layer that covers the first resin insulating layer, the first conductive circuit, and the metal layer containing Al; forming an opening that penetrates the second resin insulating layer; removing the metal layer containing Al that is exposed from the opening; forming a second conductive circuit on the second resin insulating layer; and forming a via conductor in the opening to connect the first conductive circuit and the second conductive circuit. [Brief explanation of the drawings]

[0008] [Figure 1A] 1 is a cross-sectional view illustrating one embodiment of a multilayer printed wiring board that is a target of a method for manufacturing a multilayer printed wiring board according to the present invention. [Figure 1B] 1 is a partially enlarged cross-sectional view illustrating one embodiment of a multilayer printed wiring board that is a target of a method for manufacturing a multilayer printed wiring board according to the present invention. [Figure 2A] 1A to 1C are cross-sectional views illustrating an embodiment of a method for manufacturing a multilayer printed wiring board according to the present invention. [Figure 2B] 1A to 1C are cross-sectional views illustrating an embodiment of a method for manufacturing a multilayer printed wiring board according to the present invention. [Figure 2C] 1A to 1C are cross-sectional views illustrating an embodiment of a method for manufacturing a multilayer printed wiring board according to the present invention [Figure 2D] 1A to 1C are cross-sectional views illustrating an embodiment of a method for manufacturing a multilayer printed wiring board according to the present invention [Figure 2E] 1A to 1C are cross-sectional views illustrating an embodiment of a method for manufacturing a multilayer printed wiring board according to the present invention [Figure 2F] 1A to 1C are cross-sectional views illustrating an embodiment of a method for manufacturing a multilayer printed wiring board according to the present invention [Figure 2G] 1A to 1C are cross-sectional views illustrating an embodiment of a method for manufacturing a multilayer printed wiring board according to the present invention [Figure 2H] 1A to 1C are cross-sectional views illustrating an embodiment of a method for manufacturing a multilayer printed wiring board according to the present invention [Figure 2I] 1A to 1C are cross-sectional views illustrating an embodiment of a method for manufacturing a multilayer printed wiring board according to the present invention [Figure 2J] 1A to 1C are cross-sectional views illustrating an embodiment of a method for manufacturing a multilayer printed wiring board according to the present invention [Figure 2K] 1A to 1C are cross-sectional views illustrating an embodiment of a method for manufacturing a multilayer printed wiring board according to the present invention [Figure 2L] 1A to 1C are cross-sectional views illustrating an embodiment of a method for manufacturing a multilayer printed wiring board according to the present invention [Figure 2M] 1A to 1C are cross-sectional views illustrating an embodiment of a method for manufacturing a multilayer printed wiring board according to the present invention [Figure 2N] 1A to 1C are cross-sectional views illustrating an embodiment of a method for manufacturing a multilayer printed wiring board according to the present invention [Figure 2O] 1A to 1C are cross-sectional views illustrating an embodiment of a method for manufacturing a multilayer printed wiring board according to the present invention [Figure 2P] 1A to 1C are cross-sectional views illustrating an embodiment of a method for manufacturing a multilayer printed wiring board according to the present invention [Figure 2Q] 1A to 1C are cross-sectional views illustrating an embodiment of a method for manufacturing a multilayer printed wiring board according to the present invention [Figure 2R] 1A to 1C are cross-sectional views illustrating an embodiment of a method for manufacturing a multilayer printed wiring board according to the present invention. [Figure 2S] 1A to 1C are cross-sectional views illustrating an embodiment of a method for manufacturing a multilayer printed wiring board according to the present invention. [Figure 2T] 1A to 1C are cross-sectional views illustrating an embodiment of a method for manufacturing a multilayer printed wiring board according to the present invention. [Figure 3] 1 is a schematic cross-sectional view illustrating an example of a multilayer printed wiring board manufactured by a conventional method for manufacturing a multilayer printed wiring board. DETAILED DESCRIPTION OF THE INVENTION

[0009] <Multilayer printed wiring boards to be manufactured according to the present invention> An embodiment of a multilayer printed wiring board according to the present invention will be described with reference to the drawings. In the example shown in Figures 1 and 2, the dimensions of each component, particularly the height dimension, are shown as dimensions different from the actual dimensions in order to better understand the features of the present invention.

[0010] Fig. 1 is a cross-sectional view illustrating one embodiment of a multilayer printed wiring board that is the subject of a method for manufacturing a multilayer printed wiring board according to the present invention. Fig. 1A is a cross-sectional view schematically showing a multilayer printed wiring board. In Fig. 1A, multilayer printed wiring board 10 may be a core-equipped multilayer printed wiring board 10 formed by alternately laminating conductor circuits 12 and resin insulating layers 13 on one or both sides of core substrate 11.

[0011] When conductor circuits 12 are formed on both sides of core substrate 11, conductor circuits 12 that face each other across core substrate 11 may be electrically connected via through-hole conductors 14. Resin filler layer 15 is formed inside through-hole conductor 14. Then, through-hole conductor circuits 16 are formed to cover resin filler layer 15. Note that multilayer printed wiring board 10 may be a coreless multilayer printed wiring board 10 obtained by alternately laminating conductor circuits 12 and resin insulating layers 13 on a support plate (not shown) instead of core substrate 11, and then removing the support plate. In multilayer printed wiring board 10, the total number of resin insulating layers 13 formed on both sides of core substrate 11 may be the same or different.

[0012] In multilayer printed wiring board 10, two conductor circuits 12 formed on either side of resin insulating layer 13 are electrically connected through via conductors 17. Via conductors 17 are formed in openings 13X in resin insulating layer 13 formed on the upper surface of conductor circuits 12. A solder resist layer 18 is formed on the outermost layer of multilayer printed wiring board 10. Solder resist openings 18X are formed in solder resist layer 18, reaching the upper surfaces of conductor circuits 12 located on the outermost layer. Solder bumps 19 are formed via first protective layer 19A and second protective layer 19B on the upper surface of conductor circuit 12 located on the outermost layer, which is exposed at the bottom of solder resist openings 18X.

[0013] 1B is a partially enlarged cross-sectional view showing region R of multilayer printed wiring board 10. In FIG. 1B, first conductive circuit 12A formed on first resin insulating layer 13A, which is resin insulating layer 13 located in an inner layer of multilayer printed wiring board 10, may be formed from electroless copper-plated film 12A1 and electrolytic copper-plated film 12A2 formed on the upper surface of electroless copper-plated film 12A1. Furthermore, metal layer M is formed on part of the upper surface of electrolytic copper plating film (12A2) that constitutes first conductive circuit (12A) to improve adhesion between first conductive circuit (12A) and second resin insulating layer (13B) that is laminated on first conductive circuit (12A).

[0014] Meanwhile, via conductors 17B are formed on another portion of the upper surface of first conductive circuit 12A formed on first resin insulating layer 13A, without forming metal layer M. Via conductors 17B formed on first resin insulating layer 13A may be formed from electroless copper plating film 17B1 and electrolytic copper plating film 17B2 formed on the upper surface of electroless copper plating film 17B1. The cross-sectional shape of the via conductor 17B is tapered, and the side of the via conductor 17B where the width is narrowed due to the tapered shape is the bottom of the via conductor 17B. The bottoms of via conductors (17B) are directly connected to electrolytic copper-plated film (12A2) that constitutes first conductive circuit (12A). As a result, first conductive circuit (12A) of multilayer printed wiring board (10) is directly electrically connected to second conductive circuit (12B) through the bottoms of via conductors (17B). This results in excellent adhesion between first conductive circuit (12A) and via conductors (17B), reducing the electrical resistance between first conductive circuit (12A) and via conductors (17B), and thus providing multilayer printed wiring board (10) with excellent electrical properties.

[0015] In this way, metal layer M is formed on the upper surface of first conductive circuit 12A that is not electrically connected to the bottom of via conductor 17B, in order to improve the adhesive strength between first conductive circuit 12A and second resin insulating layer 13B laminated on first conductive circuit 12A. In contrast, metal layer M is not formed on portions of the top surface of first conductive circuits 12A that are electrically and directly connected to the bottoms of via conductors 17B.

[0016] That is, multilayer printed wiring board 10 according to the present invention is characterized in that metal layer M constituting multilayer printed wiring board 10 is formed only on the top surface of conductor circuit 12, and not on the side surfaces of conductor circuit 12. Generally, the dimension of multilayer printed wiring board 10 in the thickness direction is much smaller than the dimension of multilayer printed wiring board 10 in the planar direction. Therefore, in the multilayer printed wiring board 10 of the present invention, the metal layer M is formed only on the top surface of the conductor circuit 12, rather than on the side surface of the conductor circuit 12, thereby maintaining the adhesive strength between the conductor circuit 12 and the resin insulating layer 13 and making it difficult for the resin insulating layer 13 to peel off from the conductor circuit 12.

[0017] As will be described later, multilayer printed wiring board 10 is manufactured by employing a manufacturing method that includes a manufacturing step that prevents deposition of metal layer M on resin insulating layer 13 where conductor circuits 12 are exposed. Therefore, in multilayer printed wiring board 10, the metal that constitutes metal layer M does not exist on resin insulating layer 13 formed between two adjacent conductor circuits 12 formed on the same resin insulating layer 13. As a result, multilayer printed wiring board 10 can prevent a decrease in insulation resistance due to the presence of metal layer M on resin insulating layer 13 formed between adjacent conductor circuits 12.

[0018] Furthermore, multilayer printed wiring board 10 according to the present invention has a technical feature in that metal layer M, which serves to improve the adhesive strength between conductor circuit 12 and resin insulating layer 13 laminated on conductor circuit 12, contains Al. One of the reasons that conductor circuit 12 peels off from resin insulating layer 13 in multilayer printed wiring board 10 is that there is a large difference in the expansion coefficient between conductor circuit 12 and resin insulating layer 13. Therefore, in the multilayer printed wiring board 10 of the present invention, in order to reduce the difference between the expansion coefficient of the conductor circuit 12 and the expansion coefficient of the resin insulating layer 13, a metal layer M containing Al is interposed between the conductor circuit 12 and the upper surface of the resin insulating layer 13.

[0019] Here, Al has ductility and malleability. That is, the metal layer M containing Al has malleability, which means that it stretches thin when struck, and ductility, which means that it stretches when pulled. Therefore, even when the resin insulating layer 13 is deformed due to expansion or the like, the metal layer M containing Al can conform to the deformed resin insulating layer 13. As a result, the metal layer M containing Al becomes one with the resin insulating layer 13 deformed due to expansion or the like, and can firmly maintain the adhesive state between the conductor circuit 12 and the resin insulating layer 13. In this way, the metal layer M containing Al provided in the multilayer printed wiring board 10 according to the present invention serves to firmly bond the conductor circuit 12 and the resin insulating layer 13 and maintain the adhesive strength.

[0020] The metal layer M interposed between the conductor circuit 12 and the upper surface of the resin insulating layer 13 may contain Al. The metal layer M may be formed solely of Al, or may be formed of an Al alloy containing Al and another metal. Examples of Al alloys containing Al and another metal include an Al-Cu alloy, an Al-Mn alloy, an Al-Si alloy, an Al-Mg alloy, and an Al-Mg-Si alloy. The metal layer M may contain at least one Al alloy selected from the group consisting of an Al-Cu alloy, an Al-Mn alloy, an Al-Si alloy, an Al-Mg alloy, and an Al-Mg-Si alloy, either singly or in combination of two or more. The thickness of the metal layer M may be any thickness that can accommodate deformation due to expansion or the like of the resin insulating layer 13, and is preferably, for example, 10 to 100 nm.

[0021] As explained above, the multilayer printed wiring board 10 of the present invention maintains strong adhesive strength between the conductor circuit 12 and the resin insulating layer 13 by forming the metal layer M containing Al only on the upper surface of the conductor circuit 12, and by not having the metal layer M on the resin insulating layer 13 formed between adjacent conductor circuits 12, it is possible to prevent a decrease in the insulation resistance.

[0022] <One embodiment of the method for manufacturing a multilayer printed wiring board according to the present invention> 2A to 2T are cross-sectional views illustrating one embodiment of a method for manufacturing a multilayer printed wiring board according to the present invention. Hereinafter, one embodiment of a method for manufacturing a multilayer printed wiring board according to the present invention will be described with reference to FIGS. 2A to 2T. The method for manufacturing a multilayer printed wiring board according to the present invention is a method for manufacturing a multilayer printed wiring board having a metal layer containing Al for bonding a conductor circuit and a resin insulating layer. The multilayer printed wiring board 10 manufactured by the method for manufacturing a multilayer printed wiring board according to the present invention is characterized in that the metal layer M constituting the multilayer printed wiring board 10 and used to bond the conductor circuit 12 and the insulating resin layer 13 is formed only on the top surface of the conductor circuit 12, and not on the side surface of the conductor circuit 12.

[0023] First, as shown in FIG. 2A, the first resin insulating layer 13A is formed. The first resin insulating layer 13A is formed of an epoxy resin, a phenolic resin, a polyimide resin, a polyester resin, a bismaleimide resin, a polyolefin resin, a polyphenylene ether resin, a fluororesin, or the like. Specifically, the first resin insulating layer 13A may be a resin composition containing an inorganic filler such as silica or alumina and an epoxy resin. That is, the first resin insulating layer 13A may be an electrical insulating material in which glass cloth is impregnated with a thermosetting resin such as an epoxy resin or a bismaleimide-triazine resin. 2A is formed on the upper surface of a seed layer S formed on a core substrate 11, which is a support substrate, and on the upper surface of a component mounting pad P. The core substrate 11 may be a resin substrate such as a glass epoxy substrate, a bismaleimide-triazine resin substrate, a copper-clad laminate, or an RCC substrate, a ceramic substrate such as an aluminum nitride substrate, or a silicon substrate.

[0024] Next, as shown in FIG. 2B, openings 13X reaching the component mounting pads P are formed in the first resin insulating layer 13A. The openings 13X are formed by performing a laser treatment and an exposure and development treatment on the first resin insulating layer 13A that has been subjected to a curing treatment. Resin residues generated by forming the openings 13X may be removed by a desmear treatment, or a plasma treatment or the like may be further performed after the desmear treatment. Examples of lasers used for the laser treatment include a carbon dioxide laser, an ultraviolet laser, and an excimer laser.

[0025] Next, as shown in Fig. 2C, an electroless copper plating film S1 is formed as a seed layer on the surface of first resin insulating layer 13A where openings 13X have been formed. The thickness of electroless copper plating film S1 formed on the surface of first resin insulating layer 13A is preferably 0.1 to 0.5 µm. 2D, multiple plating resists 21A are formed on electroless copper plating film S1 formed on the surface of first resin insulating layer 13A. Plating resists 21A are formed in areas where first conductive circuits 12A and via conductors 17A are not to be formed. There are no particular limitations on how plating resists 21A are formed, and they may be formed, for example, by applying a photosensitive dry film followed by exposure and development processing.

[0026] 2E, an electrolytic copper-plated film is formed in resist recesses 21B formed by the plurality of plating resists 21A formed on the electroless copper-plated film S1. The thickness of the electrolytic copper-plated film formed in plating resist recesses 21B is preferably 5 to 20 μm.

[0027] 2F, plating resist 21A is then removed using, for example, a subtractive method, and then electroless copper plating film S1 located below plating resist 21A is further removed, thereby forming first conductive circuits 12A and via conductors 17A on first resin insulating layer 13A. Plating resist 21A can be removed using, for example, an alkaline aqueous solution. Electroless copper plating film S1 can be removed by etching using an etching solution. Alternatively, a substrate having first conductive circuits 12A and via conductors 17A formed on first resin insulating layer 13A may be immersed in a dilute sulfuric acid aqueous solution for 10 seconds, rinsed with water, and then dried by air cutting.

[0028] Next, as shown in FIG. 2G, plating resist 22A for forming a metal layer is formed on first resin insulating layer 13A that is exposed after first conductive circuit 12A and via conductor 17A are formed, thereby forming plating resist recess 22B for forming a metal layer. Here, plating resist 22A is formed so that its thickness is greater than the thickness of first conductive circuit 12A and via conductor 17A formed on first resin insulating layer 13A. Therefore, plating resist 22A completely covers the side surfaces of first conductive circuit 12A and via conductor 17A. Plating resist recess 22B formed by adjacent plating resists 22A is formed, for example, from the left side wall of right-side plating resist 22A, the right side wall of left-side plating resist 22A, and the upper surface of first conductive circuit 12A or the upper surface of via conductor 17A exposed from plating resist recess 22B.

[0029] Next, as shown in Fig. 2H, metal layer M is formed on the upper surfaces of first conductive circuits 12A and via conductors 17A that are exposed from plating resist recesses 22B. Here, the side surfaces of first conductive circuits 12A and via conductors 17A are covered with plating resist 22A. Therefore, metal layer M is not formed on the side surfaces of first conductive circuits 12A and via conductors 17A. Furthermore, the metal that constitutes metal layer M is not present on first resin insulating layer 13A that is formed between adjacent first conductive circuits 12A or via conductors 17A. As a result, multilayer printed wiring board 10 can prevent a decrease in insulation resistance due to the presence of metal layer M on resin insulating layer 13 formed between adjacent conductor circuits 12.

[0030] The metal layer M may contain Al. The metal layer M may be formed solely from Al, or may be formed from an Al alloy containing Al and other metals. The metal layer M may be formed by a vacuum deposition method, a sputtering method, or the like. The thickness of the metal layer M may be such that it can follow deformation due to expansion or the like of the first resin insulating layer 13A, and may be formed to be, for example, 10 to 100 nm.

[0031] 2I, multiple plating resists 22A formed on first resin insulating layer 13A are removed from first resin insulating layer 13A. By removing multiple plating resists 22A from first resin insulating layer 13A, first resin insulating layer 13A, first conductive circuit 12A having metal layer M formed only on the upper surface, and via conductor 17A having metal layer M formed only on the upper surface are exposed.

[0032] Next, as shown in FIG. 2J, second resin insulating layer 13B is formed to cover first resin insulating layer 13A, first conductive circuit 12A having metal layer M formed only on the upper surface, and via conductor 17A having metal layer M formed only on the upper surface. Furthermore, opening 13Y is formed in second resin insulating layer 13B, reaching first conductive circuit 12A and via conductor 17A formed on first resin insulating layer 13A. Opening 13Y is formed by performing laser processing and exposure and development processing on second resin insulating layer 13B that has been subjected to a curing treatment. As with the formation of opening 13X, resin residue generated by forming opening 13Y may be removed by desmearing, or a plasma treatment or the like may be further performed after the desmearing.

[0033] Next, as shown in Fig. 2K, metal layer M exposed from openings 13Y formed in first resin insulating layer 13A and reaching first conductive circuits 12A and via conductors 17A is removed. Metal layer M exposed from openings 13Y reaching first conductive circuits 12A and via conductors 17A can be removed using a permanganic acid solution. By using a permanganic acid solution, removal of metal layer M can be performed simultaneously with desmearing, which removes resin residue generated when forming openings 13Y formed in second resin insulating layer 13B. By removing metal layer M from opening 13Y, electrolytic copper plating film 12B2 constituting first conductive circuit 12A formed below metal layer M and electrolytic copper plating layer 17B2 constituting via conductor 17A formed below metal layer M are exposed.

[0034] 2L, electroless plated film S2 is then formed on the upper surface of second resin insulating layer (13B) and on the electrolytic copper-plated layer of first conductive circuits (12A) and via conductors (17A) exposed from openings (13Y) formed in second resin insulating layer (13B). Furthermore, multiple plating resists (21C) for forming second conductive circuits (12B) and via conductors (17B) are formed on the upper surface of electroless copper-plated layer S2.

[0035] Next, as shown in Fig. 2M, an electrolytic copper-plated film is formed in plating resist recesses 21D formed by multiple plating resists 21C formed on electroless copper-plated film S2. Subsequently, as shown in Fig. 2N, second conductive circuits 12B and via conductors 17B are formed on second resin insulating layer 13B using a subtractive method in the same manner as in the formation of the conductive circuits and via conductors described above.

[0036] Next, as shown in FIG. 2O, plating resist (22C) is formed on second resin insulating layer (13B) that is exposed after second conductive circuits (12B) and via conductors (17B) are formed, thereby forming plating resist recesses (22D). Here, plating resist 22C is formed so that its thickness is greater than the thickness of second conductive circuit 12B and via conductor 17B formed on second resin insulation layer 13B. That is, plating resist 22C completely covers the entire side surface of second conductive circuit 12B and the side surface of via conductor 17B. Plating resist recess 22D formed by adjacent plating resists 22C is formed, for example, from the left side wall of right-side plating resist 22C, the right side wall of left-side plating resist 22C, and the upper surface of second conductive circuit 12B or the upper surface of via conductor 17B exposed from plating resist recess 22D.

[0037] 2P, metal layer M containing Al is formed only on the upper surfaces of second conductive circuits 12B and via conductors 17B that are exposed from plating resist recesses 22D. Metal layer M may be formed by vacuum deposition, sputtering, or the like, as described above. The thickness of metal layer M need only be such that it can accommodate deformation due to expansion, etc., of second resin insulating layer 13B.

[0038] Here, the side surfaces of second conductive circuits (12B) and via conductors (17B) are completely covered with plating resist (22C). Therefore, metal layer (M) is not formed on the side surfaces of second conductive circuits (12B) and via conductors (17B). In other words, the metal that constitutes metal layer (M) is not present on second resin insulating layer (13B) formed between adjacent second conductive circuits (12B).

[0039] Furthermore, no metal constituting metal layer M is present on second resin insulating layer 13B formed between adjacent via conductors 17B, nor on second resin insulating layer 13B formed between adjacent second conductive circuit 12B and via conductor 17B. As a result, multilayer printed wiring board 10 can prevent a decrease in insulation resistance caused by the presence of the metal that constitutes metal layer M on second resin insulating layer 13B.

[0040] Next, as shown in Fig. 2Q, multiple plating resists (22C) formed on second resin insulating layer (13B) are removed from second resin insulating layer (13B). By removing multiple plating resists (22C) from second resin insulating layer (13B), second resin insulating layer (13B), second conductive circuit (12B) having metal layer (M) formed only on its upper surface, and via conductor (17B) having metal layer (M) formed only on its upper surface are exposed.

[0041] 2R, solder resist layer 18 is formed to cover second resin insulating layer (13B), second conductive circuits (12B), and via conductors (17B). Solder resist layer 18 may be formed by applying a commercially available solder resist composition to a predetermined thickness onto the upper surface of second resin insulating layer (13B), which is the outermost layer, second conductive circuits (12B), and via conductors (17B), and then drying the solder resist composition.

[0042] 2S, solder resist openings 18X are formed in solder resist layer 18. Solder resist openings 18X are formed so as to reach second conductive circuits 12B and via conductors 17B formed in second resin insulating layer 13B. Solder resist openings 18X are formed by exposing solder resist layer 18 to ultraviolet light with a photomask (not shown) on which a solder bump formation opening pattern has been drawn, and then performing a development process using a DMTG solution or the like.

[0043] 2T, solder bumps 19 are formed in solder resist openings 18X formed in solder resist layer 18, completing multilayer printed wiring board 10. After removing metal layer M formed on the upper surfaces of second conductive circuits 12B and via conductors 17B exposed from solder resist openings 18X formed in solder resist layer 18, solder bumps 19 are formed in solder resist openings 18X via first protective layer 19A and second protective layer 19B.

[0044] Specifically, metal layer M formed on the upper surfaces of second conductive circuits 12B and via conductors 17B that are exposed from solder resist openings 18X formed in solder resist layer 18 is removed. Metal layer M exposed from solder resist openings 18X that reach second conductive circuits 12B and via conductors 17B can be removed using a permanganate solution in the same manner as above. Removing metal layer M exposed from solder resist openings 18X exposes the electrolytic copper plating film that constitutes second conductive circuits 12B and via conductors 17B.

[0045] A protective layer is formed in this order on the electrolytic copper plating film exposed from the solder resist opening 18X, first protective layer 19A and second protective layer 19B. A protective layer is formed to protect the second conductive circuit 12B and via conductor 17B located in the uppermost layer exposed from the solder resist opening 18X. The protective layer may be one layer or two layers. In FIG. 2T, this protective layer is formed from first protective layer 19A and second protective layer 19B, which are made of different materials. The protective layer may be made of gold, nickel, palladium, or an alloy thereof. After the protective layer is formed in the solder resist opening 18X, solder paste is printed and reflowed at a predetermined temperature to form the solder bump 19.

[0046] As described above, the method for manufacturing a multilayer printed wiring board according to the present invention can prevent a metal layer from being deposited on the resin insulation layer where the conductor circuits are exposed. Therefore, the multilayer printed wiring board manufactured by the method for manufacturing a multilayer printed wiring board according to the present invention can prevent a decrease in insulation resistance due to the presence of a metal layer on the resin insulation layer on which the conductor circuits and the like are formed. Moreover, the method for manufacturing a multilayer printed wiring board according to the present invention can provide a multilayer printed wiring board in which the Al-containing metal layer is formed only on the top surfaces of the conductor circuits and the like, without forming it on the side surfaces of the conductor circuits and the like, thereby maintaining sufficient adhesive strength between the conductor circuits and the resin insulation layer and preventing the resin insulation layer from peeling off from the conductor circuits. [Explanation of symbols]

[0047] 10 Multilayer printed wiring board 11 Core board 12 Conductor Circuit 12A First Conductor Circuit 12A1 electroless copper plating film 12A2 electrolytic copper plating film 12B Second conductive circuit M Al-containing metal layer 13 Resin insulation layer 13A First resin insulating layer 13B Second resin insulating layer 13X Resin insulation layer opening (first resin insulation layer) 13Y Resin insulation layer opening (second resin insulation layer) 14 through-hole conductor 15 Resin filler layer 16 Through-hole conductor circuit 17 Via conductor 17A via conductor (first resin insulation layer) 17B Via conductor (second resin insulation layer) 17B1 electroless copper plating film 17B2 electrolytic copper plating film 18 Solder resist layer 18X solder mask opening 19 Solder bumps 19A 1st protective layer 19B 2nd protective layer 21A, C Plating resist (for conductor circuits) 21B, D Plating resist recess (for conductor circuit) 22A, C Plating resist (for forming metal layers) 22B, D Plating resist recess (for forming metal layer)

Claims

1. a first resin insulating layer; a first conductive circuit formed on the first resin insulating layer; a second resin insulating layer formed on the first resin insulating layer and the first conductive circuit, the second resin insulating layer having an opening that reaches the first conductive circuit; a second conductive circuit formed on the second resin insulating layer; a via conductor formed in the opening for connecting the first conductive circuit and the second conductive circuit, a metal layer containing Al is formed only on top surfaces of the first conductive circuit, the second conductive circuit, and the via conductor; A multilayer printed wiring board, wherein the metal layer is not formed on the side surfaces of the first conductive circuit, the second conductive circuit, and the via conductor.

2. 2. The multilayer printed wiring board according to claim 1, The metal layer contains at least one Al alloy selected from an Al-Cu alloy, an Al-Mn alloy, an Al-Si alloy, an Al-Mg alloy, and an Al-Mg-Si alloy, either alone or in combination of two or more thereof.

3. A method for manufacturing a multilayer printed wiring board having a metal layer containing Al for adhering a conductor circuit and a resin insulating layer, forming a first resin insulating layer; forming a first conductive circuit on the first resin insulating layer; forming a plating resist recess by forming a plating resist on the first resin insulating layer that is exposed after the first conductive circuit is formed; forming a metal layer containing Al only on the upper surface of the first conductive circuit exposed from the plating resist recess; removing the plating resist from above the first resin insulating layer after forming the metal layer containing Al; forming a second resin insulating layer that covers the first resin insulating layer, the first conductor circuit, and the metal layer containing Al; forming an opening penetrating the second resin insulating layer; removing the metal layer containing Al exposed from the opening; forming a second conductive circuit on the second resin insulating layer; forming a via conductor in the opening to connect the first conductive circuit and the second conductive circuit.

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