Imaging element and imaging apparatus

Abstract

To provide a high-performance imaging element configured by vertically stacking semiconductor chips.SOLUTION: The imaging element includes: a first substrate which has a plurality of pixel blocks which are arranged side by side in a row direction and in a column direction and include at least one pixel; and a second substrate which has a plurality of control blocks which are arranged side by side in the row direction and in the column direction and include a conversion part for converting a signal output from the pixel into a digital signal and a through electrode part for outputting the signal converted into the digital signal by the conversion part.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an imaging element and an imaging device. [Background technology]

[0002] Imaging elements configured by stacking semiconductor chips one above the other are known (for example, Patent Document 1). Higher functionality has been demanded. Patent Document 1: Japanese Patent Application Laid-Open No. 2006-49361 Summary of the Invention

[0003] In a first aspect of the present invention, an imaging element is provided, comprising: a first substrate having a plurality of pixel blocks arranged in a row direction and a column direction and each pixel block including at least one pixel; and a second substrate having a plurality of control blocks arranged in a row direction and a column direction and each control block including a conversion unit that converts signals output from the pixels into digital signals and a through electrode unit that outputs the signals converted into digital signals by the conversion unit.

[0004] A second aspect of the present invention is an imaging device comprising the imaging element described above.

[0005] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 4 is a diagram showing an overview of an image sensor 400. [Figure 2] An example of a specific configuration of the pixel section 110 will be shown. [Figure 3] 1 shows an example of a circuit configuration of a pixel 112. [Figure 4] An example of a more specific configuration of the control circuit section 210 will be shown. [Figure 5] An example of a more specific configuration of the control block 220 will be shown below. [Figure 6]An example of a more specific configuration of the image processing unit 310 will be shown. [Figure 7] An example of a more specific configuration of the processing block 320 will be shown. [Figure 8] 10 is a diagram for explaining an example of a wiring method for the imaging element 400. FIG. [Figure 9] FIG. 2 is a schematic diagram showing the layout relationship of a plurality of control blocks 220. [Figure 10] FIG. 2 is a schematic diagram showing the layout relationship of a plurality of processing blocks 320. [Figure 11] An example of a specific configuration of the other control block 620 will be shown below. [Figure 12] 10 is a diagram for explaining an example of a wiring method for an imaging element 800 using a control block 620. FIG. [Figure 13] FIG. 6 is a schematic diagram showing the layout relationship of a plurality of control blocks 620. [Figure 14] An example of a specific configuration of yet another control block 640 will be shown below. [Figure 15] FIG. 6 is a schematic diagram showing the layout relationship of a plurality of control blocks 640. [Figure 16] An example of a specific configuration of yet another control block 660 will be shown below. [Figure 17] FIG. 6 is a schematic diagram showing the layout relationship of a plurality of control blocks 640. [Figure 18] 10 is a schematic diagram showing the details of the arrangement of the through electrodes 62. FIG. [Figure 19] 10 is a schematic diagram showing the details of the arrangement of the through electrodes 62. FIG. [Figure 20] FIG. 1 is a block diagram showing an example of the configuration of an imaging device 500 according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0008] In this specification, the X-axis and Y-axis are perpendicular to each other, and the Z-axis is perpendicular to the XY plane. The XYZ-axes form a right-handed system. The direction parallel to the Z-axis may be referred to as the stacking direction of the imaging element. In this specification, the terms "up" and "down" are not limited to the up and down directions in the direction of gravity. These terms merely refer to relative directions in the Z-axis direction. Note that in this specification, the arrangement in the X-axis direction will be described as a "row" and the arrangement in the Y-axis direction as a "column," but the matrix direction is not limited to this.

[0009] FIG. 1 is a diagram showing an overview of an imaging element 400. The imaging element 400 captures an image of a subject. The imaging element 400 generates image data of the captured subject. The imaging element 400 includes a first substrate 100, a second substrate 200, and a third substrate 300. As shown in FIG. 1, the first substrate 100 is stacked on the second substrate 200. Furthermore, the second substrate 200 is stacked on the third substrate 300.

[0010] The first substrate 100 has a pixel section 110. Light is incident on the pixel section 110. The pixel section 110 outputs a pixel signal based on the incident light. The first substrate 100 may be referred to as a pixel chip.

[0011] The second substrate 200 has a control circuit section 210 and a peripheral circuit section 230. The second substrate 200 may be referred to as a processing circuit chip.

[0012] The control circuit section 210 in this example is disposed on the second substrate 200 at a position facing the pixel section 110. The control circuit section 210 outputs a control signal to the pixel section 110 for controlling the driving of the pixel section 110. The control circuit section 210 also receives as input a pixel signal output from the pixel section 110.

[0013] The control circuit unit 210 performs signal processing on pixel signals. For example, the control circuit unit 210 performs processing to convert analog signals into digital signals. Specifically, the control circuit unit 210 performs processing to convert input pixel signals into digital signals. The control circuit unit 210 may also perform other signal processing. Examples of other signal processing include noise removal processing such as analog or digital CDS (Correlated Double Sampling).

[0014] The peripheral circuit unit 230 controls the driving of the control circuit unit 210. The peripheral circuit unit 230 is arranged around the control circuit unit 210 on the second substrate 200. The peripheral circuit unit 230 may also be electrically connected to the first substrate 100 and control the driving of the pixel unit 110. In this example, the peripheral circuit unit 230 is arranged along two opposing sides of the second substrate 200, but the arrangement of the peripheral circuit unit 230 is not limited to this example.

[0015] The third substrate 300 has an image processing unit 310 and a peripheral circuit unit 330. The third substrate 300 may be referred to as an image processing chip. In this example, the peripheral circuit unit 330 is arranged along two opposing sides of the third substrate 300, but the arrangement of the peripheral circuit unit 330 is not limited to this example.

[0016] The image processing unit 310 in this example is disposed on the third substrate 300 at a position opposite to the control circuit unit 210. The control circuit unit 210 performs image processing on the pixel signals output by the control circuit unit 210. The structure of the image sensor 400 may be either a back-illuminated type or a front-illuminated type.

[0017] 2 shows an example of a specific configuration of the pixel section 110. In this example, an enlarged view of the pixel section 110 and a pixel block 120 provided in the pixel section 110 is shown.

[0018] The pixel section 110 has a plurality of pixel blocks 120 arranged side by side in the row and column directions. In this example, the pixel section 110 has M×N (M and N are natural numbers) pixel blocks 120. In this example, the case where M is equal to N is illustrated, but M and N may be different.

[0019] Each pixel block 120 has at least one pixel 112. In this example, the pixel block 120 has m×n pixels 112 (m and n are natural numbers). For example, the pixel block 120 has 16×16 pixels 112. The number of pixels 112 corresponding to the pixel block 120 is not limited to this. In this example, the case where m is equal to n is illustrated, but m may be different from n. The pixel block 120 has multiple pixels 112 connected to a common control line in the row direction. For example, each pixel 112 in the pixel block 120 is connected to a common control line so that the pixels 112 are set to the same exposure time. In one example, n pixels 112 arranged in the row direction are connected by a common control line.

[0020] On the other hand, different exposure times may be set for each of the multiple pixel blocks 120. That is, the pixels 112 of each pixel block 120 may have the same exposure time, but may be set to different exposure times for the other pixel blocks 120. For example, when the pixels 112 of a pixel block 120 are connected in the row direction by a common control line, the pixels 112 of the other pixel blocks 120 may be connected in common by a different control line.

[0021] The pixel blocks 120 are arranged corresponding to the control blocks 220 described later. In this embodiment, one pixel block 120 is arranged for one control block 220.

[0022] The pixels 112 have a photoelectric conversion function that converts light into electric charges. The pixels 112 accumulate the electric charges generated by the photoelectric conversion. m pixels 112 are arranged side by side in the column direction and connected to a common signal line 122. The m pixels 112 are arranged side by side in n columns in the row direction in the pixel block 120.

[0023] In other words, the pixel block 120 is a group of pixels 112 connected by a common control line. The pixel block 120 can also be said to be the smallest unit of a circuit for multiple pixels 112 for which the same exposure time is set.

[0024] 3 shows an example of the circuit configuration of the pixel 112. The pixel 112 includes a photoelectric conversion unit 104, a transfer unit 123, a discharge unit 124, a reset unit 126, and a pixel output unit 127. The pixel output unit 127 includes an amplifier unit 128 and a selection unit 129. In this example, the transfer unit 123, the discharge unit 124, the reset unit 126, the amplifier unit 128, and the selection unit 129 are described as N-channel FETs, but the type of transistor is not limited to this.

[0025] The photoelectric conversion unit 104 has a photoelectric conversion function of converting light into electric charges. The photoelectric conversion unit 104 accumulates the electric charges generated by photoelectric conversion. The photoelectric conversion unit 104 is, for example, a photodiode.

[0026] The transfer unit 123 transfers the charges accumulated in the photoelectric conversion unit 104 to the storage unit 125. The transfer unit 123 is an example of a transfer gate that transfers the charges of the photoelectric conversion unit 104. In other words, the transfer unit 123 serves as the gate, the photoelectric conversion unit 104 serves as the source, and the storage unit 125 serves as the drain, forming a so-called transfer transistor. The gate terminal of the transfer unit 123 is connected to a local transfer control line for each pixel block 120 for inputting a control signal φTX1.

[0027] The discharge unit 124 discharges the charges accumulated in the photoelectric conversion unit 104 to a power supply wiring to which a power supply voltage VDD is supplied. A gate terminal of the discharge unit 124 is connected to a local discharge control line for each pixel block 120 for inputting a discharge control signal φTX2. Note that, in this example, the discharge unit 124 has been described as discharging the charges of the photoelectric conversion unit 104 to a power supply wiring to which a power supply voltage VDD is supplied, but the discharge unit 124 may also be discharged to a power supply wiring to which a power supply voltage different from the power supply voltage VDD is supplied.

[0028] The charge from the photoelectric conversion unit 104 is transferred to the accumulation unit 125 by the transfer unit 123. The accumulation unit 125 is an example of a floating diffusion (FD).

[0029] The reset unit 126 discharges the charge in the storage unit 125 to a power supply line to which a predetermined power supply voltage VDD is supplied. A gate terminal of the reset unit 126 is connected to a global reset control line across multiple pixel blocks 120 for inputting a reset control signal φRST.

[0030] The pixel output unit 127 outputs a signal based on the potential of the storage unit 125 to the signal line 122. The pixel output unit 127 has an amplifier unit 128 and a selection unit 129. The amplifier unit 128 has a gate terminal connected to the storage unit 125, a drain terminal connected to a power supply line to which a power supply voltage VDD is supplied, and a source terminal connected to the drain terminal of the selection unit 129.

[0031] The selection unit 129 controls the electrical connection between the pixel 112 and the signal line 122. When the selection unit 129 electrically connects the pixel 112 and the signal line 122, a pixel signal is output from the pixel 112 to the signal line 122. A gate terminal of the selection unit 129 is connected to a global selection control line that spans multiple pixel blocks 120 and inputs a selection control signal φSEL. A source terminal of the selection unit 129 is connected to the load current source 121.

[0032] The load current source 121 supplies a current to the signal line 122. The load current source 121 may be provided on the first substrate 100 or on the second substrate 200.

[0033] Hereinafter, any one of the charges accumulated in the photoelectric conversion unit 104, the charges transferred to the accumulation unit 125, and the signal based on the potential of the accumulation unit 125, or all of these may be collectively referred to as a pixel signal.

[0034] In other words, the pixel 112 includes at least one photoelectric conversion unit 104, and a pixel output unit 127 as a readout unit that reads out an image signal from the at least one photoelectric conversion unit 104 to a signal line 122. The pixel 112 can also be said to be the smallest unit of a circuit that outputs pixel signals that constitute an image to the signal line 122.

[0035] 4 shows an example of a more specific configuration of the control circuit unit 210. The control circuit unit 210 has control blocks 220 arranged side by side in the row and column directions. The control circuit unit 210 of this example has M×N control blocks 220.

[0036] The control blocks 220 are disposed at positions corresponding to the pixel blocks 120. For example, the control blocks 220 and the pixel blocks 120 are disposed at positions where they overlap when viewed from the stacking direction of the first substrate 100 and the second substrate 200. In this case, the areas of the control blocks 220 and the pixel blocks 120 may be substantially the same, including the margin between adjacent blocks.

[0037] 5 shows an example of a more specific configuration of the control block 220. The control block 220 controls the driving of the corresponding pixel block 120. For example, the control block 220 controls the exposure time of the pixel block 120. The control block 220 also has a processing circuit such as an AD converter, and processes the signal output by the pixel block 120. In one example, the control block 220 converts the analog pixel signal output from the corresponding pixel block 120 into a digital signal. The control block 220 in this example includes a pixel driving unit 20, a joining unit 30, a conversion unit 40, a signal output unit 50, a local I / O, and a through-electrode region 60.

[0038] The pixel driving unit 20 controls exposure of the plurality of pixels 112 and drives the plurality of pixels 112. The pixel driving unit 20 generates signals for controlling the exposure time of the pixels 112. In one example, the pixel driving unit 20 controls the exposure time for each pixel block 120 by adjusting at least one of the start timing or end timing of the exposure.

[0039] The pixel driving unit 20 is electrically connected to the plurality of pixels 112. The pixel driving unit 20 selects and drives an arbitrary pixel 112 from the plurality of pixels 112. The pixel driving unit 20 is disposed at a position corresponding to the m pixels 112 arranged in the column direction. The image sensor 400 can set the exposure time for each pixel block 120 according to the intensity of incident light, thereby expanding the dynamic range.

[0040] The bonding unit 30 bonds the first substrate 100 and the second substrate 200. The bonding unit 30 inputs pixel signals input from the first substrate 100 to the signal conversion unit 40. The bonding units 30 are provided corresponding to n pixels 112 arranged in the row direction, and input pixel signals to the signal conversion unit 40 for each column.

[0041] The conversion unit 40 converts the analog signal output by the pixel unit 110 into a digital signal. In this example, the conversion unit 40 converts the analog pixel signal into a digital signal. The conversion unit 40 sequentially converts the analog signals from m pixels 112 arranged in the column direction into digital signals. The conversion unit 40 converts the analog signals from n columns of pixels 112 in the row direction into digital signals in parallel. This can also be said to be a so-called column ADC method for one pixel block 120.

[0042] The signal output section 50 receives the digital signal from the conversion section 40. In one example, the signal output section 50 temporarily stores the digital signal. The signal output section 50 may include a latch circuit for storing the digital signal.

[0043] The local I / O 70 is an interface that controls the input and output of signals to and from the control block 220. In one example, the local I / O 70 outputs digital pixel signals that are temporarily stored in the signal output unit 50 to the image processing unit 310 through through electrodes 62, which will be described later.

[0044] The through electrode region 60 has through electrodes 62 and their forbidden regions 61. The through electrodes 62 are also called TSVs. The through electrodes 62 are electrically connected to the image processing unit 310 of the third substrate 300, and form part of a path for outputting signals to the image processing unit 310. The forbidden regions 61 are provided adjacent to the through electrodes 62, and are regions in which no elements other than the through electrodes 62 (such as transistors) are to be arranged. The region in which the through electrodes 62 are provided may be referred to as a first region, and the forbidden regions 61 may be referred to as a second region.

[0045] The thick lines in the figure indicate well separation bands 72. The well separation bands 72 are provided to more reliably electrically separate adjacent circuits when, for example, the voltages they handle are different in magnitude. Additionally, the well separation bands 72 may be provided between circuits that handle analog signals and circuits that handle digital signals. In the example of FIG. 5 , the pixel driving unit 20, the junction unit 30, and the conversion unit 40 mainly handle analog signals, while the signal output unit 50, the local I / O 70, and the through-electrode region 60 mainly handle digital signals.

[0046] In the control block 220 of Figure 5, the pixel driving unit 20 is arranged vertically from the top to the bottom along the left side. On the right side of the pixel driving unit 20, the junction unit 30 and the conversion unit 40 are arranged from the top to the bottom, with a well separation band 72 sandwiched between them. Below the conversion unit 40, the signal output unit 50 is arranged with the well separation band 72 sandwiched between them, and to the lower right of the signal output unit 50, the local I / O 70 and the through-electrode region 60 are arranged. The through electrode 62 of the through-electrode region 60 is arranged in the lower right corner of the control block 220, and is covered above and to the left by a prohibited region 61.

[0047] Instead of providing one control block 220 for one pixel block 120, one control block may be provided for N pixel blocks 120 (N is a natural number greater than or equal to 2). The N pixel blocks 120 corresponding to one pixel block are sometimes referred to as a pixel block group. For example, two pixel blocks 120 arranged side by side in the column direction may be treated as one pixel block group, and one control block 220 may be provided for each pixel block group. In this case, the control block 220 may control the exposure time for each pixel block 120.

[0048] In other words, the control block 220 is electrically connected to at least one pixel block 120 and can be said to be the smallest unit of a circuit that controls the pixels 112 of the at least one pixel block 120 .

[0049] 6 shows an example of a more specific configuration of the image processing unit 310. The image processing unit 310 has processing blocks 320 arranged in rows and columns. The image processing unit 310 in this example has M×N processing blocks 320.

[0050] The processing blocks 320 are disposed at positions corresponding to the control blocks 220. For example, the processing blocks 320 and the control blocks 220 are disposed at positions overlapping each other when viewed from the stacking direction of the second substrate 200 and the third substrate 300. In this case, the areas of the processing blocks 320 and the control blocks 220 may be substantially the same, including the margin between adjacent blocks.

[0051] 7 shows an example of a more specific configuration of the processing block 320. The processing block 320 performs image processing on pixel signals converted to digital form by the corresponding control block 220. For example, the processing block 320 performs image processing such as data interpolation and compression on the pixel signals output by the control block 220. In addition, image processing such as compression reduces the amount of data in the pixel signals output to the through silicon vias 62. The processing block 320 in this example includes a local I / O 370, a through silicon via region 360, a signal input unit 322, a processing unit 324, and a signal output unit 326.

[0052] The local I / O 370 is an interface that controls the input and output of signals to and from the processing block 320. In one example, the local I / O 370 receives digital pixel signals from the control block 220 via through electrodes 362, which will be described later.

[0053] The through silicon via region 360 has through silicon vias 362 and their forbidden regions 361. The through silicon via region 360, through silicon vias 362, and forbidden regions 361 are the same as the through silicon via region 60, through silicon vias 62, and forbidden regions 61 of the control block 220, and therefore description thereof will be omitted.

[0054] The signal input unit 322 receives a digital signal from the control block 220 via the through electrodes 62 and 362. In one example, the signal input unit 322 temporarily stores the digital signal. The signal input unit 322 may include a latch circuit for storing the digital signal.

[0055] The processing unit 324 performs image processing on the digital signal temporarily stored in the signal input unit 322. For example, the processing unit 324 performs image processing such as data interpolation and compression on the pixel signal output from the control block 220 and stored in the signal input unit 322. The processing unit 324 outputs the image-processed signal to the signal output unit 326.

[0056] The signal output unit 326 receives and temporarily stores a signal from the processing unit 324. The signal output unit 326 may include a latch circuit for storing the digital signal. The signal output unit 326 also outputs the temporarily stored signal to an external device outside the processing block 320.

[0057] 7, the through electrodes 362 and the prohibited areas 361 are provided at positions corresponding to the through electrodes 362 and the prohibited areas 361 of the corresponding control blocks 220. For example, the through electrodes 62, 362 are arranged at positions where they overlap when viewed from the stacking direction of the second substrate 200 and the third substrate 300. Furthermore, for example, the prohibited areas 61, 361 are arranged at positions where they overlap when viewed from the stacking direction of the second substrate 200 and the third substrate 300. In other words, it can be said that the through electrode areas 60, 360 are arranged at positions where they overlap when viewed from the stacking direction of the second substrate 200 and the third substrate 300.

[0058] 7, the signal input unit 322 and the local I / O 370 are also arranged in positions corresponding to the signal output unit 50 and the local I / O 70 of the corresponding control block 220. However, these do not have to be arranged in corresponding positions.

[0059] 8 is a diagram for explaining an example of a wiring method for the imaging element 400. Here, the peripheral circuit section 230 of the second substrate 200 has a global driving section 234 and an ADC setting section 236.

[0060] The global driver 234 is connected to a reset control line 143 and a selection control line 145 that output signals to each pixel block 120. The global driver 234 supplies a reset control signal φRST to the plurality of pixel blocks 120 via the reset control line 143, and supplies a selection control signal φSEL via the selection control line 145. The global driver 234 supplies a transfer selection control signal φTXSEL to the plurality of control blocks 220 via a transfer selection control line 147.

[0061] The transfer selection control signal φTXSEL is supplied from the global driver 234 to the control block 220 to control the exposure time for each pixel block 120. The control block 220, to which the transfer selection control signal φTXSEL is supplied, outputs the transfer selection control signal φTXSEL to the corresponding pixel block 120. The pixel block 120 determines whether to input the transfer selection control signal φTXSEL to the pixel 112 as the transfer control signal φTX1 or the discharge control signal φTX2. As a result, input of the transfer control signal φTX1 or the discharge control signal φTX2 to the pixel 112 is skipped.

[0062] For example, when the transfer control signal φTX1 determines the end time of exposure, the control block 220 extends the exposure time by skipping the transfer control signal φTX1. When the transfer control signal φTX1 determines the start time of exposure, the control block 220 shortens the exposure time by skipping the transfer control signal φTX1. In this way, the exposure time of the pixel block 120 can be adjusted by the transfer selection control signal φTXSEL. The same applies when the discharge control signal φTX2 determines the start or end time of exposure.

[0063] The reset control line 143, the selection control line 145, and the transfer selection control line 147 are wired globally, i.e., are provided in common to multiple pixel blocks 120. In this example, the reset control line 143, the selection control line 145, and the transfer selection control line 147 are wired so as to cross the pixel unit 110 in the row direction. The reset control line 143, the selection control line 145, and the transfer selection control line 147 may also be wired so as to cross the pixel unit 110 in the column direction.

[0064] For example, the reset control line 143 is connected to the gate terminal of the reset unit 126 of the pixel block 120 and supplies a reset control signal φRST. The selection control line 145 is connected to the gate terminal of the selection unit 129 of the pixel block 120 and supplies a selection control signal φSEL. In addition, the transfer selection control line 147 is connected to each of the multiple control blocks 220 and supplies a transfer selection control signal φTXSEL to the pixel drive unit 20.

[0065] In this example, the global driving unit 234 outputs the transfer selection control signal φTXSEL from the second substrate 200 to the first substrate 100, but the transfer selection control signal φTXSEL may be output to the control block 220 without being supplied to the first substrate 100. In this case, the transfer selection control line 147 is provided on the second substrate 200.

[0066] The ADC setting unit 236 is connected to the conversion units 40 of the multiple control blocks 220 by a common signal line 237. The signal line 237 can also be said to be a global signal line. The ADC setting unit 236 sets the gain, offset, settling time, resolution, etc. of the conversion unit 40.

[0067] Meanwhile, a transfer control line 141 and a discharge control line 142, which are local control lines from the pixel driving unit 20 of the control block 220, are connected to the pixel block 120. In this example, the transfer control line 141 is connected to the gate terminal of a transfer unit 123 provided in the pixel block 120. The transfer control line 141 supplies a transfer control signal φTX1 output from the pixel driving unit 20 to the pixel block 120. In this example, the discharge control line 142 is connected to the gate terminal of a discharge unit 124 provided in the pixel block 120. The discharge control line 142 supplies a discharge control signal φTX2 output from the pixel driving unit 20 to the pixel block 120.

[0068] The junction units 30 are connected to the signal lines 122 and the power supply lines 130. The junction units 30 are connected to the ground lines 132 set to the reference potential VGND. The junction units 30 output pixel signals to the corresponding converters 40. For example, n converters 40 are provided in the row direction.

[0069] The ground lines 132 are set to a predetermined reference potential VGND. In this example, the ground lines 132 are wired so as to cross the first substrate 100 in the row direction.

[0070] The plurality of bumps 152 are provided on the bonding surfaces where the first substrate 100 and the second substrate 200 are bonded to each other. The bumps 152 of the first substrate 100 are aligned with the bumps 152 of the second substrate 200. The plurality of opposing bumps 152 are bonded and electrically connected by applying pressure to the first substrate 100 and the second substrate 200 or the like.

[0071] The image sensor 400 of this example controls the exposure time for each pixel block 120 by changing the timing of at least one of the transfer unit 123 and the discharge unit 124 using local control lines. By combining local control lines and global control lines, the image sensor 400 can control the exposure time with fewer control lines.

[0072] Furthermore, the signal output section 50 of the control block 220 is connected to the signal input section 322 of the corresponding processing block 320 by through electrodes 62, 362. This allows signals to be transmitted and received between the control block 220 and the processing block 320.

[0073] The peripheral circuit unit 330 arranged on the third substrate 300 is connected to the multiple processing blocks 320 by global signal lines 352. The peripheral circuit unit 330 reads out, for example, pixel signals that have undergone image processing from each of the multiple processing blocks 320. The peripheral circuit unit 330 then outputs the read-out pixel signals to the I / O unit 160 of the first substrate 100 via the signal lines 354, the through electrodes 364, 64, the signal lines 238, the bumps 152, and the signal lines 162.

[0074] In addition, the second substrate 200 and the third substrate 300 are electrically joined by the through electrodes 62, 64, 362, and 364. Furthermore, the joining may be physically reinforced.

[0075] Fig. 9 is a schematic diagram showing the layout relationship of a plurality of control blocks 220. In the example of Fig. 9, four adjacent control blocks 220a, 220b, 220c, and 220d are shown.

[0076] 9, through electrodes 62a, 62b, 62c, and 62d are arranged in the center of the four control blocks 220a, 220b, 220c, and 220d, respectively, so that forbidden regions 61a, 61b, 61c, and 61d are arranged to surround the through electrodes 62a, 62b, 62c, and 62d.

[0077] This can also be said to mean that the through silicon via regions of the four control blocks 220a, 220b, 220c, and 220d are adjacent to each other. With this arrangement, the through silicon via region can be made smaller overall compared to when the through silicon vias are arranged apart from each other.

[0078] 9, the circuits of the control blocks 220a and 220b adjacent to each other in the X direction are arranged symmetrically. For example, the converter 40a of the control block 220a and the converter 40b of the control block 220b adjacent to the control block 220a in the X direction are adjacent to each other in the X direction. The circuits of the control blocks 220a and 220c adjacent to each other in the Y direction are arranged symmetrically. For example, the through silicon via region of the control block 220a (i.e., the through silicon via 62a and the prohibited region 61a) and the through silicon via region of the control block 220c adjacent to the control block 220a in the Y direction (i.e., the through silicon via 62c and the prohibited region 61c) are arranged between the converter 40a of the control block 220a and the converter 40c of the control block 220c in the Y direction. However, as long as the circuit arrangement is symmetrical, the wiring within the circuit, the direction of signal flow, the order of input and output, etc. do not have to be symmetrical.

[0079] As a result, circuits having similar functions are adjacent to each other between adjacent control blocks 220, and therefore well separation bands can be omitted, thereby improving area efficiency.

[0080] These four control blocks 220a, 220b, 220c, and 220d are treated as a unit, and the control blocks 220 are repeatedly arranged in the same manner in the X and Y directions. This repeating unit is sometimes called a unit circuit group.

[0081] Between adjacent control blocks 220 across repeating units, i.e., between unit circuit groups, the through silicon via regions 60 are separated by a region in which other elements are provided. For example, in Fig. 9, on the +X side of control block 220b, there is adjacent a control block having the same layout as control block 220a. The through silicon via regions between these control blocks are not adjacent to each other, and there is a region in between in which other elements such as local I / Os and pixel driving units are provided.

[0082] Fig. 10 is a schematic diagram showing the layout relationship of multiple processing blocks 320. In the example of Fig. 10, four adjacent processing blocks 320a, 320b, 320c, and 320d are shown, corresponding to the four adjacent control blocks 220a, 220b, 220c, and 220d in Fig. 9.

[0083] 10, through electrodes 362a, 362b, 362c, and 362d are also arranged at the centers of the four processing blocks 320a, 320b, 320c, and 320d, respectively, so that forbidden regions 61a, 61b, 61c, and 61d are arranged to surround the through electrodes 62a, 62b, 62c, and 62d.

[0084] This means that the through electrode regions of the four processing blocks 320a, 320b, 320c, and 320d are adjacent to each other. This arrangement allows the through electrode region to be smaller overall than when the through electrodes are arranged far apart.

[0085] 10, the circuits of processing blocks 320a and 320b adjacent to each other in the X direction are arranged symmetrically. For example, processing unit 324a of processing block 320a is adjacent to processing unit 324b of processing block 320b adjacent to processing block 320a in the X direction. Furthermore, the circuits of processing blocks 320a and 320c adjacent to each other in the Y direction are arranged symmetrically. However, as long as the circuit arrangement is symmetrical, the wiring within the circuit, the direction of signal flow, the order of inputs and outputs, and so on do not have to be symmetrical. These four processing blocks 320a, 320b, 320c, and 320d are used as a unit, and processing blocks 320 are repeatedly arranged in the same manner in the X and Y directions.

[0086] Fig. 11 shows an example of a specific configuration of another control block 620. In the control block 620, the same components as those in the control block 220 in Fig. 5 are given the same reference numerals and descriptions thereof will be omitted.

[0087] In the control block 620, a control circuit 80 is provided instead of the pixel driving unit 20 of the control block 220. The control circuit 80 mainly controls the control block 620. The area of ​​the control circuit 80 is also provided with functions similar to those of the local I / O 70 of the control block 220.

[0088] In the control block 620 of Figure 11, the control circuit 80 is arranged vertically from the top edge along the left edge. On the +X side of the control circuit 80, the junction unit 30 and the conversion unit 40 are arranged in this order from the top edge to the -Y side, with a well separation band 72 sandwiched between them. Below the conversion unit 40, the signal output unit 50 is arranged with the well separation band 72 sandwiched between them, and below the signal output unit 50 and the control circuit 80, a through electrode region 60 is arranged from the right edge to the left edge along the bottom edge. The through electrodes 62 in the through electrode region 60 are arranged along the bottom edge of the control block 620, and are covered by a prohibited region 61.

[0089] Fig. 12 is a diagram for explaining an example of a wiring method for an image sensor 800 using a control block 620. In the image sensor 800 of Fig. 12, the same components as those in Fig. 8 are given the same reference numerals and descriptions thereof will be omitted.

[0090] In the image sensor 800, the peripheral circuit unit 603 has a global driver 634. In addition to the functions of the global driver 234 in FIG. 8, the global driver 634 supplies a transfer control signal φTX1 and a discharge control signal φTX2 to the pixel block 120 via a transfer control line 141 and a discharge control line 142. Here, the transfer control line 141 and the discharge control line 142 are global wirings connected in common to multiple pixel blocks 120. Therefore, exposure is controlled globally across the entire pixel unit 110.

[0091] On the other hand, in the image sensor 800, the peripheral circuit unit 603 does not have the ADC setting unit 236 of the peripheral circuit unit 230. Instead, a control circuit 80 is provided in each of the control blocks 620. This control circuit 80 also has the function of the ADC setting unit 236. This allows the gain, offset, settling time, resolution, and the like in the conversion unit 40 to be set for each control block 620 in the image sensor 800.

[0092] Fig. 13 is a schematic diagram showing the layout relationship of a plurality of control blocks 620. In the example of Fig. 13, four adjacent control blocks 620a, 620b, 620c, and 620d are shown.

[0093] 13, through electrodes 62a, 62b, 62c, and 62d are also arranged in the center of the four control blocks 620a, 620b, 620c, and 620d, so that forbidden regions 61a, 61b, 61c, and 61d are arranged to surround through electrodes 62a, 62b, 62c, and 62d.

[0094] This can also be said to mean that the through silicon via regions of the four control blocks 620a, 620b, 620c, and 620d are adjacent to each other. With this arrangement, the through silicon via region can be made smaller overall compared to when the through silicon vias are arranged apart from each other.

[0095] 13, the circuits in control blocks 620a and 620b adjacent to each other in the X direction are arranged symmetrically. Furthermore, the circuits in control blocks 620a and 620c adjacent to each other in the Y direction are arranged symmetrically. However, the wiring within the circuits, the direction of signal flow, the order of inputs and outputs, and so on do not have to be symmetrical as long as the circuit arrangement is symmetrical. As a result, circuits with similar functions are adjacent between adjacent control blocks 620, so that well separation bands can be omitted and area efficiency can be improved.

[0096] These four control blocks 620a, 620b, 620c, and 620d are used as a unit, and the control blocks 620 are repeatedly arranged in the same arrangement in the X and Y directions to form the control circuit section 610. In this case, the through silicon via regions 60 of the control blocks 620 adjacent to each other in the X direction across the repeating unit are adjacent to each other. For example, in FIG. 13, to the right of the control block 620b, there is adjacent a control block having the same arrangement as the control block 620a. The through silicon via regions of these control blocks are also adjacent to each other. This allows for further improvement in area efficiency.

[0097] Figure 14 shows an example of the specific configuration of yet another control block 640. In control block 640, the same components as those in control block 620 in Figure 11 are given the same reference numerals and descriptions thereof will be omitted. Control block 640 differs from control block 620 in that control circuit 80 extends from the top edge to the bottom edge of control block 640.

[0098] Fig. 15 is a schematic diagram showing the layout relationship of a plurality of control blocks 640. In the example of Fig. 15, four adjacent control blocks 640a, 640b, 640c, and 640d are shown.

[0099] 15, through electrodes 62a, 62b, 62c, and 62d are also arranged in the center of four control blocks 640a, 640b, 640c, and 640d, so that forbidden regions 61a, 61b, 61c, and 61d are arranged to surround through electrodes 62a, 62b, 62c, and 62d.

[0100] This can also be said to mean that the through silicon via regions of the four control blocks 640a, 640b, 640c, and 640d are adjacent to each other. With this arrangement, the through silicon via region can be made smaller overall compared to when the through silicon vias are arranged apart from each other.

[0101] 15, the circuits of control blocks 640a and 640b adjacent to each other in the X direction are arranged symmetrically to form the control circuit section 610. Furthermore, the circuits of control blocks 640a and 640c adjacent to each other in the Y direction are arranged symmetrically to each other in the top and bottom. However, the wiring within the circuits, the direction of signal flow, the order of inputs and outputs, and so on do not have to be symmetrical as long as the circuit arrangement is symmetrical. As a result, circuits with similar functions are adjacent between adjacent control blocks 640, so that well separation bands can be omitted and area efficiency can be improved.

[0102] These four control blocks 640a, 640b, 640c, and 640d are used as a unit, and the control blocks 640 are repeatedly arranged in the same arrangement in the X and Y directions to form the control circuit section 630. Note that between adjacent control blocks 640 that straddle a repeating unit, the through silicon via regions 60 are separated by a control circuit 80. On the other hand, the control circuits 80 of four control blocks 640 that are adjacent to each other vertically are adjacent to each other. This can be said to increase the degree of freedom in designing the control circuit 80.

[0103] Figure 16 shows an example of a specific configuration of yet another control block 660. In the control block 660, the same components as those in the control block 620 of Figure 11 are given the same reference numerals and descriptions thereof will be omitted.

[0104] In the control block 660, the junction 30, the conversion section 40, the well isolation zone 72, the control circuit 80, and the through-electrode region 60 are arranged in this order from the top to the bottom, and extend from the left to the right. The through-electrode 62 of the through-electrode region 60 extends from the left to the right along the bottom edge of the control block 620, and is covered by the forbidden region 61.

[0105] Fig. 17 is a schematic diagram showing the layout relationship of a plurality of control blocks 640. In the example of Fig. 17, four adjacent control blocks 660a, 660b, 660c, and 660d are shown.

[0106] 17, through electrodes 62a, 62b, 62c, and 62d are also arranged in the center of the four control blocks 660a, 660b, 660c, and 660d, so that forbidden regions 61a, 61b, 61c, and 61d are arranged to surround through electrodes 62a, 62b, 62c, and 62d.

[0107] This can also be said to mean that the through silicon via regions of the four control blocks 660a, 660b, 660c, and 660d are adjacent to each other. With this arrangement, the through silicon via region can be made smaller overall compared to when the through silicon vias are arranged apart from each other.

[0108] The circuits of the control blocks 660a and 660c adjacent in the Y direction are arranged symmetrically above and below. However, as long as the circuit arrangement is symmetrical, the wiring within the circuit, the direction of signal flow, the order of inputs and outputs, etc. do not have to be symmetrical. As a result, circuits with similar functions are adjacent between adjacent control blocks 660, so well separation bands can be omitted and area efficiency can be improved.

[0109] In the example of FIG. 17, two control blocks 660a, 660c adjacent in the Y direction are used as a unit, and control blocks 660 are repeatedly arranged in the same arrangement in the X and Y directions to form a control circuit section 650. That is, two control blocks 660a, 660c adjacent in the Y direction form a unit circuit group. In this case, the through silicon via regions 60 are adjacent to each other between the control blocks 660 adjacent in the X direction across the repeating unit. For example, in FIG. 17, the through silicon via regions are also adjacent to each other between the control blocks 660a, 660b. This can further improve area efficiency.

[0110] Fig. 18 is a schematic diagram showing the details of the arrangement of the through electrodes 62. Fig. 18 shows, as an example, the arrangement of the through electrodes 62 in the arrangement relationship of the plurality of control blocks 220 in Fig. 9, but can also be applied to the other control blocks 620, 640, 660.

[0111] In the example of Fig. 18, each of the control blocks 220a, 220b, 220c, and 220d has one through electrode 62a, 62b, 62c, and 62d. Furthermore, as shown in an enlarged view in the lower right of Fig. 18, the through electrode 62d has an in-plane signal line 65d and a connection part 66d that connects the signal line 65d to another circuit. The same applies to the other through electrodes 62a, 62b, and 62c.

[0112] The through-electrode 62a is used to transmit and receive signals from the corresponding control block 220a to and from the image processing unit 310. Similarly, the through-electrodes 62b, 62c, and 62d are used to transmit and receive signals from the corresponding control blocks 220b, 220c, and 220d to and from the image processing unit 310. This allows signals to be transmitted and received from the control blocks 220a, 220b, 220c, and 220d to and from the image processing unit 310 simultaneously and / or independently of each other.

[0113] Alternatively, the through electrodes 62a, 62b, 62c, and 62d may be shared by the control blocks 220a, 220b, 220c, and 220d. In this case, for example, the control blocks 220b, 220c, and 220d may use the through electrodes 62a, 62b, 62c, and 62d in a time-division manner.

[0114] Each of the control blocks 220a, 220b, 220c, and 220d may have two or more through electrodes 62a, 62b, 62c, and 62d.

[0115] Fig. 19 is a schematic diagram showing the details of the arrangement of the through electrodes 62. Fig. 19 shows, as an example, the arrangement of the through electrodes 62 in the arrangement relationship of the plurality of control blocks 220 in Fig. 9, but can also be applied to the other control blocks 620, 640, 660.

[0116] 19, one through electrode 62 is provided for four control blocks 220a, 220b, 220c, and 220d. That is, one through electrode 62 is provided for each unit circuit group.

[0117] In this case, for example, the control blocks 220a, 220b, 220c, and 220d may use the through electrodes 62 in a time-division manner. According to the example of Fig. 19, it is sufficient to arrange fewer through electrodes than the number of control blocks, so that the through electrode region 60 can be made smaller and area efficiency can be improved. Note that the number of shared through electrodes 62 is not limited to one, and may be two or three.

[0118] In any of the above embodiments, the discharge unit 124 of the pixel 112 may be omitted. Furthermore, the transfer unit 123 may also be omitted, in which case the storage unit 125 will no longer function as a floating diffusion. Furthermore, the storage unit 125 and pixel output unit 127 may be shared with other pixels. Furthermore, the pixel 112 may be composed of multiple photoelectric conversion units 104 and first transfer units 123. Furthermore, "adjacent" means arranged next to each other, and includes cases where they are in contact with each other and cases where they are not necessarily in contact with each other.

[0119] 20 is a block diagram showing an example of the configuration of an imaging device 500 according to an embodiment. The imaging device 500 includes an imaging element 400, a system control unit 501, a drive unit 502, a photometry unit 503, a work memory 504, a recording unit 505, a display unit 506, a drive unit 514, and a photographing lens 520. While an example including the imaging element 400 will be described, an imaging element 800 may be included instead.

[0120] The photographing lens 520 guides the subject light beam incident along the optical axis OA to the image sensor 400. The photographing lens 520 is composed of a group of multiple optical lenses, and focuses the subject light beam from the scene near its focal plane. The photographing lens 520 may be an interchangeable lens that can be attached to and detached from the image capture device 500. Note that in FIG. 20, the photographing lens 520 is represented by a single virtual lens placed near the pupil.

[0121] The driver 514 drives the photographing lens 520. In one example, the driver 514 changes the focus position by moving the optical lens group of the photographing lens 520. The driver 514 may also drive an iris diaphragm in the photographing lens 520 to control the amount of subject light entering the image sensor 400.

[0122] The drive unit 502 has a control circuit that executes charge accumulation control such as timing control and area control of the image sensor 400 in accordance with instructions from the system control unit 501. Furthermore, the operation unit 508 receives instructions from the photographer using a release button or the like.

[0123] The image sensor 400 passes pixel signals to an image processing unit 511 in the system control unit 501. The image processing unit 511 generates image data by performing various image processes using the work memory 504 as a workspace. For example, when generating image data in JPEG file format, a color video signal is generated from a signal obtained using the Bayer array, and then compression processing is performed. The generated image data is recorded in a recording unit 505 and converted into a display signal, which is then displayed on a display unit 506 for a preset time.

[0124] The photometry unit 503 detects the luminance distribution of a scene prior to a series of shooting sequences for generating image data. The photometry unit 503 includes, for example, an AE sensor with approximately one million pixels. The calculation unit 512 of the system control unit 501 receives the output of the photometry unit 503 and calculates the luminance of each region of the scene.

[0125] The calculation unit 512 determines the shutter speed, aperture value, and ISO sensitivity in accordance with the calculated luminance distribution. The image sensor 400 may also serve as the photometry unit 503. The calculation unit 512 also executes various calculations for operating the imaging device 500. A part or all of the drive unit 502 may be mounted on the image sensor 400. A part of the system control unit 501 may be mounted on the image sensor 400. Furthermore, the image sensor 800 may be used instead of the image sensor 400.

[0126] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0127] It should be noted that the execution order of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0128] 20 pixel driving unit, 30 junction unit, 40 conversion unit, 50, 326 signal output unit, 60, 360 through electrode area, 61, 361 prohibited area, 62, 64, 362, 364 through electrode, 70, 370 local I / O, 80 control circuit, 100 first substrate, 104 photoelectric conversion unit, 110 pixel unit, 112 pixel, 120 pixel block, 121 load current source, 122, 162, 237, 238, 352, 354 signal line, 123 transfer unit, 124 discharge unit, 125 storage unit, 126 reset unit, 127 pixel output unit, 128 amplifier unit, 129 selection unit, 130 power line, 132 ground line, 141 transfer control line, 142 discharge control line, 143 Reset control line, 145 selection control line, 147 transfer selection control line, 152 bump, 160 I / O section, 200 second substrate, 210, 610, 630, 650 control circuit section, 220, 620, 640, 660 control block, 230, 330, 603 peripheral circuit section, 234 global drive section, 236 ADC setting section, 310 image processing section, 320 processing block, 322 signal input section, 324 processing section, 400 image sensor, 500 image sensor, 501 system control section, 502 drive section, 503 photometry section, 504 work memory, 505 recording section, 506 display section, 508 operation section, 511 image processing section, 512 calculation section, 514 drive section, 520 photographing lens, 800 image sensor

Claims

[Claim 1] a first substrate having a pixel portion in which a first photoelectric conversion unit that converts light into an electric charge and a second photoelectric conversion unit that converts light into an electric charge are arranged; a second substrate laminated together with the first substrate, the second substrate having a control circuit section in which are arranged: a first control block including a first conversion section that converts a first signal based on the charge converted by the first photoelectric conversion section into a digital signal, and a first through electrode section in which a first through hole of a first through electrode is formed, through which a first digital signal converted from the first signal to a digital signal in the first conversion section is output; and a second control block including a second conversion section that converts a second signal based on the charge converted by the second photoelectric conversion section into a digital signal, and a second through electrode section in which a second through hole of a second through electrode is formed, through which a second digital signal converted from the second signal to a digital signal in the second conversion section is output; a third substrate, which is laminated together with the first substrate, and has a third through electrode portion in which a third through hole of a third through electrode electrically connected to the first through electrode is formed, and a fourth through electrode portion in which a fourth through hole of a fourth through electrode electrically connected to the second through electrode is formed, a processing portion that processes the first digital signal output from the third through electrode and the second digital signal output from the fourth through electrode, and a fifth through electrode portion in which a fifth through hole for a fifth through electrode is formed, through which at least one digital signal of the first digital signal processed by the processing portion and the second digital signal processed by the processing portion is output; Equipped with the processing unit is disposed at a position overlapping the control circuit unit in a direction in which the second substrate and the third substrate are stacked, the fifth through electrode portion is disposed outside the processing portion on the third substrate; Image sensor.

Images