Heterogeneous integration of components onto compact devices using moire based metrology and vacuum based pick-and-place

Abstract

To provide a method for assembling a subset of a plurality of elements with a distribution selectively picked from a source wafer using pick-and-place.SOLUTION: A method for bonding one or more elements 202 onto a silicon substrate 205, where the one or more elements are physical components to be used for pick-and-place, includes the steps of: picking up the one or more elements in a state in which a vacuum superstrate 1004 remains attached to the one or more elements; arranging the picked-up one or more elements on a liquid of a product substrate using a moire based measuring method for alignment of the one or more elements on the product substrate; and securely attaching the picked-up one or more elements onto the product substrate using direct bonding.SELECTED DRAWING: Figure 11

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Provisional Patent Application No. 62 / 438,952, filed December 23, 2016, entitled "Highly Parallel Nano-Precision Pick and Place Method for Microscale Materials," which is incorporated herein by reference in its entirety.

[0002] (Technical field) The present invention relates generally to heterogeneous integration of components (e.g., electronic, optical, and energy storage devices), and more particularly to heterogeneous integration of components into compact devices using moiré-based metrology and vacuum-based pick-and-place. [Background technology]

[0003] Cutting-edge consumer and industrial applications are driving the need for devices that contain a wide variety of integrated, yet heterogeneous, functional elements. Depending on the specific application, these elements may be electronic, optical, photonic, fluidic, nanomechanical elements, or even biological systems-on-a-chip. These are ideally integrated on semiconductor substrates, such as silicon, for subsequent packaging using standard semiconductor packaging techniques and integration into larger devices.

[0004] Semiconductor fabrication is not currently suitable for heterogeneous integration. It is impractical to process so many different and incompatible fabrication steps on a single semiconductor substrate. Pick-and-place is a natural solution for short-time scale heterogeneous integration. While many technologies have previously demonstrated this for micrometer-sized components, none of the technologies have the capabilities to combine highly parallel pick-and-place, arbitrary component distribution, and nanometer-precision placement. Summary of the Invention [Means for solving the problem]

[0005] In one embodiment of the present invention, a method for assembling heterogeneous components comprises assembling a subset of elements having a selective distribution from a source wafer using pick and place, the method further comprising placing the selectively selected subset of elements on a product wafer.

[0006] (claim25) Another embodiment of the invention is a material characterized by its size, which varies from sub-10 μm on a side to over 1 mm on a side, and which is used to design the base layer portion of an application specific integrated circuit (ASIC) system on a chip (SoC).

[0007] (claim28) In another embodiment of the present invention, an application specific integrated circuit (ASIC) system on a chip (SoC) is designed and manufactured using materials selectively picked from a source wafer and assembled onto a product wafer.

[0008] ] (claim31) In a further embodiment of the present invention, an electronic design automation (EDA) methodology for designing material constructed ASIC SoCs comprises a combination of in-house developed software integrated with existing commercial EDA solutions used to perform post-Mask ECO integration, and / or pre-CTS, and / or CTS, and / or route, and / or sign-off analysis flows.

[0009] The features and technical advantages of one or more embodiments of the present invention have been outlined above in order that the detailed description of the present invention that follows may be better understood. Additional features and advantages of the present invention will be described below which form the subject of the claims of the invention. [Brief explanation of the drawings]

[0010] A better understanding of the present invention can be obtained when the following detailed description is considered in conjunction with the following drawings. [Figure 1]1A-1C are diagrams illustrating an assembly process according to an embodiment of the present invention. [Figure 2] FIG. 1 illustrates a silicon-on-insulator (SOI) wafer with three devices according to an embodiment of the present invention. [Figure 3] 1 is a flowchart illustrating a method for performing etching and encapsulation according to an embodiment of the present invention. [Figure 4] 4A-4E are cross-sectional views illustrating a process of performing etching and encapsulation using the steps shown in FIG. 3 according to an embodiment of the present invention. [Figure 5] 10A-10C illustrate a process for reducing the extent of the sacrificial layer by etching from the underside of the wafer, according to an embodiment of the present invention. [Figure 6] 10A-10C illustrate a process for reducing the extent of a sacrificial layer by etching from the top surface of a wafer, according to an embodiment of the present invention. [Figure 7] 10A-10C illustrate a process for reducing the extent of a sacrificial layer by etching from the top surface of the wafer while doping the sacrificial layer, according to an embodiment of the present invention. [Figure 8] 1 is a flowchart illustrating a method for utilizing wafer backgrinding in wafer dicing using bulk etch process concepts to facilitate subsequent pick and place in accordance with an embodiment of the present invention. [Figure 9] 9A-9C are cross-sectional views illustrating a process of utilizing wafer backgrinding for wafer dicing using the steps illustrated in FIG. 8 according to an embodiment of the present invention. [Figure 10] 10A-10C illustrate a process for picking up an element according to an embodiment of the present invention. [Figure 11] 10A-10C illustrate another process for picking up an element according to an embodiment of the present invention. [Figure 12] 10A-10C illustrate another process for picking up a single element while avoiding an etching process according to an embodiment of the present invention. [Figure 13] 11 is a flowchart illustrating a method for picking up a single element using the wafer of FIG. 10 according to an embodiment of the present invention. [Figure 14] 14A to 14E are cross-sectional views illustrating a process for picking up an element using the steps shown in FIG. 13 according to an embodiment of the present invention. [Figure 15] 9A-9C are flowcharts illustrating a method for picking up an element using the background superstrate of FIGS. 8 and 9A-9C according to an embodiment of the present invention. [Figure 16] 16A to 16E are cross-sectional views illustrating a process for picking up an element using the steps illustrated in FIG. 15 according to an embodiment of the present invention. [Figure 17] FIG. 1 illustrates a multi-layer design of the selective pick-and-place superstrate discussed in concept FP-2, according to an embodiment of the present invention. [Figure 18] FIG. 1 illustrates a selective pick-and-place superstrate with custom pickup layer 1 in concept FP-2 according to an embodiment of the present invention. [Figure 19] FIG. 1 illustrates a multi-layer design for bulk pick and place as discussed in concept FP-3, according to an embodiment of the present invention. [Figure 20] 1 is a flowchart illustrating a method for aligning, positioning, and bonding multiple elements in accordance with an embodiment of the present invention. [Figure 21] 21A-21C are cross-sectional views illustrating the process of aligning, positioning, and bonding multiple elements using the steps illustrated in FIG. 20 according to an embodiment of the present invention. [Figure 22] FIG. 1 illustrates an optimal element utilization strategy according to an embodiment. [Figure 23] FIG. 10 illustrates a dummy element for solving the variable height problem, according to an embodiment of the present invention. [Figure 24] FIG. 2 illustrates one possible configuration of a material-configurable SoC according to an embodiment of the present invention. [Figure 25] FIG. 1 illustrates a general logic material configuration according to an embodiment of the present invention. [Figure 26] FIG. 1 illustrates a standard cell-based logic circuit material configuration according to an embodiment of the present invention. [Figure 27] FIG. 1 illustrates an EDA methodology for implementing logic circuit design for a material configurable ASIC, according to an embodiment of the present invention. [Figure 28] FIG. 1 illustrates Algorithm 1 for implementing material generation based on a greedy mapping approach according to an embodiment of the present invention. [Figure 29] FIG. 2 illustrates Algorithm 2, which uses optimal graph matching techniques and k-Means clustering to perform material design generation, according to an embodiment of the present invention. [Figure 30] FIG. 10 illustrates Algorithm 3, which implements material placement and selection based on a greedy mapping approach, according to an embodiment of the present invention. [Figure 31] FIG. 10 illustrates Algorithm 4 for implementing optimal graph matching-based material selection and placement according to an embodiment of the present invention. [Figure 32] FIG. 1 illustrates Algorithm 5, which presents a post-mask clock tree synthesis algorithm, according to an embodiment of the present invention. [Figure 33] FIG. 10 illustrates Algorithm 6, which implements post-mask, post-CTS, and post-route buffer insertion according to an embodiment of the present invention. [Figure 34] FIG. 1 illustrates one possible memory material configuration according to an embodiment of the present invention. [Figure 35] FIG. 1 illustrates one possible configuration of an IO material, according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0011] As mentioned in the Background section, cutting-edge consumer and industrial applications are driving the need for devices with a variety of integrated but heterogeneous functional elements. Depending on the specific application, these elements may be electronic, optical, photonic, fluidic, nanomechanical, or even biological systems-on-a-chip. Semiconductor fabrication is currently unsuitable for heterogeneous integration. It is impractical to process so many different and incompatible fabrication steps on a single semiconductor substrate. Pick-and-place is a natural solution for short-time scale heterogeneous integration. While many technologies have previously demonstrated this for micrometer-sized components, none of these technologies have the geometry to combine highly parallel pick-and-place, arbitrary component distribution, and nanometer-precision placement.

[0012] The present invention relates generally to the heterogeneous integration of variable components, such as electronic, optical, and energy storage devices, which is desirable for many consumer, medical, and scientific applications. Pick-and-place based methods are ideally suited for applications where individual components can be manufactured separately and then assembled onto a product substrate. However, current pick-and-place technology does not allow for assembly with nanoscale precision. The present invention presents a novel technique that uses moiré-based metrology and vacuum-based pick-and-place to achieve sub-100 nm, and in some embodiments, sub-25 nm or sub-10 nm alignment in assembly.

[0013] The present invention provides the ability to assemble multiple elements as small as tens of micrometers to several millimeters, and / or highly parallel assembly (10 per step). 2 From 10 6 The present invention provides a complete assembly process with the capability to perform 3D fabrication of semiconductor devices (devices) and / or assemble to as close as 10 nm (3σ alignment error) or 5 nm (3σ alignment error) with placement accuracy significantly better than 100 nm.

[0014] In one embodiment, the present invention provides parallel nanometer-precision deterministic assembly. In one embodiment, heterogeneous functional devices fabricated on semiconductor-on-insulator wafers, including silicon-on-insulator (SOI) wafers, are picked up and then placed (and reliably attached) on target substrates with nanometer-scale precision. Here, functional device (or simply device) refers to the smallest physical unit used for pick-and-place. Such devices are likely to contain a collection of sub-elements. For example, a 1 mm x 1 mm photonic device may contain multiple photonic sub-elements and certain specialized electronic devices within it. In one embodiment, the semiconductor includes a substrate made of Si, Ge, SiGe, GaAs, InP, etc. Device fabrication on such wafers is well established, and a buried oxide (BOx) layer enables a method for selectively transferring multiple devices from specific locations. Multiple types of functional devices, such as transistors, optical devices, and MEMS, each fabricated on separate wafers, may be integrated.

[0015] In one embodiment, a commonly available assembly sequence is as follows: 1. Etching and Encapsulation 2. Bulk etch process (to facilitate subsequent pick and place) 3. Element pickup 4. Align and temporarily attach (multiple) elements to the product substrate 5. Join 6. Repeat steps 3 to 5 until the product wafer is fully assembled. These are explained in more detail below.

[0016] A simplified sequence of steps is shown in Figure 1, which is a diagram illustrating an assembly process according to an embodiment of the present invention. The entire assembly process leverages the sub-5 nm alignment capabilities of a moiré-based scheme to achieve parallel nanometer-precision deterministic assembly. Further discussion of the entire assembly process can be found in Euclid E. Moon, "Interferometric-Spatial-Phase Imaging for sub-Nanometer Three-Dimensional Positioning," Massachusetts Institute of Technology, 2004, which is incorporated herein by reference in its entirety.

[0017] The source wafer needs to undergo several pre-processing steps before it is ready for pick-and-place. For example, an encapsulation layer is needed to protect sensitive elements from chemical damage. Additionally, holes may need to be etched to access buried sacrificial layers before pick-and-place.

[0018] Referring now to FIG. 2, FIG. 2 illustrates a silicon-on-insulator (SOI) wafer 201 with three devices 202, according to an embodiment of the present invention. The SOI wafer 201 is comprised of layered silicon 203, insulator (sacrificial) layer 204, and silicon 205 substrate. In one embodiment, a device 202 is the most common form of "material" and is comprised of a transistor layer 206, a wiring (interconnect) layer 207, and a dielectric layer 208. Furthermore, as used herein, device 202 includes the silicon layer 203 of the SOI wafer 201. The device may or may not have any functionality by itself, but when assembled with other devices 202 and possibly additional wiring layers 207 and dielectric layers 208, it may be used to create a working ASIC. Additionally, a front-end high-resolution device layer with high mask costs may be present within a device 202. This is to amortize the high mask costs (for the high-resolution device layer) over the fabrication of the various ASIC devices.

[0019] In one embodiment, an element 202 can vary in size from 10 μm per side to about 100 μm or more per side. In another embodiment, an element 202 can vary in size from sub-1 μm per side to about 100 μm or more per side. The size of all components 202 may or may not be the same across an ASIC design.

[0020] The assembly techniques described above may need to be modified to suit the specific requirements of ASIC fabrication. The modified process and mechanical design concepts follow the following general guidelines: (1) assembly accuracy (sub-100 nm 3σ) is paramount, (2) assembly time is critical (but not more critical than assembly accuracy), and (3) particle-generating processes must be avoided.

[0021] The entire assembly process, starting with a device wafer and ending with a product wafer, can be divided into the following sequence of steps: (1) device wafer pre-processing (device etching and encapsulation), (2) bulk etch processing (to facilitate subsequent pick-and-place), (3) device pick-up, (4) device alignment to the product substrate, (5) device placement and bonding, and (6) repeating steps 3 through 5 until the product wafer is fully assembled.

[0022] In one embodiment, two pre-processing steps may need to be performed before multiple devices are ready for pick and place: (1) the device wafer obtained from the foundry has successive transistor, metal, and dielectric layers in which device boundary and buried oxide (BOx) access holes need to be etched, and (2) the exposed device layers need to be encapsulated to make them etchant resistant.

[0023] Reference is now made to Figure 3, which is a flow chart of a method 300 for performing etching and encapsulation according to an embodiment of the present invention. Figures 4A-4E are cross-sectional views illustrating a process for performing etching and encapsulation using the steps shown in Figure 3 according to an embodiment of the present invention.

[0024] 3 in conjunction with Figures 4A-4E, in step 301, lithography and etching of the dielectric layer 208 of one element 202 is performed as shown in Figures 4A and 4B. In one embodiment, as shown in Figures 4A and 4B, a masking material 401 is used to prevent etching of certain portions of one element 202.

[0025] In step 302, the elements 202 and silicon 203 of the SOI wafer are covered with an encapsulation layer 402, as shown in FIG. 4C.

[0026] In step 303, lithography and etching of the structure of FIG. 4C is performed to form access holes (e.g., Box access holes), as shown in FIGS. 4D and 4E. In one embodiment, a masking material 403 is used to prevent etching of the elements 202. Access holes 404 (Box access holes) are formed, as shown in FIG. 4E.

[0027] Further discussion regarding method 300 follows.

[0028] 4A-4E, the wafer has device boundaries 405 (see FIG. 4E) and access holes 404 etched into the buried sacrificial layer. The device boundary etch is necessary to separate the individual devices 202, while the access hole etch may or may not be necessary depending on subsequent processing.

[0029] In general, the encapsulation layer 402 must be resistant to etchants (specifically HF), be particle-free, and be semiconductor-grade. Additionally, the encapsulation layer 402 may help absorb and limit mechanical scratching damage to the encapsulated device. Two potential materials are aluminum oxide (Al2O3) and amorphous carbon. Al2O3 is known to be HF-resistant and can be deposited using common vacuum deposition processes such as atomic layer deposition (ALD) and chemical vapor deposition (CVD). Additionally, it is widely used as a high-k (high dielectric constant) cap layer in CMOS. Amorphous carbon is substantially HF-resistant, and semiconductor-grade chemical vapor deposition (CVD) processes are known for amorphous carbon. Amorphous carbon is primarily used as a hard mask in multiple patterning. The hard mask material must be resistant to plasma etching chemistries, especially those containing fluorine radicals. A discussion of etch stop materials for release from vapor phase HF etching can be found in Bakke et al., “Etch Stop Materials for Release by Vapor HF Etching,” 16 MicroMechanics Europe Workshop, Goteborg, Sweden, 2005, which is incorporated herein by reference in its entirety.

[0030] In one embodiment, the width of the access hole is slightly smaller than the bounding trench to ensure that the encapsulation layer 402 is etched away on the sidewalls during the etching of the access hole.

[0031] Chemical etching is a fairly slow process. For example, gas-phase HF-based etching of sacrificial oxide on SOI wafers is performed at a rate of approximately 60 nm / min at room temperature and several micrometers / min at elevated temperatures. At this rate, etching through several micrometers of underlying oxide can take many hours. To help improve overall assembly throughput, a bulk etch is performed to partially strip the underlying sacrificial layer. Although etching an individual wafer may take a long time, overall throughput can remain high by processing many wafers in a single batch.

[0032] Various possible bulk etch sequences are now described.

[0033] In one embodiment, one such concept is to reduce the extent of the sacrificial layer by etching from underneath the wafer.

[0034] 5 illustrates a process for reducing the extent of a sacrificial layer by etching from the underside of a wafer, according to an embodiment of the present invention. We start with a source wafer with a boron layer 501 and a nitrogen layer 502 embedded under the sacrificial layer 204. The boron acts as an etch stop for the subsequent MACE process 503. The boron acts as a barrier to prevent boron from diffusing into the device layers.

[0035] Now, a metal-assisted chemical etch (MACE) 503 can be performed to etch through the bulk silicon from the underside of the wafer.

[0036] The buried and sacrificial layers can be etched using an anisotropic etching technique such as DRIE504.

[0037] The width of the etched holes is smaller than the width of the elements, which allows the elements to remain attached to the bulk silicon with a fine mesh of oxide that is easy to selectively remove during pick and place.

[0038] Alternatively, in one embodiment, multiple small through-holes are etched as opposed to one large hole per element, which, if present, helps to provide greater mechanical stability.

[0039] In one embodiment, a second concept is to reduce the extent of the sacrificial layer by etching from the top surface of the wafer instead of drilling holes through the bottom surface. Etching hundreds of micrometers of silicon can be an extremely slow process, even when performed in bulk. To solve this, individual devices are modified to have access holes to the buried sacrificial layer. These provide access to the sacrificial layer from the top surface of the source wafer, effectively reducing the etching distance. The placement and geometry of these holes can be modified depending on the size of the functional device, the required etch rate, and throughput requirements. The access holes also provide a columnar array in the sacrificial layer after etching, which provides better mechanical support for the individual devices.

[0040] FIG. 6 illustrates a process for reducing the extent of a sacrificial layer by etching from the top surface of a wafer, according to an embodiment of the present invention. In one embodiment, we start with an encapsulated source wafer in which the device boundaries 405 and access holes 404 have already been etched. The access hole arrangement shown in FIG. 6 is exemplary; other arrangements can be used. Note that the access holes 404 are etched from start to finish, but the device boundaries 405 are not. This is to prevent etching of the sacrificial layer at the boundary. The boundary oxide is used as a seal to prevent etchant from leaking onto the adjacent elements 202 during pick-and-place.

[0041] Here, the sacrificial layer 204 can be etched using an etchant such as vapor-phase HF (vHF). vHF is a commonly used etchant for BOx etching in MEMS applications. This is preferred because the reactants (HF) and products are in the vapor phase, and the etchant overcomes many challenges, such as stiction. The etch is timed to leave a columnar structure beneath the etched element.

[0042] Finally, the device boundary 405 can be etched using standard lithography and etching techniques.

[0043] In another embodiment, a third concept (similar to the second concept) is to reduce the extent of the sacrificial layer by etching the underlying oxide from the top of the wafer while doping the sacrificial layer, as shown in Figure 7. Figure 7 illustrates a process for reducing the extent of the sacrificial layer by etching from the top of the wafer while doping the sacrificial layer, according to an embodiment of the present invention.

[0044] The third concept is similar to the second concept in that the oxide etch is performed from the top surface, using the access holes 404 to speed up the etching process. The difference between the second and third concepts is that the underlying oxide is doped, with a doping profile such that the dopant concentration is highest at the top surface of the sacrificial layer 204 and lowest at the bottom. Such a doping profile leads to a corresponding change in etch rate through the depth of the sacrificial layer 204, which subsequently causes the formation of pyramidal posts (tethers) 701. As will be discussed later, these pyramidal tethers 701 can facilitate the pick-and-place step.

[0045] Wafer backgrinding is a widely used technique in wafer packing and 3D integration. In one embodiment, wafer backgrinding can be used to complement various bulk etch processes.

[0046] For example, in the first concept described above, where the extent of the sacrificial layer is reduced by etching the underside of the wafer, a wafer backgrinding process can be used to reduce the required MACE depth.

[0047] Alternatively, as a way to speed up the HF etch in concepts 2 and 3 described above, the wafer can be thinned down to the sacrificial layer (see Figures 8 and 9A-9C). Now that a larger area of ​​oxide is exposed, the etch time of the subsequent HF etch would be much lower than concepts 2 and 3. This would ideally serve as an alternative to the pick-and-place process of concept FP-3 (discussed below).

[0048] 8, which is a flow chart illustrating a method 800 of utilizing wafer backgrinding for wafer dicing using the concept of a bulk etch process to facilitate subsequent pick and place, according to an embodiment of the present invention. Figures 9A-9C are cross-sectional views illustrating a process of utilizing wafer backgrinding for wafer dicing using the steps shown in Figure 8, according to an embodiment of the present invention.

[0049] Referring now to Figure 8 in conjunction with Figures 9A-9C, in step 801, one element 202 is inverted and attached to a glass carrier wafer 901 via a (commercially available) laser-release adhesive 902, as shown in Figure 9A.

[0050] In step 802, back grinding of the device substrate 205 is performed, as shown in FIG. 9B.

[0051] In step 803, the sacrificial layer 204 is etched using an acid such as HF.

[0052] It is deemed appropriate at this point to discuss various concepts related to element pickup.

[0053] In one concept (referred to as concept "FP-1"), the basic principle is to selectively release the individual elements by etching away the sacrificial layer while holding the individual elements using a vacuum superstrate. The advantage of this concept is that there is minimal mechanical disturbance involved during the pick-up process.

[0054] Figure 10 illustrates the process of picking up a single element, according to an embodiment of the present invention. Since the wafer of Figure 5 already has through-holes 405, the etchant is directed using a wafer chuck 1001. A vacuum is pulled through superstrate 1004. The vacuum channel 1002 and the etchant channel 1003 are controlled using MEMS-based valves.

[0055] 11 illustrates another process for picking up a single element, according to an embodiment of the present invention. The superstrate 1004 in this case must have vacuum holes 1101 and etchant holes 1102 (which can also be controlled using MEMS valves). As mentioned previously, the sacrificial layer around the periphery of the single element acts as a seal against etchant contamination of the adjacent elements 202.

[0056] In the second concept (referred to herein as concept "FP-2"), the basic principle here is to mechanically pull the devices off the source wafer using a vacuum superstrate.

[0057] This concept is ideally applied to the wafer of Figure 7. Material strength calculations indicate that with 100 μm elements and pyramidal tethers with tip diameters of ∼300 nm, vacuum suction should be more than sufficient to break these tethers, thus avoiding the time-consuming etching process. Figure 12 illustrates another process for picking up a single element while avoiding the etching process, according to an embodiment of the present invention.

[0058] In the third concept (referred to herein as concept "FP-3"), the basic principle is to release multiple elements by etching away a sacrificial layer while maintaining a vacuum, similar to FP-1. The difference here is that all elements are released at once and transferred to an intermediate glass substrate with a UV-release adhesive, as discussed in conjunction with Figures 13 and 14A-14E. This is done to further speed up the subsequent selective release process. Selective release is performed by exposing the underside of one element to UV light. Selective exposure can be achieved using a light modulation device such as a DMD (digital micromirror device). Further discussion of DMDs can be found in Texas Instruments, "DMD 101: Introduction to Digital Micromirror Device (DMD)," 2013, which is incorporated herein by reference in its entirety.

[0059] Referring to Figure 13, Figure 13 is a flow chart illustrating a method 1300 for picking up a single element using the wafer of Figure 10 according to an embodiment of the present invention. Figures 14A-14E are cross-sectional views illustrating a process for picking up a single element using the steps shown in Figure 13 according to an embodiment of the present invention.

[0060] Referring now to Figure 13 in conjunction with Figures 14A-14E, in step 1301, a bulk pick and place superstrate 1004' is attached to the multiple elements 202 as shown in Figures 14A and 14B.

[0061] In step 1302, the silicon substrate 205 and pyramidal posts (tethers) 701 are etched as shown in Figure 14C.

[0062] In step 1303, the silicon 203 of the SOI wafer 201 is attached to an intermediate glass substrate 1401 via a spin-coated UV release adhesive (eg, glue) 1402, as shown in FIG. 14D.

[0063] In step 1304, the underside of one element 202 is exposed to UV light from a light modulation device (e.g., DMD) 1403 to selectively release the element 202. A selective pick-and-place superstrate 1004'' is used to pick out one element 202.

[0064] In a fourth concept (herein referred to as concept "FP-4"), the concept is applied to the background superstrate of Figures 8 and 9A-9C. The basic principle, similar to FP-3, is to transfer multiple elements to an intermediate glass substrate with a UV release adhesive, as discussed in conjunction with Figures 15 and 16A-16E.

[0065] Referring to Figure 15, Figure 15 is a flow chart illustrating a method 1500 for picking up a single element using the background superstrate of Figures 8 and 9A-9C according to an embodiment of the present invention. Figures 16A-16E are cross-sectional views illustrating a process for picking up a single element using the steps shown in Figure 15 according to an embodiment of the present invention.

[0066] Now referring to Figure 15 in conjunction with Figures 16A to 16E, in step 1501, the carrier wafer is inverted and attached to an intermediate glass substrate 1601 via a spin-coated UV release adhesive (e.g., glue) 1602, as shown in Figures 16A and 16B.

[0067] In step 1502, the carrier wafer is detached by removing adhesive 902 using laser radiation 1603, as shown in Figures 16C and 16D.

[0068] In step 1503, a selective pick and place superstrate 1004'' is attached to the multiple elements 202, as shown in Figure 16E.

[0069] In step 1504, the bottom surface of one element 202 is exposed to UV light from a light modulation device (e.g., DMD) 1604 to selectively release one element 202. A selective pick-and-place superstrate 1004'' is used to pick out one element 202.

[0070] Vacuum-based pick-and-place superstrates are a critical part of the entire assembly process. They ensure that assembly precision is maintained as multiple devices are transferred from the source wafer to the product substrate.

[0071] The superstrate may be designed with the following factors in mind: 1. Pick-up force and breaking strength of functional elements 2. Parasitic movement 3.Topography control 4. Surface wear and deterioration of flatness 5.Air flow and suction design 6. Thermal Management—The superstrate can be temperature controlled to maintain optimal etchant and air temperatures. Additionally, a temperature controller can be used to induce slight deformations in the superstrate to correct registration errors. Such temperature control can be implemented using a variety of methods, including Peltier coolers and DMD-based modulation of IR sources. Further discussion of thermal management can be found in Moon et al., “Thermally Controlled Alignment for Wafer-Scale Lithography,” Journal of Micro / Nanolithography, MEMS, and MOEMS 12(3), 031109, August 28, 2013, which is incorporated herein by reference in its entirety. 7. Distortion control 8. Superstrate-element adhesion properties 9. Pickup Location Programmability—Selective pick-and-place superstrates can have an embedded layer of MEMS valves. Large arrays of MEMS valves for fluid flow control have been previously demonstrated in research papers. Alternatively, custom pickup layers can be used for each specific pickup configuration. Further discussion of pickup location programmability can be found in Vandelli et al., “Development of a MEMS Microvalve Array for Fluid Flow Control,” Journal of Microelectromechanical Systems 7.4, 1998, pp. 395-403, which is incorporated herein by reference in its entirety. 10. Fabrication - Superstrates are fabricated by bonding multiple layers that are fabricated separately. Such techniques have previously been used to fabricate wafer chucks with complex micron-scale features.

[0072] 17-19 illustrate various possible designs of pick-and-place superstrates. FIG. 17 illustrates a multi-layer design of the selective pick-and-place superstrate discussed in concept FP-2, according to an embodiment of the present invention. FIG. 18 illustrates a selective pick-and-place superstrate with custom pickup layer 1 in concept FP-2, according to an embodiment of the present invention. FIG. 19 illustrates a multi-layer design of the bulk pick-and-place discussed in concept FP-3, according to an embodiment of the present invention.

[0073] In one embodiment, a water-based temperature control technique is used to control distortion of the superstrate.

[0074] The selective pick-and-place superstrate can have an embedded layer of MEMS valves. Large arrays of MEMS valves for fluid flow control have been previously reported. Alternatively, a custom pickup layer can be used for each specific pickup configuration, as shown in Figure 18.

[0075] 17, pick and place superstrate 1700 includes layer 1 1701, which includes vacuum pads 1702 and channels 1703. Superstrate 1700 further includes layer 2 1704, which includes MEMS valves 1705 and vacuum manifolds 1706. Superstrate 1700 additionally includes layer 3 1707, which is temperature controllable and includes thermal actuators 1708 (different shading represents respective temperature gradients).

[0076] 18, pick and place superstrate 1800 includes layer 1 1801 attached to layer 2 1802 using a vacuum. Superstrate 1800 further includes layer 2 1802 bonded to layer 3 1803. Layer 2 1802 includes vacuum manifold 1804. Superstrate 1800 further includes layer 3 1803, which is temperature controllable and includes vacuum manifold 1805.

[0077] 19, pick and place superstrate 1900 includes layer 1 1901 and layer 2 1902. Layer 2 1902 includes vacuum manifold 1903. Superstrate 1900 further includes layer 3 1904, which is temperature controllable and may include HF manifold 1905. Additionally, superstrate 1900 includes thermal actuator 1906 (different shading represents respective temperature gradients).

[0078] This is one possible implementation of a superstrate. The vacuum pickup mechanism consists of a silicon plate with an array of 250 nm diameter vacuum holes. The backside of the plate is connected to a vacuum pump. Thermally conductive materials such as Si also have a low thermal expansion coefficient (~3 ppm / °C), allowing the use of water-cooling techniques for alignment control. The silicon plate can be fabricated by spin-coating photoresist onto a silicon wafer and then exposing the UV wafer to focused light from a UV-compatible DLP micromirror array to create the precise vacuum pattern desired in the assembly process. The silicon wafer can then be thoroughly etched using deep reactive ion etching to create vacuum holes in the silicon plate. The vacuum hole array uses individually addressable electrostatic MEMS actuators at each hole to open and close valves attached to that hole. The vacuum holes on the superstrate may or may not be arranged in a grid pattern substantially identical to that of the final product wafer.

[0079] The MEMS valve consists of a ~100 nm thick cantilever suspended 50 nm above the 250 nm hole on the backside of the pickup plate. Electrodes are patterned around each hole on the backside of the plate to create an electrostatic actuator used to pull the cantilever beam down to the surface and close the hole against its vacuum port. The entire surface of the vacuum plate is coated with an anti-stick coating to prevent the cantilever from sticking to the plate's surface after the electrostatic charge is removed. In this setup, each actuator is individually addressable using the same method developed for electrostatically actuated micromirror arrays. In this method, CMOS memory circuits are patterned under the bottom electrodes and used to set the actuator's on / off state. The state of each memory circuit is set using a parallel bus to address each pixel. Once the memory circuits are set, a clock pulse is applied to the entire system to set the on / off state of each actuator based on the on / off value of that actuator's associated memory circuit. Each actuator then remains in that state until the memory circuits are reset and a new clock pulse is applied.

[0080]

[0043] Reference is now made to Figure 20, which is a flow chart illustrating a method 2000 for aligning, positioning, and bonding multiple elements according to an embodiment of the present invention. Figures 21A-21C are cross-sectional views illustrating a process for aligning, positioning, and bonding multiple elements using the steps illustrated in Figure 20 according to an embodiment of the present invention.

[0081] Referring now to Figure 20 in conjunction with Figures 21A-21C, in step 2001, a product wafer 2101 is optionally spin coated with one part 2102 of a two-part adhesive at the beginning of a pick and place cycle, as shown in Figure 21B.

[0082] In step 2002, as shown in Figures 21A and 21B, just prior to the placement step, an inkjet dispenses a second liquid of adhesive 2103 at specific locations where multiple elements 202 will be placed. A placement accuracy of less than 10 μm is typically achieved using an inkjet, which is sufficient for elements 202 larger than 25 μm on a side. Further improvement in inkjet drop placement can be achieved using one or more of the following techniques: (1) reducing the gap between the inkjet nozzle plate and the substrate surface to well below 1 millimeter, and (2) reducing the scanning speed to well below 1 m / s.

[0083] In step 2003, the layered silicon 203 and the device 202 attached to the superstrate 1004 are placed on the adhesive 2103 (or 2102 and 2103) as shown in FIG. 21B.

[0084] In step 2004, the multiple elements 202 are detached from the superstrate 1004, as shown in Figure 21C.

[0085] An alternative to the spin-coating technique described above is to use two inkjets that simultaneously dispense the two components of the two-component adhesive. The inkjets can be programmed to dispense the two components so that there is at least partial overlap between the droplets. This overlap can occur before device assembly. Alternatively, the device assembly step can prompt the droplets to mix.

[0086] As shown in Figure 21A, coarse alignment is first performed as the selected elements 202 are brought closer to the product wafer 2101. Figure 21A shows the superstrate 1004 with alignment marks 2104 and observation window 2105. This is followed by fine alignment, which can be performed once an element 202 contacts the (submerged) adhesive 2103 (or 2102 and 2103). As shown in Figure 21B, the fine alignment uses alignment marks 2106 on the substrate 2101. The vacuum superstrate 1004 remains attached to the elements 202 until the adhesive reaches its gel point, after which the elements 202 are securely attached to the substrate 2101.

[0087] In one embodiment, fine alignment is performed using moire alignment marks patterned on the substrate (mark 2104) and on the product substrate (mark 2106). This type of alignment system can achieve sub-5 nm alignment accuracy. One advantage of using a liquid adhesive as the bonding agent is that it allows for submerged alignment, which ensures minimal topographical variation of the superstrate 1004 during the placement step. Further discussion of alignment can be found in Cherala et al., “Nanoscale Magnification and Shape Control System for Precision Overlay in Jet and Flash Imprint Lithography,” IEEE Trans. Mechatronics, Vol. 20, No. 1, 2015, pp. 122-132, which is incorporated herein by reference in its entirety.

[0088] Two-component adhesives ideally have a low cure time at room temperature or slightly elevated temperatures. Epoxy hardeners such as Ancamine® 2678 have a thin film set time of ∼2 seconds at room temperature and a low viscosity of 35 cPs that allows application using an inkjet nozzle. Uncured adhesives generally have viscosities ranging from 1 to 100 cPs. Optimal adhesive formulations may require blending of multi-component epoxy resins and hardeners, with accelerators if required to reduce set times.

[0089] Additionally, the adhesive should exhibit shrinkage during the curing process to bring the elements 202 closer to the product substrate 2101 after curing, thus ensuring that the superstrate 1004 does not experience unwanted interfacing with elements 202 already present on the product substrate 2101. In addition to adhesive shrinkage, adjusting the thickness of the superstrate also avoids unwanted superstrate interference with materials. Calculations show that a 4 mm thick SiC superstrate layer simply supported on four materials spaced 30 mm (maximum die size) apart will not sag more than 1 nm in the center under its own weight.

[0090] Alternatively, UV-curable adhesives can be used to temporarily attach the elements to the product substrate, which forces the superstray to be made from UV-transparent materials such as sapphire (Al2O3) or UV-transparent SiC (such SiC wafers are available from sources including Cree, Inc.).

[0091] Once the product substrate is fully populated with multiple devices, material deposition / coating steps can also be performed using vacuum-based chemical vapor deposition processes such as sputtering, atomic layer deposition (ALD), and chemical vapor deposition to further secure the multiple devices to the substrate.

[0092] Alternatively, the anodic bonding step can replace the adhesive process entirely.

[0093] Once the first set of multiple elements is assembled, the assembly process can be repeated for each additional type of element. Multilayer applications can also add intervening layers between each element of the multiple elements. These intervening layers incorporate carbon nanotube (CNT) forests and through-vias for mechanical adhesion and electrical, thermal, and optical connections.

[0094] As feature sizes have decreased, the cost of masks to pattern these features has skyrocketed. The cost of a full set of masks is approximately $1.5M for the 90nm lithography node and can reach $2M for the 65nm lithography node (according to some estimates, mask writing time increases as a power of five as feature sizes decrease). Additionally, the increased complexity of large designs increases the number of design re-spins. These two factors significantly increase the non-recurring engineering costs (NRE) of standard cell ASICs, which can be prohibitively expensive for low- to medium-volume applications such as custom chips for equipment, scientific, and medical applications. Field-programmable gate arrays (FPGAs) offer an acceptable solution for rapid prototyping and ultra-low-volume applications, but are not generally viewed as ASIC replacements due to their highly inefficient space utilization and less-than-desired timing.

[0095] A discussion of the novel application of the above-mentioned vacuum-based assembly techniques to fabricate ASICs using mass-produced material logic circuits in limited numbers is provided below. This results in the sharing of mask costs for sub-100 nm feature sizes across multiple ASIC designs, reducing the cost of each individual design. The concept of building ASICs using repeating logic feedstocks builds on previous work that showed that ASICs constructed with via / metal-structured structural materials can achieve space utilization and spatiality approaching that of cell-based ASICs. However, the proposed technology offers significant choice in terms of material type and configuration.

[0096] The assembly techniques described above are directly applicable to the problem of ASIC fabrication using discontinuous materials (where one element 202 is the material). Processing and mechanical design concepts should follow the following general guidelines: (1) assembly accuracy (sub-100 nm 3σ) is paramount, (2) assembly time is critical (but not more critical than assembly accuracy), and (3) particle-generating processes should be avoided.

[0097] Because the same material wafer is used to provide material for multiple ASIC designs, one issue that arises is that of material utilization. Referring to FIG. 22, FIG. 22 illustrates an optimal element utilization strategy, according to an embodiment. ASIC design 2, which requires a specific distribution of material 1 (different from the distribution of ASIC design 1), cannot be fully implemented using only the existing material in material wafer 1. A pick-and-place strategy is proposed in which a stockpile of material wafers for each material type is maintained. First, the most available material is used from the most degraded material wafer (wafer 1.1 in FIG. 22). Next, the process continues using the most available material from the least degraded wafer (wafer 1.2 in FIG. 22) until the product substrate is fully implemented with one type of material. At a given point, the most degraded wafer is either ignored or saved for possible scrap utilization when it has too little material (below a threshold) to be efficiently used. A scrap utilization tool is similar in construction to the pick-and-place tool described above, but instead of transferring material to a product wafer, it rearranges the material.

[0098] Materials from different source wafers generally have different material thicknesses. Assembly of such materials can cause problems with unwanted superstrate interference and lack of planarity. Avoiding unwanted superstrate interference can be achieved by several techniques. Two exemplary techniques are listed below. 1. Ensure that every fabricated material is slightly taller (e.g., 5 to 10 nm) than the previously fabricated material. (This results in a lack of planarity, which is described separately below.) The ability to guarantee a pre-specified distinct fabrication height for each material can be achieved by the following exemplary method. a) Dummy Material. For the three material case, see FIG. 23. FIG. 23 shows a dummy material 2301 ("Material 2") that solves the variable height problem, according to an embodiment of the present invention. d " and "Material 3 d ) showing the different possible thicknesses { t1< t2< …. < t n For the general case with n materials with thickness { (t n - t1+1) > (t n - t2+2) > … > (t n -t (n-1) + (n-1) )}, but with small thicknesses {1>2> … >} to avoid unwanted superstrate interference in areas other than where assembly is planned for a given step. (n-1) Additionally, to avoid unwanted superposition interference, assembly must occur in a specific arrangement, which requires that materials or dummy materials are always assembled such that a given material being assembled has its top surface higher than all other already placed materials or dummy materials in all assembly steps. b) In one embodiment, varying the thickness of the underlying adhesive layer as described above can be achieved by using separate pre-calculated total volumes deposited during the inkjet step under each material. c) Preparing various material source wafers with pre-calculated distinct thicknesses of semiconductor layers over the buried sacrificial layer. d) Etch rectangular trenches into the product wafer such that the trenches have lateral dimensions slightly larger than the corresponding material dimensions (e.g., 0.25 micrometers) and the etch depth at each material location is independently selected to ensure that the top surface of the corresponding material ultimately reaches a predetermined height including the material and its adhesion layer. 2. Ensure that all assembled materials have substantially the same height after assembly. However, adhesive curing typically involves a volumetric shrinkage of 2 to 10%, so each assembled material will have a slightly higher height before the adhesive curing step. As an example, an adhesive with 10% shrinkage and an initial thickness of 50 nm (see the discussion above regarding adhesive formulations) will provide a gap of ∼5 nm in the uncured state (see the discussion above) to allow for accurate positioning of the materials in the uncured state. The exemplary techniques 1.a) through 1.d) above, used independently or in combination, also allow each material to have substantially the same height after assembly.

[0099] The methodology discussed in Method 1 may require an optional planarization step to ensure that subsequent processing can be accurately achieved (e.g., photolithography depth of focus constraints). To solve this planarization problem, inkjet-based planarization techniques can be used. Alternatively, chemical mechanical polishing (CMP) processes can also be used to achieve the same goal.

[0100] Dimension is I d ×w d Consider an exemplary ASIC die with dimensions = 10mm x 10mm. Each material has a side length of l f = 100 μm. The number of materials per die is n f = 10,000. n ftyp = 20 kinds of materials, each of which requires n ftyp = 10 material wafers (as described above). This results in approximately 200 pick-and-place steps, each transferring an average of 50 materials per die. n per wafer dpw Assuming there are =300 dies, this equates to an average of 15,000 materials transferred per pick-and-place step overall.

[0101] Below, we discuss the EDA (Electronic Design Automation) design and CAD (Computer-Aided Design) flows required to design a material-configurable ASIC system-on-chip (SoC). Typically, an ASIC SoC contains billions of transistors optimally arranged to meet performance / speed, area, and power specifications. To efficiently design an ASIC SoC, i.e., to meet a design specification with a low turnaround time to market (TAT), third-party EDA CAD tools exist to simplify the design process. Similar to standard cell-based ASIC SoCs, material-configurable ASICs also utilize these EDA tools.

[0102] The EDA flow for configurable ASICs attempts to reuse most of the existing EDA CAD tools. However, there are few in-house developed EDA processing steps in the overall design flow. However, the in-house solutions can be easily integrated into the existing EDA tools to ensure seamless deployment of end-to-end solutions.

[0103] As described above, the material consists of transistor layers, wiring layers, and dielectric layers. The selection and placement of materials is optionally performed to suit a design specification, as discussed in the following sections. A material cell includes a substrate layer (composed of transistors, standard cells, etc.) and n metal layers (where n>=1) that form the wiring. The material may include an internal power grid structure including rings, straps, stripes, follow pins, etc. to provide power to the transistors and other components. A material-configurable SoC may include different types of materials, as described below. However, this list may not be comprehensive, and the types of materials should not be limited to these. a. Logic circuit materials: microscale circuits used to implement and design logic circuit design elements in SoCs b. Memory Materials: Microscale circuits used to implement and design memory design elements (such as SRAM) in SoCs c. IO materials: microscale circuits used to implement and design IO circuits (such as SRAM) in SoCs d. Macrocell Materials: Microscale circuits used to implement, design, and interface macrocells in SoCs e. Mixed Materials: Microscale circuits containing design elements present in other types of materials

[0104] A typical SoC, as described above, contains different types of materials. Each type of material can be instantiated multiple times. The design flow allows for heterogeneous integration of different types of materials. Heterogeneous means that these materials can be fabricated using different materials, such as Si and GaAs, different technology nodes, and memory technologies. Furthermore, different types of materials, such as logic materials, memory materials, and IO materials, may have varying thickness values. This can be due to differences in the number of metal layers, pitch values, technology nodes, etc. This type of SoC also allows for the integration of hard and soft intellectual property (IP) blocks, similar to standard cell ASIC flows.

[0105] FIG. 24 illustrates one possible configuration of a material-configurable SoC according to an embodiment of the present invention. It includes multiple logic circuit materials (1) each measuring 50 μm by 50 μm, multiple memory materials (2) each measuring 70 μm by 70 μm, multiple IO materials (3) each measuring 100 μm by 100 μm, cell materials (4) and hard IP blocks (5) each measuring 70 μm by 70 μm, and a soft IP block (6) measuring 50 μm by 50 μm. Furthermore, each type of material has a different number of metal layers and thicknesses. The logic circuit materials have metal 3 (M3) as the metal top layer, the IO materials have M11 as the metal top layer, and the hard IP blocks have M6 as the metal top layer. Material counts and arrangements may vary depending on design requirements. Different shadings of the same type of material indicate different design configurations of a particular type. For example, logic circuit material shade 2401 differs in design from material shade 2402. Similarly, other types of materials may have different configurations.

[0106] It is deemed appropriate to discuss logic circuit material design and its EDA methodology. First, the structure of logic circuit materials is described. Next, an overview of the EDA design methodology and EDA design steps for logic circuit design using existing EDA tools and in-house solutions is provided. Next, a new in-house solution developed in this flow is described, followed by a discussion of the new material design and material placement algorithms used to design and place materials in the SoC. Next, the new algorithms implemented in the back-end design phase, namely, clock tree synthesis (CTS), post-CTS, and post-route optimization, are discussed.

[0107] FIG. 25 illustrates a general logic circuit material configuration according to an embodiment of the present invention. Logic circuit materials may be composed of any combination of the following components: standard cells (1), transistors (2), gate arrays (3), macrocells (4), physical dedicated cells (5), scan cells (6), etc. These components can be connected using wiring (7) or spare open transistors (8) or spare cells (9) depending on design requirements. Logic circuit materials are composed of n metal layers (where n >= 1). Connectivity between components may or may not belong to the same timing path or group. There are a finite number of input and output ports (10). Additional ports (11) may exist around the periphery of the material to accommodate feed-through signals. The material may be composed of an internal power grid to provide power to transistors, cells, etc. The power grid may be composed of any combination of rings, straps, stripes, follow pins, etc. Voltage levels may be different in different regions of the material, forming different voltage islands (12).

[0108] FIG. 26 illustrates a standard cell-based logic circuit material configuration according to an embodiment of the present invention. It consists of only standard cells (1) implemented using the 32 nm technology node. All standard cells are open, i.e., they can be treated as spare gate seas. To power the standard cells, follow pins (2) are routed to connect power from power straps (routed using higher metal layers) to the standard cell power pins or follow pins. The M2A2 EDA flow discussed below utilizes these types of logic circuit materials. FIG. 26 shows the layout of this type of logic circuit material, generated using Cadence Innovus tools.

[0109] FIG. 27 illustrates an EDA methodology for implementing logic circuit design for a material-configurable ASIC, according to an embodiment of the present invention. The EDA flow includes multiple EDA processing steps that are uniquely fixed to achieve a goal. The flow includes steps such as design production, material selection, placement, and partial synthesis, which were developed in-house and highlighted in shading 2701. Design items highlighted in shading 2702 are items with existing commercial EDA solutions and are reused in this flow. Certain design steps, highlighted in shading 2703, that were developed to achieve the solution using existing EDA solutions and in-house solutions are also present in this flow. The steps described in this flow may not be fully comprehensive or described in full detail, and minor changes can be made to different designs to achieve the best QoR.

[0110] An overview of the design steps of the EDA flow is presented below. A detailed explanation of each step is further discussed below. In material design generation, a limited number of finite materials, n (where n >= 1), are generated based on design data from multiple standard cell-based ASIC SoCs. The solution is developed in-house by implementing various algorithmic techniques, such as greedy-based mapping, unsupervised learning, and graph matching techniques. Once the materials are generated, they serve as a library for the flow and are referred to herein as "microscale modular assembly ASICs" (M2A2).

[0111] In the M2A2 EDA flow, an input standard cell-based design may be partitioned into multiple modules to improve the physics and timing awareness of Engineering Change Order (ECO) synthesis. Design partitioning can be achieved using any of the standard partitioning algorithms, such as FM-Cut or minimum flow. Materials are then selected and randomly placed into the design / modules to meet functionality and performance specifications. This solution can be developed in-house and implemented using various techniques, such as greedy-based mapping, unsupervised learning, and graph matching techniques. This design may be partially synthesized with spare cells, if desired. The material design, placement, and design data are then processed to generate collaterals in standard industry formats: netlist files and design exchange format (DEF) files. These files are input into an ECO synthesis tool to perform full synthesis. Once the design data in the form of netlist and DEF files is generated, an industry-standard ECO tool called Cadence Conformal ECO is used to perform post-mask ECO synthesis. This enables design synthesis using pre-placed spare cells for material-configurable SoCs. A patch netlist file is generated that is loaded into a Cadence Place & Route (P&R) tool called Innovus to generate a synthesis netlist. All of the design steps described so far form the front-end design phase of the M2A2 EDA flow. It is noteworthy that, unlike traditional standard cell-based ASIC flows where synthesis is performed first and then placement, the M2A2 EDA flow performs simultaneous optimal placement and synthesis, i.e., placement and partial synthesis reactions are performed together before full ECO synthesis.

[0112] The front-end design phase is followed by the back-end finalization phase. In the back-end design phase, pre-clock tree synthesis (pre-CTS) optimization is first performed using the Cadence P&R tool Innovus. This optimization includes pin swapping and cell swapping to reduce wire length and delay. Once the pre-CTS optimization is performed, the clock tree is constructed. Today, no commercial EDA solution performs post-mask CTS, i.e., clock tree construction while keeping the underlying cells frozen or fixed. To perform post-mask CTS, a Cadence Innovus tool is first used to construct the clock tree by inserting cells into the desired area of ​​the SoC. The desired area is the area where spare clock tree buffers, inverters, and clock gating cells will be placed. An in-house solution is then developed to map or swap the newly added clock tree cells with the existing spare cells placed in the design. This can be performed using greedy mapping techniques, graph matching techniques, etc. Once the clock tree is constructed without changing the underlying layer, routing is performed using the Cadence Innovus tool. To improve performance metrics, a post-CTS and post-route buffer insertion solution is developed in-house that preserves post-mask characteristics. In existing commercial EDA tools, buffer insertion does not occur when all cells are frozen or fixed. Thus, this solution improves design metrics such as performance in terms of circuit speed.

[0113] Once the design is synthesized and routed, sign-off analysis is performed to analyze the design performance and compare it to the specification. Sign-off analysis, such as timing sign-off, physical verification, and power checks, is performed using standard commercial EDA tools. Performance mismatches can be fed back to the material placement or back-end stages, depending on the nature of the issues observed by the sign-off tool. Once the QoR is met, the design is functionally verified and a GDSII file is generated, which is the final deliverable of the EDA design stage for casting.

[0114] It is deemed appropriate at this point to discuss a materials design generation algorithm. Algorithm 1, presented in Figure 28, implements a greedy mapping-based materials generation method in accordance with an embodiment of the present invention. This algorithm designs materials using an iterative greedy mapping method, which is easy to implement but not optimal in performance.

[0115] Algorithm 2, as shown in Figure 29, performs material design generation using optimal graph matching techniques and k-means clustering (a category of algorithms in machine learning known as unsupervised learning) according to an embodiment of the present invention. This material design algorithm utilizes multiple techniques, such as a min-cost bipartite graph matching technique, logic restructuring, k-means clustering, placement legalization, and timing aware net and cell weighting, to achieve an optimal solution at each step of the algorithm to obtain the best material configuration.

[0116] It is deemed appropriate here to discuss material placement, selection, and partial synthesis algorithms. Algorithm 3, presented in Figure 30, and Algorithm 4, presented in Figure 31, implement material selection and placement based on a greedy mapping approach and optimal graph matching, respectively, according to embodiments of the present invention.

[0117] Algorithm 3 selects and places materials in a design based on an iterative greedy mapping of windows sorted by importance factors along with available materials. Iterative methods do not result in an optimal solution. To achieve the optimal mapping, Algorithm 4 was developed. It uses optimal graph matching techniques to select, place, and partially synthesize the material design. This algorithm utilizes multiple techniques, including minimum-cost bipartite graph matching, logic circuit reconfiguration, placement validation, and timing-aware net cell weighting, to achieve a good solution at each part of the algorithm to obtain the optimal placement of materials in the design.

[0118] We now discuss post-mask back-end design optimization and post-mask clock tree synthesis. Algorithm 5, shown in Figure 32, presents a post-mask clock tree synthesis algorithm according to an embodiment of the present invention. This algorithm can be divided into two phases. Phase I includes steps #1 to #4, while Phase II includes the remaining steps #5 to #20. In Phase I, the algorithm utilizes a commercial EDA solution developed by Cadence to build the clock tree by running the tool to insert cells into desired regions / sites. The desired sites are those regions on the design that have spare CTS cells. An in-house solution is then developed, presented in Phase II, which preserves post-mask properties while optimizing clock tree skew and insertion delay. The algorithm maps the CTS additional cells on the design with the spare cells placed in the design. This can be implemented using a greedy mapping approach or a minimum-cost bipartite graph matching technique.

[0119] FIG. 33 illustrates Algorithm 6, which implements post-mask, post-CTS, and post-route buffer insertion according to an embodiment of the present invention. Commercial state-of-the-art EDA tools do not perform post-mask buffer insertion. In this algorithm, timing paths are first analyzed. Next, clock and data path optimization is performed based on spare cell availability in preferred areas of the SoC. The decision to insert a spare buffer when a timing path is violated is determined by calculating the cost associated with the timing path before and after buffer insertion. Buffers are inserted if they improve timing. Similarly, clock path optimization reduces skew and insertion delay. This algorithm optimizes performance using algorithmic techniques such as minimum-cost bipartite graph matching to obtain an optimal solution for all timing paths.

[0120] We now discuss the design of memory materials. Memory materials are microscale circuits used to implement on-chip SRAM memory on SoCs. A typical SRAM includes a bit cell array with word and bit lines, sense amplifiers, column and row decoders, timer circuits, and other peripheral circuits. Memory materials may include any combination of these memory design elements. Memory materials can be self-contained with bit arrays and control circuits, or may consist of only bit cell arrays, or only control circuits such as sense amplifiers, timers, and column and row decoders. It is important to note that memory materials can be implemented using different technologies, and heterogeneous integration of these materials is supported in the design flow.

[0121] Figure 34 illustrates one possible memory material configuration according to an embodiment of the present invention. Memory material configuration 3400 includes basic memory design elements such as SRAM cell bit array (1), bit lines (2), word lines (3), IO cells (4), timer circuits (5), sense amplifiers (6), and decoders (7).

[0122] We now discuss IO material design. IO material is a microscale circuit design element dedicated to IO operation. It includes any combination of the following components: IO cells, signal IO buffers, power pads, IO pads, ESD and decapacitance circuits, etc. These components may or may not be connected via wiring. The material may include n metal layers (where n>=1). Depending on the designer's needs, there may also be programmable wiring in the IO material to connect to one of the possible design elements.

[0123] Figure 35 illustrates one possible configuration of IO material 3500, according to an embodiment of the present invention. IO material 3500 includes IO buffers (1), IO pads (2), which can be for signal or power ground, IO cells (3), traces (4), programmable traces (5), and ESD / decap circuitry (6).

[0124] M2A2-based SoCs allow for the integration of external IP blocks. These IP blocks can be hard IP blocks or soft IP blocks. Hard IP blocks are fully designed, don't-touch blocks. In contrast, soft IP blocks require design changes. These design changes can be implemented using macro materials. The components of the macro material depend on the type of macro cells used in the design. Macro material cells can also be used for seamless integration of macro cells with other components in the design, such as logic circuits, memory, etc. These materials can include basic design elements with any number of metal layers. This may include programmable interconnects for more general use of the material.

[0125] As mentioned above, existing pick-and-place techniques cannot achieve nanoscale precision assembly. However, by utilizing the present invention, nanoscale precision assembly can be achieved using a vacuum-based pick-up mechanism in conjunction with sub-nm precision Moire alignment technology, resulting in high-precision parallel assembly of materials.

[0126] The description of various embodiments of the present invention has been presented for purposes of illustration and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the disclosed embodiments. The language used herein has been selected to best explain the principles of the embodiments, practical applications, or technical improvements of the technology found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. A method of bonding one or more devices to a substrate, comprising: the one or more elements are physical components used in pick and place; picking up the one or more elements with a vacuum superstrate attached to the one or more elements; placing the picked-up element(s) on a liquid on the product substrate using Moire metrology to align the element(s) to the product substrate; firmly attaching the picked-up element or elements to the product substrate using direct bonding; A method comprising:

2. The method of claim 1 , wherein the one or more elements are of different sizes ranging from sub-10 micrometers on a side to one millimeter or more on a side.

3. The method of claim 1 , wherein the placement accuracy of the one or more elements is either sub-25 nanometers, sub-10 nanometers, or sub-5 nanometers.

4. The method of claim 1 , wherein the placement of the one or more elements is performed by performing a coarse alignment followed by a fine alignment.

5. The method of claim 1 , wherein temperature control techniques are used to control distortion of the one or more elements.

6. 10. The method of claim 1, wherein the method of assembling the one or more elements on the product substrate is used to construct an application specific integrated circuit (ASIC).

Images