Inspection system and inspection method

Abstract

To provide a technique for reducing an inspection cost in an inspection system for inspecting a plurality of substrates.SOLUTION: An inspection system includes a plurality of inspection cells to inspect a substrate. The inspection includes a plurality of types of test resources. A part of the inspection cells and the other inspection cells of the inspection cells have mutually different types of test resources among the test resources. Thus, the test resources to inspect a plurality of substrates can be reduced so as to reduce an inspection cost in the inspection system.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to an inspection system and an inspection method. [Background technology]

[0002] Patent Document 1 discloses an inspection system (substrate inspection system) equipped with multiple inspection cells (cells) for inspecting substrates. This type of inspection system is equipped with multiple types of test resources used for inspecting substrates in all inspection cells, and it is possible to inspect substrates in approximately parallel in each inspection cell. However, when substrate inspection is viewed in units of multiple test resources, there are test resources with low utilization rates. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2017-112387 Summary of the Invention [Problem to be solved by the invention]

[0004] The present disclosure provides a technique that can reduce the cost of inspection in an inspection system that inspects multiple substrates. [Means for solving the problem]

[0005] According to one aspect of the present disclosure, an inspection system is provided that includes a plurality of inspection cells that inspect substrates, the inspection including a plurality of types of test resources, and some of the plurality of inspection cells and other inspection cells having mutually different types of test resources from the plurality of types of test resources. [Effects of the Invention]

[0006] According to one aspect, the cost of inspection can be reduced in an inspection system that inspects multiple substrates. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a diagram illustrating an overall configuration of an inspection system according to an embodiment of the present disclosure. [Figure 2] 2 is a schematic cross-sectional view of the inspection system of FIG. 1 taken along the horizontal direction. [Figure 3] FIG. 2 is a schematic enlarged vertical cross-sectional view showing an inspection cell. [Figure 4] Fig. 4(A) is a diagram illustrating test resources for wafer inspection, and Fig. 4(B) is a diagram illustrating each inspection cell in one cell row in an inspection system according to a reference example. [Figure 5] Fig. 5(A) is a diagram showing each test cell in one cell row in the test system according to the first embodiment, and Fig. 5(B) is a perspective view showing an example of the arrangement of each test resource in the test system according to the first embodiment. [Figure 6] Fig. 6(A) is a diagram showing an inspection sequence and each inspection cell in a cell row according to a first modified example, and Fig. 6(B) is a diagram showing an inspection sequence and each inspection cell in a cell row according to a second modified example. [Figure 7] 4 is a flowchart showing an inspection method of the inspection system according to the first embodiment. [Figure 8] Fig. 8(A) is a diagram showing an inspection state of an inspection cell of an inspection system according to another reference example. Fig. 8(B) is a diagram showing an inspection state of an inspection cell of an inspection system according to a second embodiment. Fig. 8(C) is a diagram illustrating an inspection sequence of a burn-in test. [Figure 9] Fig. 9(A) is a diagram showing an example of the movement of the test head in the burn-in test, and Fig. 9(B) is a timing chart showing each test cell in the burn-in test. [Figure 10] FIG. 11 is a schematic cross-sectional view taken along the horizontal direction of an inspection system according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and redundant explanations may be omitted.

[0009] FIG. 1 is a diagram showing the overall configuration of an inspection system 100 according to an embodiment of the present disclosure. FIG. 2 is a schematic cross-sectional view of the inspection system 100 of FIG. 1 taken along the horizontal direction. As shown in FIGS. 1 and 2, the inspection system 100 is configured as a multi-inspection system capable of simultaneously inspecting multiple substrates using multiple inspection cells 10. An example of a substrate inspected by the inspection system 100 is a wafer W having multiple semiconductor devices, such as LSIs and semiconductor memories, which are devices to be inspected. Note that the substrate is not limited to the wafer W, and may be a carrier on which semiconductor devices are arranged, a glass substrate, a single chip, an electronic circuit board, or the like.

[0010] For example, the inspection system 100 has a cell row in which six inspection cells 10 are arranged in the horizontal direction (X-axis direction), and four of these cell rows are stacked in the vertical direction (Z-axis direction), resulting in a total of 24 inspection cells 10 arranged in a matrix. It goes without saying that the number and arrangement of the inspection cells 10 are not particularly limited. For example, the inspection system 100 may have a configuration in which multiple inspection cells 10 are arranged in the horizontal direction rather than stacked. Furthermore, the inspection system 100 may have expandability that allows the number of inspection cells 10 to be increased or decreased after the system is installed.

[0011] The inspection system 100 includes a housing 11 that houses the matrix-shaped inspection cells 10 together, forming a cell tower. The inspection system 100 also includes a control device 90 inside the housing 11 that controls the operation of the inspection system 100. The control device 90 may also be provided outside the housing 11.

[0012] The housing 11 of the inspection system 100 is divided into a loading / unloading area 12 for loading and unloading the wafer W, a transport area 13 for transporting the wafer W, and an inspection area 14 having multiple inspection cells 10 for actually inspecting the wafer W.

[0013] The loading / unloading area 12 is provided with a load port 15, an aligner 16, etc. A container C, such as a FOUP (Front Opening Unified Pod) that can accommodate multiple wafers W, is set in the load port 15. Meanwhile, the aligner 16 adjusts the attitude of the wafer W (aligning the center position, circumferential position, etc.) before transferring the wafer W to the inspection cell 10. Note that the loading / unloading area 12 or the transfer area 13 may be provided with a loader device (not shown) or the like that transfers the wafer W into and out of the container C.

[0014] The transfer area 13 has one or more transfer devices 18 capable of transferring wafers W. The transfer device 18 includes a moving mechanism (not shown) that is movable in three dimensions (X-axis direction, Y-axis direction, and Z-axis direction), and moves between the transfer area 12 and the inspection area 14 in the housing 11 under the control of the control device 90.

[0015] The transfer device 18 holds the mounting table 18a at a standby position (not shown), and under the operation of the loader device, places the wafer W on the mounting table 18a from the container C of the load port 15, and transfers the wafer W to the target inspection cell 10 in the inspection area 14. The transfer device 18 also transfers the wafer W placed on the mounting table 18a from one inspection cell 10 to another inspection cell 10. Furthermore, the transfer device 18 transfers the wafer W after inspection from the inspection area 14 to the transfer area 12 and stores it in the container C. Note that the transfer device 18 may transfer the probe card 22 between the transfer area 12 and the inspection area 14 when replacing the probe card 22 in the inspection cell 10, which will be described later.

[0016] As described above, the inspection area 14 includes a plurality of inspection cells 10 and an imaging device 19 that captures an image of the wafer W to be transported to the inspection cell 10. For example, the imaging device 19 is provided for each of a plurality of cell rows and is configured to be movable in the horizontal direction. The imaging device 19 captures an image of the wafer W to be transported to the target inspection cell 10 under the control of the control device 90. The control device 90 adjusts the position of the wafer W relative to the inspection cell 10 using the imaging information of the imaging device 19.

[0017] 3 is a schematic enlarged longitudinal cross-sectional view of the inspection cell 10. As shown in FIG. 3, each inspection cell 10 is configured by stacking a tester 20, an interface 21, and a probe card 22. The tester 20 is supported via a base 21a of the interface 21, which is connected to a frame within the housing 11. The probe card 22 is removably attached to the lower surface of the interface 21. The inspection cell 10 inspects the wafer W by electrically connecting the tester 20 and the wafer W via the interface 21 and the probe card 22.

[0018] The probe card 22 has a disk-shaped main body 221, a large number of electrodes 222 arranged on the upper surface of the main body 221, and a plurality of contact probes 223 connected to each electrode 222 and protruding downward from the lower surface of the main body 221. Each contact probe 223 electrically contacts the electrode pads and solder bumps of each semiconductor device on the wafer W transported by the transport device 18. Each contact probe 223 can, for example, contact all of the semiconductor devices on the wafer W at once, thereby enabling each semiconductor device to be tested simultaneously.

[0019] The interface 21 has a base 21a and a pogo frame 21b supported by the base 21a and having a plurality of through holes 21h near the center. A pogo block 211 consisting of a number of pogo pins is inserted into each through hole 21h. The top surface of the pogo block 211 is electrically connected to the tester 20, while the bottom surface is in electrical contact with a number of electrodes 222 of the probe card 22.

[0020] The interface 21 also has a vacuum mechanism 25 that creates a vacuum between it and the mounting table 18a that has the wafer W. The vacuum mechanism 25 includes a flange 25a that engages with the interface 21 so as to be movable up and down, a bellows 25b that encloses the space between the interface 21 and the flange 25a, and seal members 25c and 25d that enclose the spaces between the interface 21, the base 21a, and the probe card 22. Furthermore, a contact member 25e that can airtightly contact the mounting table 18a on which the wafer W is placed is provided on the lower end surface of the flange 25a. The vacuum mechanism 25 secures the base 21a and the interface 21 together and integrates the mounting table 18a, the probe card 22, and the interface 21 together by evacuating the space enclosed by the bellows 25b and the seal members 25c and 25d using a vacuum pump (not shown). The interface 21 is not limited to a configuration in which the interface 21, the probe card 22, and the wafer W are integrated by the vacuum mechanism 25, but may be a configuration in which the interface 21, the probe card 22, and the wafer W are integrated by a mechanical mechanism, for example.

[0021] Each tester 20 includes a control circuit 29 inside the case of the tester 20 that operates each component. The control circuit 29 is an electronic circuit for a computer that includes one or more processors 29a, memory 29b, and input / output and communication interfaces (not shown). The one or more processors 29a are one or a combination of a central processing unit (CPU), a graphics processing unit (GPU), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), and a circuit made up of multiple discrete semiconductors. The memory 29b includes a main memory device and an auxiliary memory device, and stores programs and other data that operate each tester 20, as well as temporarily holding information required while the processor 29a is executing the programs.

[0022] Each tester 20 also includes a main board 201 such as a motherboard (computer control board), and a test head 202 mounted on the main board 201. The main board 201 includes the above-mentioned control circuit 29, and is connected to each pogo block 211 of the interface 21. The test head 202 has equipment, electronic components, circuit boards, etc. for inspecting the wafer W, and is fixed to the main board 201 to actually control the inspection of the wafer W.

[0023] An example of the test head 202 of the tester 20 is one that includes one or more test boards 203 having test resources used to inspect the wafer W. The inspection of the wafer W is performed by executing multiple types of test resources to check the state of the wafer W. Each test resource is executed by operating a dedicated circuit (electronic circuit) formed on the test board 203. The tester 20 with the test board 203 attached (for example, by inserting the card of the test board 203 into the slot of the main board 201) inspects the wafer W based on the test resources of the test board 203. Therefore, the tester 20 can set the test resources for the inspection to be performed on the wafer W by selectively mounting the test board 203. The test resources for the inspection of the wafer W will be described in detail later.

[0024] Furthermore, the control circuit 29 of the tester 20 and the control device 90 of the inspection system 100 are connected to each other so that they can communicate with each other. When the control circuit 29 receives a control command from the control device 90, it controls each component of the tester 20 to perform an inspection on the wafer W in accordance with the test resources, and transmits the inspection results to the control device 90. The control device 90 aggregates the inspection results of each inspection cell 10, for example, into inspection data for each wafer W, and determines whether the wafer W is normal or abnormal.

[0025] The control device 90 of the inspection system 100 is a computer for controlling the entire inspection system 100, and has a processor 91, a memory 92, an input / output interface 93, and a communication interface 94. The processor 91 is one or a combination of a CPU, a GPU, an ASIC, an FPGA, a circuit made up of multiple discrete semiconductors, etc. The memory 92 includes a main memory device and an auxiliary memory device, and forms the storage unit of the control device 90.

[0026] The control device 90 is connected to each inspection cell 10, the load port 15, the aligner 16, the transport device 18, the imaging device 19, etc. via an input / output interface 93. The control device 90 is also connected to a user interface (not shown) provided in the housing 11 of the inspection system 100, etc. via the input / output interface 93. The user interface may be, for example, a monitor, a speaker, a keyboard, a mouse, or a touch panel. The control device 90 acquires information entered by a user via the user interface, and based on this information, outputs control commands to each component of the inspection system 100 to inspect the wafer W. When the control device 90 receives inspection results for the wafer W from each inspection cell 10, it notifies the user of the inspection results via the user interface.

[0027] The control device 90 of the inspection system 100 controls, for example, the transport device 18 to transport the wafer W and place the wafer W below the probe card 22 of the target inspection cell 10. The control device 90 controls the vacuum mechanism 25 of the tester 20 to evacuate the space sealed by the bellows 25b, sealing members 25c and 25d, contact member 25e, etc., thereby holding the wafer W and the mounting table 18a against the interface 21. As a result of this holding, each semiconductor device on the wafer W (each electrode pad and each solder bump) comes into contact with each contact probe 223 of the probe card 22. As a result, the tester 20 of each inspection cell 10 outputs power and signals from the control circuit 29 to each semiconductor device on the wafer W, and also receives signals returned from the wafer W in the tester 20 to perform electrical testing of the wafer W. Note that the inspection cell 10 may be configured to inspect all of the devices to be inspected by repeatedly bringing one wafer W into contact with each of the contact probes 223 multiple times, for example, when the number of inspection units (such as IC chips) capable of inspecting the number of devices to be inspected on the wafer W is small. In this case, the inspection system 100 is provided with a stage capable of moving the wafer W for each of the inspection cells 10. For example, the inspection system 100 brings each of the contact probes 223 into contact with one wafer W to perform a test, then releases the contact, moves the wafer W using the stage to shift the contact position, and makes each of the contact probes 223 contact again to perform a test.

[0028] FIG. 4(A) is a diagram illustrating test resources for inspecting a wafer W. FIG. 4(B) is a diagram illustrating each inspection cell in one cell row in an inspection system 100' according to a reference example. As shown in FIG. 4(A), an inspection sequence having multiple types of test resources is set for inspecting a wafer W. The inspection sequence is configured by arranging multiple types of test resources in series along the time axis. In other words, each test resource corresponds to a specific inspection process (test) divided in the inspection of each semiconductor device on the wafer W. For example, each test resource is executed by a circuit on a dedicated test board 203 mounted on the main board 201 as described above.

[0029] 4A illustrates an example of an inspection sequence having an inspection process A (test resource A), an inspection process B (test resource B), an inspection process C (test resource C), and an inspection process D (test resource D). These inspection processes include, for example, a test to check whether each semiconductor device on the wafer W operates normally, a burn-in test to continuously apply loads such as power and clocks, a logic test to check the logic signals of the semiconductor device, and an analog test to check the analog electrical characteristics of the semiconductor device (presence or absence of leakage, etc.).

[0030] The inspection system 100 completes the inspection of one wafer W by performing all of the inspection processes A to D on that wafer W. The classification of the inspection processes A to D (test resources A to D) is for convenience of explanation, and for example, one inspection process may have the function of performing multiple types of tests. Furthermore, the inspection processes A to D (test resources A to D) generally perform different types of tests on the wafer W, but may partially execute the same processing content (for example, processing such as supplying a clock).

[0031] As shown in FIG. 4B, the inspection system 100′ according to the reference example is configured to have the same four test resources A to D in all of the multiple inspection cells 10. For example, the inspection system 100′ has a tester 20 in which four test boards 203 (see FIG. 3) are installed on a main board 201 in all of the inspection cells 10. The inspection system 100′ configured in this manner can perform similar inspections on wafers W in all of the inspection cells 10.

[0032] However, since the inspection system 100' according to the reference example has test resources A to D in each inspection cell 10, the entire system has large-scale test resources. This increases the inspection cost, footprint, and overall inspection throughput of the inspection system 100'. In particular, the operating period (operating rate) of test resource A and test resource D is only a few percent of the total inspection period for the entire wafer W. Providing test resources with short operating periods in all inspection cells 10 can have a cost impact on the system.

[0033] First Embodiment Therefore, the inspection system 100 according to the first embodiment is configured so that some of the multiple inspection cells 10 have different types of test resources from the other inspection cells 10. The configuration of this inspection system 100 will be described below with reference to FIGS. 5(A) and 5(B). FIG. 5(A) is a diagram showing each inspection cell in one cell row in the inspection system 100 according to the first embodiment. FIG. 5(B) is a perspective view showing an example of the arrangement of test resources in the inspection system 100 according to the first embodiment.

[0034] For example, the top row of cells in the inspection system 100 has six inspection cells 10 arranged horizontally. Hereinafter, the inspection cells 10 in this row of cells will be referred to as inspection cell 1, inspection cell 2, inspection cell 3, inspection cell 4, inspection cell 5, and inspection cell 6, in that order from left to right.

[0035] Inspection cell 1 has test resource A but does not have the other test resources B to D. Inspection cells 2 to 5 have test resources B and C but do not have the other test resources A and D. Inspection cell 5 has test resource D but does not have the other test resources A to C. In other words, the inspection cells 10 arranged in the horizontal direction have test resources A to D required for inspecting wafer W separately arranged, and one inspection cell 10 does not have four test resources A to D.

[0036] In the inspection of a wafer W, this inspection system 100 transfers the wafer W to inspection cell 1 to perform inspection process A, then transfers the wafer W to one of inspection cells 2 to 5 to perform inspection processes B and C, and finally transfers the wafer W to inspection cell 6 to perform inspection process D. That is, even if the inspection system 100 moves the wafer W according to the inspection sequence and performs inspection in different inspection cells 10, it is possible to perform all four inspection processes A to D and obtain the same inspection results as the inspection system 100 according to the reference example. Furthermore, the inspection system 100 can significantly reduce the number of test resources A to D across the multiple inspection cells 10 as a whole.

[0037] 5(B), the inspection system 100 can allocate test resources A, B, C, and D to the inspection cells 10 in each vertically stacked cell row. As a result, the inspection system 100 can efficiently inspect the wafer W by transporting the wafer W in the horizontal direction for each cell row using the transport device 18 and performing the inspection processes A to D (test resources A to D), respectively.

[0038] In particular, the inspection system 100 increases the number of inspection cells 10 having test resources B and C with long operating periods among test resources A to D, while decreasing the number of inspection cells 10 having test resources A and D with short operating periods (see also FIG. 4(A)). This allows inspection cell 1 to inspect wafers W in a short period and send them to inspection cells 2 to 5. Meanwhile, inspection cells 2 to 5 can inspect wafers W over a long period of time by transporting them in a dispersed manner. Then, inspection cell 6 can sequentially inspect wafers W inspected in inspection cells 2 to 5 in a short period of time.

[0039] The placement of test resources A to D in each inspection cell 10 may be optimized based on the operating period of each test resource A. For example, as in the first modified example shown in FIG. 6A, if the operating periods of test resources A and D are shorter than those of test resources B and C, test resources A and D may be provided in inspection cell 1, and test resources B and C may be provided in other inspection cells 2 to 6. In this case, when inspecting a wafer W, the inspection system 100 may perform test resource A in inspection cell 1, perform test resource C in one of inspection cells 2 to 6, and then return to inspection cell 1 to perform test resource D.

[0040] 6(B), when the operating period of test resource B is long or the size of test resource B is larger than the other test resources A, C, and D, test cells 2 to 4 may be set to perform only test resource B. Then, test resources A, C, and D are allocated to the remaining test cell 10, for example, by combining test resource C, which has the next longest operating period, with test resource D. As an example, FIG. 6(B) shows an example in which test resource A is allocated to test cell 1, and test resources C and D are allocated to test cells 5 and 6.

[0041] The inspection system 100 according to the first embodiment is basically configured as described above, and its operation (inspection method) will be described below with reference to Fig. 7. Fig. 7 is a flowchart showing the inspection method of the inspection system 100 according to the first embodiment.

[0042] The control device 90 of the inspection system 100 manages the inspection sequence for each wafer W, the operating status of each inspection cell 10, the operating status of the transport device 18, etc., during the inspection of the wafer W. For example, the control device 90 monitors which test resource in the inspection sequence has been executed for each wafer W, or which test resource is currently being executed, and controls the transport of the wafer W to the inspection cell 10 of the test resource to be executed next, the operation of the inspection cell 10, etc. For example, the control device 90 performs the processing flow of steps S101 to S108 shown in FIG. 7.

[0043] The control device 90 controls the transfer device 18 to remove the wafer W from the container C in the loading / unloading area 12 and transfer the wafer W to the inspection cell 1 having the test resource A among the inspection cells 10 (step S101). Before transferring the wafer W, the control device 90 determines whether the inspection cell 10 and cell row to which the wafer W is to be transferred are available, and transfers the wafer W to an available inspection cell 10 and cell row. The same applies when transferring the wafer W between the subsequent inspection cells 10.

[0044] Next, the control device 90 operates the inspection cell 1 to perform test resource A on the wafer W and receives the inspection results (step S102). After that, the control device 90 receives the wafer W that has been inspected by test resource A using the transfer device 18, and transfers the wafer W to one of the inspection cells 2 to 5 that have test resources B and C among the inspection cells 10 (step S103). Note that the next wafer W is transferred to the inspection cell 1 from which the wafer W was transferred under the control of the control device 90.

[0045] Then, the control device 90 operates the inspection cell 10 (one of inspection cells 2 to 5) to which the wafer W that has been subjected to test resource A has been transferred, executes test resources B and C, and receives the inspection results (step S104). As described above, test resources B and C have long operating periods, but the inspection system 100 can reduce the amount of empty space in each inspection cell 10 by distributing the wafer W among multiple inspection cells 2 to 5. Thereafter, the control device 90 receives the wafer W that has been subjected to the inspection by test resources B and C using the transfer device 18, and transfers the wafer W to inspection cell 6, which has test resource D, among the inspection cells 10 (step S105).

[0046] The control device 90 operates the transported inspection cell 6 to execute the test resource D and receives the inspection results (step S106). Finally, the control device 90 receives the wafer W that has been inspected by the test resource D, in other words, that has undergone all inspections, using the transport device 18, and transports the wafer W into a container C in the load / unload area 12 that contains inspected wafers W (step S107).

[0047] Furthermore, the control device 90 creates inspection data by integrating the inspection results of the wafers W inspected in each inspection cell 10, determines the state (normal, abnormal) of the wafers W throughout the entire inspection sequence, and stores the data in the memory 92 (step S108). The inspection system 100 can continuously inspect multiple wafers W by sequentially transferring uninspected wafers W to available inspection cells 10 and repeating the above processing flow.

[0048] The inspection system 100 and inspection method of the present disclosure are not limited to the above-described embodiment and may be modified in various ways. For example, the inspection system 100 and inspection method have been described with reference to an example in which a wafer W is transported to each inspection cell 10 in the same cell row. However, the inspection system 100 may transport the wafer W vertically between the inspection cells 10 using the transport device 18. For example, if inspection cells 2 to 5 in the same cell row are not available after test resource A finishes testing in inspection cell 1, the wafer W may be transported to available inspection cells 2 to 5 in another cell row. Furthermore, if an abnormality is detected in the wafer W in the test resource that first performs testing (e.g., inspection cell 1), the inspection system 100 may stop the subsequent testing of the wafer W in the other inspection cells 10 (e.g., inspection cells 2 to 6).

[0049] Furthermore, for example, in the above embodiment, a pattern in which test resources A to D are executed in this order in the inspection sequence has been described. That is, the inspection system 100 is configured to transport the wafer W to an available inspection cell 10 among the multiple inspection cells 10 in accordance with the order of test resources A to D in the inspection sequence, and perform inspection in that inspection cell 10. However, if no problems arise in the inspection of the wafer W, the order of test resources A to D may be changed depending on the availability of the inspection cells 10. In other words, the control device 90 can transport the wafer W to the optimal inspection cell 10 among the multiple inspection cells 10 that executes each test resource, based on the multiple types of test resources A to D in the inspection sequence.

[0050] As an example, after performing test resource A in inspection cell 1, if there are no available test cells 2 to 5, inspection system 100 may first transport wafer W to inspection cell 6 to perform test resource D. Then, after performing test resource D, inspection system 100 can take measures such as transporting wafer W to one of inspection cells 2 to 5 to perform test resources B and C.

[0051] Second Embodiment Next, an inspection system 100A according to a second embodiment will be described with reference to FIGS. 8(A) to 9(B). FIG. 8(A) is a diagram showing the inspection state of an inspection cell 10A' of an inspection system 100A' according to another reference example. FIG. 8(B) is a diagram showing the inspection state of an inspection cell 10A of an inspection system 100A according to the second embodiment. FIG. 8(C) is a diagram illustrating an inspection sequence of a burn-in test. FIG. 9(A) is a diagram showing an example of movement of a test head 202. FIG. 9(B) is a timing chart of each of the inspection cells 1 to 3 in a burn-in test. In the following description, the same components as those in the first embodiment will be assigned the same reference numerals, and detailed description thereof will be omitted.

[0052] To facilitate understanding of the test system 100A according to the second embodiment, a test cell 10A' of a test system 100A' according to another reference example will be described first. The test cell 10A' according to the other reference example has a tester 20 integrated with a main board 201' and a test head 202'. In other words, the test head 202' is immovably fixed to the main board 201'.

[0053] The interface 21 of the inspection cell 10 and the probe card 22 are provided below the main board 201′. The wafer W transferred to the transfer device 18 (see FIG. 2) is brought into electrical contact with each contact probe 223 of the probe card 22 based on the operation of the vacuum mechanism 25 (see FIG. 3) and the like.

[0054] On the other hand, the test head 202′ includes therein functional units such as a device power supply 205, a clock 206, an analog measurement system 207, a logic measurement system 208, and other measurement systems 209. For example, some or all of the device power supply 205, the clock 206, the analog measurement system 207, the logic measurement system 208, and other measurement systems 209 may be provided on the above-mentioned test board 203 (see FIG. 3).

[0055] The device power supply 205 is connected to a power supply (not shown) and supplies power to the wafer W during inspection of the wafer W. The clock 206 generates a clock pulse signal used in inspection of the wafer W and outputs the clock to the wafer W under the control of the test head 202'. The analog measurement system 207 measures, for example, electrical characteristics (voltage change, current change, etc.) of the semiconductor device during inspection of the wafer W. The logic measurement system 208 measures, for example, signals collected based on outputs of clocks, commands, logic signals, etc. during inspection of the wafer W. The other measurement system 209 measures, for example, the presence or absence of leakage in the semiconductor device during inspection of the wafer W.

[0056] The inspection cell 10A' according to the above-described another reference example inspects the wafer W by operating the tester 20, which integrates the main board 201' and the test head 202'. In this case, the inspection system 100A' installs the same test head 202' in all of the multiple inspection cells 10A'.

[0057] However, depending on the type of wafer W inspection, inspections may be performed using only some of the functions of the test head 202 for most of the total period, with other functions barely being used. One example of this is a burn-in test (test resource B) in which a load is continuously applied to the semiconductor devices on the wafer W to check their durability, as shown in FIG. 8(C). In the burn-in test, only power and clock signals are continuously supplied from the tester 20 to the wafer W for several tens of hours, and analog and logic signals are collected at appropriate times (e.g., every hour). Therefore, the analog measurement system 207, logic measurement system 208, other measurement system 209, etc., have short operating periods compared to the total period of the burn-in test, and are only required at appropriate times.

[0058] For this reason, as shown in Figure 8(B), the inspection system 100A of the second embodiment is configured so that the number of test heads 202 is less than the number of main boards 201 of the tester 20, and one test head 202 is shared by multiple inspection cells 10.

[0059] Specifically, the main board 201 is equipped with basic functions for inspecting the wafer W (device power supply 205, clock 206) in addition to the control circuit 29 (see FIG. 3). The basic functions may be pre-implemented on the main board 201, or may be integrated by attaching the test board 203. On the other hand, the main board 201 is configured not to have a function for receiving and processing signals from semiconductor devices on the wafer W (analog measurement system 207, logic measurement system 208, other measurement system 209).

[0060] Conversely, the test head 202 is detachable from and relatively movable with respect to the main board 201, and while it does not have the basic function of inspecting the wafer W, it does have the function of receiving and processing signals from semiconductor devices. In other words, the test head 202 has the functions of an analog measurement system 207, a logic measurement system 208, and other measurement systems 209 (including the test board 203).

[0061] The test head 202 is also provided with a moving mechanism 204. The moving mechanism 204 moves within the housing 11 under the control of the control device 90, and transports the test head 202 between the multiple inspection cells 10A. The tester 20 also has a connection structure (not shown) that automatically connects the main board 201 and the test head 202 when the test head 202 moves to the main board 201.

[0062] In the inspection system 100A configured as described above, some of the inspection cells 10A (e.g., inspection cell 1) have test heads 202, while the other inspection cells (e.g., inspection cell 2) do not. In other words, when the states of the inspection cells 10A are viewed at the same time, it can be said that the inspection cells 10A have different types of test resources. After performing processing in the inspection cell 10A to which it has been moved, the test head 202 is carried out by the movement mechanism 204 and carried into the next inspection cell 10A, whereby it can perform processing in the next inspection cell 10A. The processing content of the test head 202 is preferably set according to the progress of the inspection sequence in each inspection cell 10A. In this case, the inspection system 100A can also reduce the number of test heads 202 (analog measurement system 207, logic measurement system 208, and other measurement system 209), thereby enabling cost reduction.

[0063] The inspection system 100A according to the second embodiment is basically configured as described above, and its operation will be described below with reference to Figures 9(A) and 9(B). The test head 202 is configured to be able to move each inspection cell 10A in one cell row by a movement mechanism 204. Note that Figure 9(A) illustrates an example in which the first test head 202a moves between inspection cells 1 to 3 and is connected to the appropriate main board 201, and the second test head 202b moves between inspection cells 4 to 6 and is connected to the appropriate main board 201.

[0064] When performing a burn-in test on a wafer W shown in FIG. 8B, inspection cells 1 to 6 perform test resource Bs, which collects signals from semiconductor devices, at appropriate timings during the burn-in test (test resource B), and therefore require the function of the test head 202. Therefore, as shown in FIG. 9B, the control device 90 slightly shifts the timing of the inspections in inspection cells 1 to 3, thereby shifting the timing of connecting the test head 202 to the main board 201 across inspection cells 1 to 3. In other words, even in the inspection method of the inspection system 100A, the process of inspection by inspection cell 1, the process of inspection by inspection cell 2, and the process of inspection by inspection cell 3 can be said to be different types of test resources at the same time. This inspection method allows the inspection system 100A to smoothly continue inspecting the wafer W without overlapping the timings at which the test head 202 is used in inspection cells 1 to 3 (and inspection cells 4 to 6).

[0065] 9(A) and 9(B) show an example in which the test head 202 moves between three inspection cells 1 to 3 and 4 to 6, but this number is not limited thereto, and for example, a configuration in which one test head 202 moves to inspection cells 1 to 6 is also possible. Furthermore, the inspection system 100A is not limited to a configuration in which the test head 202 moves in the cell row, but may also be a configuration in which the test head 202 moves in the vertical direction (up and down). Inspection by the inspection system 100A that moves the test head 202 is not limited to burn-in testing, and a similar configuration can be used when the operating periods of test resources are different in length.

[0066] Furthermore, the inspection system 100 is not limited to a configuration in which the test head 202 side of the inspection cell 10A is moved. For example, the inspection system 100A may be provided with a prober device that moves the main board 201, the interface 21, the probe card 22, and the wafer W (including the mounting table 18a) while the test head 202 side is fixed.

[0067] Third Embodiment FIG. 10 is a schematic horizontal cross-sectional view of an inspection system 100B according to a third embodiment. As shown in FIG. 10, the inspection system 100B may include a buffer 17 for storing multiple test heads 202 in the transport area 13 or elsewhere. The control device 90 of the inspection system 100B can select a test head 202 based on the test resources of the inspection cell 10A and move the selected test head 202 to the inspection cell 10A using a movement mechanism 204 at an appropriate time. This allows the inspection system 100B to stock test heads 202 capable of performing multiple types of tests and provide the test heads 202 to the inspection cell 10A as needed. For example, the inspection system 100B can separately store the test heads 202 for the analog measurement system 207, the test heads 202 for the logic measurement system 208, and the test heads 202 for the other measurement systems 209. In this case, the inspection system 100B preferably adjusts the number of stored test heads 202 based on the operating period of each test.

[0068] The technical ideas and effects of the present disclosure explained in the above embodiments will be described below.

[0069] A first aspect of the present disclosure is an inspection system 100, 100A, 100B having a plurality of inspection cells 10, 10A for inspecting a substrate (wafer W), the inspection including a plurality of types of test resources, and some of the plurality of inspection cells 10, 10A (e.g., inspection cell 1) and other inspection cells (inspection cell 2) have mutually different types of test resources from the plurality of types of test resources.

[0070] As described above, the inspection systems 100, 100A, and 100B can reduce the overall test resources and lower the cost of inspection by having different types of test resources in some of the inspection cells 1 and other of the inspection cells 2. For example, the inspection systems 100, 100A, and 100B can reduce costs and promote miniaturization and a smaller footprint by reducing the number of hardware test resources (test boards 203 and functional parts of the test head 202) that have short operating periods. Furthermore, the inspection systems 100, 100A, and 100B can improve the operating rate of the inspection cells 10 and 10A as a whole during inspection.

[0071] The inspection system 100 also includes a transfer device 18 capable of transferring substrates (wafers W) to the multiple inspection cells 10, and a control device 90 that controls the multiple inspection cells 10 and the transfer device 18. The control device 90 sequentially transfers the substrate to the multiple inspection cells 10 having different types of test resources, and executes all of the multiple types of test resources in the inspection of the substrate. This allows the inspection system 100 to execute the multiple types of test resources on all of the substrates to be inspected, enabling reliable and stable inspection of the substrates.

[0072] Furthermore, the number of test cells 10 is optimized based on the operating period of each of the multiple types of test resources, which allows the test system 100 to prevent the occurrence of idle test cells 10 and further improve the operating rate of the entire test.

[0073] Furthermore, the number of inspection cells 10 in test resources with long operating periods is greater than the number of inspection cells 10 in test resources with short operating periods. This allows the inspection system 100 to appropriately allocate the inspection cells 10, further increasing the operating rate.

[0074] Furthermore, the control device 90 controls the transport device 18 based on the inspection sequence along the inspection time axis, and transports the substrate (wafer W) to the most suitable inspection cell 10 among the multiple inspection cells 10. This allows the inspection system 100 to reduce the number of waiting inspection cells 10 as much as possible and inspect multiple substrates in parallel.

[0075] Furthermore, the control device 90 transports the substrate (wafer W) to an available inspection cell 10 among the multiple inspection cells 10 in accordance with the order of the multiple types of test resources set in the inspection sequence. This enables the inspection system 100 to properly inspect the substrate in accordance with the inspection sequence.

[0076] Furthermore, the control device 90 changes the order of the multiple types of test resources set in the inspection sequence, and transports the substrate (wafer W) to an available inspection cell 10 among the multiple inspection cells 10. This enables the inspection system 100 to further increase the operating rate of the available inspection cells 10, and enables efficient inspection of multiple substrates.

[0077] Furthermore, the multiple inspection cells 10A have a main board 201 electrically connected to the substrate (wafer W), and the inspection systems 100A and 100B have a test head 202 detachably connected to the main board 201, and the main board 201 and the test head 202 are relatively movable. By making the main board 201 and the test head 202 relatively movable, the inspection systems 100A and 100B can connect the test head 202 to the main board 201 at an appropriate timing to perform inspection.

[0078] Furthermore, main board 201 has at least the function of supplying power and a clock to the substrate (wafer W), and test head 202 has at least the function of processing signals received from the substrate while connected to main board 201. As a result, inspection systems 100A and 100B have functions that should be common to substrate inspections mounted on main board 201, enabling continuous substrate inspection.

[0079] Furthermore, the multiple inspection cells 10A continue to supply power and clocks to the substrate (wafer W) to perform a burn-in test to check the tolerance of the substrate, and the test head 202 is connected to the test head 202 at the timing when the signals of the substrate are processed in the burn-in test. This allows the inspection systems 100A and 100B to perform the burn-in test well while reducing the number of test heads 202.

[0080] Furthermore, the inspection systems 100A and 100B include a movement mechanism 204 that moves the test head 202 relative to the main board 201, and a control device 90 that controls the operation of the movement mechanism 204. This enables the inspection systems 100A and 100B to stably inspect the substrate (wafer W) by moving the test head 202 using the movement mechanism 204.

[0081] Furthermore, the test heads 202 are stored in the buffer 17 of the inspection system 100B, and the control device 90 selects a test head 202 according to the test resource and moves the selected test head 202 to the inspection cell 10. This allows the inspection system 100B to change the ratio of test heads 202 for each test resource, thereby further reducing costs.

[0082] The plurality of inspection cells 10 also include a tester 20 that outputs signals to a substrate (wafer W) based on test resources, and a probe card 22 that is connected to the tester 20 and has a plurality of contact probes 223 that come into contact with the substrate. This allows the inspection systems 100, 100A, and 100B to inspect the substrate more stably.

[0083] The inspection cells 10 are arranged in a matrix, with multiple cells lined up horizontally and multiple cells lined up vertically, thereby reducing the footprint of the inspection systems 100, 100A, and 100B and shortening the time required to transport a substrate (wafer W) to each of the inspection cells 10 and 10A.

[0084] A second aspect of the present disclosure is an inspection method for an inspection system 100, 100A, 100B including a plurality of inspection cells 10, 10A that inspect substrates (wafers W), the inspection including a plurality of types of test resources, including (A) a step of performing inspection using test resources possessed by some inspection cells 1 of the plurality of inspection cells 10, 10A, and (B) a step of performing inspection using test resources of a different type from some inspection cells 1 possessed by other inspection cells 2 of the plurality of inspection cells 10, 10A. Even in this case, the inspection method can reduce the inspection cost when inspecting a plurality of substrates.

[0085] The inspection systems 100, 100A, 100B and inspection methods according to the presently disclosed embodiments are illustrative in all respects and not restrictive. The embodiments may be modified and improved in various ways without departing from the spirit and scope of the appended claims. The features described in the above embodiments may be configured differently and may be combined within a consistent range. [Explanation of symbols]

[0086] 1~6, 10, 10A inspection cell 18 Conveyor equipment 90 Control device 100, 100A, 100B Inspection Systems W wafer

Claims

1. 1. An inspection system including a plurality of inspection cells for inspecting substrates, The test includes multiple types of test resources; some of the plurality of test cells and the other of the plurality of test cells have different types of test resources from each other among the plurality of types of test resources; Inspection system.

2. a transport device capable of transporting the substrate to the plurality of inspection cells; a control device that controls the plurality of inspection cells and the transport device, the control device sequentially transports the substrate to the plurality of inspection cells having the mutually different types of test resources, and executes the inspection of the substrate using all of the plurality of types of test resources. The inspection system of claim 1 .

3. the plurality of test cells are allocated in numbers optimized based on the operating periods of the plurality of types of test resources; The inspection system of claim 2 .

4. the number of test cells in the test resource having the long operating period is greater than the number of test cells in the test resource having the short operating period; The inspection system of claim 3 .

5. the control device controls the transport device based on an inspection sequence along a time axis of the inspection, and transports the substrate to an optimal inspection cell among the plurality of inspection cells. The inspection system of claim 2 .

6. the control device transports the substrate to an available inspection cell among the plurality of inspection cells in accordance with the order of the plurality of types of test resources set in the inspection sequence. The inspection system of claim 5 .

7. the control device changes the order of the plurality of types of test resources set in the inspection sequence and transports the substrate to an available inspection cell among the plurality of inspection cells. The inspection system of claim 5 .

8. the plurality of test cells each have a main board electrically connected to the substrate; the inspection system includes a test head detachably connected to the main board; the main board and the test head are movable relative to each other; The inspection system of claim 1 .

9. the main board has a function of supplying at least power and a clock to the board; the test head has a function of processing at least a signal received from the board when connected to the main board; The inspection system of claim 8 .

10. the plurality of test cells continue to supply power and clocks to the substrate, and perform a burn-in test to check the durability of the substrate; the test head is connected to the test head at a timing when a signal of the board is processed in the burn-in test. The inspection system of claim 9.

11. a moving mechanism for moving the test head relative to the main board; a control device for controlling the operation of the movement mechanism, The inspection system of claim 8 .

12. the test head is stored in a buffer of the inspection system; the control device selects the test head according to the test resource and moves the selected test head to the inspection cell; The inspection system of claim 11.

13. The plurality of test cells include a tester that outputs a signal to the board based on the test resource; a probe card connected to the tester and having a plurality of contact probes that contact the substrate; 13. The inspection system according to any one of claims 1 to 12.

14. the plurality of inspection cells are arranged in a matrix, with a plurality of cells aligned along the horizontal direction and a plurality of cells aligned along the vertical direction; 13. The inspection system according to any one of claims 1 to 12.

15. 1. An inspection method for an inspection system having a plurality of inspection cells for inspecting substrates, comprising: The test includes multiple types of test resources; (A) performing the inspection using the test resources included in some of the inspection cells; (B) performing the inspection using the test resources of the other inspection cells among the plurality of inspection cells that are different in type from the test resources of the some inspection cells. Testing method.

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