Superlattice structure, electron spin-controlled semiconductor laser, and method of manufacturing superlattice structure

Abstract

To provide a superlattice structure having a sufficient spin relaxation time, an electron spin-controlled semiconductor laser, and a method of manufacturing a superlattice structure.SOLUTION: A superlattice structure has a laminate including a plurality of barrier layers and a plurality of well layers, and the plurality of barrier layers and the plurality of well layers each include a III-V compound semiconductor with a zincblende structure. In the laminate, the barrier layers and the well layers are laminated alternately in the <110> direction. A spin relaxation time of electrons in the laminate is based on the number of periods of the lamination of the barrier layers and the well layers, the number of periods of the lamination of the barrier layers and the well layers in the laminate being 2 or more and 50 or less. The thickness of each of the plurality of barrier layers is 0.2 nm or more and 6 nm or less, and the spin relaxation time is 0.1 ns or more and 10 ns or less.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a superlattice structure, an electron spin-controlled semiconductor laser, and a method for manufacturing the superlattice structure. [Background technology]

[0002] Light-emitting devices such as light-emitting diodes (LEDs) and lasers are used in a variety of fields. In recent years, research and development has been conducted on electron spin-controlled semiconductor lasers that output circularly polarized light by aligning the electron spins in the light-emitting layer.

[0003] For example, Patent Document 1 discloses a semiconductor light-emitting device that utilizes spin polarization. The semiconductor light-emitting device described in Patent Document 1 uses a GaAs / AlGaAs quantum well with few crystal defects, and by adjusting the thicknesses of the well layer and barrier layer, spin-polarized electrons are confined within the well layer, thereby increasing the light-emitting efficiency. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2018-010897 Summary of the Invention [Problem to be solved by the invention]

[0005] The semiconductor light-emitting device described in Patent Document 1 confines spins in a well layer that is a two-dimensional plane. <110> It has been disclosed that by confining spins in a two-dimensional plane perpendicular to the direction, the spin relaxation time can be reduced to between 4 nsec and 6 nsec at room temperature. However, spin-polarized electrons can only move within the two-dimensional plane of the well layer, and cannot move in a direction perpendicular to the well layer. In bulk structures that allow movement in three dimensions, the spin relaxation time at room temperature is approximately 0.1 nsec, and further improvement is required.

[0006] The present disclosure is an invention made in view of the above circumstances, and provides a superlattice structure having a sufficient spin relaxation time, an electron spin-controlled semiconductor laser, and a method for manufacturing the superlattice structure. [Means for solving the problem]

[0007] (1) A superlattice structure according to a first aspect has a stacked structure including a plurality of barrier layers and a plurality of well layers, each of which contains a III-V group compound semiconductor having a zinc blende structure. In the stacked structure, the barrier layers and the well layers are <110> The barrier layers are alternately stacked in the direction of the well layer. The spin relaxation time of electrons in the stack is based on the number of stacking periods of the barrier layers and the well layers. The number of stacking periods of the barrier layers and the well layers in the stack is 2 to 50. The thickness of each of the plurality of barrier layers is 0.2 to 6 nm. This superlattice structure has a spin relaxation time of 0.1 to 10 nsec.

[0008] (2) In the superlattice structure according to the above aspect, at least one of the plurality of barrier layers and the plurality of well layers may contain n-type impurities.

[0009] (3) In the superlattice structure according to the above aspect, at least one of the barrier layers and the well layers may contain p-type impurities.

[0010] (4) In the superlattice structure according to the above aspect, at least one of the barrier layers and the well layers may be an intrinsic semiconductor.

[0011] (5) The superlattice structure according to the above aspect may further include a semiconductor substrate or a semiconductor layer, wherein the stack or the semiconductor layer is stacked on a (110) plane of the semiconductor substrate.

[0012] (6) An electron spin-controlled semiconductor laser according to a second aspect includes the superlattice structure according to the above aspect.

[0013] (7) The electron spin-controlled semiconductor laser according to the above aspect may include a spin transport layer having the superlattice structure. The sheet impurity densities of the barrier layers constituting the superlattice structure may each be 10 10 cm -2 Over 10 13 cm -2 The following is also acceptable.

[0014] (8) The electron spin-controlled semiconductor laser according to the above aspect may include a spin transport layer having the superlattice structure. The sheet impurity densities of the well layers constituting the superlattice structure may each be 10 10 cm -2 Over 10 13 cm -2 The following is also acceptable.

[0015] (9) The electron spin-controlled semiconductor laser according to the above aspect may include an active layer having the superlattice structure, and each of the well layers constituting the superlattice structure may have a thickness of 2 nm to 20 nm.

[0016] (10) The electron spin-controlled semiconductor laser according to the above aspect may include an active layer and a spin transport layer, each of which may have the superlattice structure.

[0017] (11) A method for manufacturing a superlattice structure according to a third aspect includes a design step of determining the number of periods of stacking of barrier layers and well layers based on a desired spin relaxation time, and forming the barrier layers and the well layers in accordance with the number of periods determined in the design step. <110> and a lamination step of laminating the barrier layers and the well layers alternately in the direction of the gate insulating film. The barrier layers and the well layers each contain a III-V compound semiconductor with a zinc blende structure. The thickness of the barrier layers laminated in the lamination step is set to be 0.2 nm or more and 6 nm or less.

[0018] (12) In the method for manufacturing a superlattice structure according to the above aspect, the designing step may further include a step of determining at least one of the thickness of the barrier layer and the sheet impurity density of the barrier layer or the well layer based on the desired spin relaxation time. [Effects of the Invention]

[0019] The superlattice structure and electron spin-controlled semiconductor laser according to the above aspects have a sufficient spin relaxation time, and the method for manufacturing the superlattice structure according to the above aspects makes it possible to design the spin relaxation time. [Brief explanation of the drawings]

[0020] [Figure 1] FIG. 1 is a cross-sectional view of a superlattice structure according to a first embodiment. [Figure 2] 2 is an example of an electronic state of the superlattice structure according to the first embodiment. [Figure 3] 1 shows the relationship between the number of stacking periods of well layers and barrier layers in the superlattice structure of Example 1 and the spin relaxation time of the superlattice structure. [Figure 4] 10 shows the change in spin relaxation time of the superlattice structure when the thickness of the barrier layer and the sheet impurity density of the well layer in the superlattice structure of Example 2 are changed. [Figure 5] 10 shows the change in spin relaxation time of the superlattice structure when the thickness of the barrier layer and the sheet impurity density of the well layer in the superlattice structure of Example 3 are changed. [Figure 6] 10 shows the change in spin relaxation time of the superlattice structure when the thickness of the barrier layer and the sheet impurity density of the barrier layer in the superlattice structure of Example 4 are changed. [Figure 7] 1 is a cross-sectional view of an electron spin-controlled semiconductor laser according to a first embodiment. [Figure 8] 1 is a plan view of an electron spin-control semiconductor laser according to a first embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0021] The present disclosure will be described in detail below with reference to the drawings as appropriate. The drawings used in the following description may show characteristic portions enlarged for convenience in order to make the features of the present disclosure easier to understand, and the dimensional ratios of each component may differ from the actual ones. The materials, dimensions, arrangements, numbers, numerical values, configurations, etc. exemplified in the following description are merely examples, and the present disclosure is not limited thereto and may be appropriately modified and implemented within the scope that does not change the gist of the disclosure.

[0022] "Superlattice structure" 1 is a cross-sectional view of a superlattice structure 10 according to the first embodiment. The superlattice structure 10 has a stack of multiple well layers 1 and multiple barrier layers 2.

[0023] The laminate is laminated on, for example, a substrate 3. The substrate 3 is, for example, a semiconductor substrate. The substrate 3 is, for example, a III-V compound semiconductor substrate, such as gallium arsenide, indium phosphide, or gallium nitride. The substrate 3 may also be, for example, a group IV semiconductor substrate, such as silicon or germanium. The substrate 3 may be a semi-insulating substrate or a p-type or n-type doped conductive substrate. The thickness of the substrate 3 is not important, and it may be, for example, a thin semiconductor layer with a thickness of 100 nm.

[0024] The stacking plane of the stack is the (110) plane. <110> In this specification, the collective orientation is indicated by <> and the individual planes by (). For negative indices, a "-" (bar) is placed above the number in crystallography, but in this specification, a negative sign is placed before the number.

[0025] The stacking direction of the well layer 1 and the barrier layer 2 is <110> By setting the stacking direction to the direction of the effective magnetic field felt by electrons in the well layer 1, the orientation direction of the spins in the well layer 1 can be aligned with the direction of the effective magnetic field felt by electrons in the well layer 1. <110> The effective magnetic field direction of the superlattice structure 10 is <110> It is a direction. <110> Optically or electrically generating spins aligned in the direction increases the spin relaxation time of these electron spins.

[0026] For example, when a laminate is formed on the (100) plane, the spin orientation direction ( <100> The direction of the magnetic field is perpendicular to the direction in which the effective magnetic field is applied to the electron. In this case, the effective magnetic field acts in a direction that rotates the spin, shortening the spin relaxation time.

[0027] The superlattice structure 10 is a stacked body in which stacked structures of well layers 1 and barrier layers 2 are repeatedly stacked. The number of stacking periods of the well layers 1 and barrier layers 2 in the stacked body is 2 or more and 50 or less. The inventors have found that the spin relaxation time can be controlled by the number of stacking periods of the well layers 1 and barrier layers 2. The spin relaxation time of the superlattice structure 10 tends to be longer as the number of stacking periods of the well layers 1 and barrier layers 2 decreases. Therefore, the number of stacking periods can be determined based on the desired spin relaxation time.

[0028] The well layer 1 includes, for example, a III-V group compound semiconductor having a zinc blende structure, such as gallium arsenide, indium gallium arsenide, or aluminum gallium arsenide.

[0029] The semiconductor constituting the well layer 1 may be an intrinsic semiconductor, or may contain n-type impurities or p-type impurities. Known n-type impurities can be used. For example, when the well layer 1 is made of gallium arsenide, examples of n-type impurities include Si, Sn, S, Se, and Te. Known p-type impurities can be used. For example, when the well layer 1 is made of gallium arsenide, examples of p-type impurities include Be, Zn, and C. When conductivity is required (for example, when a superlattice structure is used in the spin transport layer described below), the well layer 1 preferably contains n-type impurities or p-type impurities.

[0030] The thickness of each well layer 1 can be designed, for example, according to the required spin relaxation time. The thickness of each well layer 1 is, for example, 2 nm to 20 nm, and preferably 5 nm to 15 nm. If the thickness of the well layer 1 is thin, spin relaxation due to the Elliott-Yafet mechanism will be strengthened, resulting in a short spin relaxation time. Furthermore, the second level will have higher energy than the barrier layer and will be in a continuous state, which will strengthen spin relaxation. If the thickness of the well layer 1 is thick, spin relaxation due to intersubband scattering will be strengthened, resulting in a short spin relaxation time. The thicknesses of the well layers 1 may be the same or different.

[0031] The barrier layer 2 contains a III-V compound semiconductor with a zinc blende structure that has a smaller electron affinity than the material that constitutes the well layer 1. For example, if the well layer 1 is made of gallium arsenide, the barrier layer 2 can be made of aluminum gallium arsenide. The difference in electron affinity between the well layer 1 and the barrier layer 2 (well potential depth) is determined by the thermal distribution of electrons (k B T) is preferably 5 times or more.

[0032] The semiconductor constituting the barrier layer 2 may be an intrinsic semiconductor, or may contain n-type impurities or p-type impurities. Known n-type impurities and p-type impurities can be used. When electrical conductivity is required (for example, when a superlattice structure is used in the spin transport layer described below), the barrier layer 2 preferably contains n-type impurities or p-type impurities.

[0033] The thickness of each barrier layer 2 is 0.2 nm or more and 6 nm or less, preferably 0.2 nm or more and less than 6 nm, and more preferably 0.2 nm or more and 3 nm or less. If the thickness of the barrier layer 2 is thin, the spin relaxation time becomes short. If the thickness of the barrier layer 2 is thick, the movement of electrons in three-dimensional directions is restricted, and electron conduction in the perpendicular direction is restricted. This is because if the thickness of the barrier layer 2 is thick, electrons leaking from the two well layers 1 sandwiching the barrier layer 2 cannot combine with each other, and the electrons are isolated in the well layers 1.

[0034] 2 shows an example of the electronic state of the superlattice structure 10 according to the first embodiment. The horizontal axis of FIG. <110> As shown by the dotted lines in Figure 2, well layers 1 with a potential of 0 eV and barrier layers 2 with a potential of 0.26 eV are alternately stacked. The solid lines near 0.03 eV and extending from 0.10 eV to 0.15 eV represent the wave function of electrons. As shown in Figure 2, electrons are not localized in the well layer 1, but move in the perpendicular direction ( <110> It can be seen that electrons are bound in the three-dimensional directions and spread throughout the entire superlattice structure 10. The superlattice structure 10 is a structure in which electrons can move in three-dimensional directions.

[0035] The spin relaxation time of the superlattice structure 10 according to this embodiment is 0.1 nsec or more and 10 nsec or less.

[0036] 3 shows the relationship between the number of stacking periods of well layers 1 and barrier layers 2 in superlattice structure 10 of Example 1 and the spin relaxation time of superlattice structure 10. In Example 1 shown in FIG. 3, well layer 1 is made of GaAs with a thickness of 10 nm, and barrier layer 2 is made of AlGaAs with a thickness of 1.5 nm. Both well layer 1 and barrier layer 2 are undoped, and electrons and holes are generated by photoexcitation. The spin relaxation time was measured by both simulation and actual measurement.

[0037] The photoexcited carrier density in well layer 1 was calculated by dividing the number of electron-hole pairs generated from the photoexcitation intensity and absorption coefficient by the area of ​​the laser beam spot. The spin relaxation time was measured using a procedure known as time-resolved photoluminescence. The simulation and actual measurements were in close agreement, confirming the accuracy of the simulation.

[0038] 3, the spin relaxation time of superlattice structure 10 correlates with the number of periods of the stack of well layers and barrier layers. The smaller the number of periods, the longer the spin relaxation time of superlattice structure 10 tends to be. When the number of periods is in the range of 2 to 50, the spin relaxation time of superlattice structure 10 satisfies the range of 0.1 nsec to 10 nsec.

[0039] FIG. 4 shows the change in spin relaxation time of the superlattice structure 10 of Example 2 when the thickness of the barrier layer 2 and the sheet impurity density of the well layer 1 are changed. The sheet impurity density can be determined, for example, by Hall measurement or secondary ion mass spectrometry. The sheet impurity density can be converted to volume density by dividing it by the thickness of the well layer 1. In Example 2 shown in FIG. 4, the well layer 1 is made of GaAs with a thickness of 10 nm, and the barrier layer 2 is made of AlGaAs with a thickness of 1 to 10 nm. The well layer 1 is doped with Si as an n-type impurity, and the sheet impurity density of the well layer 1 is changed. The number of stacking periods of the well layer 1 and the barrier layer 2 is five.

[0040] As shown in FIG. 4, the spin relaxation time of superlattice structure 10 correlates with the thickness of barrier layer 2 and the sheet impurity density of well layer 1. The thinner the barrier layer 2, the shorter the spin relaxation time of superlattice structure 10 tends to be. Furthermore, the higher the sheet impurity density of well layer 1, the shorter the spin relaxation time of superlattice structure 10 tends to be. When the thickness of barrier layer 2 is in the range of 0.2 nm to 6 nm, the spin relaxation time of superlattice structure 10 satisfies the range of 0.1 nsec to 10 nsec. Furthermore, in the region where the spin relaxation time is short, the effect of the sheet impurity density of well layer 1 on the spin relaxation time is small, and the spin relaxation time of superlattice structure 10 satisfies the range of 0.1 nsec to 10 nsec, regardless of the sheet impurity density of well layer 1.

[0041] As shown in Figures 3 and 4, the spin relaxation time of the superlattice structure 10 varies depending on the number of periods of the stack of the well layers 1 and the barrier layers 2 and the thickness of the barrier layers 2. This indicates that the spin relaxation time in the superlattice structure 10 is governed by the spin relaxation mechanism (Dyakonov-Perel mechanism). In this mechanism, the spin relaxation time depends on the magnitude of the effective magnetic field for the spin and the electron scattering time. When the thickness of the barrier layers 2 changes, the magnitude of the effective magnetic field for the spin changes, and the spin relaxation time changes. Furthermore, when the number of periods changes, the electron scattering time changes, and the spin relaxation time changes.

[0042] 5 shows the change in the spin relaxation time of superlattice structure 10 when the thickness of barrier layer 2 and the sheet impurity density of well layer 1 in superlattice structure 10 of Example 3 are changed. Example 3 shown in FIG. 5 differs from Example 2 in that the number of periods in the stacking of well layer 1 and barrier layer 2 is changed to 10. Other conditions in Example 3 are the same as in Example 2. As shown in FIG. 5, even when the number of periods is changed, the spin relaxation time of superlattice structure 10 shows the same tendency as in Example 2, and the spin relaxation time of superlattice structure 10 satisfies the range of 0.1 nsec to 10 nsec.

[0043] FIG. 6 shows the change in spin relaxation time of superlattice structure 10 when the thickness of barrier layer 2 and the sheet impurity density of barrier layer 2 in superlattice structure 10 of Example 4 are changed. Example 4 differs from Example 2 in that well layer 1 is not doped with Si as an n-type impurity, but barrier layer 2 is doped with Si as an n-type impurity, and the sheet impurity density of barrier layer 2 is changed. Other conditions in Example 4 are the same as in Example 2. As shown in FIG. 6, even when barrier layer 2 is doped with an impurity (donor or acceptor), the spin relaxation time of superlattice structure 10 shows the same tendency as in Example 2, and the spin relaxation time of superlattice structure 10 satisfies the range of 0.1 nsec to 10 nsec.

[0044] As described above, the superlattice structure according to this embodiment allows spins to move in the perpendicular direction and has a sufficient spin relaxation time. Therefore, the superlattice structure according to this embodiment allows spins to propagate not only in two dimensions but also in three dimensions, making it applicable to a variety of applications.

[0045] "Method of manufacturing superlattice structures" The method for manufacturing the superlattice structure 10 according to this embodiment includes a design step and a stacking step.

[0046] The length of the spin relaxation time and the electron conductivity required vary depending on the intended use of the superlattice structure. In the design process, the desired spin relaxation time is determined depending on the intended use of the superlattice structure.

[0047] Once the desired spin relaxation time is determined, the number of periods of the stack of well layers 1 and barrier layers 2 is determined based on the spin relaxation time. The relationship between the number of periods and the spin relaxation time is determined in advance by a study or simulation, for example, as shown in FIG.

[0048] In the design process, the thickness of the barrier layer 2 may be determined based on the desired spin relaxation time. The relationship between the thickness of the barrier layer 2 and the spin relaxation time is determined in advance by a preliminary study or simulation, for example, as shown in Figure 3. The thickness of the barrier layer 2 is set to be in the range of 0.2 nm to 6 nm.

[0049] In the design process, the sheet impurity densities in the well layer 1 and the barrier layer 2 may be determined based on the desired spin relaxation time. The relationship between the sheet impurity densities and the spin relaxation time in the well layer 1 and the barrier layer 2 is determined in advance by a study or simulation, for example, as shown in FIGS.

[0050] In the lamination process, the well layer 1 and the barrier layer 2 are laminated according to the conditions determined in the design process. <110> The conditions determined in the design process are the number of stacking periods, the thickness of the barrier layer 2, and the sheet impurity densities of the well layer 1 and the barrier layer 2, as described above.

[0051] The method for manufacturing the superlattice structure 10 according to this embodiment makes it possible to freely design the spin relaxation time of the superlattice structure 10. Furthermore, the method for manufacturing the superlattice structure 10 according to this embodiment makes it possible to fabricate a superlattice structure in which spins are movable in the perpendicular direction and which has a sufficient spin relaxation time.

[0052] "Electron spin-controlled semiconductor laser" Fig. 7 is a cross-sectional view of the electron spin-controlled semiconductor laser 20 according to the first embodiment. Fig. 8 is a plan view of the electron spin-controlled semiconductor laser 20 according to the first embodiment. Fig. 7 is a cross-sectional view taken along line AA in Fig. 8.

[0053] The electron spin-controlled semiconductor laser 20 comprises a first reflecting layer 21, an electrode 22, a spacer layer 23, an active layer 24, an oxide layer 25, a spin transport layer 26, a first magnetic electrode 27, a second magnetic electrode 28, and a second reflecting layer 29.

[0054] The direction perpendicular to the plane in which the first reflective layer 21 extends is defined as the Z direction. One direction within the plane in which the first reflective layer 21 extends is defined as the X direction, and the direction perpendicular to the X direction within the plane is defined as the Y direction. The Z direction is perpendicular to the X and Y directions. The direction from the active layer 24 toward the second reflective layer 29 is defined as the +Z direction, and the opposite direction is defined as the -Z direction. In this specification, the +Z direction may be expressed as "up" and the -Z direction as "down," but these expressions are used for convenience and do not define the direction of gravity.

[0055] The first reflective layer 21 is, for example, a laminated film in which low-refractive index layers 21A and high-refractive index layers 21B are alternately stacked. The low-refractive index layers 21A have a lower refractive index than the high-refractive index layers 21B. The first reflective layer 21 is, for example, a III-V group compound semiconductor, such as aluminum gallium arsenide (Al x Ga 1-x For example, the low refractive index layer 21A and the high refractive index layer 21B are both made of aluminum gallium arsenide, but have different composition ratios. The first reflective layer 21 is not limited to this configuration as long as it can reflect light generated in the active layer 24.

[0056] The electrode 22 is in contact with the first reflective layer 21. The electrode 22 injects holes into the active layer 24. The electrode 22 may be made of any conductive material. The electrode 22 may be made of, for example, gold, copper, silver, or aluminum.

[0057] The spacer layer 23 is located between the first reflective layer 21 and the active layer 24. The spacer layer 23 is a semiconductor layer. The spacer layer 23 is, for example, an undoped semiconductor. The spacer layer 23 may be a single layer or multiple layers.

[0058] The active layer 24 is a semiconductor. In the active layer 24, injected electrons recombine with holes to emit light. The active layer 24 is sandwiched between, for example, the first reflective layer 21 and the second reflective layer 29. The active layer 24 is made of, for example, gallium arsenide, indium gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, indium gallium nitride, silicon germanium, or the like. The wavelength of the light emitted from the active layer 24 can be designed depending on the material constituting the active layer 24, and is, for example, 400 nm or more and 2000 nm or less.

[0059] The above-described superlattice structure 10 can be applied to the active layer 24. In this case, the thickness of each of the multiple well layers 1 constituting the superlattice structure 10 is preferably 2 nm or more and 20 nm or less.

[0060] The oxide layer 25 is, for example, aluminum oxide. The oxide layer 25 is on the active layer 24. The oxide layer 25 narrows the area of ​​a portion of the spin transport layer 26, thereby constricting the current. The oxide layer 25 causes current concentration in a specific portion of the spin transport layer 26, enabling efficient light generation. The oxide layer 25 can be formed by selective oxidation from the outer surface.

[0061] The spin transport layer 26 is in contact with the active layer 24. The spin transport layer 26 is a semiconductor layer. The spin transport layer 26 is made of, for example, aluminum gallium arsenide with a low aluminum concentration. The spin transport layer 26 transports spins injected from the first magnetic electrode 27 or the second magnetic electrode 28 to the active layer 24.

[0062] The above-described superlattice structure 10 can be applied to the spin transport layer 26. The sheet impurity densities of the multiple well layers 1 constituting the superlattice structure 10 are each 10 10 cm -2 Over 10 13 cm -2 The sheet impurity density of each of the plurality of barrier layers 2 constituting the superlattice structure 10 is preferably 10 or less. 10 cm -2 Over 10 13 cm -2It is preferable that the following is true: By doping at least one of the well layer 1 and the barrier layer 2 with impurities, spins injected from the first magnetic electrode 27 or the second magnetic electrode 28 can be easily transported to the active layer 24.

[0063] The above-described superlattice structure 10 may be applied to both the active layer 24 and the spin transport layer 26 .

[0064] The first magnetic electrode 27 is in contact with the spin transport layer 26. The first magnetic electrode 27 is, for example, on the spin transport layer 26. A non-magnetic layer may be provided between the first magnetic electrode 27 and the spin transport layer 26. The first magnetic electrode 27 includes a ferromagnetic material. The first magnetic electrode 27 is configured to receive the magnetization M generated by the ferromagnetic material. 27 The coercive force of the first magnetic electrode 27 is preferably, for example, 10 Oe or more. The first magnetic electrode 27 is made of, for example, Fe, FeCoB, FeCo, NiFe, FePt, CoPt, or the like.

[0065] When a current is applied from the first magnetic electrode 27 to the spin transport layer 26, the magnetization M 27 , spin-polarized electrons are injected into the spin transport layer 26. For example, the first magnetic electrode 27 injects up-spin electrons into the active layer 24 via the spin transport layer 26.

[0066] The second magnetic electrode 28 is in contact with the spin transport layer 26. The second magnetic electrode 28 is, for example, on the spin transport layer 26. A non-magnetic layer may be provided between the second magnetic electrode 28 and the spin transport layer 26. The second magnetic electrode 28 includes a ferromagnetic material. The same material as that of the first magnetic electrode 27 can be used for the second magnetic electrode 28. The second magnetic electrode 28 is configured to receive the magnetization M generated by the ferromagnetic material. 28 Magnetization M 28 is the magnetization M 27 is oriented in the opposite direction to the direction in which the

[0067] When a current is applied from the second magnetic electrode 28 to the spin transport layer 26, the magnetization M 28spin-polarized electrons are injected into the spin transport layer 26 by the second magnetic electrode 28. The polarization direction of the spin electrons injected into the spin transport layer 26 from the second magnetic electrode 28 is opposite to the polarization direction of the spin electrons injected into the spin transport layer 26 from the first magnetic electrode 27. For example, the second magnetic electrode 28 injects down-spin electrons into the active layer 24 via the spin transport layer 26.

[0068] The second reflective layer 29 is located in a position where it sandwiches the active layer 24 together with the first reflective layer 21. The second reflective layer 29 is, for example, a laminated film in which low refractive index layers 29A and high refractive index layers 29B are alternately stacked. The low refractive index layers 29A have a lower refractive index than the high refractive index layers 29B. The second reflective layer 29 is, for example, a III-V group compound semiconductor, such as aluminum gallium arsenide (Al x Ga 1-x For example, the low refractive index layer 29A and the high refractive index layer 29B are both made of aluminum gallium arsenide, but have different composition ratios. The second reflective layer 29 is not limited to this configuration as long as it can reflect light generated in the active layer 24.

[0069] The electron spin-controlled semiconductor laser 20 according to the first embodiment can be fabricated by repeatedly stacking and processing each layer. Each layer can be formed using, for example, molecular beam epitaxy, chemical vapor deposition (CVD), or sputtering. Each layer can be processed by, for example, photolithography.

[0070] Next, the operation of the electron spin control semiconductor laser 20 according to the first embodiment will be described. When a potential difference is applied between the electrode 22 and the first magnetic electrode 27, electrons are injected from the first magnetic electrode 27 into the spin transport layer 26 in accordance with the potential difference. The injected electrons are magnetized M 27 The electrons are spin-polarized by the electron transport layer 26 and become up-spin electrons. The up-spin electrons reach the active layer 24 via the spin transport layer 26. Holes are also injected into the active layer 24 from the electrode 22 side.

[0071] In the active layer 24, up-spin electrons and holes recombine to generate photons. For example, when an up-spin electron recombines with a heavy hole in the valence band, it emits left-handed circularly polarized light (σ - ) is emitted.

[0072] Similarly, when a potential difference is applied between the electrode 22 and the second magnetic electrode 28, electrons are injected from the second magnetic electrode 28 into the spin transport layer 26 in accordance with the potential difference. The injected electrons are magnetized M 28 The electrons are spin-polarized by the electron transport layer 26 and become down-spin electrons. The down-spin electrons reach the active layer 24 via the spin transport layer 26. Holes are also injected into the active layer 24 from the electrode 22 side.

[0073] In the active layer 24, down-spin electrons and holes recombine to generate photons. For example, when a down-spin electron recombines with a heavy hole in the valence band, it generates right-handed circularly polarized light (σ + ) is emitted.

[0074] In the electron spin-controlled semiconductor laser 20, the state of circular polarization of emitted light changes depending on the spin polarization state of electrons in the active layer 24. When the above-described superlattice structure 10 is applied to the spin transport layer 26, the spins injected from the first magnetic electrode 27 or the second magnetic electrode 28 can be propagated to the active layer 24 with little loss. Furthermore, when the above-described superlattice structure 10 is applied to the active layer 24, the spin relaxation time in the active layer can be varied depending on the structure, making it possible to control the polarization modulation characteristics of the output light.

[0075] The light generated in the active layer 24 is reflected between the first reflective layer 21 and the second reflective layer 29, and the electron spin-controlled semiconductor laser 20 emits light by stimulated emission.

[0076] The electron spin-controlled semiconductor laser 20 according to the first embodiment can increase the degree of polarization of the output light by applying the above-described superlattice structure 10 to the spin transport layer 26. Furthermore, the electron spin-controlled semiconductor laser 20 according to the first embodiment can control the polarization modulation characteristics of the light by applying the above-described superlattice structure 10 to the active layer 24.

[0077] Although the preferred embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to specific embodiments and modifications, and various modifications and variations are possible within the scope of the gist of the present invention as set forth in the claims. [Industrial Applicability]

[0078] The superlattice structure according to the present disclosure can be used when it is desired to propagate spins in three dimensions with high efficiency. The superlattice structure according to the present disclosure can be applied to, for example, the above-mentioned electron spin-controlled semiconductor laser and spin devices other than electron spin-controlled semiconductor lasers. [Explanation of symbols]

[0079] 1. Well layer 2. Barrier layer 3. Circuit Board 10 Superlattice structure 20 Electron spin control semiconductor laser 21 1st reflective layer 21A, 29A Low refractive index layer 21B, 29B high refractive index layer 22 electrodes 23 Spacer layer 24 Active layer 25 Oxide layer 26 Spin transport layer 27 First magnetic electrode 28 Second magnetic electrode 29 Second reflective layer

Claims

1. a stacked body including a plurality of barrier layers and a plurality of well layers; the plurality of barrier layers and the plurality of well layers each contain a group III-V compound semiconductor having a zinc blende structure; In the stacked body, the barrier layers and the well layers are stacked alternately in a <110> direction, a spin relaxation time of electrons in the stack is based on the number of stacking periods of the barrier layer and the well layer; the number of stacking periods of the barrier layers and the well layers in the stacked body is 2 or more and 50 or less; each of the plurality of barrier layers has a thickness of 0.2 nm or more and 6 nm or less; A superlattice structure having a spin relaxation time of 0.1 nsec or more and 10 nsec or less.

2. The superlattice structure of claim 1 , wherein at least one of the plurality of barrier layers and the plurality of well layers contains n-type impurities.

3. The superlattice structure of claim 1 , wherein at least one of the plurality of barrier layers and the plurality of well layers contains p-type impurities.

4. The superlattice structure of claim 1 , wherein at least one of the plurality of barrier layers and the plurality of well layers is an intrinsic semiconductor.

5. Further comprising a semiconductor substrate or semiconductor layer; The superlattice structure according to claim 1 , wherein the stack is stacked on a (110) plane of the semiconductor substrate or the semiconductor layer.

6. An electron spin-controlled semiconductor laser comprising the superlattice structure according to any one of claims 1 to 5.

7. a spin transport layer having the superlattice structure; The sheet impurity density of each of the plurality of barrier layers constituting the superlattice structure is 10 １０ cm －２ 10 above １３ cm －２ 7. The electron spin-controlled semiconductor laser according to claim 6, wherein:

8. a spin transport layer having the superlattice structure; The sheet impurity density of each of the plurality of well layers constituting the superlattice structure is 10 １０ cm －２ 10 above １３ cm －２ 7. The electron spin-controlled semiconductor laser according to claim 6, wherein:

9. An active layer is provided, the active layer has the superlattice structure, 7. The electron spin-control semiconductor laser according to claim 6, wherein each of the plurality of well layers constituting the superlattice structure has a thickness of 2 nm or more and 20 nm or less.

10. an active layer and a spin transport layer; 7. The electron spin-controlled semiconductor laser according to claim 6, wherein the active layer and the spin transport layer each comprise the superlattice structure.

11. a design step of determining the number of periods of stacking of barrier layers and well layers based on a desired spin relaxation time; a lamination step of alternately laminating the barrier layers and the well layers in a <110> direction in accordance with the number of periods determined in the design step, the barrier layer and the well layer each contain a group III-V compound semiconductor having a zinc blende structure; The method for manufacturing a superlattice structure, wherein the thickness of the barrier layer deposited in the deposition step is 0.2 nm to 6 nm.

12. 12. The method for manufacturing a superlattice structure according to claim 11, wherein the designing step further comprises a step of determining at least one of a thickness of the barrier layer and a sheet impurity density of the barrier layer or the well layer based on the desired spin relaxation time.

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