Semiconductor drive device and semiconductor module

Abstract

To provide a semiconductor drive device capable of improving the characteristics thereof, and a semiconductor module.SOLUTION: According to an embodiment, a semiconductor drive device includes a circuit section. The circuit section is configured to output a first output signal and a second output signal based on a first sawtooth wave and a second sawtooth wave different from the first sawtooth wave. The first output signal changes from a first potential to a second potential at a first time. The first output signal changes from the second potential to the first potential at a second time. The second output signal changes from a third potential to a fourth potential at the first time. The second output signal changes from the fourth potential to the third potential at a third time. The third time is after the first time and before the second time.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor driving device and a semiconductor module. [Background technology]

[0002] Semiconductor device drivers drive semiconductor devices such as transistors, and it is desirable to improve the characteristics of semiconductor device drivers. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-168543 Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments of the present invention provide a semiconductor driver and a semiconductor module that can improve characteristics. [Means for solving the problem]

[0005] According to an embodiment of the present invention, a semiconductor driving device includes a circuit unit configured to output a first output signal and a second output signal based on a first sawtooth wave and a second sawtooth wave different from the first sawtooth wave. The first output signal changes from a first potential to a second potential at a first time. The first output signal changes from the second potential to the first potential at a second time. The second output signal changes from a third potential to a fourth potential at the first time. The second output signal changes from the fourth potential to the third potential at a third time. The third time is after the first time and before the second time. [Brief explanation of the drawings]

[0006] [Figure 1]1(a) to 1(d) are schematic views illustrating the semiconductor driving device according to the first embodiment. [Figure 2] FIG. 2 is a schematic view illustrating the semiconductor driving device according to the first embodiment. [Figure 3] 3(a) to 3(c) are schematic views illustrating the semiconductor driving device according to the first embodiment. [Figure 4] FIG. 4 is a schematic view illustrating the semiconductor driving device according to the first embodiment. [Figure 5] FIG. 5 is a schematic view illustrating the semiconductor driving device according to the first embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In this specification and in each drawing, elements similar to those previously described with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted where appropriate.

[0008] (First embodiment) 1(a) to 1(d) are schematic views illustrating the semiconductor driving device according to the first embodiment. FIG. 2 is a schematic view illustrating the semiconductor driving device according to the first embodiment. 3(a) to 3(c) are schematic views illustrating the semiconductor driving device according to the first embodiment. As shown in FIG. 2, the semiconductor driving device 110 according to the embodiment includes a circuit section 70.

[0009] The circuit section 70 is configured to output a first output signal and a second output signal based on the first sawtooth wave and the second sawtooth wave.

[0010] 1(a) illustrates a first sawtooth wave W1. FIG. 1(b) illustrates a second sawtooth wave W2. FIG. 1(c) illustrates a first output signal DS1. FIG. 1(d) illustrates a second output signal DS2. The horizontal axis of these figures represents time tm.

[0011] 1(c), the first output signal DS1 changes from the first potential V1 to the second potential V2 at a first time t1, and from the second potential V2 to the first potential V1 at a second time t2.

[0012] 1(d), the second output signal DS2 changes from the third potential V3 to the fourth potential V4 at the first time t1. The second output signal DS2 changes from the fourth potential V4 to the third potential V3 at the third time t3. The third time t3 is after the first time t1 and before the second time t2.

[0013] Such first output signal DS1 and second output signal DS2 are output from the circuit section 70. As shown in Figure 2, the circuit section 70 may be configured to provide the first output signal DS1 and the second output signal DS2 to the semiconductor device 50.

[0014] For example, the semiconductor device 50 may include a transistor 50T including a first gate 51G and a second gate 52G. For example, one of the first output signal DS1 and the second output signal DS2 is supplied to the first gate 51G. The other of the first output signal DS1 and the second output signal DS2 is supplied to the second gate 52G. The transistor 50T is, for example, an IGBT (Insulated Gate Bipolar Transistor). The transistor 50T is, for example, a multi-gate IGBT. The first gate 51G is, for example, a main gate. The second gate 52G is, for example, a control gate. The first gate 51G and the second gate 52G are provided on the same element. The first gate 51G and the second gate 52G are electrically isolated from each other. Independent control signals are input to the first gate 51G and the second gate 52G.

[0015] The first output signal DS1 and the second output signal DS2 are supplied to the semiconductor device 50 (e.g., a multi-gate IGBT). The first time t1 corresponds to, for example, the turn-on time. The second time t2 corresponds to, for example, the turn-off time. At the first time t1 during turn-on, the first gate 51G and the second gate 52G are turned on substantially simultaneously. This reduces turn-on loss. Meanwhile, during turn-off, the second gate 52G is turned off at the third time t3, which is before the second time t2 when the first gate 51G is turned off. This reduces turn-off loss.

[0016] The first output signal DS1 and the second output signal DS2 are simultaneous when turned on, but have a time difference when turned off. A first reference example can be considered in which a delay circuit or the like is used to obtain the time difference when turned off. In the first reference example, one output signal is delayed by the delay circuit. The other output signal is generated from the delayed output signal. In this case, a time difference also occurs when the two signals are turned on.

[0017] On the other hand, a second reference example can be considered in which a switch circuit and a delay circuit are combined. In the second reference example, the switch circuit switches between an operation in which the command signal does not pass through the delay circuit when turned on and passes through the delay circuit when turned off. In this case, the command signal is applied to the second gate 52G, and a signal delayed from the command signal is applied to the first gate 51G. Due to the delayed signal from the command signal, a non-reaction time occurs when turned off, resulting in loss.

[0018] In contrast, in the embodiment, two sawtooth waves are used to obtain a time difference at the time of turn-off. This allows a time difference at the time of turn-off to be obtained without causing a time difference at the time of turn-on. There is no need to use a delay circuit. The second output signal DS2 can be turned off at the third time t3 before the command signal is turned off (the second time t2). This makes it possible to suppress the occurrence of unresponsive time.

[0019] In the embodiment, a desired output waveform can be obtained with a simple configuration. According to the embodiment, a semiconductor driving device with improved characteristics can be provided. In the semiconductor device 50 supplied by the semiconductor driving device 110 according to the embodiment, loss can be reduced.

[0020] As shown in Figures 1(c) and 1(d), the difference between the third time t3 and the second time t2 is defined as a first time difference Δt1. The first time difference Δt1 may be, for example, 1 μs or more and 20 μs or less. The difference between the first time t1 and the second time t2 is defined as a second time difference Δt2. The ratio of the first time difference Δt1 to the second time difference Δt2 may be, for example, 0.01 or more and 0.2 or less.

[0021] For example, the first potential V1 is lower than the second potential V2. The third potential V3 is lower than the fourth potential V4. The third potential V3 may be substantially the same as the first potential V1. The fourth potential V4 may be substantially the same as the second potential V2. When the first output signal DS1 is at the second potential V2, the semiconductor device 50 is in one conductive state. When the second output signal DS2 is at the fourth potential V4, the semiconductor device 50 is in one conductive state. When the first output signal DS1 is at the first potential V1 and the second output signal DS2 is at the third potential V3, the semiconductor device 50 is in a non-conductive state.

[0022] In one example, the first potential V1 and the third potential V3 are −15 V. The second potential V2 and the fourth potential V4 are +15 V.

[0023] As shown in FIGS. 1(a) and 1(b), the first bias value of the first sawtooth wave W1 is different from the second bias value of the second sawtooth wave W2. In this example, the first bias value of the first sawtooth wave W1 is substantially 0. The second bias value of the second sawtooth wave W2 is a first potential difference Vos (offset voltage). The first potential difference Vos (offset voltage) is greater than 0. The potential of the second sawtooth wave W2 is higher than the potential of the first sawtooth wave W1. The difference between the potential of the second sawtooth wave W2 and the potential of the first sawtooth wave W1 is the first potential difference Vos.

[0024] The first amplitude Va1 of the first sawtooth wave W1 is the same as the second amplitude Va2 of the second sawtooth wave W2. For example, the ratio of the first potential difference Vos between the first bias value and the second bias value to the first amplitude Va1 of the first sawtooth wave W1 may be, for example, not less than 0.1 and not more than 10.

[0025] The first period T1 of the first sawtooth wave W1 is substantially the same as the second period T2 of the second sawtooth wave W2. The first phase of the first sawtooth wave W1 is substantially the same as the second phase of the second sawtooth wave W2. The rising timing of the first sawtooth wave W1 substantially coincides with the rising timing of the second sawtooth wave W2.

[0026] 1(a), the circuitry 70 may be configured to output a first output signal DS1 based on a first difference ΔV1 between the time-varying third wave W3 and the first sawtooth wave W1. As shown in FIG. 1(b), the circuitry 70 may be configured to output a second output signal DS2 based on a second difference ΔV2 between the third wave W3 and the second sawtooth wave W2.

[0027] Figure 3(a) illustrates the first sawtooth wave W1. Figure 3(b) illustrates the second sawtooth wave W2. Figure 3(c) illustrates the third signal S3. Figures 3(a) to 3(c) illustrate periods longer than those illustrated in Figures 1(a) and 1(b).

[0028] 3(c), the third wave W3 may include, for example, a sine wave. The third period T3 of the sine wave is longer than the first period T1 of the first sawtooth wave W1. The third period T3 is longer than the second period T2 of the second sawtooth wave W2.

[0029] The amplitude of the third wave W3 is, for example, smaller than the first amplitude Va1. The amplitude of the third wave W3 is, for example, smaller than the second amplitude Va2. The maximum value of the potential of the third wave W3 is, for example, lower than the maximum value of the first sawtooth wave W1. The maximum value of the potential of the third wave W3 is, for example, lower than the maximum value of the first sawtooth wave W1. The minimum value of the potential of the third wave W3 is, for example, higher than the minimum value of the second sawtooth wave W2. The third wave W3 intersects with the first sawtooth wave W1 and the second sawtooth wave W2. For example, the third wave W3 intersects with the first sawtooth wave W1 and the second sawtooth wave W2 twice during the first period T1.

[0030] For example, the time when the value of the first sawtooth wave W1 transitions from being smaller than the value of the third wave W3 to being larger corresponds to the second time t2. The time when the value of the second sawtooth wave W2 transitions from being smaller than the value of the third wave W3 to being larger corresponds to the third time t3. Because an offset is provided between the first sawtooth wave W1 and the second sawtooth wave W2, the third time t3 is shifted with respect to the second time t2.

[0031] As shown in FIG. 1(a), the value of the first sawtooth wave W1 increases during the period from the first time t1 to the fourth time t4. The fourth time t4 occurs after the second time t2. At the first time t1 (or the fourth time t4), the value of the first sawtooth wave W1 decreases. The absolute value of the slope of the decrease in the value of the first sawtooth wave W1 is greater than the absolute value of the slope of the increase in the value of the first sawtooth wave W1.

[0032] 1(b), the value of the second sawtooth wave W2 increases from the first time t1 to the fourth time t4. At the first time t1 (or the fourth time t4), the value of the second sawtooth wave W2 decreases. The absolute value of the slope of the decrease in the value of the second sawtooth wave W2 is greater than the absolute value of the slope of the increase in the value of the second sawtooth wave W2.

[0033] The first period T1 and the second period T2 correspond to the time from the first time t1 to the fourth time t4.

[0034] As shown in FIG. 2, the circuit section 70 may include a first circuit 71 and a second circuit 72. The first circuit 71 is configured to output a first sawtooth signal S1 of a first sawtooth wave W1 and a second sawtooth signal S2 of a second sawtooth wave W2. The first sawtooth signal S1 and the second sawtooth signal S2 are, for example, carrier signals. The first circuit 71 may be, for example, a carrier signal generating section. The first circuit 71 may be, for example, a sawtooth waveform generating section. The first circuit 71 is configured to simultaneously output the first sawtooth signal S1 and the second sawtooth signal S2.

[0035] The second circuit 72 is configured to output a first output signal DS1 and a second output signal DS2 based on the first sawtooth signal S1 and the second sawtooth signal S2. For example, the second circuit 72 may be a PWM signal generator.

[0036] The circuit section 70 may further include a third circuit 73. The third circuit 73 is configured to output a time-varying third signal S3. The third signal S3 corresponds to a third wave W3.

[0037] The second circuit 72 is configured to output a first output signal DS1 based on a first difference ΔV1 (see FIG. 1(a)) between the third signal S3 and the first sawtooth signal S1. The second circuit 72 is configured to output a second output signal DS2 based on a second difference ΔV2 (see FIG. 1(b)) between the third signal S3 and the second sawtooth signal S2. The second circuit 72 may include, for example, a comparator.

[0038] The second circuit 72 may include a comparator that receives the third signal S3 and the first sawtooth signal S1 as inputs. When the potential of the first sawtooth signal S1 is higher than the potential of the third signal S3, the first output signal DS1 is at a first potential V1. When the potential of the third signal S3 is higher than the potential of the first sawtooth signal S1, the first output signal DS1 is at a second potential V2. The second circuit 72 may include a comparator that receives the third signal S3 and the second sawtooth signal S2 as inputs. When the potential of the second sawtooth signal S2 is higher than the potential of the third signal S3, the second output signal DS2 is at a third potential V3. When the potential of the third signal S3 is higher than the potential of the second sawtooth signal S2, the second output signal DS2 is at a fourth potential V4.

[0039] 3(c), the third signal S3 may include, for example, a sine wave. The third circuit 73 may be, for example, a sine wave generator. The third period T3 of the sine wave is longer than the first period T1 and longer than the second period T2. The third circuit 73 may be, for example, a reference signal generator.

[0040] 2, the circuit portion 70 may include a first terminal 77a and a second terminal 77b. The first terminal 77a may be configured to output a first output signal DS1. The second terminal 77b may be configured to output a second output signal DS2. In an embodiment, the first terminal 77a may be configured to output one of the first output signal DS1 and the second output signal DS2. The second terminal 77b may be configured to output the other of the first output signal DS1 and the second output signal DS2.

[0041] 2, a gate drive circuit 76 may be provided. The gate drive circuit 76 may be included in the circuit unit 70. The gate drive circuit 76 may be provided separately from the circuit unit 70. The gate drive circuit 76 may be included in the semiconductor drive device 110. The gate drive circuit 76 may be provided separately from the semiconductor drive device 110.

[0042] The gate drive circuit 76 is configured to supply one of the first output signal DS1 and the second output signal DS2 to the first gate 51G. The gate drive circuit 76 is configured to supply the other of the first output signal DS1 and the second output signal DS2 to the second gate 52G. The gate drive circuit 76 may include a photocoupler. This provides good electrical isolation between the high-power semiconductor device 50 and the semiconductor driver 110.

[0043] 2, a fifth circuit 75 may be provided. The fifth circuit 75 may be included in the circuit unit 70. The fifth circuit 75 may be provided separately from the circuit unit 70. The fifth circuit 75 may be included in the semiconductor driving device 110. The fifth circuit 75 may be provided separately from the semiconductor driving device 110.

[0044] The fifth circuit 75 is configured to output a control signal CS1. The control signal CS1 is used to control the first phase, the second phase, the first bias value, and the second bias value. The control signal CS1 is supplied to the second circuit 72. In the second circuit 72, a first sawtooth signal S1 and a second sawtooth signal S2 may be generated based on the control signal CS1. The fifth circuit 75 is, for example, a control signal generating unit.

[0045] For example, the controller 78 is configured to control the fifth circuit 75 and the third circuit 73 based on a command C1 (e.g., a command signal) supplied from the outside. The controller 78 may be provided separately from the circuit unit 70. The controller 78 may be included in the semiconductor driving device 110. The controller 78 may be provided separately from the semiconductor driving device 110.

[0046] 4 and 5 are schematic views illustrating the semiconductor driving device according to the first embodiment. 4 and 5, in the semiconductor driving device 111 according to the embodiment, the circuit section 70 further includes a fourth circuit 74. Except for this, the configuration of the semiconductor driving device 111 may be the same as the configuration of the semiconductor driving device 110.

[0047] A first operation OP1 and a second operation OP2 may be performed by the fourth circuit 74. Figure 4 corresponds to the first operation OP1. Figure 5 corresponds to the second operation OP2.

[0048] As already described, the circuit portion 70 may include a first terminal 77a and a second terminal 77b. As shown in FIG. 4, in a first operation OP1, the first terminal 77a is configured to output a first output signal DS1. In the first operation OP1, the second terminal 77b is configured to output a second output signal DS2. As shown in FIG. 5, in a second operation OP2, the first terminal 77a is configured to output a second output signal DS2. In the second operation OP2, the second terminal 77b is configured to output the first output signal DS1.

[0049] In a first operation OP1, the first output signal DS1 is supplied to the first gate 51G, and the second output signal DS2 is supplied to the second gate 52G. In a second operation OP2, the first output signal DS1 is supplied to the second gate 52G, and the second output signal DS2 is supplied to the first gate 51G. The operation of the main gate and the operation of the control gate are interchanged. For example, more stable operation can be achieved.

[0050] The fourth circuit 74 is configured to switch between the first operation OP1 and the second operation OP2. The fourth circuit 74 is, for example, a switch unit.

[0051] (Second embodiment) A semiconductor module 210 (see FIG. 2) according to the second embodiment includes the semiconductor driving device 110 according to the first embodiment and a semiconductor device 50. A semiconductor module 211 (see FIGS. 4 and 5) according to the second embodiment includes the semiconductor driving device 111 according to the first embodiment and a semiconductor device 50.

[0052] In the semiconductor module 210 and the semiconductor module 211, the circuit unit 70 may perform the operations described in relation to the first embodiment. For example, the circuit unit 70 is configured to supply a first output signal DS1 and a second output signal DS2 to the semiconductor device 50. The semiconductor device 50 includes a transistor 50T. The transistor 50T includes a first gate 51G and a second gate 52G. One of the first output signal DS1 and the second output signal DS2 is supplied to the first gate 51G. The other of the first output signal DS1 and the second output signal DS2 is supplied to the second gate 52G.

[0053] The transistor 50T is, for example, an IGBT. Turn-on loss and turn-off loss can be reduced. The transistor 50T further includes, for example, an emitter 50E and a collector 50C. The emitter 50E and the collector 50C are connected to a target device 58. The target device 58 is, for example, a load.

[0054] The embodiments may include the following technical solutions. (Technical proposal 1) A circuit unit is provided, the circuit section is configured to output a first output signal and a second output signal based on a first sawtooth wave and a second sawtooth wave different from the first sawtooth wave; A semiconductor driving device, wherein the first output signal changes from a first potential to a second potential at a first time, the first output signal changes from the second potential to the first potential at a second time, the second output signal changes from a third potential to a fourth potential at the first time, and the second output signal changes from the fourth potential to the third potential at a third time, the third time being after the first time and before the second time.

[0055] (Technical proposal 2) The semiconductor driving device according to Technical Solution 1, wherein the first bias value of the first sawtooth wave is different from the second bias value of the second sawtooth wave.

[0056] (Technical proposal 3) a first period of the first sawtooth wave is substantially the same as a second period of the second sawtooth wave; The semiconductor driving device according to Technical Solution 2, wherein the first phase of the first sawtooth wave is substantially the same as the second phase of the second sawtooth wave.

[0057] (Technical proposal 4) the circuitry is configured to output the first output signal based on a first difference between a time-varying third wave and the first sawtooth wave; The semiconductor driving device according to Technical Solution 3, wherein the circuit unit is configured to output the second output signal based on a second difference between the third wave and the second sawtooth wave.

[0058] (Technical proposal 5) the third wave includes a sine wave; The semiconductor driving device according to Technical Solution 4, wherein the third period of the sine wave is longer than the first period and longer than the second period.

[0059] (Technical proposal 6) the circuit section includes a first circuit and a second circuit, the first circuit is configured to output a first sawtooth signal of the first sawtooth wave and a second sawtooth signal of the second sawtooth wave; The semiconductor driving device according to Technical Solution 3, wherein the second circuit is configured to output the first output signal and the second output signal based on the first sawtooth signal and the second sawtooth signal.

[0060] (Technical proposal 7) the circuit section further includes a third circuit; the third circuit is configured to output a time-varying third signal; the second circuit is configured to output the first output signal based on a first difference between the third signal and the first sawtooth signal; The semiconductor driving device described in Technical Solution 6, wherein the second circuit is configured to output the second output signal based on a second difference between the third signal and the second sawtooth signal.

[0061] (Technical proposal 8) the third signal comprises a sine wave; The semiconductor driving device according to Technical Solution 7, wherein the third period of the sine wave is longer than the first period and longer than the second period.

[0062] (Technical proposal 9) A semiconductor driving device described in any one of technical proposals 3 to 8, wherein the ratio of a first potential difference between the first bias value and the second bias value to a first amplitude of the first sawtooth wave is greater than or equal to 0.1 and less than or equal to 10.

[0063] (Technical proposal 10) the circuit portion further includes a fifth circuit; The semiconductor driving device described in any one of Technical Solutions 3 to 9, wherein the fifth circuit is configured to output control signals for controlling the first phase, the second phase, the first bias value, and the second bias value.

[0064] (Technical proposal 11) when the potential of the first sawtooth signal is higher than the potential of the third signal, the first output signal is at the first potential; When the potential of the third signal is higher than the potential of the first sawtooth signal, the potential is the second potential; when the potential of the second sawtooth signal is higher than the potential of the third signal, the second output signal is at the third potential; when the potential of the third signal is higher than the potential of the second sawtooth signal, the second output signal is at the fourth potential; the second potential is higher than the first potential, The semiconductor driving device according to Technical Solution 7, wherein the fourth potential is higher than the third potential.

[0065] (Technical proposal 12) a potential of the second sawtooth signal is higher than a potential of the first sawtooth signal; the maximum value of the third signal is lower than the maximum value of the first sawtooth signal; The semiconductor driving device according to Technical Solution 7, wherein the minimum value of the third signal is higher than the minimum value of the second sawtooth signal.

[0066] (Technical proposal 13) the circuit portion includes a first terminal and a second terminal; In a first operation, the first terminal is configured to output the first output signal and the second terminal is configured to output the second output signal; The semiconductor driving device according to any one of Technical Solutions 1 to 11, wherein in a second operation, the first terminal is configured to output the second output signal, and the second terminal is configured to output the first output signal.

[0067] (Technical proposal 14) the circuit section further includes a fourth circuit; The semiconductor driving device described in Technical Solution 13, wherein the fourth circuit is configured to switch between the first operation and the second operation.

[0068] (Technical proposal 15) the circuit unit is configured to provide the first output signal and the second output signal to a semiconductor device; the semiconductor device includes a transistor including a first gate and a second gate; one of the first output signal and the second output signal is supplied to the first gate; The semiconductor driving device according to any one of Technical Solutions 1 to 14, wherein the other of the first output signal and the second output signal is supplied to the second gate.

[0069] (Technical proposal 16) The semiconductor driving device according to Technical Proposal 15, wherein the transistor is an IGBT (Insulated Gate Bipolar Transistor).

[0070] (Technical proposal 17) the circuit unit further includes a gate drive circuit; the gate drive circuit is configured to provide the one of the first output signal and the second output signal to the first gate; The semiconductor driving device according to Technical Solution 15 or 16, wherein the gate driving circuit is configured to supply the other of the first output signal and the second output signal to the second gate.

[0071] (Technical proposal 18) The semiconductor driving device according to Technical Solution 17, wherein the gate driving circuit includes a photocoupler.

[0072] (Technical proposal 19) A semiconductor driving device according to any one of claims 1 to 14; a semiconductor device; Equipped with the circuit unit is configured to provide the first output signal and the second output signal to the semiconductor device; the semiconductor device includes a transistor including a first gate and a second gate; one of the first output signal and the second output signal is supplied to the first gate; the other of the first output signal and the second output signal is supplied to the second gate.

[0073] (Technical proposal 20) The semiconductor module according to Technical Proposal 19, wherein the transistor is an IGBT (Insulated Gate Bipolar Transistor).

[0074] According to the embodiments, a semiconductor driving device and a semiconductor module that can improve characteristics are provided.

[0075] The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, the specific configurations of the elements, such as the circuit section, circuits, and semiconductor devices included in the semiconductor drive device and semiconductor module, are within the scope of the present invention as long as a person skilled in the art can implement the present invention in a similar manner and obtain similar effects by appropriately selecting them from within the known range.

[0076] Furthermore, any combination of two or more elements of each specific example within the scope of technical feasibility is also included within the scope of the present invention as long as it includes the gist of the present invention.

[0077] In addition, all semiconductor driving devices and semiconductor modules that can be implemented by a person skilled in the art by making appropriate design modifications based on the semiconductor driving devices and semiconductor modules described above as embodiments of the present invention also fall within the scope of the present invention, as long as they include the gist of the present invention.

[0078] In addition, within the scope of the concept of the present invention, a person skilled in the art may come up with various modifications and alterations, and it will be understood that these modifications and alterations also fall within the scope of the present invention.

[0079] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0080] 50: semiconductor device, 50C: collector, 50E: emitter, 50T: transistor, 51G, 52G: first and second gates, 58: target device, 70: circuit section, 71-75: first to fifth circuits, 76: gate drive circuit, 77a, 77b: first and second terminals, 78: controller, 110, 111: semiconductor drive device, 210, 211: semiconductor module, C1: command, CS1: control signal, DS1, DS2: first and second output signals, OP1, OP2: first and second operations, S1, S2: first and second sawtooth wave signals, S3: third signal, T1-T3: first to third periods, V1-V4: first to fourth potentials, Va1, Va2: first and second amplitudes, Vos: first potential difference, W1, W2: 1st and 2nd sawtooth waves, W3: 3rd wave, t1~t4: 1st to 4th times, ΔV1, ΔV2: 1st and 2nd difference, Δt1, Δt2: 1st and 2nd time difference

Claims

1. A circuit unit is provided, the circuit section is configured to output a first output signal and a second output signal based on a first sawtooth wave and a second sawtooth wave different from the first sawtooth wave; A semiconductor driving device, wherein the first output signal changes from a first potential to a second potential at a first time, the first output signal changes from the second potential to the first potential at a second time, the second output signal changes from a third potential to a fourth potential at the first time, and the second output signal changes from the fourth potential to the third potential at a third time, the third time being after the first time and before the second time.

2. 2. The semiconductor driving device according to claim 1, wherein a first bias value of the first sawtooth wave is different from a second bias value of the second sawtooth wave.

3. a first period of the first sawtooth wave is substantially the same as a second period of the second sawtooth wave; 3. The semiconductor driving device according to claim 2, wherein a first phase of the first sawtooth wave is substantially the same as a second phase of the second sawtooth wave.

4. the circuit section includes a first circuit and a second circuit, the first circuit is configured to output a first sawtooth signal of the first sawtooth wave and a second sawtooth signal of the second sawtooth wave; 4. The semiconductor driving device according to claim 3, wherein the second circuit is configured to output the first output signal and the second output signal based on the first sawtooth wave signal and the second sawtooth wave signal.

5. the circuit section further includes a third circuit; the third circuit is configured to output a time-varying third signal; the second circuit is configured to output the first output signal based on a first difference between the third signal and the first sawtooth signal; 5. The semiconductor driving device according to claim 4, wherein the second circuit is configured to output the second output signal based on a second difference between the third signal and the second sawtooth signal.

6. the third signal comprises a sine wave; 6. The semiconductor driving device according to claim 5, wherein the third period of the sine wave is longer than the first period and longer than the second period.

7. the circuit portion includes a first terminal and a second terminal; In a first operation, the first terminal is configured to output the first output signal and the second terminal is configured to output the second output signal; 2. The semiconductor driving device according to claim 1, wherein, in a second operation, the first terminal is configured to output the second output signal, and the second terminal is configured to output the first output signal.

8. the circuit section further includes a fourth circuit; The semiconductor driving device according to claim 7 , wherein the fourth circuit is configured to switch between the first operation and the second operation.

9. the circuit section is configured to provide the first output signal and the second output signal to a semiconductor device; the semiconductor device includes a transistor including a first gate and a second gate; one of the first output signal and the second output signal is supplied to the first gate; 9. The semiconductor driving device according to claim 1, wherein the other of the first output signal and the second output signal is supplied to the second gate.

10. The semiconductor driving device according to claim 1; a semiconductor device; Equipped with the circuit section is configured to supply the first output signal and the second output signal to the semiconductor device; the semiconductor device includes a transistor including a first gate and a second gate; one of the first output signal and the second output signal is supplied to the first gate; the other of the first output signal and the second output signal is supplied to the second gate.

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