Manufacturing method of substrate for display panel

Abstract

To provide a manufacturing method of a substrate for a display panel capable of protecting a component arranged at a lower layer of two insulator films in different construction materials, while securely removing both of the insulator films.SOLUTION: A manufacturing method of a substrate for a display panel includes: a second step of forming a semiconductor part 32A on an upper layer side of a glass substrate 21GS, as well as forming a protective film 32B on at least part of a display area AA for displaying an image at the upper layer side of the glass substrate 21GS; a fifth step of forming an insulator film 35 so as to cover the semiconductor part 32A and the protective film 32B from the upper layer side; a sixth step of forming an insulator film 36 in a construction material different from that of the insulator film 35 so as to cover the insulator film 35 from the upper layer side; an eighth step of removing, by etching, a portion overlapping the protective film 32B from the insulator film 35 and the insulator film 36; and a ninth step of removing the protective film 32B by etching.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a method for manufacturing a display panel substrate. [Background technology]

[0002] Conventionally, a known display panel substrate is described in Patent Document 1 below. The display panel substrate described in Patent Document 1 includes a semiconductor portion (semiconductor thin film) that constitutes a thin-film transistor and two insulating layers (interlayer insulating layers) that cover the semiconductor portion. When light passes through two insulating layers made of different materials, the difference in the refractive index of light causes the light to be reflected at the boundary between the two insulating layers, raising concerns about a decrease in light transmittance. For this reason, Patent Document 1 describes a method for improving light transmittance by removing the two insulating layers in the opening region by etching. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-242803 Summary of the Invention [Problem to be solved by the invention]

[0004] When the insulating film is removed by etching as in the above configuration, there is a concern that the film disposed below the insulating film may be etched (over-etched). This may result in a thinning of a portion of the film, affecting light transmittance and resulting in a deterioration in display quality. However, if the etching time for both insulating films is shortened to prevent over-etching of the components disposed below both insulating films, there is a concern that both insulating films may not be completely removed, resulting in residue.

[0005] The technology disclosed in this specification was developed based on the above circumstances, and aims to provide a method for manufacturing a display panel substrate that can reliably remove two insulating layers made of different materials while protecting components arranged below both insulating layers. [Means for solving the problem]

[0006] As a means for solving the above problem, the method for manufacturing a display panel substrate disclosed in this specification is characterized by comprising: a semiconductor portion forming step of forming a semiconductor portion on an upper layer side of an insulating substrate; a first film forming step of forming a first film composed of any one of a transparent electrode material, a semiconductor material, and a metal material on at least a part of a display area on the upper layer side of the insulating substrate where an image is displayed; a first insulating film forming step, which is performed after the semiconductor portion forming step and the first film forming step, of forming a first insulating film so as to cover the semiconductor portion and the first film from above; a second insulating film forming step, which is performed after the first insulating film forming step, of forming a second insulating film made of a material different from the first insulating film so as to cover the first insulating film from above; a first etching step, which is performed after the second insulating film forming step, of etching away portions of the first insulating film and the second insulating film that overlap with the first film; and a second etching step, which is performed after the first etching step, of etching away the first film.

[0007] Furthermore, the first film can be made of the same material as the semiconductor portion, so that the semiconductor portion forming step and the first film forming step can be performed in the same step, thereby reducing the number of steps required.

[0008] Furthermore, the method may include a third insulating film formation process that is performed before the semiconductor portion formation process and the first film formation process, and that forms a third insulating film made of a material different from the first film on the upper side of the insulating substrate, and in the first film formation process, the first film may be formed in a manner that covers at least a portion of the third insulating film from the upper side.

[0009] Furthermore, in the first etching step, the first insulating film and the second insulating film can be removed by dry etching, and in the second etching step, the first film can be removed by wet etching.

[0010] The first film may have a light-blocking property. [Effects of the Invention]

[0011] The technology described in this specification provides a method for manufacturing a display panel substrate that can reliably remove two insulating layers made of different materials while protecting components disposed below both insulating layers. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a schematic cross-sectional view of a liquid crystal display device according to a first embodiment. [Figure 2] 1 is a schematic plan view of a liquid crystal panel and a flexible substrate provided in a liquid crystal display device according to Embodiment 1. [Figure 3] FIG. 1 is a circuit diagram showing a pixel arrangement in a display area of ​​an array substrate provided in a liquid crystal panel according to a first embodiment. [Figure 4] FIG. 1 is a cross-sectional view showing a state in which a base coat film is formed in a first step included in the manufacturing process of the array substrate according to the first embodiment. [Figure 5] FIG. 1 is a cross-sectional view showing a state in which a semiconductor portion and a protective film are formed in a second step included in the manufacturing process of the array substrate according to the first embodiment. [Figure 6] FIG. 10 is a cross-sectional view showing a state in which an insulating film 35 is formed in a fifth step included in the manufacturing process of the array substrate according to the first embodiment. [Figure 7] FIG. 10 is a cross-sectional view showing a state in which an insulating film 36 is formed in a sixth step included in the manufacturing process of the array substrate according to the first embodiment. [Figure 8] FIG. 10 is a cross-sectional view showing a state in which a source electrode and a drain electrode are formed in a seventh step included in the manufacturing process of the array substrate according to the first embodiment. [Figure 9]FIG. 10 is a cross-sectional view showing a state in which parts of the insulating films 33, 35, and 36 are removed by etching in an eighth step included in the manufacturing process of the array substrate according to the first embodiment. [Figure 10] FIG. 10 is a cross-sectional view showing a state in which the protective film is removed by etching in a ninth step included in the manufacturing process of the array substrate according to the first embodiment. [Figure 11] FIG. 10 is a cross-sectional view showing a state in which a source electrode and a drain electrode are formed in a seventh step included in the manufacturing process of the array substrate according to the second embodiment. [Figure 12] FIG. 10 is a cross-sectional view showing a state in which the base coat film and the insulating films 33, 35, and 36 are partially removed by etching in an eighth step included in the manufacturing process of the array substrate according to the second embodiment. [Figure 13] FIG. 10 is a cross-sectional view showing a state in which the protective film is removed by etching in a ninth step included in the manufacturing process of the array substrate according to the second embodiment. [Figure 14] FIG. 10 is a cross-sectional view showing a state in which an insulating film 237 is formed in an eighth step included in the manufacturing process of the array substrate according to the third embodiment. [Figure 15] FIG. 10 is a cross-sectional view showing a state in which a part of the insulating films 236 and 237 is removed by etching in a ninth step included in the manufacturing process of the array substrate according to the third embodiment. [Figure 16] FIG. 10 is a cross-sectional view showing a state in which the protective film is removed by etching in a tenth step included in the manufacturing process of the array substrate according to the third embodiment. [Figure 17] FIG. 10 is a cross-sectional view showing a state in which an insulating film 237 is formed in an eighth step included in the manufacturing process of the array substrate according to the fourth embodiment. [Figure 18] 10 is a cross-sectional view showing a state in which a part of the base coat film and insulating films 233, 235, 236, and 237 are removed by etching in a ninth step included in the manufacturing process of the array substrate according to the fourth embodiment. [Figure 19] FIG. 10 is a cross-sectional view showing a state in which the protective film is removed by etching in a tenth step included in the manufacturing process of the array substrate according to the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] <Embodiment 1> Embodiment 1 will be described with reference to Figures 1 to 10. In this embodiment, an array substrate 21 provided in a liquid crystal display device 10 is exemplified as a display panel substrate. Note that X-axis, Y-axis, and Z-axis are shown in some of the drawings, and the directions of the axes are depicted as being in the directions shown in the drawings. The liquid crystal display device 10 includes at least a liquid crystal panel 11 (display panel) and a backlight device 12 (illumination device) that irradiates light onto the liquid crystal panel 11.

[0014] The backlight device 12 has a known configuration and includes, for example, a light source such as an LED and optical members that convert light from the light source into planar light by applying an optical effect to the light. As shown in Fig. 2, the liquid crystal panel 11 has an overall rectangular shape in a planar view. The central portion of the screen of the liquid crystal panel 11 is a display area AA where an image is displayed. The frame-shaped outer peripheral portion of the screen of the liquid crystal panel 11 that surrounds the display area AA is a non-display area NAA where no image is displayed. In Fig. 2, the area surrounded by a dashed line is the display area AA.

[0015] As shown in Fig. 1, the liquid crystal panel 11 is formed by bonding together a pair of substrates 20, 21. Of the pair of substrates 20, 21, the one disposed on the front side is a counter substrate 20 (CF substrate), and the one disposed on the back side is an array substrate 21 (display panel substrate, active matrix substrate). The counter substrate 20 and the array substrate 21 are each formed by laminating various films on the inner surface of glass substrates 20GS, 21GS, which are both nearly transparent and have excellent light-transmitting properties. The glass substrates 20GS, 21GS contain, for example, alkali-free glass as a main material.

[0016] The array substrate 21 is larger than the counter substrate 20, and a portion of it protrudes laterally relative to the counter substrate 20. A flexible substrate 13 is mounted on the protruding portion 21A of the array substrate 21. The flexible substrate 13 is configured by forming a large number of wiring patterns on an insulating and flexible base material. One end of the flexible substrate 13 is connected to the array substrate 21, and the other end is connected to an external control substrate (signal supply source) (not shown). Various signals supplied from the control substrate are transmitted to the liquid crystal panel 11 via the flexible substrate 13.

[0017] As shown in FIG. 2, a circuit section 14 (peripheral circuit section) is provided in the non-display area NAA of the liquid crystal panel 11. The circuit section 14 includes a first circuit section 14A and a second circuit section 14B. A pair of first circuit sections 14A are arranged so as to sandwich the display area AA from both sides in the X-axis direction. The first circuit section 14A is provided in a strip-shaped range extending along the Y-axis direction. The first circuit section 14A is for supplying scanning signals to gate wiring 25 (described later) and is provided monolithically on the array substrate 21. The first circuit section 14A is a GDM (Gate Driver Monolithic) circuit. The first circuit section 14A includes a shift register circuit that outputs scanning signals at predetermined timing, a buffer circuit that amplifies the scanning signals, and the like.

[0018] The second circuit unit 14B is disposed at a position sandwiched between the display area AA and the flexible substrate 13 in the Y-axis direction. The second circuit unit 14B is provided in a strip-shaped range extending along the X-axis direction. The second circuit unit 14B is for supplying image signals (data signals) to the source lines 26 described below, and is provided monolithically on the array substrate 21. The second circuit unit 14B includes a demultiplexer circuit (source signal division circuit) and the like. The second circuit unit 14B has a switch function that divides the image signals (source signals) supplied by the source driver 14C and distributes them to each source line 26.

[0019] As shown in FIG. 1, the pair of substrates 20, 21 are disposed opposite each other with a gap in the Z-axis direction, which is the normal direction to the plate surfaces of the substrates 20, 21. Between the pair of substrates 20, 21 are at least a liquid crystal layer 22 and a sealing portion 23 that seals the liquid crystal layer 22. The liquid crystal layer 22 contains liquid crystal molecules, which are a substance whose optical properties change when an electric field is applied. The sealing portion 23 has a rectangular frame shape (endless ring) in plan view as a whole, and surrounds the liquid crystal layer 22 all around in the non-display area NAA. The sealing portion 23 maintains a gap (cell gap) equal to the thickness of the liquid crystal layer 22. A polarizing plate 24 is attached to the outer surface of each of the pair of substrates 20, 21.

[0020] As shown in FIG. 3, a plurality of gate lines 25 (scanning lines) and source lines 26 (image lines) are arranged in a grid pattern on the inner surface of the display area AA of the array substrate 21. The gate lines 25 extend generally along the X-axis direction across the display area AA. A plurality of gate lines 25 are arranged side by side at intervals in the Y-axis direction. Scanning signals output from the first circuit unit 14A described above are supplied to the plurality of gate lines 25 in order from the upper row side in FIG. 3. The source lines 26 extend generally along the Y-axis direction across the display area AA and intersect with the gate lines 25. A plurality of source lines 26 are arranged at intervals in the X-axis direction. An image signal output from the second circuit unit 14B described above is distributed to the source lines 26.

[0021] A pixel TFT 27 and a pixel electrode 28 are provided near the intersection of the gate line 25 and the source line 26. The pixel TFTs 27 and the pixel electrodes 28 are regularly arranged in groups along the X-axis and Y-axis directions. The pixel TFT 27 is connected to the gate line 25, the source line 26, and the pixel electrode 28. When driven based on a scanning signal supplied to the gate line 25, the pixel TFT 27 charges the pixel electrode 28 to a potential based on an image signal supplied to the source line 26.

[0022] Next, various films laminated on the glass substrate 21GS of the array substrate 21 will be described in detail with reference to FIG. 10. FIG. 10 illustrates a cross-sectional configuration of the display area AA (pixel TFT 27) of the array substrate 21 during the manufacturing process. As shown in FIG. 10, the glass substrate 21GS is laminated with at least a base coat film 31, a semiconductor film 32, an insulating film 33 (gate insulating film), a metal film 34, an insulating film 35, an insulating film 36, and a metal film 37, in this order from the lower layer side (the glass substrate 21GS side). Note that the backlight device 12 is disposed on the outer surface side (the lower surface side in FIG. 1) of the array substrate 21, as shown in FIG. 1. Therefore, light emitted from the backlight device 12 enters the glass substrate 21GS from below in FIG. 10, passes through the glass substrate 21GS, and then passes through the films 31 to 37 formed on the glass substrate 21GS.

[0023] The metal films 34, 37 are each a single layer film made of one type of metal material, or a laminated film or alloy made of different types of metal materials, and thus have electrical conductivity and light-blocking properties. The base coat film 31 and the insulating film 33 are made of inorganic materials (inorganic resin materials), such as SiO (silicon oxide, silicon oxide) and SiN (silicon nitride). The insulating film 35 is made of SiN (silicon nitride). The insulating film 36 is made of SiO (silicon oxide, silicon oxide). In the array substrate 21, a planarization film (not shown) made of an organic material (organic resin material), such as PMMA (acrylic resin), is provided to cover the insulating film 36 from the upper layer side (upper side in FIG. 10), and the pixel electrode 28 (see FIG. 3) and the common electrode (not shown) are provided on the upper layer side of this planarization film.

[0024] The semiconductor film 32 is made of a crystalline polysilicon semiconductor material prepared by a known method such as laser crystallization. The polysilicon semiconductor material of the semiconductor film 32 has higher electron mobility than oxide semiconductor materials. The semiconductor film 32 may be made of an oxide semiconductor material. The semiconductor film 32 may contain at least one metal element selected from the group consisting of In, Ga, and Zn, and may be, for example, an In-Ga-Zn-O-based semiconductor (e.g., indium gallium zinc oxide). Here, the In-Ga-Zn-O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc). The ratio (composition ratio) of In, Ga, and Zn is not particularly limited, and examples include In:Ga:Zn=2:2:1, In:Ga:Zn=1:1:1, and In:Ga:Zn=1:1:2. The In-Ga-Zn-O-based semiconductor used in the semiconductor film 32 may be amorphous or crystalline.

[0025] The semiconductor film 32 may contain other oxide semiconductors instead of the In—Ga—Zn—O-based semiconductor. For example, it may contain an In—Sn—Zn—O-based semiconductor (e.g., In2O3-SnO2-ZnO; InSnZnO). The In—Sn—Zn—O-based semiconductor is a ternary oxide of In (indium), Sn (tin), and Zn (zinc). Alternatively, the semiconductor film 32 may include an In-W-Zn-O-based semiconductor containing W (tungsten), an In-W-Sn-Zn-O-based semiconductor, an In-Al-Zn-O-based semiconductor, an In-Al-Sn-Zn-O-based semiconductor, a Zn-O-based semiconductor, an In-Zn-O-based semiconductor, a Zn-Ti-O-based semiconductor, a Cd-Ge-O-based semiconductor, a Cd-Pb-O-based semiconductor, CdO (cadmium oxide), an Mg-Zn-O-based semiconductor, an In-Ga-Sn-O-based semiconductor, an In-Ga-O-based semiconductor, a Zr-In-Zn-O-based semiconductor, an Hf-In-Zn-O-based semiconductor, an Al-Ga-Zn-O-based semiconductor, a Ga-Zn-O-based semiconductor, an In-Ga-Zn-Sn-O-based semiconductor, or the like.

[0026] As shown in Fig. 10, a pixel TFT 27 is arranged in the display area AA. The pixel TFT 27 is a so-called top-gate TFT and includes a gate electrode 34A, a source electrode 37A, a drain electrode 37B, and a semiconductor portion 32A. The semiconductor portion 32A is made of a semiconductor film 32. The gate electrode 34A is arranged above the semiconductor portion 32A, overlapping the semiconductor portion 32A with an insulating film 33 interposed therebetween. The gate electrode 34A is arranged above the semiconductor portion 32A, overlapping a central portion of the semiconductor portion 32A.

[0027] The gate electrode 34A is made of a metal film 34. The gate electrode 34A is connected to the gate wiring 25 (see FIG. 3). When a scanning signal is supplied to the gate electrode 34A, an electric field acting on the semiconductor portion 32A from the gate electrode 34A generates a channel region in the upper layer side (gate electrode 34A side) of the semiconductor portion 32A.

[0028] The source electrode 37A is made of a metal film 37. At least a portion of the source electrode 37A is disposed above the semiconductor portion 32A, with the insulating films 33, 35, and 36 interposed between them. The source electrode 37A is disposed above one end portion of the semiconductor portion 32A. The source electrode 37A is connected to the source wiring 26 (see FIG. 3). The source electrode 37A is connected to the semiconductor portion 32A through a contact hole 41 formed in the insulating films 33, 35, and 36.

[0029] The drain electrode 37B is made of a metal film 37. At least a portion of the drain electrode 37B is arranged to overlap the upper side of the semiconductor portion 32A with the insulating films 33, 35, and 36 interposed therebetween. The drain electrode 37B is arranged to overlap the other end portion of the semiconductor portion 32A. The drain electrode 37B is connected to the semiconductor portion 32A through a contact hole 42 formed in the insulating films 33, 35, and 36. In this way, since both the source electrode 37A and the drain electrode 37B are made of the metal film 37, the number of metal film layers can be reduced compared to when the source electrode 37A and the drain electrode 37B are made of different metal films.

[0030] 3, pixel electrodes 28 made of a transparent electrode film are arranged in the display area AA. The pixel electrodes 28 are connected to the drain electrodes 27C through contact holes (not shown). A common electrode (not shown) made of a transparent electrode film is arranged in the display area AA across almost the entire area. The transparent electrode film constituting the pixel electrodes 28 and the common electrode is made of a transparent electrode material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). The common electrode is arranged to overlap all of the pixel electrodes 28. A plurality of slits are formed in the common electrode in the portions that overlap the plurality of pixel electrodes 28.

[0031] A common potential signal serving as a common potential (reference potential) is supplied to the common electrode. When the pixel electrode 28 is charged to a potential based on an image signal transmitted to the source line 26 in response to the driving of the pixel TFT 27, a potential difference is generated between the pixel electrode 28 and the common electrode. This generates a fringe electric field (oblique electric field) between the edge of the slit in the common electrode and the pixel electrode 28, which includes a component normal to the surface of the array substrate 21 in addition to a component along the surface of the array substrate 21. Therefore, by utilizing this fringe electric field, the orientation state of the liquid crystal molecules contained in the liquid crystal layer 22 can be controlled, and a predetermined display is produced based on the orientation state of the liquid crystal molecules. In other words, the liquid crystal panel 11 according to this embodiment operates in a fringe field switching (FFS) mode. However, the operating mode of the liquid crystal panel 11 is not limited to this mode.

[0032] Next, a description will be given of a manufacturing method of the array substrate 21 (a manufacturing method of a display panel substrate). The manufacturing method of the array substrate 21 includes the following steps: a first step of forming a base coat film 31 on a glass substrate 21GS; a second step of forming a semiconductor film 32, performing annealing treatment or the like, and then patterning the semiconductor film 32 to form a semiconductor portion 32A and a protective film 32B; a third step of forming an insulating film 33; a fourth step of forming and patterning a metal film 34; a fifth step of forming an insulating film 35; a sixth step of forming an insulating film 36; a seventh step of forming and patterning a metal film 37; an eighth step of removing parts of the insulating films 35 and 36 by etching; and a ninth step of removing the protective film 32B by etching.

[0033] The term "patterning" used above refers to film processing based on a general photolithography method. Specifically, a photoresist film is formed on the film to be processed, the photoresist film is exposed to light by an exposure device through a photomask having a predetermined pattern, the photoresist film is developed, and etching is performed through the developed photoresist film, thereby processing the film to be processed, i.e., patterning the film.

[0034] In the first step (the third insulating film forming step carried out before the semiconductor portion forming step and the first film forming step), as shown in Figure 4, a base coat film 31 (third insulating film) made of a material different from the protective film 32B is formed on the upper side of the glass substrate 21GS (insulating substrate).

[0035] In the second step (semiconductor portion forming step and first film forming step) performed after the first step, the semiconductor film 32 is patterned to form a semiconductor portion 32A and a protective film 32B on the upper layer side of the glass substrate 21GS (more specifically, on the base coat film 31), as shown in Fig. 5. That is, the protective film 32B is formed so as to cover part of the base coat film 31 from the upper layer side. The protective film 32B is formed in part (opening region) of the display area AA where an image is displayed, and is made of the same material (semiconductor material) as the semiconductor portion 32A.

[0036] In a third step performed after the second step, an insulating film 33 is formed so as to cover the semiconductor portion 32A and the protective film 32B from above. In a fourth step performed after the third step, a metal film 34 is formed and patterned to form a gate electrode 34A.

[0037] In a fifth step (first insulating film forming step) performed after the fourth step, an insulating film 35 (first insulating film) made of SiN is formed so as to cover the gate electrode 34A and the insulating film 33 (and consequently the semiconductor portion 32A and the protective film 32B) from above, as shown in Fig. 6. In a sixth step (second insulating film forming step) performed after the fifth step, an insulating film 36 (second insulating film made of a material different from the first insulating film) made of SiO is formed so as to cover the insulating film 35 from above, as shown in Fig. 7. In a seventh step performed after the sixth step, a metal film 37 is formed and patterned to form a source electrode 37A and a drain electrode 37B, as shown in Fig. 8.

[0038] In an eighth step (first etching step performed after the second insulating film forming step) performed after the seventh step, portions of the insulating films 33, 35, and 36 that overlap with the protective film 32B are removed by etching, as shown in Fig. 9. As a result, portions of the insulating films 33, 35, and 36 are removed, thereby forming openings 51. In the eighth step, the insulating films 33, 35, and 36 are removed by, for example, dry etching.

[0039] In the ninth step (second etching step) performed after the eighth step, the protective film 32B is removed by etching, as shown in FIG. 10 . The protective film 32B is removed, thereby forming an opening 52. In the ninth step, wet etching or dry etching is performed depending on the material of the protective film 32B. For example, if the protective film 32B is an In—Ga—Zn—O-based semiconductor, the protective film 32B is removed by wet etching. If the protective film 32B is a silicon semiconductor material, the protective film 32B is removed by dry etching. In FIG. 10 , the residue of the protective film 32B after etching is denoted by the reference symbol 32D. In this embodiment, a planarizing film (not shown) is formed after the ninth step. As a result, the openings 151 and 152 formed in the eighth and ninth steps are filled with the planarizing film.

[0040] Next, the effects of this embodiment will be described. In this embodiment, the eighth step can remove the insulating films 33, 35, and 36 from a portion of the display area AA. This can prevent light from being reflected at the boundary surfaces of the insulating films 33, 35, and 36, thereby increasing the light transmittance of the array substrate 21. Here, in the eighth step, the protective film 32B can protect the components disposed thereunder (the base coat film 31 and the glass substrate 21GS). This ensures sufficient etching time for the insulating films 33, 35, and 36, and ensures reliable removal of the insulating films 33, 35, and 36.

[0041] Furthermore, the protective film 32B is made of a semiconductor material and is made of a different material from the insulating films 33, 35, and 36. Therefore, in the eighth step, the protective film 32B is less likely to be over-etched, and the components disposed below it (the base coat film 31 and the glass substrate 21GS) can be more reliably protected. If the protective film 32B is over-etched in the eighth step, the protective film 32B may become thin in parts, affecting light transmittance and potentially resulting in a deterioration in display quality. In the above method, the protective film 32B is removed by etching in the ninth step, thereby preventing a deterioration in display quality due to the protective film 32B.

[0042] Furthermore, the protective film 32B is made of the same material as the semiconductor portion 32A. This allows the step of forming the semiconductor portion 32A (semiconductor portion forming step) and the step of forming the protective film 32B (first film forming step) to be performed in the same step (second step), thereby reducing the number of work steps.

[0043] The method also includes a first step, which is performed before the second step, of forming a base coat film 31 made of a different material from the protective film 32B on the upper side of the glass substrate 21GS. In the second step, the protective film 32B is formed so as to cover a portion of the base coat film 31 from the upper side. As a result, in the eighth step, the base coat film 31 can be protected by the protective film 32B. Since the protective film 32B and the base coat film 31 are made of different materials, in the ninth step, an etching method can be performed that has a higher etching rate for the protective film 32B and a lower etching rate for the base coat film 31. In this way, in the ninth step, etching of the base coat film 31 can be prevented, and partial thinning of the base coat film 31 can be prevented.

[0044] In the eighth step, the insulating films 33, 35, and 36 are removed by dry etching, and in the ninth step, the protective film 32B is removed by wet etching. By using a material for the protective film 32B that has a high etching rate in wet etching but a low etching rate in dry etching, it is possible to prevent the protective film 32B from being etched in the eighth step. This allows the protective film 32B to reliably protect the components disposed below the protective film 32B.

[0045] <Embodiment 2> A second embodiment of the present invention will be described with reference to Figures 11 to 13. The same parts as those in the above-described embodiment are designated by the same reference numerals, and duplicated explanations will be omitted. The array substrate 121 of this embodiment differs from the above-described embodiment in that a protective film 132B is formed between the glass substrate 21GS and the base coat film 31. In this embodiment, a protective film forming step (first film forming step) of forming the protective film 132B is performed before the step of forming the semiconductor portion 32A (semiconductor portion forming step).

[0046] The protective film 132B is preferably made of a material that can be wet etched, and examples thereof include transparent electrode materials such as ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide), and light-shielding metal materials such as Mo (Molybdenum), W (Tungsten), and MoW (Molybdenum Tungsten), which is an alloy of Mo and W.

[0047] In this embodiment, as shown in FIG. 11 , in the seventh step, a metal film 37 is formed and patterned to form a source electrode 37A and a drain electrode 37B. Then, in the eighth step (a first etching step performed after the second insulating film formation step), as shown in FIG. 12 , portions of the base coat film 31 and the insulating films 33, 35, and 36 that overlap with the protective film 132B are removed by, for example, dry etching. As a result, portions of the base coat film 31 and the insulating films 33, 35, and 36 are removed, forming an opening 151. In this embodiment, the protective film 132B is interposed between the base coat film 31 and the glass substrate 21GS. Therefore, in the eighth step, the glass substrate 21GS can be protected by the protective film 132B.

[0048] In the ninth step (second etching step) performed after the eighth step, the protective film 132B is removed by, for example, wet etching, as shown in Fig. 13. As a result, the protective film 132B is removed, thereby forming an opening 152. Furthermore, if the protective film 132B has a light-shielding property, and if residues 132D of the protective film 132B are left behind in the ninth step, the residues 132D can be used as a black matrix. This makes it possible to prevent color mixing in light transmitted through the array substrate 121.

[0049] <Embodiment 3> A second embodiment of the present invention will be described with reference to FIGS. 14 to 16. The same components as those in the above-described embodiments are designated by the same reference numerals, and redundant description will be omitted. In an array substrate 221 of this embodiment, the configuration of a pixel TFT 227 differs from that of the above-described embodiments. The pixel TFT 227 is a so-called bottom-gate TFT, and includes a gate electrode 234A, a source electrode 237A, a drain electrode 237B, and a semiconductor portion 232A, as shown in FIG. 14.

[0050] The gate electrode 234A is arranged to overlap the lower layer side of the semiconductor portion 232A with insulating films 233 and 235 interposed therebetween. The gate electrode 234A is arranged to overlap the central portion of the semiconductor portion 232A. The source electrode 237A is arranged to overlap at least a portion thereof on the upper layer side of the semiconductor portion 232A. The source electrode 237A is arranged to overlap one end portion of the semiconductor portion 232A. The drain electrode 237B is arranged to overlap at least a portion thereof on the upper layer side of the semiconductor portion 232A. The drain electrode 237B is arranged to overlap the other end portion of the semiconductor portion 232A.

[0051] The manufacturing method of the array substrate 221 of this embodiment includes the following steps: a first step of depositing a base coat film 31 on a glass substrate 21GS; a second step of depositing and patterning a metal film to form a gate electrode 234A; a third step of depositing an insulating film 233; a fourth step of depositing an insulating film 235; a fifth step of depositing a semiconductor film, performing an annealing treatment or the like, and then patterning the semiconductor film to form a semiconductor portion 232A and a protective film 232B; a sixth step of depositing and patterning a metal film to form a source electrode 237A and a drain electrode 237B; a seventh step (first insulating film forming step) of depositing an insulating film 236 (first insulating film); an eighth step (second insulating film forming step) of depositing an insulating film 237 (second insulating film); a ninth step of etching away portions of the insulating film 236 and the insulating film 237; and a tenth step of etching away the protective film 232B. In this embodiment, the insulating film 233 is made of SiN, and the insulating film 235 is made of SiO. The insulating film 236 is made of SiO, and the insulating film 237 is made of SiN.

[0052] In the eighth step, as shown in FIG. 14, an insulating film 237 (second insulating film) is formed. Then, in a ninth step (first etching step performed after the second insulating film forming step) performed after the eighth step, portions of the insulating films 236 and 237 that overlap with the protective film 232B are removed by etching, as shown in FIG. 15. As a result, portions of the insulating films 236 and 237 are removed, thereby forming openings 251. In this eighth step, the insulating films 236 and 237 are removed by dry etching. As shown in FIG. 14, the protective film 232B is interposed between the insulating films 235 and 236. As a result, in the eighth step, the insulating film 235 can be protected by the protective film 232B.

[0053] In a tenth step (second etching step) performed after the ninth step, the protective film 232B is removed by etching, as shown in FIG. 16. As a result, the protective film 232B is removed, thereby forming an opening 252. In FIG. 16, the residue of the protective film 232B after etching is denoted by the reference symbol 232D. In the tenth step, wet etching or dry etching is performed depending on the material of the protective film 232B. For example, if the protective film 232B is an In—Ga—Zn—O-based semiconductor, the protective film 232B is removed by wet etching, and if the protective film 232B is a silicon semiconductor material, the protective film 232B is removed by dry etching.

[0054] <Embodiment 4> A fourth embodiment of the present invention will be described with reference to FIGS. 17 to 19. The same parts as those in the above-described embodiments are designated by the same reference numerals, and redundant description will be omitted. The array substrate 321 of this embodiment differs from the third embodiment in that a protective film 332B is formed between the glass substrate 21GS and the base coat film 31. In this embodiment, a protective film forming step (first film forming step) for forming the protective film 332B is performed before a step for forming the semiconductor portion 232A (semiconductor portion forming step). The protective film 332B is preferably made of a material that can be wet-etched. For example, transparent electrode materials such as ITO (indium tin oxide) and IZO (indium zinc oxide) or light-shielding metal materials such as Mo (molybdenum), W (tungsten), or MoW (molybdenum tungsten), which is an alloy of Mo and W, can be used.

[0055] In this embodiment, in the eighth step (second insulating film forming step), an insulating film 237 (second insulating film) is formed as shown in FIG. 17. Then, in the ninth step (first etching step performed after the second insulating film forming step), as shown in FIG. 18, portions of the base coat film 31 and the insulating films 233, 235, 236, and 237 that overlap with the protective film 332B are removed by, for example, dry etching. As a result, portions of the base coat film 31 and the insulating films 233, 235, 236, and 237 are removed, thereby forming an opening 351. In this embodiment, the protective film 332B is interposed between the base coat film 31 and the glass substrate 21GS. Therefore, in the ninth step, the glass substrate 21GS can be protected by the protective film 332B.

[0056] In a tenth step (second etching step) performed after the ninth step, the protective film 332B is removed by, for example, wet etching, as shown in Fig. 19. As a result, the protective film 332B is removed to form an opening 352. Furthermore, if the protective film 332B has a light-shielding property, residues 332D of the protective film 332B that were not completely removed in the tenth step can be used as a black matrix.

[0057] <Other embodiments> The technology disclosed in this specification is not limited to the embodiments described above and illustrated in the drawings, and the following embodiments, for example, are also included in the technical scope. (1) In the above embodiment, the electrodes (gate electrode, source electrode, drain electrode) of the pixel TFT are made of a metal film. However, the present invention is not limited to this, and it is also possible to use a conductive film other than a metal film (for example, a low-resistance film obtained by subjecting a semiconductor film to a resistance-reducing treatment, a transparent conductive film, etc.). (2) The planar shape of the liquid crystal panel 11 is not limited to a square, but may be a circle, a semicircle, an oval, an ellipse, a trapezoid, or the like. (3) This technology can be applied to display panels other than the liquid crystal panel 11. For example, it can be applied to a display panel in which functional organic molecules (medium layer) other than the liquid crystal layer 22 are sandwiched between two substrates 20 and 21, or to a self-luminous display panel such as an organic EL (electroluminescence) panel. [Explanation of symbols]

[0058] 21, 121, 221, 321... Array substrate (substrate for display panel), 21GS... Glass substrate (insulating substrate), 31... Base coat film (third insulating film), 32A, 232A... Semiconductor portion, 32B... Protective film (first film), 35, 236... Insulating film (first insulating film), 36, 237... Insulating film (second insulating film), AA... Display area

Claims

1. a semiconductor portion forming step of forming a semiconductor portion on an upper layer side of an insulating substrate; a first film forming step of forming a first film made of any one of a transparent electrode material, a semiconductor material, and a metal material on at least a part of a display area where an image is displayed on an upper layer side of the insulating substrate; a first insulating film forming step, which is performed after the semiconductor portion forming step and the first film forming step, and which forms a first insulating film so as to cover the semiconductor portion and the first film from above; a second insulating film forming step, which is performed after the first insulating film forming step, of forming a second insulating film made of a different material from the first insulating film so as to cover the first insulating film from above; a first etching step, which is performed after the second insulating film forming step, of removing portions of the first insulating film and the second insulating film that overlap with the first film by etching; a second etching step, which is carried out after the first etching step, of removing the first film by etching.

2. The method for manufacturing a display panel substrate according to claim 1 , wherein the first film is made of the same material as the semiconductor portion.

3. a third insulating film forming step, which is performed before the semiconductor portion forming step and the first film forming step, and which forms a third insulating film made of a material different from the first film on an upper layer side of the insulating substrate; 3. The method for manufacturing a display panel substrate according to claim 1, wherein in the first film forming step, the first film is formed so as to cover at least a part of the third insulating film from above.

4. In the first etching step, the first insulating film and the second insulating film are removed by dry etching; 3. The method for manufacturing a display panel substrate according to claim 1, wherein the first film is removed by wet etching in the second etching step.

5. 3. The method for manufacturing a display panel substrate according to claim 1, wherein the first film has a light-shielding property.

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