Semiconductor device

Abstract

To contribute to the reduction of loss, low radiation noise, and miniaturization of semiconductor devices.SOLUTION: A semiconductor device comprises a parallel circuit of MOSFETs (10p, 10n) which are unipolar type switching elements and IGBT (20p, 20n) which are bipolar type switching elements. The size of IGBT (20p, 20n) which are bipolar switching elements, is larger than the chip size of MOSFET (10p, 10n) which are unipolar type switching elements.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device including a parallel circuit of a unipolar switching element and a bipolar switching element. [Background technology]

[0002] There are known semiconductor devices for power control used in power conversion devices such as inverters. For example, Patent Document 1 listed below discloses a technology for configuring a semiconductor device for power control using a parallel circuit in which a unipolar switching element and a bipolar switching element are connected in parallel, and for reducing loss by controlling the timing of turning on and off both switching elements. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2017-228912 Summary of the Invention [Problem to be solved by the invention]

[0004] The technology of Prior Art Document 1 requires complex control, such as providing a time difference between the turn-on timing of the unipolar switching element and the bipolar switching element, and the turn-off timing of the unipolar switching element and the bipolar switching element, and switching the turn-on and turn-off timing of both switching elements between low current and high current ranges, which leads to an increase in the complexity and size of the control circuit that controls both switching elements.

[0005] Furthermore, switching elements generate radiation noise due to the current change rate (dI / dt) and voltage change rate (dV / dt) during switching. In particular, unipolar switching elements have high switching speeds, resulting in high dI / dt and dV / dt, and thus generating large radiation noise. Reducing radiation noise is also an issue in semiconductor devices that include parallel circuits of unipolar and bipolar switching elements.

[0006] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a technique that can contribute to reducing loss, radiation noise, and miniaturization of semiconductor devices. [Means for solving the problem]

[0007] A semiconductor device according to the present disclosure includes a parallel circuit of a unipolar switching element and a bipolar switching element, and the size of the bipolar switching element is larger than the chip size of the unipolar switching element. [Effects of the Invention]

[0008] The present disclosure can contribute to reducing loss, radiation noise, and size of semiconductor devices. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a diagram showing a configuration of a semiconductor device according to a first embodiment. [Figure 2] FIG. 10 is a sequence diagram showing the results of a double pulse test on the semiconductor device according to the first embodiment. [Figure 3] FIG. 10 is a sequence diagram showing the results of a double pulse test on the semiconductor device according to the second embodiment. [Figure 4] FIG. 11 is a sequence diagram showing the results of a double pulse test on the semiconductor device according to the third embodiment. [Figure 5] FIG. 11 is a sequence diagram showing the results of a double pulse test on the semiconductor device according to the fourth embodiment. [Figure 6] FIG. 13 is a sequence diagram showing the results of a double pulse test on the semiconductor device according to the fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] <First Embodiment> Fig. 1 is a diagram showing the configuration of a semiconductor device according to embodiment 1. Fig. 1 shows an inverter circuit configured using the semiconductor device according to embodiment 1.

[0011] The semiconductor device according to the first embodiment includes a parallel circuit in which a unipolar switching element and a bipolar switching element are connected in parallel. The inverter circuit shown in Fig. 1 includes a parallel circuit of a unipolar switching element and a bipolar switching element in each of a high-potential arm (also referred to as an "upper arm") and a low-potential arm (also referred to as a "lower arm").

[0012] That is, the upper arm is a parallel circuit of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 10p, which is a unipolar switching element, and an IGBT (Insulated Gate Bipolar Transistor) 20p, which is a bipolar switching element, and the lower arm is a parallel circuit of a MOSFET 10n, which is a unipolar switching element, and an IGBT 20n, which is a bipolar switching element. DS and the parasitic capacitance C between the collector and emitter of IGBT20p and 20n. CE In addition, a freewheeling diode FWD is connected in anti-parallel to each of the MOSFETs 10p and 10n and the IGBTs 20p and 20n. Note that the unipolar switching elements and bipolar switching elements that make up the parallel circuits are not limited to MOSFETs and IGBTs, and may be any elements.

[0013] The upper arm MOSFET 10p and IGBT 20p are driven by a high-voltage integrated circuit (HVIC) 30p, which is a high-potential side control circuit, and the lower arm MOSFET 10n and IGBT 20n are driven by a low-voltage integrated circuit (LVIC) 30n, which is a low-potential side control circuit.

[0014] In the semiconductor device according to the first embodiment, the chip size of the bipolar switching element (hereinafter simply referred to as "size") is larger than the size of the unipolar switching element in each parallel circuit. That is, in FIG. 1, the size of IGBT 20p is larger than the size of MOSFET 10p, and the size of IGBT 20p is larger than the size of MOSFET 10n.

[0015] The MOSFETs 10p and 10n, which are unipolar switching elements, have a faster switching speed than the IGBTs 20p and 20n, which are bipolar switching elements. Therefore, when the MOSFETs 10p and 10n are switched, the radiation noise caused by dI / dt and dV / dt tends to increase. However, since the IGBTs 20p and 20n are connected in parallel to the MOSFETs 10p and 10n, the parasitic capacitance C CE The parasitic capacitance of the MOSFETs 10p and 10n functions as a snubber capacitor that reduces the radiation noise of the MOSFETs 10p and 10n. Since the magnitude of the parasitic capacitance depends on the chip size, the snubber capacitor (parasitic capacitance C CE ) capacity is increased, and the effect of being able to sufficiently reduce radiation noise is obtained.

[0016] In this embodiment, there is no time difference between the turn-on timing of the unipolar switching elements and the bipolar switching elements and the turn-off timing of the unipolar switching elements and the bipolar switching elements. In other words, the unipolar switching elements and the bipolar switching elements are turned on and off simultaneously. In this case, the HVIC 30p and the LVIC 30n do not need to perform complex control. This prevents the HVIC 30p and the LVIC 30n from becoming too complicated and large, contributing to the miniaturization of semiconductor devices.

[0017] The semiconductor device according to the first embodiment is only required to include a parallel circuit of at least a unipolar switching element (MOSFET 10p or MOSFET 10n) and a bipolar switching element (IGBT 20p or IGBT 20n). The other elements, such as the HVIC 30p, the LVIC 30n, and the freewheeling diode FWD, may be incorporated into the semiconductor device or may be externally attached to the semiconductor device.

[0018] FIG. 2 is a sequence diagram showing the results of a double-pulse test on the semiconductor device according to the first embodiment. FIG. 2 representatively shows test results for the MOSFET 10p and IGBT 20p of the upper arm. In the double-pulse test of FIG. 2, the test in which the MOSFET 10p and the IGBT 20p are turned on by the first pulse (a test including the period from time t1 to t2) is a test in the low current range, and the test in which the MOSFET 10p and the IGBT 20p are turned on by the second pulse (a test including the period from time t3 to t4) is a test in the high current range. In FIG. 2, in the sequence diagram for "upper-arm control signal," the dotted line is a graph for the MOSFET 10p and the solid line is a graph for the IGBT 20p. In each of the sequence diagrams for "upper-arm current," "upper-arm voltage," "upper-arm recovery current," and "upper-arm recovery voltage," the dotted line is a graph for the MOSFET 10p, the dashed line is a graph for the IGBT 20p, and the solid line is a graph for the entire upper arm. The same applies to FIGS. 3 to 6 shown below.

[0019] At time t1 or t3, the control signals input from the HVIC 30p to the MOSFET 10p and the IGBT 20p both become H (High) level, and the MOSFET 10p and the IGBT 20p are simultaneously turned on. At this time, the MOSFET 10p is turned on at high speed, but the parasitic capacitance C CE functions as a snubber capacitor, dI / dt and dV / dt are smoothed, resulting in a reduction in radiation noise. Furthermore, when both MOSFET 10p and IGBT 20p are turned on, the current flowing through the upper arm is divided between MOSFET 10p and IGBT 20p, lowering the on-voltage of the upper arm and reducing losses.

[0020] When the upper arm is turned on, a recovery current and a recovery voltage are generated in the lower arm. DS and the parasitic capacitance C of IGBT20n CE functions as a snubber capacitor, the dV / dt of the recovery voltage becomes gentler, and the radiation noise is reduced. DS and the parasitic capacitance C of IGBT20n CE reduces the surge voltage generated in the lower arm and contributes to reducing losses (although the recovery current increases slightly, the loss reduction due to the lower surge voltage is greater than the loss increase due to the recovery current).

[0021] At time t2 or t4, the control signals input to the MOSFET 10p and the IGBT 20p both go to L (Low) level, and the MOSFET 10p and the IGBT 20p are simultaneously turned off.

[0022] Thus, the semiconductor device according to the first embodiment can contribute to reducing loss, radiation noise, and size of the semiconductor device.

[0023] <Embodiment 2> In the second embodiment, a time difference is provided between the turn-off timings of the unipolar switching elements and the bipolar switching elements that make up the parallel circuit. Specifically, the unipolar switching elements and the bipolar switching elements are turned on simultaneously, and the unipolar switching elements are turned off in that order, followed by the bipolar switching elements. Although more complex control is required than in the first embodiment, the time difference between the turn-off timings can be constant, which prevents the HVIC 30p and the LVIC 30n from becoming too complicated and large compared to the technology of Patent Document 1 mentioned above.

[0024] Fig. 3 is a sequence diagram showing the results of a double-pulse test on the semiconductor device according to the second embodiment. Fig. 3 representatively shows the test results for the MOSFET 10p and IGBT 20p of the upper arm. In the double-pulse test of Fig. 3, too, the test in which the MOSFET 10p and the IGBT 20p are turned on by the first pulse (the test including the period from time t1 to t3) is a test in the low current range, and the test in which the MOSFET 10p and the IGBT 20p are turned on by the second pulse (the test including the period from time t4 to t6) is a test in the high current range.

[0025] At time t1 or t4, the control signals input from the HVIC 30p to the MOSFET 10p and the IGBT 20p both become H level, and the MOSFET 10p and the IGBT 20p are turned on simultaneously. At this time, the MOSFET 10p is turned on at high speed, but the parasitic capacitance C CE functions as a snubber capacitor, dI / dt and dV / dt are smoothed, resulting in a reduction in radiation noise. Furthermore, when both MOSFET 10p and IGBT 20p are turned on, the current flowing through the upper arm is divided between MOSFET 10p and IGBT 20p, lowering the on-voltage of the upper arm and reducing losses.

[0026] When the upper arm is turned on, a recovery current and a recovery voltage are generated in the lower arm. DSand the parasitic capacitance C of IGBT20n CE functions as a snubber capacitor, the dV / dt of the recovery voltage becomes gentler, and the radiation noise is reduced. DS and the parasitic capacitance C of IGBT20n CE reduces the surge voltage generated in the lower arm and contributes to reducing losses (although the recovery current increases slightly, the loss reduction due to the lower surge voltage is greater than the increase in loss due to the recovery current).

[0027] At time t2 or t5, the control signal input to MOSFET 10p goes low, and the control signal input to IGBT 20p remains high, so MOSFET 10p turns off and IGBT 20p remains on.

[0028] After that, at time t3 or t6, the control signal input to the IGBT 20p becomes L level, and the IGBT 20p is turned off. At this time, the parasitic capacitance C DS functions as a snubber capacitor, and reduces dV / dt and dI / dt, resulting in an effect on radiation noise. DS This reduces the surge voltage that occurs when the IGBT 20p is turned on, and therefore also has the effect of reducing loss.

[0029] Thus, the effects of reducing loss, radiation noise, and size of the semiconductor device can also be achieved in the second embodiment. In particular, compared to the first embodiment, the effect of reducing radiation noise caused by dI / dt and dV / dt at turn-off is enhanced.

[0030] <Third Embodiment> In the third embodiment, a time difference is provided between the turn-on timings of the unipolar switching elements and the bipolar switching elements that make up the parallel circuit. Specifically, the bipolar switching elements are turned on in that order, and the unipolar switching elements are turned off simultaneously. Although more complex control is required than in the first embodiment, the time difference between the turn-on timings only needs to be constant, which prevents the HVIC 30p and LVIC 30n from becoming too complex and large compared to the technology of Patent Document 1 mentioned above.

[0031] Fig. 4 is a sequence diagram showing the results of a double-pulse test on the semiconductor device according to the third embodiment. Fig. 4 representatively shows the test results for the MOSFET 10p and IGBT 20p of the upper arm. In the double-pulse test of Fig. 4, too, the test in which the MOSFET 10p and the IGBT 20p are turned on by the first pulse (the test including the period from times t1 to t3) is a test in the low current range, and the test in which the MOSFET 10p and the IGBT 20p are turned on by the second pulse (the test including the period from times t4 to t6) is a test in the high current range.

[0032] At time t1 or t4, the control signal input from the HVIC 30p to the MOSFET 10p is maintained at L level, and the control signal input to the IGBT 20p changes from L level to H level. Therefore, the MOSFET 10p remains in the off state, and the IGBT 20p turns on. Because the turn-on speed of the IGBT 20p is slower than that of the MOSFET 10p, the dI / dt at turn-on is gentle, resulting in a reduction in radiation noise.

[0033] When the upper arm is turned on, a recovery current and a recovery voltage are generated in the lower arm. DS and the parasitic capacitance C of IGBT20n CE functions as a snubber capacitor, the dV / dt of the recovery voltage becomes gentler, and the radiation noise is reduced.DS and the parasitic capacitance C of IGBT20n CE reduces the surge voltage generated in the lower arm and contributes to reducing losses (although the recovery current increases slightly, the loss reduction due to the lower surge voltage is greater than the loss increase due to the recovery current).

[0034] After that, at time t2 or t5, the control signal input to MOSFET 10p goes high, turning MOSFET 10p on. Both MOSFET 10p and IGBT 20p are turned on, and the current flowing through the upper arm is divided between MOSFET 10p and IGBT 20p. This reduces the on-voltage of the upper arm, resulting in a reduction in loss.

[0035] At time t3 or t6, the control signals input to the MOSFET 10p and the IGBT 20p both go to L level, and the MOSFET 10p and the IGBT 20p are simultaneously turned off.

[0036] Thus, the effects of reducing loss, radiation noise, and size of the semiconductor device can also be achieved in the third embodiment. In particular, compared to the first embodiment, the effect of reducing radiation noise caused by dI / dt and dV / dt at turn-on is enhanced.

[0037] <Fourth Embodiment> In the fourth embodiment, a time difference is provided between the turn-on and turn-off timings of the unipolar and bipolar switching elements that make up the parallel circuit. Specifically, the bipolar switching elements are turned on in the order of first, followed by the unipolar switching elements, as in the third embodiment, and the unipolar switching elements are turned off in the order of first, followed by the bipolar switching elements, as in the second embodiment. Although more complex control is required than in the first embodiment, the time difference between the turn-on and turn-off timings can be constant, which prevents the HVIC 30p and LVIC 30n from becoming too complicated and large compared to the technology of Patent Document 1 described above.

[0038] Fig. 5 is a sequence diagram showing the results of a double-pulse test on the semiconductor device according to the fourth embodiment. Fig. 5 representatively shows the test results for the MOSFET 10p and IGBT 20p of the upper arm. In the double-pulse test of Fig. 5, too, the test in which the MOSFET 10p and the IGBT 20p are turned on by the first pulse (the test including the period from times t1 to t4) is a test in the low current range, and the test in which the MOSFET 10p and the IGBT 20p are turned on by the second pulse (the test including the period from times t5 to t8) is a test in the high current range.

[0039] At time t1 or t5, the control signal input from the HVIC 30p to the MOSFET 10p is maintained at L level, and the control signal input to the IGBT 20p changes from L level to H level. Therefore, the MOSFET 10p remains in the off state, and the IGBT 20p turns on. Because the turn-on speed of the IGBT 20p is slower than that of the MOSFET 10p, the dI / dt at turn-on is gentle, resulting in a reduction in radiation noise.

[0040] When the upper arm is turned on, a recovery current and a recovery voltage are generated in the lower arm. DS and the parasitic capacitance C of IGBT20n CE functions as a snubber capacitor, the dV / dt of the recovery voltage becomes gentler, and the radiation noise is reduced. DS and the parasitic capacitance C of IGBT20n CE reduces the surge voltage generated in the lower arm and contributes to reducing losses (although the recovery current increases slightly, the loss reduction due to the lower surge voltage is greater than the loss increase due to the recovery current).

[0041] After that, at time t2 or t6, the control signal input to MOSFET 10p goes high, turning MOSFET 10p on. Both MOSFET 10p and IGBT 20p are turned on, and the current flowing through the upper arm is divided between MOSFET 10p and IGBT 20p. This reduces the on-voltage of the upper arm, resulting in a reduction in loss.

[0042] At time t3 or t7, the control signal input to MOSFET 10p goes to L level, and the control signal input to IGBT 20p remains at H level, so MOSFET 10p turns off and IGBT 20p remains on.

[0043] After that, at time t4 or t8, the control signal input to the IGBT 20p becomes L level, and the IGBT 20p is turned off. At this time, the parasitic capacitance C DS functions as a snubber capacitor, and reduces dV / dt and dI / dt, resulting in an effect on radiation noise. DS This reduces the surge voltage that occurs when the IGBT 20p is turned on, and therefore also has the effect of reducing loss.

[0044] Thus, in the fifth embodiment, the effects of both the second and third embodiments are achieved, resulting in lower loss, lower radiation noise, and a smaller size of the semiconductor device. In particular, in this embodiment, the on / off switching of the parallel circuit is mainly performed by bipolar switching elements, so radiation noise is mainly generated by the switching of the bipolar switching elements, and unipolar switching elements generate almost no radiation noise. Since radiation noise from unipolar switching elements tends to be small in the low current range and radiation noise from bipolar switching elements tends to be small in the high current range, this embodiment is effective when applied in a range where the current is higher than a certain value.

[0045] <Fifth Embodiment> In the fifth embodiment, the order in which the unipolar switching elements and the bipolar switching elements are turned on and off is reversed from that in the fourth embodiment. Specifically, the unipolar switching elements are turned on first, followed by the bipolar switching elements, and the bipolar switching elements are turned off first, followed by the unipolar switching elements. In the present embodiment, the time difference between the turn-on and turn-off timings can be constant, which prevents the HVIC 30p and the LVIC 30n from becoming too complicated and large, compared to the technology of Patent Document 1.

[0046] Fig. 6 is a sequence diagram showing the results of a double-pulse test on the semiconductor device according to the fifth embodiment. Fig. 6 representatively shows the test results of the MOSFET 10p and IGBT 20p of the upper arm. In the double-pulse test of Fig. 6, too, the test in which the MOSFET 10p and the IGBT 20p are turned on by the first pulse (the test including the period from times t1 to t4) is a test in the low current range, and the test in which the MOSFET 10p and the IGBT 20p are turned on by the second pulse (the test including the period from times t5 to t8) is a test in the high current range.

[0047] At time t1 or t5, the control signal input from the HVIC 30p to the MOSFET 10p changes from L level to H level, and the control signal input to the IGBT 20p is maintained at L level. Therefore, the MOSFET 10p turns on, and the IGBT 20p remains in the off state. The MOSFET 10p turns on quickly, but the parasitic capacitance C CE functions as a snubber capacitor, dI / dt and dV / dt become gentler, resulting in a reduction in radiated noise.

[0048] When the upper arm is turned on, a recovery current and a recovery voltage are generated in the lower arm. DS and the parasitic capacitance C of IGBT20n CEfunctions as a snubber capacitor, the dV / dt of the recovery voltage becomes gentler, and the radiation noise is reduced. DS and the parasitic capacitance C of IGBT20n CE reduces the surge voltage generated in the lower arm and contributes to reducing losses (although the recovery current increases slightly, the loss reduction due to the lower surge voltage is greater than the loss increase due to the recovery current).

[0049] After that, at time t2 or t6, the control signal input to IGBT 20p goes high, turning IGBT 20p on. Both MOSFET 10p and IGBT 20p are turned on, and the current flowing through the upper arm is divided between MOSFET 10p and IGBT 20p. This reduces the on-voltage of the upper arm, resulting in a reduction in loss.

[0050] At time t3 or t7, the control signal input to MOSFET 10p is maintained at H level, and the control signal input to IGBT 20p goes to L level. Therefore, MOSFET 10p remains on, and IGBT 20p turns off.

[0051] After that, at time t4 or t8, the control signal input to the MOSFET 10p goes to L level, and the MOSFET 10p turns off. At this time, the parasitic capacitance C CE functions as a snubber capacitor, and reduces dV / dt and dI / dt, resulting in an effect on radiation noise. CE reduces the surge voltage that occurs when the MOSFET 10p is turned on, and therefore also has the effect of reducing loss.

[0052] Thus, the fifth embodiment also achieves the effects of reducing loss, radiated noise, and size of the semiconductor device. In particular, in this embodiment, the on / off switching of the parallel circuit is mainly performed by unipolar switching elements, so radiated noise is mainly generated by the switching of the unipolar switching elements, and bipolar switching elements generate almost no radiated noise. Since there is a tendency for radiated noise from unipolar switching elements to be small in low current ranges and for radiated noise from bipolar switching elements to be small in high current ranges, this embodiment is effective when applied in regions where the current is lower than a certain value.

[0053] <Sixth Embodiment> The substrate of the bipolar switching element and the unipolar switching element may be conventional silicon (Si), or may be a wide bandgap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), diamond, etc. If the bipolar switching element and the unipolar switching element are made of a wide bandgap semiconductor, this can contribute to the miniaturization of semiconductor devices.

[0054] In particular, when the unipolar switching element is made of a wide bandgap semiconductor, an increase in loss can be prevented even if the chip size of the unipolar switching element is made smaller than the size of the bipolar switching element.

[0055] Furthermore, if the unipolar switching element is a MOSFET made of SiC (SiC-MOSFET) and the bipolar switching element is an IGBT, the following effects can be obtained. SiC-MOSFETs have a negative temperature characteristic, i.e., the higher the temperature, the easier it is for current to flow. In the high current range, the current diverted to the IGBT increases, and the heat generated by the IGBT is greater than that of the SiC-MOSFET. However, when the temperature of the semiconductor device rises due to heat generated by the IGBT, the current diverted to the SiC-MOSFET, which has a negative temperature characteristic, increases, and the current diverted to the IGBT decreases accordingly, suppressing the heat generated by the IGBT and preventing damage to the IGBT. When the current diverted to the SiC-MOSFET increases, the heat generated by the SiC-MOSFET increases, but the high thermal conductivity of the SiC-MOSFET prevents damage due to heat.

[0056] It is possible to freely combine the embodiments, and to modify or omit the embodiments as appropriate.

[0057] <Additional Notes> Various aspects of the present disclosure are summarized below as appendices.

[0058] (Appendix 1) A parallel circuit of a unipolar switching element and a bipolar switching element is provided, The size of the bipolar switching element is larger than the chip size of the unipolar switching element. Semiconductor device.

[0059] (Appendix 2) a control circuit for driving the unipolar switching element and the bipolar switching element; The control circuit when the unipolar switching element and the bipolar switching element are turned on, the bipolar switching element and the unipolar switching element are turned on simultaneously; when the unipolar switching element and the bipolar switching element are turned off, the bipolar switching element and the unipolar switching element are turned off simultaneously; 2. The semiconductor device according to claim 1.

[0060] (Appendix 3) a control circuit for driving the unipolar switching element and the bipolar switching element; The control circuit when the unipolar switching element and the bipolar switching element are turned on, the bipolar switching element and the unipolar switching element are turned on simultaneously; When the unipolar switching element and the bipolar switching element are turned off, the unipolar switching element is turned off first, and then the bipolar switching element is turned off. 2. The semiconductor device according to claim 1.

[0061] (Appendix 4) a control circuit for driving the unipolar switching element and the bipolar switching element; The control circuit When the unipolar switching element and the bipolar switching element are turned on, the bipolar switching element is turned on first, and then the unipolar switching element is turned on; when the unipolar switching element and the bipolar switching element are turned off, the bipolar switching element and the unipolar switching element are turned off simultaneously; 2. The semiconductor device according to claim 1.

[0062] (Appendix 5) a control circuit for driving the unipolar switching element and the bipolar switching element; The control circuit When the unipolar switching element and the bipolar switching element are turned on, the bipolar switching element is turned on first, and then the unipolar switching element is turned on; When the unipolar switching element and the bipolar switching element are turned off, the unipolar switching element is turned off first, and then the bipolar switching element is turned off. 2. The semiconductor device according to claim 1.

[0063] (Appendix 6) a control circuit for driving the unipolar switching element and the bipolar switching element; The control circuit When the unipolar switching element and the bipolar switching element are turned on, the unipolar switching element is turned on first, and then the bipolar switching element is turned on; When the unipolar switching element and the bipolar switching element are turned off, the bipolar switching element is turned off first, and then the unipolar switching element is turned off. 2. The semiconductor device according to claim 1.

[0064] (Appendix 7) The unipolar switching element is made of a wide bandgap semiconductor. 7. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0065] (Appendix 8) the unipolar switching element is a MOSFET made of SiC, The bipolar switching element is an IGBT. 8. The semiconductor device according to claim 7. [Explanation of symbols]

[0066] 10p, 10n MOSFET, 20p, 20n IGBT, 30p HVIC, 30n LVIC.

Claims

1. A parallel circuit of a unipolar switching element and a bipolar switching element is provided, The size of the bipolar switching element is larger than the chip size of the unipolar switching element. Semiconductor device.

2. a control circuit for driving the unipolar switching element and the bipolar switching element; The control circuit when the unipolar switching element and the bipolar switching element are turned on, the bipolar switching element and the unipolar switching element are turned on simultaneously; when the unipolar switching element and the bipolar switching element are turned off, the bipolar switching element and the unipolar switching element are turned off simultaneously; The semiconductor device according to claim 1 .

3. a control circuit for driving the unipolar switching element and the bipolar switching element; The control circuit when the unipolar switching element and the bipolar switching element are turned on, the bipolar switching element and the unipolar switching element are turned on simultaneously; When the unipolar switching element and the bipolar switching element are turned off, the unipolar switching element is turned off first, and then the bipolar switching element is turned off. The semiconductor device according to claim 1 .

4. a control circuit for driving the unipolar switching element and the bipolar switching element; The control circuit When the unipolar switching element and the bipolar switching element are turned on, the bipolar switching element is turned on first, and then the unipolar switching element is turned on; when the unipolar switching element and the bipolar switching element are turned off, the bipolar switching element and the unipolar switching element are turned off simultaneously; The semiconductor device according to claim 1 .

5. a control circuit for driving the unipolar switching element and the bipolar switching element; The control circuit When the unipolar switching element and the bipolar switching element are turned on, the bipolar switching element is turned on first, and then the unipolar switching element is turned on; When the unipolar switching element and the bipolar switching element are turned off, the unipolar switching element is turned off first, and then the bipolar switching element is turned off. The semiconductor device according to claim 1 .

6. a control circuit for driving the unipolar switching element and the bipolar switching element; The control circuit When the unipolar switching element and the bipolar switching element are turned on, the unipolar switching element is turned on first, and then the bipolar switching element is turned on; When the unipolar switching element and the bipolar switching element are turned off, the bipolar switching element is turned off first, and then the unipolar switching element is turned off. The semiconductor device according to claim 1 .

7. The unipolar switching element is made of a wide bandgap semiconductor. The semiconductor device according to claim 1 .

8. the unipolar switching element is a MOSFET made of SiC, The bipolar switching element is an IGBT. The semiconductor device according to claim 7 .

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