Switching control circuit, integrated circuit, and power supply circuit

Abstract

To provide a switching control circuit capable of switching a transistor regardless of a limit of a control range of a comparator.SOLUTION: A switching control circuit 204a includes: a drive circuit 300 that turns off a transistor that controls an inductor current; an estimation circuit 301 that estimates whether an effective value of an AC voltage is a first level or a second level higher than the first level based on an on / off state of the transistor and an output voltage; a first output circuit that, when the inductor current becomes a first value, changes a slope of an output with a first slope if the effective value is the first level and changes the slope of the output with a second slope larger than the first slope if the effective value is the second level; and a second output circuit 303 that outputs, as the first period, a period from when the inductor current becomes the first value to when the output becomes a level corresponding to the output voltage.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a switching control circuit, an integrated circuit, and a power supply circuit. [Background technology]

[0002] A typical power factor correction circuit (hereinafter referred to as a PFC (Power Factor Correction) circuit) that operates in critical mode improves the power factor by making the waveform of the peak value of the inductor current flowing through the inductor similar to the waveform of the rectified voltage obtained by rectifying an AC voltage (for example, Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2023-044599 [Patent Document 2] U.S. Patent No. 7,538,525 Summary of the Invention [Problem to be solved by the invention]

[0004] A switching control circuit, which controls a PFC circuit by switching a transistor, determines the on-width of the transistor according to the output voltage. In this case, the switching control circuit may determine the on-width by comparing a voltage according to the output voltage with, for example, a ramp wave using a comparator. If the voltage according to the output voltage is low, the switching control circuit may not be able to correctly determine the on-width due to the limit of the control range of the comparator.

[0005] The present invention has been made in view of the above-mentioned problems of the prior art, and has as its object to provide a switching control circuit that can switch a transistor regardless of the limit of the control range of a comparator. [Means for solving the problem]

[0006] A first aspect of the present invention that solves the above-described problems is a switching control circuit that controls switching of the transistor in a power supply circuit that generates an output voltage of a target level from the AC voltage, the switching control circuit including: an inductor to which a voltage corresponding to an AC voltage is applied; and a transistor that controls an inductor current flowing through the inductor, the switching control circuit comprising: a drive circuit that turns on the transistor after the inductor current reaches a first value, and turns off the transistor after a first period corresponding to the output voltage has elapsed; an estimation circuit that estimates whether an effective value of the AC voltage is a first level or a second level higher than the first level, based on a second period during which the transistor is off, the first period, and the output voltage; a first output circuit that, when the inductor current reaches the first value, changes an output slope with a first slope if the effective value is the first level, and changes the output slope with a second slope greater than the first slope if the effective value is the second level; and a second output circuit that outputs, as the first period, a period from when the inductor current reaches the first value until the output reaches a level corresponding to the output voltage.

[0007] A second aspect of the present invention that solves the above-mentioned problem is a power supply circuit that generates an output voltage of a target level from an AC voltage, the power supply circuit including: an inductor to which a voltage corresponding to the AC voltage is applied; a transistor that controls an inductor current flowing through the inductor; and a switching control circuit that controls switching of the transistor, the switching control circuit including a drive circuit that turns on the transistor after the inductor current reaches a first value, and turns off the transistor after a first period corresponding to the output voltage has elapsed; a second period during which the transistor is off; the first period; a first output circuit that, when the inductor current reaches the first value, changes an output slope with a first slope if the effective value is at the first level, and changes an output slope with a second slope greater than the first slope if the effective value is at the second level; and a second output circuit that outputs a period from when the inductor current reaches the first value until when the output reaches a level according to the output voltage, as the first period. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a switching control circuit that can switch a transistor regardless of the limit of the control range of a comparator. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a diagram illustrating an example of an AC-DC converter 10. FIG. [Figure 2] FIG. 2 is a diagram illustrating an example of a power factor correction IC 26a. [Figure 3] FIG. 2 is a diagram illustrating an example of a switching control circuit 204a. [Figure 4] FIG. 10 is a diagram illustrating an example of the operation of the estimation circuit 301. [Figure 5A] FIG. 10 is a diagram showing an example in which the gradient of the output Vr is changed with a gradient S1. [Figure 5B]FIG. 10 is a diagram showing an example in which the gradient of the output Vr is changed with a gradient S2. [Figure 6] FIG. 10 is a diagram illustrating an example of the operation of a switching control circuit 204a. [Figure 7] FIG. 10 is a diagram illustrating an example of the operation of a switching control circuit 204a. [Figure 8] FIG. 10 is a diagram illustrating an example of the operation of a switching control circuit 204a. [Figure 9] FIG. 10 is a diagram illustrating an example of the operation of a switching control circuit 204a. [Figure 10] FIG. 10 is a diagram illustrating an example of a switching control circuit 204b. [Figure 11] FIG. 10 is a diagram illustrating an example of the operation of a switching control circuit 204b. [Figure 12] FIG. 10 is a diagram illustrating an example of the operation of a switching control circuit 204b. [Figure 13] FIG. 2 is a diagram illustrating an example of an AC-DC converter 12. [Figure 14] FIG. 2 is a diagram illustrating an example of a power factor correction IC 26b. [Figure 15] FIG. 5 is a diagram illustrating an example of an oscillator circuit 502. [Figure 16] FIG. 2 is a diagram illustrating an example of a power factor correction IC 26c. [Figure 17] FIG. 5 is a diagram illustrating an example of an oscillator circuit 506. DETAILED DESCRIPTION OF THE INVENTION

[0010] At least the following points become clear from the description of this specification and the accompanying drawings. Note that hereinafter, the "circuit" in this embodiment includes not only analog circuits and wired logic type logic circuits, but also functional blocks (or means) included in DSPs (Digital Signal Processors), microcomputers, etc., that are capable of executing digital arithmetic processing.

[0011] Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. The same or equivalent components, members, etc. shown in each drawing are designated by the same reference numerals, and redundant explanations will be omitted where appropriate.

[0012] =====This Embodiment===== <<<Overview of AC-DC Converter 10>>> FIG. 1 is a diagram showing the configuration of an AC-DC converter 10 according to an embodiment of the present invention. The AC-DC converter 10 is a boost-type PFC circuit that generates an output voltage Vout at a target level from the AC voltage Vac of a commercial power supply.

[0013] The AC-DC converter 10 is configured to include an input line filter 20, a full-wave rectifier circuit 21, capacitors 22 and 25, a transformer 23, a diode 24, a power factor correction IC 26a, an NMOS transistor 27, and resistors 28, 30, and 31. Note that the AC-DC converter 10 corresponds to a "power supply circuit", and the current flowing from the commercial power supply to the AC-DC converter 10 is defined as an input current Iin.

[0014] The input line filter 20 attenuates both noise from the AC power supply (e.g., nodes N1 and N2) side and noise from the AC-DC converter 10 side. An AC voltage Vac is applied to the nodes N1 and N2 of the input line filter 20. Then, the input line filter 20 applies an AC voltage Vac with attenuated noise to the full-wave rectifier circuit 21.

[0015] The full-wave rectifier circuit 21 in FIG. 1 full-wave rectifies a given input AC voltage Vac and outputs it as an input voltage Vrec to the capacitor 22 and the transformer 23. Note that the AC voltage Vac is, for example, a voltage with an effective value of 100V or 240V and a frequency of 50 to 60 Hz. Hereinafter, in this embodiment, the voltage is basically the potential difference with respect to a reference point (GND in the figure), but the AC voltage Vac indicates the voltage between terminals. Note that 100V corresponds to a "first level", and 240V corresponds to a "second level". However, as long as they are two different execution values, they are not limited to 100V or 240V.

[0016] The capacitor 22 smoothes the input voltage Vrec, the capacitor 25 is an element charged with the output voltage of the boost chopper circuit, and the transformer 23 has a main coil L1 and an auxiliary coil L2 magnetically coupled to the main coil L1. In this embodiment, the auxiliary coil L2 is wound so that the voltage generated in the auxiliary coil L2 has the opposite polarity to the voltage generated in the main coil L1. The voltage Vzcd generated in the auxiliary coil L2 is applied to a terminal ZCD of a power factor correction IC 26a (described later). The main coil L1 corresponds to an "inductor."

[0017] The main coil L1 and the NMOS transistor 27 form a boost chopper circuit together with the capacitor 25. Therefore, the charging voltage of the capacitor 25 becomes the DC output voltage Vout.

[0018] Furthermore, when the inductor current IL flows in the main coil L1 in the direction of the arrow, the direction of the inductor current IL is the positive direction, and when the inductor current IL flows in the opposite direction to the arrow, the direction of the inductor current IL is the negative direction.

[0019] The power factor correction IC 26a is an integrated circuit that controls the switching of the NMOS transistor 27 so that the level of the output voltage Vout becomes a target level (e.g., 400 V) while correcting the input power factor of the AC-DC converter 10. Specifically, the power factor correction IC 26a drives the NMOS transistor 27 based on the inductor current IL flowing through the main coil L1 and the output voltage Vout. The power factor correction IC 26a is provided with terminals ZCD, FB, OUT, and CS, which will be described in detail later. In this embodiment, terminals other than the terminal ZCD and the like of the power factor correction IC 26a (e.g., a ground terminal) are omitted for convenience.

[0020] The NMOS transistor 27 is a power transistor for controlling the power to the load 11 of the AC-DC converter 10. In this embodiment, the NMOS transistor 27 is an N-type MOS (Metal Oxide Semiconductor) transistor, but is not limited to this and may be, for example, another switching element such as a bipolar transistor. The gate electrode of the NMOS transistor 27 is connected to the terminal OUT.

[0021] The resistor 28 is an element for detecting the inductor current IL flowing through the NMOS transistor 27. When the NMOS transistor 27 is turned on, the inductor current IL flows through the resistor 28, and the resistor 28 generates a voltage Vcs corresponding to the inductor current IL. The voltage Vcs is applied to the terminal CS of the power factor correction IC 26a.

[0022] The resistors 30 and 31 form a voltage divider circuit that divides the output voltage Vout and generates a feedback voltage Vfb that is used when switching the NMOS transistor 27. The feedback voltage Vfb generated at the node to which the resistors 30 and 31 are connected is applied to the terminal FB.

[0023] <<<About the power factor correction IC26a>>> ==Configuration of Power Factor Correction IC26a== 2 is a diagram showing an example of a power factor correction IC 26a that causes the AC-DC converter 10 to operate critically. The power factor correction IC 26a includes comparators 200 and 202, an AD converter (ADC: Analog-to-Digital Converter) 201, a reference voltage circuit (VREF) 203, a switching control circuit 204a, and a buffer circuit 205. The switching control circuit 204a is formed by a digital circuit.

[0024] The comparator 200 is a circuit that detects when the inductor current IL becomes almost zero (hereinafter, almost zero will be referred to as "zero") and compares the voltage Vzcd with a reference voltage Vref0. When the voltage Vvcd becomes lower than the reference voltage Vref0, the comparator 200 outputs a high-level (hereinafter referred to as "H" level) signal Sa. On the other hand, when the voltage Vzcd becomes higher than the reference voltage Vref0, the comparator 200 outputs a low-level (hereinafter referred to as "L" level) signal Sa. The comparator 200 is also provided to cause the AC-DC converter 10 to operate in a critical state. The reference voltage Vref0 corresponds to the voltage value of the voltage Vzcd when the inductor current IL becomes zero, and is equivalent to a "first value."

[0025] The AD converter 201 converts the feedback voltage Vfb into a digital value.

[0026] The comparator 202 is a circuit that detects whether the inductor current IL flowing through the NMOS transistor 27 when the NMOS transistor 27 is on is an overcurrent, and compares the voltage Vcs with the reference voltages Vref1 / Vref2 from the reference voltage circuit 203. When the comparator 202 detects that the inductor current IL is an overcurrent, it outputs an “H” level signal Sb.

[0027] The reference voltage circuit 203 outputs a reference voltage Vref1 when the effective value of the AC voltage Vac is, for example, 100 V based on a signal Ssel from an estimation circuit 301 (described later), and outputs a reference voltage Vref2 when the effective value of the AC voltage Vac is, for example, 240 V. The voltage level of the reference voltage Vref2 is lower than the voltage level of the reference voltage Vref1. The inductor current IL when the voltage Vcs becomes the reference voltage Vref1 corresponds to a "first current," and the inductor current IL when the voltage Vcs becomes the reference voltage Vref2 corresponds to a "second current."

[0028] Therefore, when the effective value of the AC voltage Vac is 240 V, the current value of the inductor current IL detected as an overcurrent is smaller than the current value of the inductor current IL detected as an overcurrent when the effective value of the AC voltage Vac is 100 V. This prevents the thermal energy generated in the NMOS transistor 27 from increasing, thereby preventing the NMOS transistor 27 from being destroyed. Note that the comparator 202 corresponds to an "overcurrent detection circuit."

[0029] The switching control circuit 204a is a circuit that outputs a drive signal Vq for driving the NMOS transistor 27 based on a feedback voltage Vfb and a signal Sa corresponding to the inductor current IL. The switching control circuit 204a is a digital circuit configured with a wired logic circuit that performs various calculations, and is configured to include, for example, logic gates, flip-flops, and memories. However, the switching control circuit 204a may also be a DSP (Digital Signal Processor) or a microcomputer. Details of the switching control circuit 204a will be described later.

[0030] The buffer circuit 205 is a drive circuit that drives the NMOS transistor 27 based on the drive signal Vq. Specifically, when the drive signal Vq goes high, the buffer circuit 205 applies a drive voltage Vdr to the gate electrode of the NMOS transistor 27 to turn on the NMOS transistor 27, and when the drive signal Vq goes low, the buffer circuit 205 applies a drive voltage Vdr to the gate electrode of the NMOS transistor 27 to turn off the NMOS transistor 27.

[0031] ==Configuration of Switching Control Circuit 204a== 3 is a diagram illustrating an example of the switching control circuit 204a. The switching control circuit 204a outputs a drive signal Vq based on the inductor current IL and the feedback voltage Vfb.

[0032] The switching control circuit 204 a includes a drive circuit 300 , an estimation circuit 301 , an oscillation circuit 302 , an output circuit 303 , and a storage circuit 1000 .

[0033] ===Drive circuit 300=== The drive circuit 300 outputs a drive signal Vq based on the signals Sa, Sb, and Sc. Specifically, after the inductor current IL becomes zero and the comparator 200 in FIG. 2 outputs a high-level signal Sa, the drive circuit 300 outputs a high-level drive signal Vq to turn on the NMOS transistor 27. After that, when an on-period Ton (described later) elapses and the output circuit 303 (described later) outputs a high-level signal Sc, the drive circuit 300 outputs a low-level drive signal Vq to turn off the NMOS transistor 27. Furthermore, when the comparator 202 in FIG. 2 detects that the inductor current IL flowing through the NMOS transistor 27 is an overcurrent and outputs a high-level signal Sb, the drive circuit 300 outputs a low-level drive signal Vq. The on-period Ton corresponds to the "first period."

[0034] ===Estimation circuit 301=== The estimation circuit 301 estimates the effective value of the AC voltage Vac based on the drive signal Vq. Specifically, the estimation circuit 301 stores the off-period Toff for each switching of the NMOS transistor 27 in the storage circuit 1000, and estimates the effective value of the AC voltage Vac based on the stored off-period Toff, on-period Ton, and output voltage.

[0035] As will be described in detail later, the on-period Ton is determined by the feedback voltage Vfb and is approximately constant, for example, over a half cycle of the AC voltage Vac, i.e., one cycle of the rectified voltage Vrec. When the on-period Ton is constant, the higher the voltage level of the rectified voltage Vrec, the larger the peak value of the inductor current IL. The period from when the NMOS transistor 27 is turned off until the inductor current IL becomes zero (i.e., the off-period Toff, during which the drive signal Vq is at an "L" level) becomes longer. Therefore, as shown in FIG. 4, the off-period Toff reaches a peak value Toffp, which is the maximum value during a half cycle of the AC voltage Vac, at the time when the voltage level of the AC voltage Vac, i.e., the rectified voltage Vrec, reaches its maximum value (e.g., at times t0 and t1 in FIG. 4).

[0036] The estimation circuit 301 then detects the off period Toff and stores the off period Toff for each switching of the NMOS transistor 27 in the storage circuit 1000. The estimation circuit 301 then calculates, for example, the time between times t0 and t1 in FIG. 4 based on the stored off period Toff, and determines the peak value Toffp at the timing of times t0 and t1. Specifically, the off period Toff when the stored off period Toff is maximum in a half cycle of the AC voltage Vac is set as the peak value Toffp, and the estimation circuit 301 calculates the peak value Vinp in the half cycle of the AC voltage Vac based on the following equation (1): Vinp=Vout / (1+Ton / Toffp)...Equation (1)

[0037] The estimation circuit 301 then estimates the effective value of the AC voltage Vac based on whether the calculated peak value Vinp is higher than a predetermined level. The estimation circuit 301 outputs a signal Ssel at an "L" level when the effective value of the AC voltage Vac is 100 V, and outputs a signal Ssel at an "H" level when the effective value of the AC voltage Vac is 240 V. The predetermined level is a level at which the effective values ​​of 100 V and 240 V can be distinguished (for example, a level indicating 200 V).

[0038] Although the estimation circuit 301 determines the peak value Toffp and then calculates the peak value Vinp, the estimation circuit 301 may also calculate the voltage level Vin of the rectified voltage Vrec at any time using the off-period Toff and detect the peak value Vinp of the voltage level Vin. Specifically, the voltage level Vin when the calculated voltage level Vin of the rectified voltage Vrec is maximum in a half cycle of the AC voltage Vac may be set as the peak value Vinp. Furthermore, when the voltage level Vin exceeds a predetermined level, the effective value of the AC voltage Vac may be estimated to be 240 V. The off-period Toff corresponds to the "second period."

[0039] In addition, in the above-mentioned Patent Document 1, the timing of the peak point Toffp is also detected, but the calculations required to perform accurate control are complex, which increases the design and development costs and tends to increase the circuit size.

[0040] ===Oscillator circuit 302=== The oscillator circuit 302 changes the output Vr based on the drive signal Vq and the signal Ssel. Specifically, when the estimation circuit 301 outputs the signal Ssel at the "L" level, the oscillator circuit 302 changes the slope of the output Vr by a slope S1 when the drive circuit 300 outputs the drive signal Vq at the "H" level at time t10 in FIG. 5A.

[0041] On the other hand, when the estimation circuit 301 outputs a high-level signal Ssel, the oscillator circuit 302 changes the slope of the output Vr at a slope S2 greater than the slope S1 when the drive circuit 300 outputs a high-level drive signal Vq at time t15 in FIG. 5A. Furthermore, when the drive circuit 300 outputs a low-level drive signal Vq at time t11 in FIG. 5A and time t16 in FIG. 5B, the oscillator circuit 302 outputs an output Vr of 0. The oscillator circuit 302 corresponds to a "first output circuit," with the slope S1 corresponding to a "first slope" and the slope S2 corresponding to a "second slope." The oscillator circuit 302 may also be configured with a counter whose increment values ​​are different for the slopes S1 and S2.

[0042] ===Output circuit 303=== The output circuit 303 is a circuit that outputs a signal Sc indicating an on-period Ton based on the output Vr and the feedback voltage Vfb. Specifically, the output circuit 303 outputs an "H" level signal Sc when the output Vr reaches a level corresponding to the feedback voltage Vfb after the inductor current becomes zero. Therefore, the output circuit 303 outputs the period from when the inductor current becomes zero and the drive circuit 300 outputs an "H" level drive signal Vq to when the output circuit 303 outputs an "H" level signal Sc, i.e., the period during which the "H" level drive signal Vq is being output, as the on-period Ton.

[0043] The output circuit 303 includes an error amplifier circuit (ERR) 400, a PI control circuit (PI) 401, and a comparator 402.

[0044] The error amplifier circuit 400 calculates an error E1, which is the difference between a reference voltage Vref, which is the reference for a target level of output voltage Vout (for example, 400 V), and the feedback voltage Vfb. The feedback voltage Vfb is a digital value converted from the feedback voltage Vfb by the AD converter 201 in FIG. 2.

[0045] The PI control circuit 401 calculates the integral value of the error E1, and outputs a level Vx for matching the level of the feedback voltage Vfb with the level of the reference voltage Vref based on the integral value.

[0046] The comparator 402 is a circuit that determines the on-period Ton and compares the output Vr with the level Vx. Specifically, the comparator 402 outputs a signal Sc of "H" level when the output Vr reaches a level corresponding to the feedback voltage Vfb after the inductor current becomes zero. On the other hand, the comparator 402 outputs a signal Sc of "L" level when the output Vr does not reach the level Vx. The output circuit 303 corresponds to a "second output circuit."

[0047] ==Operation of switching control circuit 204a when effective value is 100V== Fig. 6 is a diagram showing an example of the operation of the switching control circuit 204a. In Fig. 6, it is assumed that the estimation circuit 301 outputs the signal Ssel at "L" level.

[0048] First, at time t20, when the inductor current IL decreases and becomes zero, the comparator 200 outputs a signal Sa of "H" level, and the drive circuit 300 outputs a signal Vq of "H" level.

[0049] When the drive circuit 300 outputs the drive signal Vq at "H" level, the NMOS transistor 27 turns on and the inductor current IL increases.

[0050] Furthermore, when the drive signal Vq goes to the "H" level, the oscillation circuit 302 changes the slope of the output Vr with a slope S1.

[0051] At time t21 when the output Vr reaches level Vx, the comparator 402 outputs a high-level signal Sc, and the drive circuit 300 outputs a low-level drive signal Vq. Then, the NMOS transistor 27 is turned off, and the inductor current IL begins to decrease.

[0052] At time t22 when the inductor current IL becomes zero, the NMOS transistor 27 is turned on, similarly to time t10. The period from time t21 to t22 is referred to as period P1. Thereafter, the same operation is carried out.

[0053] At time t23 when the rectified voltage Vrec has a high phase angle, the NMOS transistor 27 is turned on, similarly to time t20.

[0054] At time t24 when the output Vr reaches the level Vx, the NMOS transistor 27 is turned off, similarly to time t21.

[0055] Then, at time t25 when the inductor current IL becomes zero, the NMOS transistor 27 is turned on, as at time t22. If the period from time t24 to t25 is defined as period P2, period P2 is longer than period P1. Therefore, the estimation circuit 301 can detect that the rectified voltage Vrec reaches the peak value Vinp around time t23.

[0056] 7 is a diagram showing an example of the operation of the switching control circuit 204a when an overcurrent is detected. In FIG. 7, it is assumed that the estimation circuit 301 outputs the signal Ssel at the "L" level.

[0057] First, at time t30 when the inductor current IL decreases and becomes zero, the comparator 200 outputs a signal Sa of "H" level, and the drive circuit 300 outputs a signal Vq of "H" level.

[0058] When the drive circuit 300 outputs the drive signal Vq at "H" level, the NMOS transistor 27 turns on and the inductor current IL increases.

[0059] Furthermore, when the drive signal Vq goes to the "H" level, the oscillation circuit 302 changes the slope of the output Vr with a slope S1.

[0060] At time t31 when the voltage Vcs becomes the reference voltage Vref1, the comparator 202 outputs a high-level signal Sb, causing the drive circuit 300 to output a low-level drive signal. Then, the NMOS transistor 27 is turned off, and the inductor current IL begins to decrease.

[0061] At time t32 when the inductor current IL becomes zero, the NMOS transistor 27 is turned on, just as at time t30. Thereafter, the same operation is carried out.

[0062] The heat energy generated by the NMOS transistor 27 is equal to the rectified voltage Vrec multiplied by the inductor current IL. Therefore, in the case of Fig. 7, since the effective value of the AC voltage Vac is low at 100 V, the NMOS transistor 27 is unlikely to be destroyed even if the value of the inductor current IL that the comparator 202 detects as an overcurrent is high.

[0063] ==Operation of the switching control circuit 204a when the effective value is 240V== Fig. 8 is a diagram showing an example of the operation of the switching control circuit 204a. In Fig. 8, it is assumed that the estimation circuit 301 outputs the signal Ssel at "H" level. The operation from time t40 to t45 is the same as the operation from time t20 to t25 in Fig. 6. On the other hand, the operation in Fig. 8 differs from the operation in Fig. 6 in that the oscillation circuit 302 changes the output Vr at a slope S2.

[0064] In this way, when the effective value of the AC voltage Vac is high, for example, 240 V, the estimation circuit 301 changes the slope of the output Vr at a slope S2 greater than the slope S1. This allows the output voltage Vout to be sufficiently high and the on-period Ton to be short, so that even if the level Vx becomes low, the comparator 402 is prevented from being unable to output the signal Sc due to the limit of its control range. Furthermore, because the comparator 402 can output the signal Sc in this way, intermittent operation of the AC-DC converter 10 is prevented.

[0065] Furthermore, if the period from time t41 to t42 is defined as period P3 and the period from time t44 to t45 is defined as period P4, period P4 is longer than period P3. Therefore, the estimation circuit 301 can detect that the rectified voltage Vrec reaches the peak value Vinp around time t43.

[0066] 9 is a diagram showing an example of the operation of the switching control circuit 204a when an overcurrent is detected. In FIG. 9, it is assumed that the estimation circuit 301 outputs an "H" level signal Ssel. The operation from time t50 to t53 is the same as the operation from time t30 to t33 in FIG. 7. On the other hand, the operation in FIG. 9 differs from the operation in FIG. 7 in that the reference voltage for detecting that the inductor current IL flowing through the NMOS transistor 27 is an overcurrent is a reference voltage Vref2 that is lower than the reference voltage Vref1.

[0067] 9, the effective value of the AC voltage Vac is high at 240 V, and therefore if the current value of the inductor current IL detected as an overcurrent by the comparator 202 is high, there is a possibility that the NMOS transistor 27 will be destroyed. Therefore, the reference voltage for detecting that the inductor current IL flowing through the NMOS transistor 27 is an overcurrent is set to reference voltage Vref2, which is lower than reference voltage Vref1, and the current value detected as an overcurrent becomes smaller, thereby preventing the NMOS transistor 27 from being destroyed.

[0068] == Variations == ==Configuration of Switching Control Circuit 204b== 10 is a diagram showing an example of the switching control circuit 204b. The switching control circuit 204b outputs a drive signal Vq based on the inductor current IL and the feedback voltage Vfb.

[0069] The switching control circuit 204 b includes a drive circuit 300 , an estimation circuit 304 , an output circuit 303 , an oscillation circuit 305 , and a storage circuit 1000 .

[0070] ===Estimation circuit 304=== Like the estimation circuit 301, the estimation circuit 304 stores the off-period Toff for each switching of the NMOS transistor 27 in the storage circuit 1000. The estimation circuit 304 outputs the signal Ssel and determines the timing at which the off-period Toff reaches its peak value (i.e., the timings of times t0 and t1 in FIG. 4 ) based on the stored off-period Toff. The estimation circuit 304 outputs a signal Phase that corresponds to the phase angle of the AC voltage Vac, i.e., that increases as the off-period Toff becomes longer. Specifically, the estimation circuit 304 outputs a signal Phase with a maximum level at times t0 and t1, and outputs a signal Phase with a minimum level near the center of times t0 and t1, i.e., when the phase angle of the AC voltage Vac is low.

[0071] ===Oscillator Circuit 305=== The oscillator circuit 305 changes the output Vr based on the drive signal Vq, the signal Ssel, and the signal Phase. Specifically, when the estimation circuit 304 outputs the signal Ssel at an "L" level and the drive circuit 300 outputs the drive signal Vq at an "H" level, the oscillator circuit 305 changes the slope of the output Vr by changing the slope S1 so that it is proportional to the signal Phase.

[0072] On the other hand, when the estimation circuit 304 outputs a high-level signal Ssel, the oscillator circuit 305 changes the slope of the output Vr so that the slope S2 is proportional to the signal Phase when the drive circuit 300 outputs a high-level drive signal Vq. Furthermore, when the drive circuit 300 outputs a low-level drive signal Vq, the oscillator circuit 305 outputs a zero-level output Vr. The oscillator circuit 305 corresponds to a "first output circuit."

[0073] ==Operation of Switching Control Circuit 204b for Improving Dead Angle== ===Operation of switching control circuit 204b when effective value is 100V=== Fig. 11 is a diagram showing an example of the operation of the switching control circuit 204b. In Fig. 11, it is assumed that the estimation circuit 304 outputs the signal Ssel at "L" level.

[0074] First, at time t60, when the inductor current IL decreases and becomes zero, the comparator 200 outputs a signal Sa of "H" level, and the drive circuit 300 outputs a signal Vq of "H" level.

[0075] When the drive circuit 300 outputs the drive signal Vq at "H" level, the NMOS transistor 27 turns on and the inductor current IL increases.

[0076] Furthermore, when the drive signal Vq becomes "H" level, the oscillation circuit 305 changes the slope of the output Vr at a slope S1 proportional to the signal Phase.

[0077] At time t61 when the output Vr reaches level Vx, the comparator 402 outputs a high-level signal Sc, and the drive circuit 300 outputs a low-level drive signal Vq. Then, the NMOS transistor 27 is turned off, and the inductor current IL begins to decrease.

[0078] At time t62 when the inductor current IL becomes zero, the NMOS transistor 27 is turned on, similarly to time t60. The period from time t60 to t61 is referred to as period P5. Thereafter, the same operation is carried out.

[0079] At time t63 when the rectified voltage Vrec has a high phase angle, the NMOS transistor 27 is turned on, similarly to time t60.

[0080] At time t64 when the output Vr reaches the level Vx, the NMOS transistor 27 is turned off, similarly to time t61.

[0081] Then, at time t65 when the inductor current IL becomes zero, the NMOS transistor 27 is turned on, just as at time t62. If the period from time t53 to t54 is designated period P6, period P6 is shorter than period P5. Therefore, when the AC voltage Vac, i.e., the rectified voltage Vrec, has a low phase angle, the on-period Ton is long, and when the AC voltage Vac has a high phase angle, the on-period Ton is short. This allows a large amount of inductor current IL to flow at low phase angles, suppressing distortion of the input current Iin due to the occurrence of a dead angle at low phase angles.

[0082] The term "dead angle" refers to a phenomenon in which the current for charging capacitor 22 stops flowing when the absolute value of AC voltage Vac is near a small value, resulting in the input current Iin not flowing. In this case, the waveform of input current Iin is not similar to the waveform of AC voltage Vac, which causes a deterioration in power factor and total harmonic distortion. Furthermore, "the absolute value of AC voltage Vac is small" means that when the level of AC voltage Vac is positive, the level of AC voltage Vac is low, i.e., the phase angle is low.

[0083] ===Operation of switching control circuit 204b when effective value is 240V=== FIG. 12 is a diagram showing an example of the operation of the switching control circuit 204b. In FIG. 12, it is assumed that the estimation circuit 304 outputs a signal Ssel of "H" level. Also, the operation from time t70 to t75 is the same as the operation from time t60 to t65 in FIG. 11. On the other hand, the operation in FIG. 12 is different from the operation in FIG. 11 in that when the oscillation circuit 305 changes the output Vr, it changes with a slope S2 proportional to the signal Phase.

[0084] Also, if the period from time t70 to t71 is defined as period P7 and the period from time t73 to t74 is defined as period P8, then period P8 is shorter than period P7. Thus, even when the effective value of the AC voltage Vac is 240V, a large amount of inductor current IL flows at a low phase angle, and distortion of the input current Iin due to the occurrence of a dead angle at the low phase angle is suppressed.

[0085] Also, similarly, a technique for eliminating the dead angle is described in Patent Document 2 mentioned above. However, in Patent Document 2, it is necessary to provide a voltage dividing circuit for detecting the rectified voltage Vrec. As a result, when implementing the technique of Patent Document 2, the AC-DC converter becomes large, and furthermore, the cost increases.

[0086] <<<Overview of the AC-DC Converter 12>>> FIG. 13 is a diagram showing the configuration of the AC-DC converter 12. The AC-DC converter 12 is a boost-type PFC circuit that generates an output voltage Vout at a target level from the AC voltage Vac of a commercial power supply. Note that the AC-DC converter 12 is an example of an AC-DC converter when the power factor correction IC is composed of an analog circuit.

[0087] The AC-DC converter 12 includes an input line filter 20, a full-wave rectifier circuit 21, capacitors 22, 25, 33, and 34, a transformer 23, a diode 24, a power factor correction IC 26b, an NMOS transistor 27, and resistors 28, 30, 31, and 32. The AC-DC converter 12 corresponds to a "power supply circuit," and the current flowing from the commercial power supply to the AC-DC converter 12 is referred to as an input current Iin.

[0088] The resistor 32 and capacitors 33 and 34 are elements for phase compensation of the feedback-controlled power factor correction IC 26b. The resistor 32 and capacitor 33 are connected in series between a terminal COMP (described later) and the ground, and the capacitor 34 is connected in parallel to them.

[0089] <<<About the power factor correction IC26b>>> ==Configuration of power factor correction IC26b== 14 is a diagram showing an example of a power factor correction IC 26b. The power factor correction IC 26b is an integrated circuit that controls the switching of the NMOS transistor 27 so that the level of the output voltage Vout becomes a target level (for example, 400 V) while improving the input power factor of the AC-DC converter 12.

[0090] Specifically, the power factor correction IC 26b drives the NMOS transistor 27 based on the inductor current IL flowing through the main coil L1 and the output voltage Vout. The power factor correction IC 26b is provided with terminals ZCD, FB, OUT, CS, and COMP. For convenience, terminals other than the terminal ZCD of the power factor correction IC 26b (e.g., a ground terminal) are omitted.

[0091] The power factor correction IC 26b includes comparators 500 and 504, a drive circuit 501, an oscillation circuit 502, an on-period output circuit 503, a reference voltage circuit 505, an estimation circuit 301, and a memory circuit 1000. The estimation circuit 301 and the memory circuit 1000 are configured as digital circuits, as in the case of the switching control circuit 204a, but the other circuits are configured as analog circuits, unlike the power factor correction IC 26a.

[0092] The comparator 500 is a circuit that detects when the inductor current IL becomes zero, and compares the voltage Vzcd with a reference voltage Vref0. When the voltage Vvcd becomes lower than the reference voltage Vref0, the comparator 500 outputs a signal Sa at an "H" level. On the other hand, when the voltage Vzcd becomes higher than the reference voltage Vref0, the comparator 500 outputs a signal Sa at an "L" level.

[0093] The drive circuit 501 outputs a drive signal Vq based on the signals Sa, Sb, and Sc. Specifically, after the inductor current IL becomes zero and the comparator 500 outputs a high-level signal Sa, the drive circuit 501 outputs a high-level drive signal Vq to turn on the NMOS transistor 27. Thereafter, when the on-period Ton elapses and an on-period output circuit 503 (described later) outputs a high-level signal Sc, the drive circuit 501 outputs a low-level drive signal Vq to turn off the NMOS transistor 27. Furthermore, when a comparator 504 (described later) detects that the inductor current IL flowing through the NMOS transistor 27 is an overcurrent and outputs a high-level signal Sb, the drive circuit 501 outputs a low-level drive signal Vq.

[0094] The drive circuit 501 includes an SR flip-flop 600 and an OR circuit 601. The SR flip-flop 600 outputs an "H" level drive signal Vq when the comparator 500 outputs an "H" level signal Sa, and outputs an "L" level drive signal Vq when the OR circuit 601 outputs an "H" level signal Sd.

[0095] The OR circuit 601 is an element that performs an OR operation on the signals Sb and Sc, and resets the SR flip-flop 600 when the signal Sb or Sc is input at an "H" level.

[0096] The oscillator circuit 502 changes the output Vr based on the drive signal Vq and the signal Ssel. Specifically, when the estimation circuit 301 outputs the signal Ssel at the "L" level and the drive circuit 501 outputs the drive signal Vq at the "H" level, the oscillator circuit 502 changes the output Vr with a slope S1.

[0097] On the other hand, when the estimation circuit 301 outputs a high-level signal Ssel, the oscillator circuit 502 changes the slope of the output Vr at a slope S2 that is greater than the slope S1 when the drive circuit 501 outputs a high-level drive signal Vq. Also, when the drive circuit 501 outputs a low-level drive signal Vq, the oscillator circuit 502 outputs a 0V output Vr. The oscillator circuit 502 corresponds to a "first output circuit."

[0098] 15, the oscillator circuit 502 includes a current source 700, an inverter circuit 701, an NMOS transistor 702, and a capacitor 703. The current source 700 supplies a current Iramp having a larger value to the capacitor 703 when an "H" level signal Ssel is input than when an "L" level signal Ssel is input. When the value of the current Iramp is small, the output Vr changes with a slope S1, and when the value of the current Iramp is large, the output Vr changes with a slope S2.

[0099] When the drive circuit 501 outputs a drive signal Vq at an "L" level, the inverter circuit 701 outputs a signal Vp at an "H" level, turns on the NMOS transistor 702, and discharges the capacitor 703. As a result, when the drive circuit 501 outputs a drive signal Vq at an "L" level, the output Vr becomes 0 V.

[0100] On the other hand, when the drive circuit 501 outputs a drive signal Vq at a high level, the inverter circuit 701 outputs a signal Vp at a low level, turns off the NMOS transistor 702, and charges the capacitor 703 with a current Iramp. As a result, when the drive circuit 501 outputs a drive signal Vq at a high level, the oscillator circuit 502 changes the output Vr at a slope S1 or S2 in accordance with the signal Ssel.

[0101] The on-period output circuit 503 is a circuit that outputs a signal Sc indicating the on-period Ton based on the output Vr and the feedback voltage Vfb. Specifically, the on-period output circuit 503 outputs an "H" level signal Sc when the output Vr reaches a level corresponding to the feedback voltage Vfb after the inductor current becomes zero. Therefore, the on-period Ton is the period from when the inductor current becomes zero and the drive circuit 501 outputs an "H" level drive signal Vq to when the on-period output circuit 503 outputs an "H" level signal Sc.

[0102] The on-period output circuit 503 includes an error voltage output circuit 610 and a comparator 611. The error voltage output circuit 610 generates an error current Ie according to the error between a reference voltage Vref corresponding to a target level of the output voltage Vout and the feedback voltage Vfb, charges the capacitors 33 and 34 via the terminal COMP, and generates a voltage Vcomp.

[0103] The comparator 611 is a circuit that compares the voltage Vcomp with the output Vr. Specifically, the voltage Vcomp is applied to the inverting input terminal of the comparator 611, and the output Vr is applied to the non-inverting input terminal of the comparator 611. Therefore, when the level of the output Vr is lower than the level of the voltage Vcomp, the comparator 611 outputs a signal Sc at an "L" level, and when the level of the output Vr becomes higher than the level of the voltage Vcomp, the comparator 611 outputs a signal Sc at an "H" level. The on-period output circuit 503 corresponds to a "second output circuit."

[0104] The comparator 504 is a circuit that detects whether the inductor current IL flowing through the NMOS transistor 27 when the NMOS transistor 27 is on is an overcurrent, and compares the voltage Vcs with the reference voltages Vref1 / Vref2 from the reference voltage circuit 505. When the comparator 504 detects that the inductor current IL is an overcurrent, it outputs an “H” level signal Sb.

[0105] The reference voltage circuit 505 outputs a reference voltage Vref1 based on the signal Ssel from the estimation circuit 301, for example, when the effective value of the AC voltage Vac is 100 V, and outputs a reference voltage Vref2 when the effective value of the AC voltage Vac is 240 V. The voltage level of the reference voltage Vref2 is lower than the voltage level of the reference voltage Vref1. The comparator 504 corresponds to an "overcurrent detection circuit."

[0106] <<<About the power factor correction IC26c>>> ==Configuration of Power Factor Correction IC26c== 16 is a diagram showing an example of a power factor correction IC 26c. The power factor correction IC 26c is an integrated circuit that controls the switching of the NMOS transistor 27 so that the level of the output voltage Vout becomes a target level (for example, 400 V) while improving the input power factor of the AC-DC converter 12.

[0107] Specifically, the power factor correction IC 26c drives the NMOS transistor 27 based on the inductor current IL flowing through the main coil L1 and the output voltage Vout. The power factor correction IC 26c is provided with terminals ZCD, FB, OUT, CS, and COMP. For convenience, terminals other than the terminal ZCD of the power factor correction IC 26c (for example, a ground terminal) are omitted.

[0108] The power factor correction IC 26c includes comparators 500 and 504, a drive circuit 501, an oscillation circuit 506, an on-period output circuit 503, a reference voltage circuit 505, an estimation circuit 304, and a memory circuit 1000. The estimation circuit 304 is configured by a digital circuit, similar to the switching control circuit 204b, but differs from the power factor correction IC 26b in that the oscillation circuit 506 changes the slope of the output Vr depending on the signal Phase from the estimation circuit 304.

[0109] The oscillator circuit 506 changes the output Vr based on the drive signal Vq, the signal Ssel, and the signal Phase. Specifically, when the estimation circuit 304 outputs the signal Ssel at an "L" level and the drive circuit 501 outputs the drive signal Vq at an "H" level, the oscillator circuit 506 changes the slope of the output Vr by changing the slope S1 so that it is proportional to the signal Phase.

[0110] On the other hand, when the estimation circuit 304 outputs a high-level signal Ssel, and the drive circuit 501 outputs a high-level drive signal Vq, the oscillator circuit 506 changes the slope S2 of the output Vr so that the slope S2 is proportional to the signal Phase. Also, when the drive circuit 501 outputs a low-level drive signal Vq, the oscillator circuit 506 outputs a 0V output Vr. The oscillator circuit 506 corresponds to the "first output circuit."

[0111] 17, the oscillator circuit 506 includes a current source 704, an inverter circuit 701, an NMOS transistor 702, and a capacitor 703. The current source 704 supplies the capacitor 703 with a current Iramp that is larger when an "H" level signal Ssel is input than when an "L" level signal Ssel is input, and makes the value of the current Iramp proportional to the signal Phase. When the value of the current Iramp is small, the output Vr changes at a slope S1 proportional to the signal Phase, and when the value of the current Iramp is large, the output Vr changes at a slope S2 proportional to the signal Phase.

[0112] ===Summary=== The AC-DC converter 10 of this embodiment has been described above. The switching control circuit 204a includes a drive circuit 300, an estimation circuit 301, an oscillation circuit 302, and an output circuit 303. The estimation circuit 301 estimates the effective value of the AC voltage Vac. When the effective value of the AC voltage Vac is 100 V, the oscillation circuit 302 changes the output Vr at a slope S1. When the effective value of the AC voltage Vac is 240 V, the oscillation circuit 302 changes the output Vr at a slope S2 greater than the slope S1. When the effective value of the AC voltage Vac is high, the oscillation circuit 302 changes the output Vr at a steeper slope. This allows the drive signal Vq to be output with a short on-period Ton without being affected by the limits of the control range, even if the level Vx is low. This makes it possible to provide a switching control circuit that can switch a transistor regardless of the limits of the comparator's control range.

[0113] The estimation circuit 301 also determines the peak value of the off period Toff, and estimates whether the effective value of the AC voltage Vac is 100 V or 240 V based on the peak value, the on period Ton, and the off period Toff. As a result, when the effective value of the AC voltage Vac is 100 V, the AC-DC converter 10 can supply the necessary power to the load 11 with a long on period Ton, and when the effective value of the AC voltage Vac is 240 V, the AC-DC converter 10 can supply only the small amount of power required by the load 11 with a short on period Ton.

[0114] The switching control circuit 204a also includes a storage circuit 1000 that stores the off period Toff for each switching of the NMOS transistor 27. This allows the estimation circuit 301 to determine the peak value Toffp based on the stored off period, and also to determine when, for example, the timings of t0 and t1 in FIG.

[0115] Furthermore, the longer the off period Toff, the greater the slope of the output Vr of the oscillator circuit 302. This makes it possible to suppress the dead angle that occurs at a low phase angle of the AC voltage Vac, and to supply power to the load 11 even at a low phase angle.

[0116] Furthermore, the estimation circuit 301 determines the timing at which the off-period Toff reaches its peak value, and the oscillation circuit 302 increases the slope of the output Vr as the off-period Toff becomes longer based on the timing. As a result, the on-period Ton decreases and increases linearly according to the phase angle of the AC voltage Vac, and the dead angle that occurs at low phase angles of the AC voltage Vac is suppressed.

[0117] Furthermore, when the effective value of the AC voltage Vac is 100 V, the comparator 202 detects an overcurrent when the voltage Vcs corresponding to the inductor current IL flowing through the NMOS transistor 27 becomes equal to the reference voltage Vref1. On the other hand, when the effective value of the AC voltage Vac is 240 V, the comparator 202 detects an overcurrent when the voltage Vcs corresponding to the inductor current IL flowing through the NMOS transistor 27 becomes equal to the reference voltage Vref2, which is higher than the reference voltage Vref1. This allows an overcurrent to be appropriately detected based on the effective value of the AC voltage Vac, and prevents the NMOS transistor 27 from being damaged by heat.

[0118] The above-described embodiments are intended to facilitate understanding of the present invention and are not intended to limit the present invention. Furthermore, the present invention may be modified or improved without departing from the spirit thereof, and the present invention includes equivalents thereof. [Explanation of symbols]

[0119] 10,12 AC-DC converter 11 Load 20 Input Line Filter 21 Full wave rectifier circuit 22, 25, 33, 34, 703 capacitors 23 Transformer 24 Diode 26a, 26b, 26c Power factor correction IC 27,702 NMOS transistors 28,30~32 Resistance 200,202,402,500,504,611 Comparators 201 AD converter 203,505 Reference voltage circuit 204a, 204b Switching control circuit 205 Buffer Circuit 300,501 Drive circuit 301,304 Estimation circuit 302,305 Oscillator circuit 303 Output circuit 400 Error amplifier circuit 401 PI control circuit 502,506 Oscillator Circuit 503 ON period output circuit 600 SR Flip-Flop 601 OR circuit 610 Error voltage output circuit 700,704 current source 701 Inverter circuit 1000 memory circuit

Claims

1. A switching control circuit includes an inductor to which a voltage corresponding to an AC voltage is applied and a transistor that controls an inductor current flowing through the inductor, and controls switching of the transistor in a power supply circuit that generates an output voltage of a target level from the AC voltage, a drive circuit that turns on the transistor after the inductor current reaches a first value, and turns off the transistor after a first period corresponding to the output voltage has elapsed; an estimation circuit that estimates whether an effective value of the AC voltage is at a first level or a second level higher than the first level, based on a second period during which the transistor is turned off, the first period, and the output voltage; a first output circuit that, when the inductor current reaches the first value, changes an output slope with a first slope if the effective value is at the first level, and changes an output slope with a second slope greater than the first slope if the effective value is at the second level; a second output circuit configured to output a period from when the inductor current reaches the first value until when the output reaches a level corresponding to the output voltage, as the first period; A switching control circuit comprising:

2. 2. The switching control circuit according to claim 1, The estimation circuit determining a peak value of the second period in a half cycle of the AC voltage, and estimating whether the effective value of the AC voltage is at the first level or the second level based on the peak value, the first period, and the output voltage; Switching control circuit.

3. 3. The switching control circuit according to claim 2, a memory circuit that stores the second period for each switching of the transistor; Equipped with The estimation circuit determining the peak value based on the stored second period; Switching control circuit.

4. 4. The switching control circuit according to claim 3, The first output circuit As the second period becomes longer, the slope of the output becomes larger. Switching control circuit.

5. 5. The switching control circuit according to claim 4, The estimation circuit determining a timing when the second period reaches the peak value; The first output circuit and increasing the slope of the output as the second period becomes longer based on the determined plurality of timings. Switching control circuit.

6. An integrated circuit comprising: a switching control circuit according to any one of claims 1 to 5; and an overcurrent detection circuit that detects an overcurrent when a current flowing through the transistor becomes a first current when the effective value is at the first level, and detects an overcurrent when a current flowing through the transistor becomes a second current smaller than the first current when the effective value is at the second level, The drive circuit When the current flowing through the transistor becomes an overcurrent, the transistor is turned off. Integrated circuit.

7. A power supply circuit that generates an output voltage of a target level from an AC voltage, an inductor to which a voltage corresponding to the AC voltage is applied; a transistor for controlling an inductor current flowing through the inductor; a switching control circuit for controlling the switching of the transistor; Including, The switching control circuit a drive circuit that turns on the transistor after the inductor current reaches a first value, and turns off the transistor after a first period corresponding to the output voltage has elapsed; an estimation circuit that estimates whether an effective value of the AC voltage is at a first level or a second level higher than the first level, based on a second period during which the transistor is turned off, the first period, and the output voltage; a first output circuit that, when the inductor current reaches the first value, changes an output slope with a first slope if the effective value is at the first level, and changes an output slope with a second slope greater than the first slope if the effective value is at the second level; a second output circuit configured to output a period from when the inductor current reaches the first value until when the output reaches a level corresponding to the output voltage, as the first period; A power supply circuit comprising:

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