Polycrystalline silicon substrate and manufacturing method thereof

Abstract

To provide a polycrystalline silicon substrate that can be used as a silicon wafer or carrier substrate to reduce the occurrence of disconnections during wiring.SOLUTION: A polycrystalline silicon is formed into a plate shape having a first surface and a second surface, and at least the first surface has a difference of 60 nm or less between the maximum height and the minimum height of the surface measured within a 50 μm long range across the grain boundary, and the 50 μm long range is divided into a plurality of sections and the maximum value of the surface slope calculated from the maximum height and the minimum height measured for each section is 2 nm / μm or less.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a polycrystalline silicon substrate suitable for use as a silicon wafer or carrier substrate used in manufacturing semiconductor devices. [Background technology]

[0002] Silicon wafers used in semiconductor devices require highly smooth surfaces because fine circuits are formed on their surfaces using thin-film deposition technology. Furthermore, carrier substrates used in the manufacture of semiconductor devices using WLP (Wafer Level Package) or PLP (Panel Level Package) also require high smoothness, similar to silicon wafers, because semiconductor devices are formed on them through processes such as rewiring and mounting of semiconductor chips.

[0003] For this reason, single-crystal silicon has traditionally been used for these silicon wafers and carrier substrates. Polycrystalline silicon has grain boundaries, which create localized steps and inclinations on the surface at the grain boundaries, potentially causing disconnections during wiring. Therefore, polycrystalline silicon has not yet replaced single-crystal silicon. However, while single-crystal silicon is limited to circular shapes due to its manufacturing process, polycrystalline silicon can also be manufactured in rectangular shapes, which offers advantages in terms of product yield. Therefore, there is a need to improve the surface smoothness of polycrystalline silicon so that its applications can be expanded to the single-crystal silicon field.

[0004] Patent Document 1 discloses a support substrate for a bonded wafer formed by bonding an active layer substrate and a support substrate with an insulating film interposed therebetween, the support substrate comprising a support substrate body and a polycrystalline silicon layer deposited on the bonding surface side of the support substrate body, the grain size of the polycrystalline silicon layer being 0.419 μm or less. In this case, the surface of the polycrystalline silicon is polished to a smooth surface.

[0005] On the other hand, Patent Document 2 discloses a polishing method in which polycrystalline silicon is polished using a polishing liquid containing an abrasive that is an oxide, hydroxide, carbide, or nitride of Ti, Zr, Si, Al, Ce, Ca, or Mg, and an oxidizing agent that is one or more of colloidal silica, zirconium oxide, aluminum oxide, and cerium oxide, thereby preventing steps from occurring on the surface of polycrystalline silicon. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent Publication No. 2021-190660 [Patent Document 2] Japanese Patent Application Laid-Open No. 2008-264952 Summary of the Invention [Problem to be solved by the invention]

[0007] However, high smoothness cannot be obtained simply by controlling the grain size of polycrystalline silicon described in Patent Document 1 or the step on the polycrystalline silicon surface described in Patent Document 2, and it is difficult to prevent breaks in wiring when the silicon is used as a silicon wafer or carrier substrate.

[0008] The present invention has been made in view of the above circumstances, and has as its object to provide a polycrystalline silicon substrate that can be used as a silicon wafer or carrier substrate and that can reduce the occurrence of disconnections during wiring. [Means for solving the problem]

[0009] The polycrystalline silicon substrate of the present invention is formed from polycrystalline silicon in the shape of a plate having a first surface and a second surface, and at least the first surface has a difference of 60 nm or less between the maximum height and the minimum height of the surface measured within a 50 μm long range across the grain boundary, and the 50 μm long range is divided into a plurality of sections and the maximum value of the surface slope calculated from the maximum height and the minimum height measured for each section is 2 nm / μm or less.

[0010] By satisfying both the requirement that the difference between the maximum and minimum heights of the surface within a 50μm-long range caused by the grain boundaries be 60nm or less and the maximum value of the surface slope be 2nm / μm or less, it is possible to prevent the occurrence of disconnections during wiring. If a length of 50μm is set to intersect the grain boundaries, the grain boundaries will necessarily be included within that range, so the difference between the maximum and minimum heights within that range, in other words the step between the grains at the grain boundaries, was identified and controlled to 60nm or less.

[0011] On the other hand, even if the difference between the maximum height and the minimum height (step) within this 50 μm length is 60 nm or less, if there is a localized steep slope within that 50 μm range, the conductive film formed on top of that steep slope may not adhere well to the area, potentially resulting in a break in the wire. Therefore, this 50 μm length was divided into multiple sections and the maximum slope measured was controlled to be 2 nm / μm or less. If the difference between the maximum height and the minimum height (step) exceeds 60 nm or the maximum slope exceeds 2 nm / μm, there is a risk of a break in the wire in either case. By doing so, the polycrystalline silicon substrate of the present invention can have high smoothness at least on the first surface, and can reduce the occurrence of breaks in wiring when used as a silicon wafer or carrier substrate.

[0012] In the polycrystalline silicon carrier substrate of the present invention, the arithmetic mean surface roughness Sa of the surface is preferably 30 nm or less.

[0013] Sa is the arithmetic mean roughness calculated in the surface direction. In addition to the difference between the maximum height and minimum height at the grain boundary and the maximum value of the slope, by setting Sa to 30 nm or less, it becomes possible to perform wiring with higher accuracy and finer resolution.

[0014] The method for manufacturing a polycrystalline silicon substrate of the present invention includes a polishing step in which a plate-shaped member made of polycrystalline silicon is pressed against a rotating polishing pad and polished while a slurry containing a polishing liquid and abrasive grains is supplied onto the polishing pad, the polishing liquid having an acidic and alkaline content adjusted to a pH of more than 7 and not more than 8, and the abrasive grains having an average particle size of 60 nm or more and not more than 200 nm.

[0015] In the case of single-crystal silicon substrates, the surface is generally polished using an alkaline solution, which etches uniformly across the surface because it is a single crystal. However, when this alkaline solution is applied to polycrystalline silicon, each crystal is etched at a different etching rate, resulting in increased steps and slopes at the grain boundaries.

[0016] The polishing solution used in the present invention adjusts the acidity and alkalinity to a pH greater than 7 and equal to or less than 8, thereby preventing excessive etching during polishing, while polishing with relatively large abrasive grains reduces the steps and slopes at the grain boundaries. When the pH of the polishing solution exceeds 8 and becomes more alkaline, anisotropic etching (which exhibits different etching rates depending on the crystal orientation) increases the steps and slopes. When the pH of the polishing solution is 7 or less, the etching effect is reduced, making it difficult to achieve a smooth finish, and the chemical polishing action is reduced, which may leave scratches due to mechanical polishing by the abrasive grains. On the other hand, if the average particle size of the abrasive grains is less than 60 nm, they are not very effective in reducing the steps and inclinations at the grain boundaries, and if it exceeds 200 nm, polishing scratches are likely to occur. [Effects of the Invention]

[0017] According to the present invention, although the polycrystalline silicon is used, the grain boundary steps on the surface are small and the maximum slope is also small, so that the occurrence of disconnections in the conductive film formed thereon by thin film formation technology can be suppressed. Therefore, the polycrystalline silicon substrate of the present invention can be suitably used as a silicon wafer or carrier substrate. [Brief explanation of the drawings]

[0018] [Figure 1] 1 is a cross-sectional view showing a carrier substrate according to an embodiment of the present invention, to which a polycrystalline silicon substrate is applied. [Figure 2] 1 is a schematic diagram for explaining the grain boundaries of polycrystalline silicon, in which the black lines indicate the grain boundaries and the areas surrounded by the black lines indicate the crystal grains. [Figure 3] FIG. 10 is a perspective view schematically showing a part of a polishing step. [Figure 4] 1A to 1C are cross-sectional views showing a process for manufacturing a semiconductor device using a carrier substrate. [Figure 5] FIG. 1 is a height profile diagram measured across grain boundaries on the surface of a polycrystalline silicon substrate. DETAILED DESCRIPTION OF THE INVENTION

[0019] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0020] The polycrystalline silicon substrate of one embodiment illustrates an example in which the present invention is applied to a carrier substrate (hereinafter simply referred to as a carrier substrate) for semiconductor device manufacturing. This carrier substrate 1 is made of polycrystalline silicon, and as shown in Figure 1, a first surface 1a and a second surface 1b opposite to the first surface 1a are formed parallel to each other, and an outer peripheral surface 1c connecting the peripheries of the first surface 1a and the second surface 1b is formed in a cylindrical or rectangular tube shape (in other words, the first surface 1a and the second surface 1b are formed in a circular or rectangular shape, and the carrier substrate 1 as a whole is a disk-shaped or rectangular plate-shaped plate-like substrate).

[0021] The dimensions of this carrier substrate 1 are not necessarily limited, but the thickness t1 is 0.3 mm to 2.0 mm, and if it is disk-shaped, the diameter d is 200 mm to 430 mm, preferably 300 mm to 430 mm, and if it is rectangular, one side d (since the planar shape is not specified in Figure 1, the same symbol d is used) is 200 mm to 900 mm, preferably 300 mm to 900 mm, and more preferably 500 mm to 900 mm. In the case of a rectangular plate-shaped carrier substrate 1, it may be square, rectangular, or polygonal. It is preferable that the carrier substrate 1 as a finished product has a thickness tolerance of ±0.05 mm.

[0022] In this carrier substrate 1, if the first surface 1a is the semiconductor device formation surface, on this first surface 1a, the difference between the maximum height and minimum height of the surface measured within a range (an imaginary straight line on the surface) of 50 μm in length (see the dashed line of the length indicated by L1 in the schematic diagram of Figure 2) that intersects across the grain boundaries of the polycrystalline silicon (hereinafter, this may be referred to as the grain boundary step or simply the step) is 60 nm or less, and the maximum value of the surface slope (hereinafter, this may be referred to as the grain boundary slope or simply the slope) calculated from the maximum height and minimum height measured for each of the multiple sections divided within that 50 μm range is 2 nm / μm or less.

[0023] In this case, the difference between the maximum and minimum heights of the surface at the grain boundary and the maximum value of the slope can be measured, for example, using a laser microscope equipped with a white light interferometer (VK-X3000) manufactured by Keyence Corporation. The grain boundary of the polycrystalline silicon is confirmed using the laser microscope at a magnification of 10x from a measurement field of view (field of view size: 1 x 1.4 mm), and the surface height is measured in white light interferometer mode in a direction intersecting the grain boundary. In this case, a length of 50 μm is set within the field of view to ensure that the grain boundary falls within the measurement range, and the surface is measured in a 50 μm range intersecting the grain boundary in white light interferometer mode. The arithmetic mean surface roughness Sa can be calculated from the field of view (field of view size: 1×1.4 mm) obtained by the above measurement of the crystal grain boundary, using an application attached to the above laser microscope.

[0024] From the surface height profile obtained in this 50 μm-long range, the maximum height and minimum height are measured, and the difference between them is calculated. Furthermore, the 50 μm range is divided into multiple sections, for example, 0 μm to 10 μm, 10 μm to 20 μm, and five sections of 10 μm each, and the maximum height and minimum height are measured for each section. These measurements are divided by the length of the section (10 μm in this case) to calculate the slope of each section, and the maximum value is taken as the maximum surface slope. The length of the divided sections does not have to be 10 μm, as long as the 50 μm range can be divided into two or more sections, preferably three or more sections. For example, if the 50 μm range is divided into five sections, the maximum grain boundary slope in the five sections is 2 nm / μm or less.

[0025] By satisfying both the requirement that the difference between the maximum and minimum heights of the surface within a 50 μm length caused by the grain boundaries is 60 nm or less and the maximum value of the surface slope is 2 nm / μm or less, a high level of smoothness of the first surface can be obtained, and the occurrence of disconnections during wiring can be suppressed. The difference between the maximum and minimum heights of the surface within a 50 μm length represents the step between the grains at the grain boundaries, since the grain boundaries are included within that length. If the difference between the maximum and minimum heights (step) within this 50 μm length exceeds 60 nm, there is a risk of disconnections during wiring due to the large step. The grain boundary step within this 50 μm length is preferably 20 nm or less, and more preferably 10 nm or less. Although not particularly limited, the grain boundary step within a length of 50 μm may be 0.01 nm or more, 0.1 nm or more, or 1 nm or more.

[0026] On the other hand, even if the difference between the maximum and minimum heights of the surface within a 50 μm length is 60 nm or less, if there is a locally steep slope within that range, there is a risk of wire breakage at the steep slope, so the maximum value of the surface slope was controlled to be 2 nm / μm or less. If the difference between the maximum and minimum heights (step) exceeds 60 nm or the maximum value of the slope exceeds 2 nm / μm, there is a risk of wire breakage. The maximum value of this grain boundary inclination is preferably 1 nm / μm or less, and more preferably 0.2 nm / μm or less. Although not particularly limited, the minimum value of the grain boundary tilt may be 0.001 nm / μm or more, 0.01 nm / μm or more, or 0.1 nm / μm or more.

[0027] Furthermore, the first surface 1a of the carrier substrate 1 preferably has an arithmetic mean surface roughness Sa in the surface direction of 30 nm or less. Unlike Ra, this arithmetic mean surface roughness Sa is the arithmetic mean roughness measured in the plane direction, and the greater the volume fraction of the area that differs in height from the reference plane (Z = 0 plane), the larger the roughness Sa. In addition to the difference between the maximum and minimum heights and the slope at the grain boundaries mentioned above, a surface roughness Sa of 30 nm or less enables wiring with higher precision and finer resolution. The arithmetic mean surface roughness Sa is preferably 15 nm or less, and more preferably 2 nm or less. Although not particularly limited, the arithmetic mean surface roughness Sa may be 0.01 nm or more, or may be 0.1 nm or more.

[0028] In the above embodiment, the grain boundary step and grain boundary inclination, as well as the arithmetic mean surface roughness Sa, of the first surface 1a of the carrier substrate 1 are specified, but the second surface 1b may also be formed to have the same configuration as the first surface 1a.

[0029] Next, a method for manufacturing this carrier substrate (polycrystalline silicon substrate) 1 will be described. This carrier substrate is manufactured through an ingot production process in which a polycrystalline silicon ingot is produced by casting, a machining process in which the ingot is shaped and sliced ​​to form a plate-shaped member, a polishing process in which the surface of the plate-shaped member is polished, and a cleaning process in which the plate-shaped member is cleaned after polishing. The steps will be explained below in order.

[0030] (ingot production process) A polycrystalline silicon ingot can be produced by heating and melting a silicon raw material in a crucible made of quartz or the like coated with a release agent, and then either cooling and solidifying the silicon melt directly in the crucible, or pouring the silicon melt from the crucible into a mold made of graphite or the like and then cooling and solidifying it. As the silicon raw material, for example, massive chunks obtained by crushing high-purity silicon are used, and a dopant such as boron (B) is added as needed. Since the ingot is solidified in a crucible or mold, it is possible to form the ingot into not only a cylindrical shape but also a prismatic shape or other shapes.

[0031] (machining process) The ends of the ingot are cut off to shape the outer shape, and the shaped ingot is sliced ​​to a predetermined thickness using a wire saw or the like to form a plate-shaped member. This machining process forms a plate-shaped member with a thickness t1 of 0.3 mm to 1.2 mm. If chipping or the like occurs on the edge of the plate-shaped member after machining, the plate-shaped member may be etched with an alkaline aqueous solution to remove the chipping or the like.

[0032] (polishing process) In the polishing step, the surface of the sliced ​​plate-shaped member is roughly polished and then finish-polished. In rough polishing, the surface of a plate-shaped member is polished by minute grinding using a polishing liquid and abrasive grains on a lapping machine. The abrasive grains used here are coarse, for example, with a particle size of several hundred microns. Dry rough polishing can also be performed without using a polishing liquid, in which the abrasive grains are fixed to the lapping machine.

[0033] For the final polishing, a so-called CMP (Chemical Mechanical Polishing) device is used. As shown in Figure 3, this CMP device 5 has a head 6 that holds a plate-shaped member 2 made of polycrystalline silicon and a horizontally rotatable polishing pad 7. The plate-shaped member 2 is attached horizontally to the head 6, and the polishing pad 7 is rotated as shown by arrow A. A slurry, a mixture of polishing liquid and abrasive grains, is supplied onto the polishing pad 7 as shown by arrow B, while the plate-shaped member 2 is pressed against the upper surface of the polishing pad 7, thereby polishing the plate-shaped member. The surface of the plate-shaped member is polished by the chemical polishing action of dissolution by the polishing liquid and the mechanical polishing action of grinding by the abrasive grains.

[0034] The polishing pad 7 used here is made of nonwoven fabric, polyurethane pad, etc., and the abrasive grains are preferably made of, for example, SiO2, but the average grain size used is 60 nm or more and 200 nm or less, which is larger than the grain size used in normal CMP polishing (for example, grain size of 50 nm or less).

[0035] The polishing solution is adjusted to a pH of more than 7 but not exceeding 8 by adjusting the acidity and alkalinity. It can be said to be nearly neutral, but it is slightly alkaline because it is prepared by adjusting the acidity and alkalinity. Specifically, for example, it is prepared by adding weakly acidic citric acid to a strongly alkaline aqueous solution of potassium hydroxide (KOH). The potassium hydroxide (KOH) aqueous solution is prepared so that its pH is about 10 (for example, 9.5 to 10.5), and citric acid is added to this to adjust the pH to more than 7 but not exceeding 8.

[0036] A slurry made by mixing these abrasive grains and polishing liquid is supplied onto the polishing pad, while a plate-shaped polycrystalline silicon member that has been roughly polished in advance is pressed against the rotating polishing pad and polished.The action of the abrasive grains, mainly with a large particle size, improves the mechanical action during polishing and reduces the steep gradient that occurs at the grain boundaries, while the chemical action of the polishing liquid suppresses the progress of anisotropic etching between the crystal grains, making it less likely that steps will occur at the grain boundaries.

[0037] Furthermore, by setting the average particle size of the abrasive grains to a relatively coarse particle size of 60 nm or more and 200 nm or less, the mechanical polishing action of the abrasive grains is enhanced, allowing the grain boundary steps to be removed and a smooth finish to be achieved. If the average particle size of the abrasive grains is less than 60 nm, it is not effective in reducing the steps and slopes at the crystal grain boundaries, and if it exceeds 200 nm, the chemical polishing action of the polishing liquid is weak, making polishing scratches more likely to occur. The average particle size of the abrasive grains is preferably 80 nm or more and 200 nm or less.

[0038] By controlling these polishing liquids and abrasive grains, a carrier substrate 1 can be obtained in which the difference between the maximum and minimum heights of the surface measured within a 50 μm length across the grain boundary is 60 nm or less, and the maximum slope within that 50 μm length is 2 nm / μm or less. Furthermore, the arithmetic mean surface roughness Sa in the surface direction of the first surface 1a can be set to 30 nm or less.

[0039] (Cleaning process) Finally, the polished plate-like member is washed with pure water to complete the desired carrier substrate.

[0040] 4, an example of a method for manufacturing a semiconductor device using the carrier substrate 1 manufactured as described above will be described. A temporary fixing layer 11 is formed on the polished first surface 1a. This temporary fixing layer 11 is a layer provided for peeling the carrier substrate 1 from the rewiring layer 12 when use as the carrier substrate 1 has been completed, and is made of a substance that peels easily or a material whose adhesive strength decreases when irradiated with a laser or the like. 4(a), a rewiring layer 12 is formed on this temporary fixing layer 11 by thin-film formation technology, and then, as shown in FIG. 4(b), a semiconductor chip 13 is mounted on the rewiring layer 12 and this semiconductor chip 13 is sealed with a sealing resin 14 such as an epoxy-based resin. Then, after peeling the carrier substrate 1 from the temporary fixing layer 11, as shown in FIG. 4(c), electrode terminals 15 such as solder balls are fixed to the exposed rewiring layer 12, and the resulting structure is divided into required sizes to produce packaged semiconductor devices 16.

[0041] The first surface 1a of this carrier substrate 1 is formed so that the difference between the maximum and minimum heights of the surface measured within a 50 μm length across the grain boundary is 60 nm or less, and the maximum value of the grain boundary slope is 2 nm / μm or less, so that the steps and slopes at the grain boundary are small, making it possible to prevent breaks in the rewiring layer 12 formed thereon. In this case, if the arithmetic mean surface roughness Sa of the first surface 1a is 30 nm or less, wiring can be formed with higher accuracy and finer definition.

[0042] Although the present invention has been described in the embodiment as being applied to a carrier substrate for semiconductor device manufacturing, the present invention can also be applied to silicon wafers as a substitute for single crystal silicon because the difference between the maximum and minimum heights of the surface at the grain boundaries is 60 nm or less, and the maximum slope is 2 nm / μm or less, which is close to the surface condition of single crystal silicon. By setting the arithmetic mean surface roughness Sa to 30 nm or less, an even smoother silicon wafer can be obtained. [Example]

[0043] Polycrystalline silicon substrates were fabricated from the polycrystalline silicon plate-shaped member by changing the conditions (abrasive grains, pH of polishing liquid) for the finish polishing in the polishing step of the above manufacturing method.

[0044] Two types of polishing liquids were used for polishing: one consisting of an aqueous solution of potassium hydroxide (KOH) adjusted to a pH of 9.5 to 10.5 by adding KOH to water, and the other consisting of an aqueous solution of potassium hydroxide adjusted to a pH of 7.5 to 7.9 by adding citric acid. The abrasive grains used were made of SiO2 and had an average grain size shown in Table 1. These abrasive grains were mixed into the polishing liquid at a concentration of 15 mass % to prepare a slurry. The polishing pad was made of nonwoven fabric and rotated at a rotation speed of 40 rpm to 60 rpm. A polycrystalline silicon plate member was pressed against the polishing pad at a pressure of 2 MPa to 4 MPa while supplying slurry onto the pad for polishing.

[0045] As a reference example, a single crystal silicon substrate (wafer) formed from single crystal silicon by a conventional method (polishing using an alkaline polishing liquid and abrasive grains) was used. The polycrystalline silicon substrate was a square with an outer shape of 515 mm x 510 mm, and the single crystal silicon substrate was a circle with a diameter of 125 mm.

[0046] The height of the polished surface of these silicon substrates was measured using a laser microscope (VK-X3000) equipped with a white light interferometer manufactured by Keyence Corporation in white light interferometry mode, with the grain boundaries placed within a field of view (field of view size: 1 × 1.4 mm), and the maximum grain boundary step height and grain boundary inclination were determined. The arithmetic mean surface roughness Sa was also calculated using this laser microscope. The grain boundary step was determined by setting a 50 μm long range where the grain boundary entered at any grain boundary, intersecting the grain boundary, and calculating the difference between the measurement value at the highest point (maximum height) and the measurement value at the lowest point (minimum height). The maximum value of the grain boundary slope was determined by setting a 50 μm long range where the grain boundary entered at any grain boundary, intersecting the grain boundary, measuring the maximum and minimum heights for each 9.7 μm long section, and dividing the five measurements obtained by 9.7 μm to calculate the slope for each section. The maximum of these five values ​​was determined to be the maximum surface slope. The arithmetic mean surface roughness Sa was calculated using an application attached to the laser microscope. In each measurement, five measurements were taken at different locations on each sample, and the maximum values ​​were shown in the table.

[0047] Additionally, TTV was measured to confirm flatness. TTV was calculated as the difference between the maximum and minimum thickness values ​​by measuring the thickness of the substrate using a multicolor laser coaxial displacement meter (CL-3000 manufactured by Keyence Corporation). Thickness can be measured by shining a laser (spot diameter: 10 μm) at the same position on both the front and back surfaces of the substrate and detecting the reflected light. There were 36 measurement points on a 515mm x 510mm rectangular substrate, with the 515mm side horizontal and the 510mm side vertical, and measurements were taken at 100mm pitches in both the vertical and horizontal directions, starting from a position 7.5mm horizontally and 5.5mm vertically from the corner of the substrate. For the 125mm diameter wafer used as a reference example, nine measurement points were taken: four points on the outer periphery of the circle (5mm from the edge), four points on the inner periphery (32mm from the edge), and one point at the center. Measurements were taken at each of the four points on the outer and inner peripheries, one at a 90° angle. The results are shown in Table 1. The numerical value before mmt in the silicon type column is the substrate thickness (millimeter).

[0048] [Table 1]

[0049] In all of Examples 1 to 12, the grain boundary step on the surface was 60 nm or less, and the maximum grain boundary slope was 2 nm / μm or less, so it is expected that wiring would not break even if it was applied thereon. Furthermore, among these Examples, Examples 2 to 12 all had an arithmetic mean roughness Sa of 30 nm or less, indicating a smooth surface condition. Among these, Examples 3, 4, 7, 8, 11, and 12, which used an average abrasive grain size of 80 nm or more, had a grain boundary step of 20 nm or less, a grain boundary slope of 1.0 nm / μm or less, and a surface roughness Sa of 15 nm or less, resulting in an excellent surface condition. In particular, Examples 4, 8, and 12 had a surface roughness Sa comparable to that of the single-crystal silicon substrate used as a reference example. In Example 1, the average particle size of the abrasive grains was large, so the grain boundary gradient was gentle, but the arithmetic mean roughness Sa of the surface was slightly large. Although the grain boundary step was somewhat large, it was 60 nm or less, so it is expected that no disconnection defects will occur. It is believed that Examples 2 to 12, which have an arithmetic mean roughness Sa of 30 nm or less, can achieve wiring with higher precision and finer resolution.

[0050] Regarding flatness (TTV), all examples were confirmed to be flat with a TTV of 10 μm or less. A TTV of 20 μm or less is considered to be practically sufficient flatness. Table 2 shows that flatness improves when the substrate thickness increases from 0.8 mm to 1.1 mm or 2.0 mm. A thicker substrate increases rigidity, making it less likely to warp or undulate during polishing. It is assumed that this results in more uniform pressure from the polishing platen across the surface, improving flatness. Better substrate flatness reduces warping during wiring formation, allowing for larger packages. The reason why there is not much change in TTV even when the substrate thickness is increased from 1.1 mm to 2.0 mm is thought to be due to the limitations of the equipment conditions caused by the warp of the polishing table being about 5 μm.

[0051] On the other hand, in Comparative Example 1, because an alkaline polishing solution was used, the grain boundary steps were large and the abrasive grain size was small, so the maximum slope value was also large. Furthermore, the surface roughness Sa was also large. In Comparative Example 2, because polishing was performed using a polishing solution with a pH adjusted to 7.5 to 7.9, the grain boundary steps were smaller than in Comparative Example 1 and were comparable to those in Example 1. However, because the average abrasive grain size was as small as in Comparative Example 1, the maximum slope value of the grain boundaries was large and the surface roughness Sa was also large. When a film was formed on Comparative Example 1, breaks occurred at the grain boundary steps, and in Comparative Example 2 as well, there was a risk that the conductive film would not adhere well at the location showing the maximum slope value, leading to breaks.

[0052] Figure 5 shows the profile of the surface height measured on the surface of a sample using a laser microscope equipped with a white light interferometer, with (a) showing Example 2 and (b) showing Comparative Example 1. In both figures, the horizontal axis represents the length along the surface, with L1 representing 50 μm and the surface being divided into five sections with lengths indicated by L2. The vertical axis represents the surface height, with H1 representing the difference between the maximum and minimum heights within a 50 μm length range, H2 representing the difference between the maximum and minimum heights of the section showing the maximum grain boundary tilt, and H2 / L2 representing the grain boundary tilt.

[0053] As in the examples, by increasing the particle size of the abrasive grains, the abrasive grains are more likely to catch on the grain boundary steps and scrape them away, reducing the steepness of the inclination. As a result, it is assumed that the surface roughness Sa is also reduced. This surface roughness Sa tends to decrease slightly as the grain boundary inclination decreases, even when the grain boundary steps are the same. As mentioned above, the surface roughness Sa increases as the volume fraction of the part that differs in height from the reference plane (Z = 0 plane) increases. Therefore, it is believed that Comparative Example 2, which had the same grain boundary steps, had a steeper grain boundary inclination, and therefore the volume of the part that differs in height from the reference plane (Z = 0 plane) increased, resulting in a larger Sa.

[0054] As in Example 3, by further increasing the average grain size of the abrasive grains, it is possible to reduce the grain boundary step and grain boundary inclination. Furthermore, as in Example 4, by further increasing the average grain size of the abrasive grains, it is possible to almost completely eliminate the grain boundary inclination. As a result of almost completely eliminating the inclination of the grain boundaries, the grain boundary step also disappears, and it is recognized that adjacent crystal faces are aligned as almost the same plane. As a result, it is possible to obtain a polycrystalline silicon substrate with a surface roughness equal to or greater than that of a single-crystal silicon wafer. [Explanation of symbols]

[0055] 1. Carrier substrate (polycrystalline silicon substrate) 1a Front page 12 Redistribution layer 13 Semiconductor chips 16 Semiconductor Devices

Claims

1. A polycrystalline silicon substrate, characterized in that polycrystalline silicon is formed into a plate shape having a first surface and a second surface, and at least the first surface has a difference between the maximum height and the minimum height of the surface measured within a 50 μm long range across a grain boundary of 60 nm or less, and the 50 μm long range is divided into a plurality of sections and the maximum value of the surface slope calculated from the maximum height and the minimum height measured for each section is 2 nm / μm or less.

2. 2. The polycrystalline silicon substrate according to claim 1, wherein the arithmetic mean surface roughness Sa of the surface is 30 nm or less.

3. A method for manufacturing a polycrystalline silicon substrate, comprising a polishing step of pressing a plate-shaped member made of polycrystalline silicon against a polishing pad while supplying a slurry containing a polishing liquid and abrasive grains onto a rotating polishing pad to polish it, wherein the polishing liquid has a pH greater than 7 and equal to or less than 8 by adjusting the amount of acid and alkali, and the abrasive grains have an average particle size of 60 nm or more and 200 nm or less.

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