Package structure and packaging method

Abstract

To provide a package structure and a packaging method that improve process simplification and manufacturing cost.SOLUTION: A package structure 100 includes a substrate 102, a chip 104 disposed on the substrate 102 and having a backside surface 104S away from the substrate 102, a heat sink 108 disposed above the substrate 102 and having a surface 108S facing the back side surface 104S of the chip 104, and a thermal interface material 106 disposed between the chip 104 and the heat sink 108. There is no organic adhesive between the chip 104 and the heat sink 108.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] This application claims priority to Taiwan Patent Application No. 113121773, filed June 13, 2024, all of which are incorporated herein by reference.

[0002] The present invention relates to packaging technology, and more particularly to a packaging structure and a packaging method. [Background technology]

[0003] Electronic components are evolving toward lighter, thinner, smaller, higher performance, higher transmission, and higher efficiency, resulting in ever-increasing heat dissipation per unit area. For example, while the heat dissipation of a central processing unit (CPU) element using a Pentium processor previously was only 20W, it now exceeds 80W with the Pentium IV, causing CPU temperatures to reach over 150°C during operation. According to a forecast by the U.S. International Technology Roadmap for Semiconductors (ITRS) regarding future trends in the development of the semiconductor industry, the heat output of low-level computers will increase from the current approximately 100W to nearly 120W over the next few years, while the heat output of high-level computers will increase significantly from the initial 150W to over 180W. Operating frequencies will also increase from 2GHz to over 4GHz. As the functionality and heating power density of electronic components increase dramatically, the requirements for thermal management will become increasingly stringent.

[0004] Thermal interface materials (TIMs) are a type of material commonly used in integrated circuit (IC) packaging and heat dissipation for electronic components. Their primary function is to bridge the contact gap between two materials, enhance the system's heat dissipation performance, and effectively reduce thermal impedance. A good thermal interface material must possess the following properties: (1) excellent heat dissipation performance, i.e., high thermal conductivity and low thermal impedance; (2) ease of assembly and rework; (3) high compressibility to withstand external compressive stress when fixed to the mating surface, properly filling the gap between the interfaces and promoting heat flow; (4) good wettability with electronic components and heat sinks; and (5) high reliability and long life. Current thermal interface materials mainly include thermal grease, elastomeric thermal pads, phase-change materials, and low-melting-point alloys.

[0005] While existing packaging technologies using thermal interface materials have generally been suitable for their intended purposes, they are not entirely satisfactory in all respects and there is still room for improvement in terms of process simplification and manufacturing costs. Summary of the Invention [Problem to be solved by the invention]

[0006] To provide a package structure and a packaging method that simplify the process and improve the manufacturing cost. [Means for solving the problem]

[0007] An embodiment of the present disclosure provides a package structure that includes a substrate, a chip disposed on the substrate and having a backside surface remote from the substrate, a heat sink disposed on the substrate and having a surface facing the backside surface, and a thermal interface material disposed between the chip and the heat sink, wherein no organic adhesive is present between the chip and the heat sink.

[0008] An embodiment of the present disclosure provides a packaging method. The packaging method includes disposing a chip on a substrate, the chip having a backside away from the substrate. The packaging method includes providing a heat sink, the heat sink having a surface facing the backside of the chip. The packaging method includes disposing a thermal interface material on the chip or the heat sink via impression bonding. The packaging method includes adhering the heat sink to the chip such that the thermal interface material is disposed between the chip and the heat sink. [Brief explanation of the drawings]

[0009] The concepts of the embodiments of the present disclosure will be better understood based on the following detailed description and the accompanying drawings. It should be noted that, according to standard industry practice, the various features in the drawings are not necessarily drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of illustration. It is also emphasized that the accompanying drawings illustrate only typical embodiments of the present disclosure and are therefore not intended to limit the scope, as the present disclosure may be applied to other embodiments as well. [Figure 1] FIG. 1 is a cross-sectional view of various stages in the manufacture of a package structure according to some embodiments. [Figure 2] FIG. 2 is a cross-sectional view of various stages in the manufacture of a package structure according to some embodiments. [Figure 3] 3A-3D are cross-sectional views of various stages in the manufacture of a package structure according to some embodiments. [Figure 4] 4A-4C are cross-sectional views of various stages in the manufacture of a package structure according to some embodiments. [Figure 5] FIG. 5 is a cross-sectional view of a package structure according to some embodiments. [Figure 6] 6A-6C are cross-sectional views of various stages in the manufacture of a package structure according to another embodiment. [Figure 7] 7A-7C are cross-sectional views of various stages in the manufacture of a package structure according to another embodiment. [Figure 8] 8A-8D are cross-sectional views of various stages in the manufacture of a package structure according to another embodiment. [Figure 9] 9A-9C are cross-sectional views of various configurations of package structures according to further embodiments. [Figure 10] FIG. 10 is a cross-sectional view of various configurations of package structures according to further embodiments. [Figure 11] FIG. 11 is a cross-sectional view of various configurations of package structures according to further embodiments. [Figure 12] FIG. 12 is a cross-sectional view of various configurations of package structures according to further embodiments. [Figure 13] 13A-13C are cross-sectional views of various configurations of package structures according to further embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0010] Several different implementations or examples are disclosed below for implementing different features of the provided subject matter. To illustrate the present disclosure, examples of specific elements and their arrangements are described below. For example, a statement herein that a first feature is formed on a second feature may include an embodiment in which the first feature is in direct contact with the second feature, or may also include an embodiment in which other features exist between the elements of the first feature and the elements of the second feature. In other words, the elements of the first feature may not be in direct contact with the elements of the second feature. Furthermore, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity and does not, in itself, dictate a relationship between the various embodiments and / or configurations described.

[0011] Additionally, spatially relative terms such as "lower," "below," "bottom," "top," "upper," "top," and similar terms are used for simplicity in the description to describe the relationship of one element or feature to another element(s) and feature(s) in the figures. Spatially relative terms are intended to encompass different orientations of the device for use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein may be interpreted accordingly.

[0012] Several embodiments of the present disclosure are described. Additional steps may be provided before, between, and / or after the steps described in these embodiments. Some of the steps described may be replaced or eliminated in different embodiments. Additional features may be added to the semiconductor device structure. Some of the features described below may be replaced or eliminated in different embodiments. Although some embodiments describe operations being performed in a particular order, these operations may be performed in another logical order.

[0013] Conventional technologies require first bonding the thermal interface material to the heat sink or chip using an organic adhesive to prevent it from shifting from the position where it is pressed between the heat sink and the chip (which would prevent the contact gap between them from being filled). Therefore, in the package structure obtained by pressing the chip and heat sink together, an organic adhesive (such as a fixing adhesive or flux) exists between the heat sink and the chip, and the heat dissipation performance may be affected by the properties of the organic adhesive itself. Furthermore, the costs of obtaining and disposing of the organic adhesive increase the overall production cost. Furthermore, solid residues from the organic adhesive may remain at the bonding interface, forming voids that reduce the reliability of the package structure. This may also prevent the thermal interface material from fully adhering to the chip and the heat sink, leading to reduced heat dissipation performance.

[0014] To solve the above problems, the present disclosure uses a pressure-bonding technique that enables thermal interface materials to be fixed at room temperature (above 0°C) without the need for additional organic adhesives. By applying pressure to the thermal interface material before compressing the chip and heat sink, the thermal interface material is fixed in direct contact with the chip or heat sink, achieving temporary positioning. This prevents the thermal interface material from shifting before the chip and heat sink are compressed, eliminating the need for organic adhesives used in conventional technologies. Therefore, the package structure and packaging method provided by the present disclosure can save costs associated with obtaining and disposing of organic adhesives. Furthermore, because the thermal interface material is in direct contact with the chip and heat sink rather than being separated by organic adhesive, heat generated during chip operation can be directly transferred to the heat sink by the thermal interface material, achieving better heat dissipation performance.

[0015] 1-4 are cross-sectional views of a package structure 100 at various stages in the manufacture of the package structure 100, according to some embodiments.

[0016] As shown in FIG. 1 , in one embodiment, the chip 104 is disposed on the substrate 102. In some embodiments, the substrate 102 may include a printed circuit board (PCB), a wafer substrate, an integrated circuit (IC), an interposer, a chip carrier, a circuit carrier, and a display device. In some embodiments, the chip 104 may include a semiconductor chip. A semiconductor chip may be, for example, a small piece of a semiconductor wafer formed by performing semiconductor processing on the semiconductor wafer and then separating the semiconductor wafer into individual dies. The chip 104 may include an integrated circuit for processing and / or storing data, such as a field programmable gate array (FPGA), a processing unit (e.g., a graphics processing unit (GPU)), a central processing unit (CPU), an application specific integrated circuit (ASIC), or a memory device (e.g., a memory controller or memory). In some embodiments, the chip 104 may include a single crystal of a material such as Si, Ge, SiC, sapphire, GaAs, or GaN. In some embodiments, the chip 104 may be attached to the substrate 102 using a polymer adhesive, a solder, or a combination thereof.

[0017] In one embodiment, the chip 104 has a back surface 104S (the upward-facing surface of the chip 104 in FIG. 1 ) that is away from the substrate 102. In one embodiment, the chip 104 optionally includes a metal layer 1040 on the back surface 104S and an outermost metal layer 1042 on the metal layer 1040. Specifically, the outermost metal layer 1042 is on the side of the metal layer 1040 that is away from the substrate 102. In some embodiments, the metal layer 1040 and the outermost metal layer 1042 are configured to improve the heat dissipation performance of the package structure 100 and reduce the thermal impedance of the package structure 100, although the present disclosure is not limited thereto.

[0018] In some embodiments, the metal layer 1040 can include at least one of Al / Ti / NiV, Al / Cr / NiV, Al / NiV, Al / W, Ti / NiV, TiW, WTi, WTi / Ti, Cr / NiV, Cr, W, Ti / Ni, Al / Ti / Ni, Ti, W / Ni, W / NiV, WTi / Ni, WTi / NiV, TiW / Ni, and TiW / NiV. In some embodiments, the thickness of the metal layer 1040 can be 0.001 to 10 μm (e.g., 0.5 to 1.6 μm). The outermost metal layer 1042 can include at least one of Au, Ag, Cu, Rh, Ir, Pd, Pt, and any suitable metal material and has a thickness of 0.001 to 10 μm (e.g., 0.1 to 2 μm). In some embodiments, methods for forming the metal layer 1040 and the outermost metal layer 1042 can include sputtering, evaporation, electroplating, and any suitable deposition process.

[0019] 2-3, in one embodiment, the thermal interface material 106 is disposed on the chip 104 by impression bonding. In some embodiments, the thermal interface material 106 is configured to fill the contact gap between the chip 104 and the heat sink 108 (as shown in FIG. 4), thereby enhancing the overall heat dissipation performance of the package structure 100 and effectively reducing the thermal impedance of the package structure 100.

[0020] In some embodiments, the thermal interface material 106 is disposed on the chip 104 by indentation bonding. Specifically, as shown in FIGS. 2-3 , downward arrows indicate the direction of applied pressure. By applying pressure to the thermal interface material 106 (e.g., using a press head 700), indentations 702 are formed on the thermal interface material 106 where the pressure is applied. The applied pressure forms a diffusion bond between the thermal interface material 106 and the chip 104, securing the thermal interface material 106 onto the chip 104 and achieving temporary positioning. This prevents the thermal interface material from shifting before the heat sink 108 (as shown in FIG. 4 ) and the chip 104 are pressed together, eliminating the need for an organic adhesive application step. In FIG. 2 , a press head 700 is used to apply single-point pressure to the thermal interface material 106, forming indentations 702. In FIG. 3 , two press heads 700 are used to apply multiple-point pressure to the thermal interface material 106. Although FIGS. 2-3 only show single-point and two-point indentations, the present invention is not limited thereto. In other embodiments, single-point or multi-point pressure can be applied to any location on the surface of the thermal interface material 106 to form single-point, two-point, or three-point depressions on the thermal interface material 106, depending on actual needs. For example, in FIGS. 2-3, single-point or multi-point pressure is applied to the thermal interface material 106 (e.g., using a press head 700) in a direction toward the surface of the outermost metal layer 1042 of the chip 104. Also, as shown in FIGS. 2-3, the press head 700 and depressions 702 have circular profiles, but the present invention is not limited thereto. In other embodiments, the press head 700 may have a profile of any shape, and the depressions 702 have a profile corresponding to the profile of the press head 700. Also, as shown in the drawings, the side of the press head 700 that applies single-point or multi-point pressure is shown as hemispherical, but the present invention is not limited thereto. Other embodiments may have different shapes such as strips, boxes, matrices, polygons, irregular shapes, etc.

[0021] In some embodiments, indentation bonding may be performed by applying pressure to the surface of the thermal interface material 106 at a temperature of 0° C. or higher (e.g., 5° C., 10° C., 15° C., 20° C., 25° C., 30° C., 35° C., 40° C., or a temperature of 40° C. or higher), with the applied force being 0.1 grams-force per square millimeter (gf / mm 2 ) and maintained for 0.1 seconds or more (such as 0.5 seconds, 1 second, 5 seconds, 10 seconds, 15 seconds, 20 seconds, 25 seconds, 30 seconds, 45 seconds, 1 minute, or 1 minute or more) to secure the thermal interface material 106 onto the outermost metal layer 1042. In some embodiments, a multi-point pressure is applied to the thermal interface material 106 during impression bonding, with the force applied at each point being 0.1 gram-force per square millimeter (gf / mm 2 ) (e.g., 0.5 grams-force per square millimeter (gf / mm 2 ), gram force per square millimeter (gf / mm 2 ), 5 grams-force per square millimeter (gf / mm 2 ) etc.

[0022] In some embodiments, the thermal interface material 106 can include at least one of a phase change material, a metal alloy, and any other suitable thermal interface material. In some embodiments, the thermal interface material can include an indium-based alloy. In this disclosure, the term "indium-based alloy" as used herein refers to an alloy that includes at least indium. The indium-based alloy is formed from (1) indium and (2) at least one of Bi, Sn, and Ag, and can be, for example, an indium-bismuth alloy, an indium-bismuth-tin alloy, an indium-tin alloy, or an indium-silver alloy. In some embodiments, the indium-based alloy includes at least one of: 30-35 wt% Bi, 15-18 wt% Sn, and balance In, and having a melting point of 55-65° C.; 30-35 wt% Bi, and balance In, and having a melting point of 70-75° C.; 52-60 wt% Bi, 15-18 wt% Sn, and balance In, and having a melting point of 80-85° C.; 48-50 wt% Sn, and balance In, and having a melting point of 110-120° C.; and 0.1-15 wt% Ag, and balance In, and having a melting point of 140-280° C. In some embodiments, the thermal interface material is pure indium and has a melting point of 150-160° C.

[0023] As shown in FIG. 4 , in one embodiment, a heat sink 108 is provided. In some embodiments, the heat sink 108 can be a heat-dissipating metal lid and / or cooling fins, although the present disclosure is not limited thereto. Any type and shape of heat dissipation device (such as a heat pipe, a cooling fan, a water-cooled circulating heat dissipation element, or other suitable heat dissipation element) can be selected according to actual requirements. As shown in the drawing, in an embodiment, the heat sink 108 is a heat-dissipating metal lid having a recess 108C for accommodating the chip 104.

[0024] In some embodiments, the recess 108C is located on a side of the heat sink 108 adjacent to the chip 104 (the downward-facing side of the heat sink 108 in FIG. 4 ), and the lateral width W1 of the recess 108C is greater than the lateral width W2 of the chip 104 so that the chip 104 is accommodated within the recess 108C when the heat sink 108 and the chip 104 are pressed together ( FIG. 4 ). In some embodiments, the material of the heat sink 108 can include a metal and / or a metal alloy, e.g., Cu, Al, Co, Ni, nickel-plated copper, combinations thereof, or any suitable metal material. In other embodiments, the heat sink 108 can be made of an alloy, a composite material such as silicon carbide, aluminum nitride (AlN), graphite, or a combination thereof.

[0025] In one embodiment, the heat sink 108 has a surface 108S facing the backside 104S of the chip 104. In one embodiment, the surface 108S of the heat sink 108 (the downward-facing surface of the heat sink 108 in FIG. 4 ) is located on the recess 108C of the heat sink 108. In one embodiment, the heat sink 108 selectively includes a metal layer 1080 on the surface 108S and an outermost metal layer 1082 on the metal layer 1080. Specifically, the outermost metal layer 1082 is located on the side of the metal layer 1080 away from the heat sink 108. In some embodiments, the metal layer 1080 and the outermost metal layer 1082 are configured to enhance the heat dissipation performance of the package structure 100 and reduce the thermal impedance of the package structure 100, although the present disclosure is not limited thereto.

[0026] In some embodiments, the metal layer 1080 can include at least one of Au, Ag, Cu, Ti, Ti / Ni, Ni, and W. In some embodiments, the thickness of the metal layer 1080 can be 0.001 μm to 10 μm (e.g., 0.5 μm to 1.6 μm). In some embodiments, the outermost metal layer 1082 can include at least one of Au, Ag, Cu, Rh, Ir, Pd, Pt, and any suitable metal material and have a thickness of 0.001 μm to 10 μm (e.g., 0.1 μm to 2 μm). In some embodiments, methods for forming the metal layer 1080 and the outermost metal layer 1082 can include sputtering, evaporation, electroplating, or any suitable deposition process.

[0027] 4 , in one embodiment, the heat sink 108 is bonded to the chip 104 such that the thermal interface material 106 is disposed between the chip 104 and the heat sink 108. In one embodiment, an adhesive 110 is applied onto the substrate 102, and then the bottom surface 108B of the heat sink 108 is bonded to the substrate 102 by the adhesive 110, such that the heat sink 108 is in direct contact with the thermal interface material 106, and the thermal interface material 106 is in direct contact with both the chip 104 and the heat sink 108 simultaneously. The thermal interface material 106 is then melted by a hot-press process 800, which simultaneously soft-bakes the adhesive 110 (i.e., turns the adhesive 110 into a partially cured adhesive 110C). In this way, the process can be simplified, and production costs and time can be reduced.

[0028] In one embodiment, the hot pressing process 800 involves applying a pressure of 1 gram force per square centimeter (gf / cm ) to the heat sink 108 in the process chamber at a temperature of 50° C. or higher (e.g., 135° C., 145° C., 155° C., 165° C., etc.) for 2 seconds to 10 minutes (e.g., 5 seconds, 10 seconds, 20 seconds, 30 seconds, 45 seconds, 1 minute, 3 minutes, 5 minutes, etc.). 2) or more (e.g., 55 grams-force / cm 2 , 900 grams-force / cm 2 , 3700 grams-force / cm 2 , etc.). The process chamber for performing the hot pressing process 800 may be a pressurized or vacuum process chamber. A pressurized process chamber refers to a process chamber with a chamber pressure of 1 atmosphere or more. A vacuum process chamber refers to a process chamber with a chamber pressure of 1 atmosphere or less. Performing the hot pressing process 800 in a pressurized or vacuum process chamber can effectively remove residual gases from the thermal interface material 106, thereby reducing the possibility of void formation between the thermal interface material 106 and the chip 104 and between the thermal interface material 106 and the heat sink 106 and increasing the coverage of the thermal interface material 106 on the chip 104 (e.g., 90% or more, 95% or more, or 99% or more). This approach helps improve the reliability and heat dissipation performance of the package structure 100. As used herein, the term "coverage" refers to the ratio of the projected area of ​​the thermal interface material 106 on the chip 104 projected onto the surface 108S of the heat sink 108 by ultrasound or X-ray after the packaging process is complete to the projected area of ​​the chip 104 projected onto the surface 108S of the heat sink 108. Generally, a higher coverage indicates fewer voids being created in the thermal interface material 106.

[0029] 5 is a cross-sectional view of a package structure according to some embodiments. The package structure 100 includes a substrate 102, a chip 104 disposed on the substrate 102, a heat sink 108 disposed on the substrate 102, and a thermal interface material 106 disposed between the chip 104 and the heat sink 108. The chip 104 has a back surface 104S away from the substrate 102. The heat sink 108 has a front surface 108S facing the back surface 104S of the chip 104. No organic adhesive is present between the chip 104 and the heat sink 108. In one embodiment, the thermal interface material 106 is in direct contact with an outermost metal layer 1042 of the chip 104 and an outermost metal layer 1082 of the heat sink 108.

[0030] Furthermore, as shown in FIG. 5 , the absence of an organic adhesive between the chip 104 and the heat sink 108 avoids the risk of solid residues of the organic adhesive creating voids at the bonding interface, further improving the reliability and heat dissipation performance of the package structure 100. Therefore, in this embodiment, heat generated during operation of the chip 104 can be directly transferred to the heat sink 108 via the thermal interface material 106. In contrast, in conventional technologies, because an organic adhesive (e.g., a fixing adhesive, flux, etc.) exists between the chip and the heat sink, the heat dissipation performance may be affected by the properties of the organic adhesive itself. Solid residues from the organic adhesive may remain at the bonding interface and form voids. This may prevent the thermal interface material from completely adhering to the chip and the heat sink, leading to reduced heat dissipation performance.

[0031] 6-8 are cross-sectional views of various stages in the fabrication of a package structure according to another embodiment. Note that some processes or devices are the same or similar to those described in the above-described embodiment, and therefore reference numbers and / or letters may be repeated. Compared to the above-described embodiment in which the thermal interface material 106 is disposed on the chip 104, the thermal interface material 106 in this embodiment is first disposed on the heat sink 108 by indentation bonding.

[0032] 6, in some embodiments, a heat sink 108 is provided. In this embodiment, the heat sink 108 is a heat-dissipating metal lid, so the heat sink 108 has a recess 108C for accommodating the chip 104, but the present invention is not limited thereto. According to actual requirements, any type and shape of heat dissipation device (such as a heat pipe, a cooling fan, a water-cooled circulating heat dissipation element, or other suitable heat dissipation element) can be selected.

[0033] As shown in FIGS. 7-8, the thermal interface material 106 is disposed on the heat sink 108. The thermal interface material 106 is disposed on the heat sink 108 by indentation bonding. Specifically, the downward arrows shown in FIGS. 7-8 represent the direction of applied pressure. By applying pressure to the thermal interface material 106 (e.g., using a press head 700), an indentation 702 is formed on the thermal interface material 106 at the location where the pressure is applied. The applied pressure forms a diffusion bond between the thermal interface material 106 and the chip 104, fixing the thermal interface material 106 onto the chip 104 and achieving temporary positioning. This prevents the thermal interface material from shifting before the heat sink 108 (as shown in FIG. 4) and the chip 104 are pressed together, eliminating the need for an organic adhesive application step. In FIG. 7, the press head 700 is used to apply a single point of pressure to the thermal interface material 106, forming the indentation 702. In FIG. 8 , two press heads 700 are used to apply multi-point pressure to the thermal interface material 106. Although only single-point and two-point indentations are shown in the drawings, the present invention is not limited thereto. In other embodiments, single-point or multi-point pressure can be applied to any position on the surface of the thermal interface material 106 to form single-point, two-point, or three-point depressions on the thermal interface material 106, depending on actual needs. For example, in FIGS. 7-8 , single-point or multi-point pressure is applied to the thermal interface material 106 (e.g., using press heads 700) in a direction toward the surface of the outermost metal layer 1082 of the heat sink 108. Also, while the press heads 700 and depressions 702 have circular profiles as shown in the drawings, the present invention is not limited thereto. In other embodiments, the press heads 700 may have any shape of profile, and the depressions 702 have a profile corresponding to the profile of the press heads 700.

[0034] In some embodiments, indentation bonding may be performed by applying pressure to the surface of the thermal interface material 106 at a temperature of 0° C. or above, with the applied force being 0.1 grams-force per square millimeter (gf / mm 2) and maintained for 0.1 seconds or more to secure the thermal interface material 106 onto the outermost metal layer 1042. In some embodiments, a multi-point pressure is applied to the thermal interface material 106 during impression bonding, with the force applied at each point being 0.1 gram-force per square millimeter (gf / mm 2 ) is greater than.

[0035] 7-8 continue from FIGS. 4-5 and illustrate that, in one embodiment, the heat sink 108 is bonded to the chip 104 such that a thermal interface material is disposed between the chip 104 and the heat sink 108. In one embodiment, an adhesive 110 is applied to the substrate 102, and then the bottom surface 108B of the heat sink 108 is bonded to the substrate 102 by the adhesive 110, so that the heat sink 108 is in direct contact with the thermal interface material 106, and the thermal interface material 106 is in direct contact with both the chip 104 and the heat sink 108 simultaneously. The thermal interface material 106 is then melted by a hot pressing process 800, which simultaneously soft-bakes the adhesive 110 (i.e., turns the adhesive 110 into a partially cured adhesive 110C). This simplifies the process and reduces both production costs and production time.

[0036] 9-13 are cross-sectional views of various configurations of packaging structures 200, 300, 400, 500, 600 according to other embodiments.

[0037] In some embodiments, the package structure 200 shown in FIG. 9 is similar to the package structure 100 shown in FIG. 5 , except that the heat sink 108 bonded to the substrate is a heat-dissipating metal lid, and after the heat sink 108 is bonded to the chip 104, another heat sink 108F, which is a cooling fin, is disposed on the heat-dissipating metal lid. This further increases the heat dissipation area through the cooling fin. Specifically, in one embodiment, after the heat sink 108 is bonded to the chip 104, a thermal interface material 106A is disposed on the surface of the heat sink 108 away from the chip 104, and then the heat sink 108F is disposed on the thermal interface material 106A. The thermal interface material 106A can also be disposed on the heat sink 108 using indentation bonding, allowing the thermal interface material 106A to form a diffusion bond on the surface of the heat sink 108 away from the chip 104. Then, after placing the heat sink 108F on the thermal interface material 106A, a hot pressing process 800 (shown in FIG. 4) can be used to melt the thermal interface material 106A and fill the contact gap between the heat sink 108 and 108F. In some embodiments, the package structure 300 shown in FIG. 10 is similar to the package structure 100 shown in FIG. 5, except that the heat sink 108 is a cooling fin. The cooling fin has a larger heat dissipation area than the heat dissipation metal lid, and therefore can conduct the heat generated during operation of the chip 104 faster and achieve better heat dissipation performance.

[0038] In some embodiments, the package structure 400 shown in FIG. 11 is similar to the package structure 100 shown in FIG. 5 , except that there are multiple chips 104 disposed on the substrate 102, and a single thermal interface material 106 covers all of the chips 104. Covering all of the chips 104 with a single thermal interface material 106 simplifies the process. Note that although FIG. 11 shows only two chips 104, the present invention is not limited thereto. In other embodiments, various numbers of chips, such as three, four, or more chips 104, can be disposed on the substrate 102 depending on actual requirements.

[0039] 12 is similar to the package structure 400 shown in FIG. 11 , except that rather than using a single thermal interface material 106 to cover all of the chips 104 as shown in FIG. 11 , the thermal interface material 106 includes multiple separate segments, each segment corresponding one-to-one to a respective chip 104. By having each segment of the thermal interface material 106 correspond one-to-one to each chip 104, it is possible to tailor the thermal interface material 106 to the specific needs of each chip 104, such as variations in material properties or operating temperature. Additionally, because a single thermal interface material 106 is not used to cover all of the chips, the amount of thermal interface material 106 is saved, which can reduce manufacturing costs.

[0040] In some embodiments, the package structure 600 shown in FIG. 13 is similar to the package structure 500 shown in FIG. 12 , except that both the metal layer 1080 and the outermost metal layer 1082 of the heat sink 108 include separate segments, with each segment corresponding to a respective chip 104 and each segment of the outermost metal layer 1082 corresponding to each chip 104. Therefore, by having each segment of the thermal interface material 106 correspond to each chip 104, it is possible to tailor the thermal interface material 106 to the specific needs of each chip 104, such as variations in material properties or operating temperature. Furthermore, because a single thermal interface material 106 is not used to cover all chips, the amount of thermal interface material 106 is saved, thereby reducing manufacturing costs. While FIG. 13 illustrates each segment of the metal layer 1080 and each segment of the outermost metal layer 1082 corresponding to each chip 104, the present disclosure is not limited thereto. The heat sink 108 may include a single outermost metal layer 1082 (such as the outermost metal layer 1082 shown in FIGS. 5, 9-12), separate segments of the metal layer 1080 separated from one another (such as the metal layer 1080 shown in FIG. 13), and segments of the metal layer 1080 corresponding one-to-one to each chip 104. In yet another embodiment, the heat sink 108 may include a single metal layer 1080 (such as the metal layer 1080 shown in FIGS. 5, 9-12), separate segments of the outermost metal layer 1082 separated from one another (such as the outermost metal layer 1082 shown in FIG. 13), and segments of the outermost metal layer 1082 corresponding one-to-one to each chip 104.

[0041] 11 to 13, the heat sink 108 is shown as a heat-dissipating metal lid, but the present invention is not limited thereto. The heat sink 108 may also be a cooling fin. Furthermore, another heat sink 108F may be disposed on the heat sink 108 (as shown in FIG. 9), and the heat sink 108F may also be a cooling fin to further increase the heat dissipation area and achieve better heat dissipation performance.

[0042] In some embodiments, the outermost metal layer 1042, 1082 may be partially or fully fused to the thermal interface material 106, depending on the thickness of the outermost metal layer 1042, 1082. After packaging is complete, heat generated during chip operation causes the thermal interface material 106 to react with the outermost metal layer 1042, 1082 at the bond between the thermal interface material 106 and the outermost metal layer 1042, 1082. Therefore, when the thickness of the outermost metal layer 1042, 1082 is relatively thin (e.g., Au with a thickness of 0.1 μm or less), the outermost metal layer 1042, 1082 may be completely fused to the thermal interface material 106, and when the thickness of the outermost metal layer 1042, 1082 is relatively thick, only a portion of the outermost metal layer 1042, 1082 is fused to the thermal interface material 106, so that other portions of the outermost metal layer 1042, 1082 that are not fused to the thermal interface material 106 can still be observed.

[0043] Hereinafter, several examples and comparative examples are provided to specifically illustrate the effects that can be achieved by joining a metal layer and a thermal interface material in the embodiments of the present disclosure.

[0044] Comparative Example 1: Direct placement of thermal interface material on the chip

[0045] In Comparative Example 1, a chip 104 having a metal layer 1040 (made of an Al / Ti / NiV material) and an outermost metal layer 1042 (made of an Au material) was provided, and 100 square millimeters (10 mm x 10 mm) of thermal interface material 106 (made of a 100 wt% indium material) was placed directly on the outermost metal layer 1042 without using any organic adhesive to obtain Comparative Example 1. Because the step of applying pressure to the thermal interface material was not performed, the force of applying pressure is represented in Table 1 below as 0.0 grams force per square millimeter (gf / mm 2 )

[0046] Examples 1-7: Placing thermal interface material on chips by impression bonding

[0047] In Examples 1 to 7, a chip 104 having a metal layer 1040 (made of an Al / Ti / NiV material) and an outermost metal layer 1042 (made of an Au material) was first provided, and a 100 square millimeter (10 mm x 10 mm) thermal interface material 106 (made of a 100 wt% indium material) was placed on the outermost metal layer 1042 by impression bonding as a bonding step without using any organic adhesive. Specifically, pressure was applied to two points on the thermal interface material 106 by a press head 700 in a temperature environment of 18 to 20°C, and the thermal interface material 106 and the outermost metal layer 1042 of the chip 104 were diffusion bonded at the pressure-applied points, thereby obtaining Examples 1 to 7. The force applied to each point during the two-point pressurization step in Examples 1 to 7 was 1.0 gram-force per square millimeter (gf / mm 2 ), 1.6 grams-force per square millimeter (gf / mm 2 ), 2.5 grams-force per square millimeter (gf / mm 2 ), 3.3 grams-force per square millimeter (gf / mm 2 ), 4.3 grams-force per square millimeter (gf / mm 2 ), 5.0 grams-force per square millimeter (gf / mm 2 ), and 5.8 grams-force per square millimeter (gf / mm 2 ) was.

[0048] Bonding Test

[0049] After completing the manufacturing of Comparative Example 1 and Examples 1 to 7, the chips 104 bonded with the thermal interface materials 106 of Comparative Example 1 and Examples 1 to 7 were attached to the turntable of a spin tool. The turntable was rotated at a set rotation speed for 20 seconds, and then the chips 104 were observed to see if the thermal interface material 106 had fallen off. The results of the bonding test are shown in Table 1. In Table 1, "bonded" indicates that the thermal interface material 106 was still bonded to the chip 104 after rotation, and "fallen off" indicates that the thermal interface material 106 had fallen off from the chip 104 after rotation.

[0050] [Table 1]

[0051] According to the results shown in Table 1, in Comparative Example 1, the thermal interface material 106 is not fixed to the chip 104 by impression bonding, so the thermal interface material 106 peels off from the chip 104 at a rotation speed of 10 rpm. In comparison, in Examples 1 to 4, as the force applied to each point during the two-point pressurization step increases (up to 1.0 gram-force per square millimeter (gf / mm 2 ) to 3.3 gram-force per square millimeter (gf / mm 2 )), improving the bond between the thermal interface material 106 and the chip 104. In addition, in Examples 5 to 7, the force applied to each point during the two-point pressing step was 4.3 grams-force per square millimeter (gf / mm 2 ), the thermal interface material 106 remained firmly bonded to the chip 104 even at a high rotation speed of 2,000 rpm. These results confirmed that fixing the thermal interface material 106 by impression bonding effectively achieved the desired positioning of the thermal interface material 106.

[0052] In summary, the present disclosure provides a package structure and packaging method that does not require an organic adhesive between the chip and the heat sink. By bonding a thermal interface material to the chip or heat sink by impression bonding before compressing the chip and the heat sink, the thermal interface material is fixed in direct contact with the chip or the heat sink, achieving temporary positioning. This prevents the thermal interface material from shifting out of position before the chip and the heat sink are compressed, eliminating the need for the organic adhesive used in existing technologies. This reduces the costs of obtaining and disposing of organic adhesive and achieves better heat dissipation. Furthermore, the risk of solid organic adhesive residues causing voids at the bonding interface is avoided, further improving the reliability and heat dissipation performance of the package structure.

[0053] The foregoing has outlined features of some embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use this disclosure as a basis for designing or modifying other processes and structures to carry out the same purposes and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure. [Explanation of symbols]

[0054] 100, 200, 300, 400, 500, 600 package structure 102 Circuit Board 104 chips 104S back 1040 metal layer 1042 Outermost metal layer 106, 106A thermal interface material 108, 108F heat sink 108B Bottom 108C Recess 108S surface 1080 metal layer 1082 Outermost metal layer 110, 110C adhesive 700 Press Head 702 Indentation 800 Hot Press Process W1, W2 width

Claims

1. A substrate; a chip disposed on the substrate and having a backside remote from the substrate; a heat sink disposed on the substrate and having a surface facing the backside of the chip; a thermal interface material disposed between the chip and the heat sink; A package structure in which there is no organic adhesive between the chip and the heat sink.

2. 2. The package structure of claim 1, wherein the chip includes a metal layer on the backside, the metal layer including at least one of Al / Ti / NiV, Al / Cr / NiV, Al / NiV, Al / W, Ti / NiV, TiW, WTi, WTi / Ti, Cr / NiV, Cr, W, Ti / Ni, Al / Ti / Ni, Ti, W / Ni, W / NiV, WTi / Ni, WTi / NiV, TiW / Ni, and TiW / NiV, and having a thickness of 0.001 to 10 μm.

3. 3. The package structure of claim 2, wherein the chip further comprises an outermost metal layer adjacent to the thermal interface material, the outermost metal layer comprising at least one of Au, Ag, Cu, Rh, Ir, Pd, and Pt, and having a thickness of 0.001 to 10 μm.

4. The package structure of claim 3 , wherein the outermost metal layer of the chip is configured to be at least partially fused to the thermal interface material.

5. 2. The package structure of claim 1, wherein the heat sink comprises a metal layer of the substrate, the metal layer comprising at least one of Au, Ag, Cu, Ti, Ti / Ni, Ni, and W, and having a thickness of 0.001 to 10 μm.

6. The package structure according to claim 5 , wherein the number of the chips is plural, and the metal layer of the heat sink includes a plurality of isolated segments that correspond to the chips and are isolated from each other.

7. 6. The package structure of claim 5, wherein the heat sink further comprises an outermost metal layer adjacent to the thermal interface material, the outermost metal layer comprising at least one of Au, Ag, Cu, Rh, Ir, Pd, and Pt, and having a thickness of 0.001 to 10 μm.

8. The package structure according to claim 7 , wherein the number of the chips is plural, and the outermost metal layer of the heat sink includes a plurality of isolated segments that correspond to the chips and are isolated from each other.

9. The package structure of claim 7 , wherein the outermost metal layer of the heat sink is configured to be at least partially fused to the thermal interface material.

10. The package structure according to claim 1 , wherein the number of the chips is plural, and the thermal interface material includes a plurality of separated segments corresponding to the chips and separated from each other.

11. The thermal interface material comprises an indium-based alloy, the indium-based alloy comprising: 30-35 wt% Bi, 15-18 wt% Sn, and the balance In, and having a melting point of 55-65°C; 30-35 wt % Bi, balance In, and having a melting point of 70-75°C; 52-60 wt% Bi, 15-18 wt% Sn, and the balance In, and having a melting point of 80-85°C; 48-50 wt % Sn, balance In, and having a melting point of 110-120°C; 2. The package structure of claim 1, comprising at least one of an alloy containing 0.1-15 wt % Ag and the balance In, and having a melting point of 140-280°C.

12. 2. The package structure of claim 1, wherein the thermal interface material is pure indium and has a melting point of 150-160°C.

13. 10. The package structure of claim 1, wherein the coverage of the thermal interface material on the chip is 90% or more.

14. The package structure according to claim 1 , wherein the heat sink is a heat-dissipating metal lid and / or a cooling fin.

15. 10. The package structure of claim 1, wherein the material of the heat sink comprises at least one of Cu, Al, Co, Ni, nickel-plated copper, alloys, silicon carbide, aluminum nitride, graphite, or a combination thereof.

16. placing a chip on the substrate with its backside facing away from the substrate; providing a heat sink having a surface facing the backside of the chip; disposing a thermal interface material on the chip or the heat sink by impression bonding; and bonding the heat sink to the chip such that a thermal interface material is disposed between the chip and the heat sink.

17. 17. The packaging method of claim 16, wherein the impression bonding comprises applying a single point pressure to the thermal interface material to secure the thermal interface material to the chip or the heat sink.

18. 17. The packaging method of claim 16, wherein the impression bonding comprises applying multi-point pressure to the thermal interface material to secure the thermal interface material to the chip or the heat sink.

19. The indentation bonding is performed by applying a force of 0.1 gf / mm to the thermal interface material at a temperature of 0°C or higher. ２ 17. The packaging method of claim 16, further comprising applying the above force to secure the thermal interface material to the chip or the heat sink.

20. 17. The packaging method of claim 16, wherein bonding the heat sink to the chip includes performing a hot pressing process to achieve a coverage of the molten thermal interface material on the chip of 90% or more.

21. The hot pressing process step involves applying 1 gf / cm to the heat sink at a temperature of 50° C. or higher for 2 seconds to 10 minutes in a process chamber under pressure or vacuum. ２ 21. The packaging method of claim 20, including the step of applying the above force.

22. 17. The packaging method of claim 16, further comprising forming a metal layer on the backside of the chip before placing the thermal interface material on the chip.

23. 17. The packaging method of claim 16, wherein before placing the thermal interface material on the chip, the method further comprises forming an outermost metal layer on the metal layer on the backside of the chip.

24. 24. The packaging method of claim 23, wherein the outermost metal layer of the chip is at least partially fused to the thermal interface material.

25. 17. The packaging method of claim 16, wherein before disposing the thermal interface material on the heat sink, the method further comprises forming a metal layer on the surface of the heat sink.

26. 17. The packaging method of claim 16, wherein before disposing the thermal interface material on the heat sink, the method further comprises forming a metal layer on the surface of the heat sink.

27. 27. The packaging method of claim 26, wherein the outermost metal layer of the heat sink is at least partially fused to the thermal interface material.

28. 17. The packaging method of claim 16, wherein the heat sink is a heat-dissipating metal lid, and after bonding the heat sink to the chip, the packaging method further comprises arranging a cooling fin on the heat-dissipating metal lid.

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