High-speed serial interface and data transmission method

Abstract

The embodiments of the present application relate to the field of chip technology, and provide a high-speed serial interface and a data transmission method, so as to reduce the power consumption of the physical layer circuit of the high-speed serial interface when service data is not being transmitted. The high-speed serial interface includes a physical layer circuit of a transmitting end, a monitor, a clock gating circuit, a control bit stream generating circuit, and a random bit stream generating circuit, and further, the monitor is configured to indicate to the clock gating circuit to stop sending a clock signal to a partial module in the physical layer circuit of the transmitting end when service data is not being transmitted. The control bit stream generating circuit transmits a first control bit stream through the serializer / deserializer to indicate that the transmitting end has turned off the partial module in the physical layer circuit of the transmitting end, or to indicate that the transmitting end turns off the partial module in the physical layer circuit of the transmitting end, or to indicate to the receiving end to turn off the partial module in the physical layer circuit of the receiving end. The random bit stream generating circuit transmits a random bit stream. The embodiments of the present application are used in the process of reducing the power consumption of the physical layer circuit.

Description

[Technical field]

[0001] This application claims priority to Chinese Patent Application No. 202111679102.7, entitled “HIGH-SPEED SERIAL INTERFACE AND DATA TRANSMISSION METHOD,” filed with the State Intellectual Property Office of the People's Republic of China on December 31, 2021, which is incorporated herein by reference in its entirety.

[0002] TECHNICAL FIELD The embodiments of the present application relate to the field of chip technology, and in particular to high-speed serial interfaces and data transmission methods. [Background technology]

[0003] After the rate of high-speed serial interface increases to 64GT / s or more, the bit error rate becomes high. Forward error correction (FEC) technique needs to be used at the transmitting end to encode the data to be transmitted. In addition, at the receiving end, FEC decoding and error correction needs to be performed on the data output by the Receiver (RX) circuit of the Serializer and Deserializer (SerDes). In addition, to ensure that the number of 0s and 1s in the data sent by the transmitting end to the SerDes are balanced, a scrambler needs to be used to scramble the data obtained by FEC encoding to ensure that the number of 0s and 1s in the data are balanced.

[0004] In a conventional physical layer device, such as a Peripheral Component Interface Express (PCIe), when no service packets are sent on the link within a short period of time, the sending end needs to insert an idle bit stream in the sending direction for data padding to ensure that the SerDes at the sending end can send data continuously. However, in this case, when the sending end sends the idle bit stream, high power consumption occurs at the sending end and the receiving end, and the power consumption of the device is high. Summary of the Invention

[0005] The embodiments of the present application provide a high-speed serial interface and a data transmission method to reduce the power consumption of the physical layer circuit of the high-speed serial interface when service data is not being transmitted. [Means for solving the problem]

[0006] In order to achieve the aforementioned objectives, the following technical solutions are used in the embodiments of this application.

[0007] According to a first aspect, a high-speed serial interface is provided. The high-speed serial interface includes a physical layer circuit of a transmitting end, a monitor, a clock gating circuit, a control bit stream generating circuit, a random bit stream generating circuit, and a serializer / deserializer. The monitor is configured to indicate to the clock gating circuit that when the transmitting end is not transmitting service data, the monitor stops transmitting a clock signal to a partial module in the physical layer circuit of the transmitting end. The clock gating circuit is configured to stop transmitting a clock signal to the partial module in the physical layer circuit of the transmitting end. The control bit stream generating circuit is configured to transmit a first control bit stream through the serializer / deserializer when it is determined that the clock gating circuit has stopped transmitting the clock signal, and the first control bit stream is used to indicate that the transmitting end has turned off the partial module in the physical layer circuit of the transmitting end, or the first control bit stream is used to indicate that the transmitting end turns off the partial module in the physical layer circuit of the transmitting end, or the first control bit stream is used to indicate to the receiving end to turn off the partial module in the physical layer circuit of the receiving end. The random bit stream generating circuit is configured to transmit a random bit stream to the serializer / deserializer.

[0008] Therefore, when there is no need to transmit service data currently, the high-speed serial interface may stop transmitting a clock signal to the partial module in the physical layer circuit of the transmitting end, so that the partial module in the physical layer circuit of the transmitting end is in a non-driving state. This can reduce the power consumption of the physical layer circuit of the transmitting end. In addition, the control bit stream generating circuit may further transmit a first control bit stream to indicate that the physical layer circuit needs to be turned off. In this way, the first control bit stream is equivalent to an on / off indication indicating that the receiving end may also turn off the partial module in the physical layer circuit of the receiving end without receiving service data. In order to allow the clock and data recovery CDR circuit of the serializer / deserializer to remain in a locked state to avoid errors, a random bit stream is further transmitted after the first control bit stream is transmitted. Neither the first control bit stream nor the random bit stream passes through the partial module in the physical layer circuit of the transmitting end nor the partial module in the physical layer circuit of the receiving end. In this way, both the physical layer circuit of the transmitting end and the physical layer circuit of the receiving end can perform the function of reducing power consumption.

[0009] In one possible design, the partial module in the physical layer circuit of the transmitting end includes at least one of a forward error correction FEC encoding circuit or a scrambling circuit, and the partial module in the physical layer circuit of the receiving end includes at least one of an FEC decoding circuit or a descrambling circuit. In the physical layer circuit of the transmitting end, the FEC circuit and the scrambling / descrambling circuit consume power. Therefore, when service data is not currently being transmitted, the FEC circuit and the scrambling / descrambling circuit can be turned off to reduce power consumption. Of course, in this application, the partial modules in the physical layer circuit of the transmitting end that need to be turned off are not limited to the FEC encoding circuit and the scrambling circuit, and the partial modules in the physical layer circuit of the receiving end are also not limited to the FEC decoding circuit and the descrambling circuit. Other power consuming circuits may be further included. For example, the partial module in the physical layer circuit of the transmitting end may further include a data distribution circuit, and the partial module in the physical layer circuit of the receiving end may further include a symbol lock circuit, a deskew circuit, etc.

[0010] In one possible design, the high-speed serial interface further includes a data link layer at the transmitting end, and the monitor is specifically configured to monitor whether the data link layer at the transmitting end transmits service data to the physical layer circuit of the transmitting end, and when it is determined that the data link layer at the transmitting end does not transmit service data to the physical layer circuit of the transmitting end, determine that the transmitting end is not transmitting service data. Specifically, the data link layer at the transmitting end not transmitting service data is equivalent to the transmitting end not currently transmitting service data, and a partial module in the physical layer circuit of the transmitting end may be turned off to reduce power consumption.

[0011] In one possible design, the monitor is further configured to: send a first signal to the control bitstream generating circuit when it is determined that the clock gating circuit has stopped sending the clock signal to the partial module in the physical layer circuit of the transmitting end, the first signal being used to indicate to the control bitstream generating circuit to send the first control bitstream; and send a second signal to the random bitstream generating circuit when it is determined that the control bitstream generating circuit has completed sending the first control bitstream, the second signal being used to indicate to the random bitstream generating circuit to send the random bitstream. Specifically, in the present application, when it is determined that the service data is not being sent, the monitor may trigger the bitstream generating circuit to send the first control bitstream, and may further trigger the random bitstream generating circuit to send the random bitstream. None of the bitstreams pass through the partial module in the physical layer circuit of the transmitting end. Of course, the monitor may not alternatively trigger the sending of the two bitstreams, and a control circuit other than the monitor may alternatively monitor the state of each circuit. Upon determining that service data is not being transmitted, the control circuit may indicate to the bitstream generation circuit to transmit the first control bitstream and may further indicate to the random bitstream generation circuit to transmit a random bitstream.

[0012] In one possible design, the monitor is further configured, as indicated by the clock gating circuit, to send a clock signal to the partial module in the physical layer circuit of the transmitting end when the transmitting end resumes transmitting the service data, the clock gating circuit is further configured to send a clock signal to the partial module in the physical layer circuit of the transmitting end, the random bit stream generation circuit is further configured to stop transmitting the random bit stream when it is determined that the clock gating circuit has started transmitting the clock signal, the control bit stream generation circuit is further configured to send a second control bit stream via the serializer / deserializer when it is determined that the transmitting end resumes transmitting the service data, the second control bit stream is used to indicate that the transmitting end has turned on the partial module in the physical layer circuit of the transmitting end, or the second control bit stream is used to indicate that the transmitting end turns on the partial module in the physical layer circuit of the transmitting end, or the second control bit stream is used to indicate the receiving end to turn on the partial module in the physical layer circuit of the receiving end, and the physical layer circuit of the transmitting end is configured to start transmitting the service data via the serializer / deserializer.

[0013] Specifically, when transmission of the service data is resumed, the monitor may be further configured to further indicate to the random bit stream generating circuit to stop transmitting the random bit stream and to indicate to the control bit stream generating circuit to send a second control bit stream, which may be used to indicate to turn on a partial module in the physical layer circuit of the receiving end so that the physical layer circuit of the receiving end can resume transmission of the service data.

[0014] In one possible design, the first control bitstream includes multiple repeated bitstream identifiers, a first marker end identifier, and a first bitstream content, where the first bitstream content is used to indicate that the transmitting end has turned off a partial module in the physical layer circuit of the transmitting end, or the first control bitstream is used to indicate the transmitting end to turn off a partial module in the physical layer circuit of the transmitting end, or the first control bitstream is used to indicate the receiving end to turn off a partial module in the physical layer circuit of the receiving end, and the first marker end identifier is used to indicate the position of an end bit of the first control bitstream. The second control bit stream includes a plurality of repeating bit stream identifiers, a second marker end identifier, and a second bit stream content, the second bit stream content is used to indicate that the transmitting end has turned on a partial module in the physical layer circuit of the transmitting end, or the second control bit stream is used to indicate that the transmitting end turns on a partial module in the physical layer circuit of the transmitting end, or the second control bit stream is used to indicate the receiving end to turn on a partial module in the physical layer circuit of the receiving end, and the second marker end identifier is used to indicate the position of the end bit of the second control bit stream. The random bit stream is used to enable the clock and data recovery CDR circuit of the serializer / deserializer to remain in a locked state, and the random bit stream includes a balanced amount of 0s and 1s. The implementation of the first control bit stream and the second control bit stream is not limited in this application.

[0015] According to a second aspect, a high-speed serial interface is provided. The high-speed serial interface includes a physical layer circuit at a receiving end, a bitstream detection circuit, a clock gating circuit, and a serializer / deserializer. The bitstream detection circuit is configured to receive a first control bitstream via the serializer / deserializer, and the first control bitstream is used to indicate that the transmitting end has turned off a partial module in the physical layer circuit at the transmitting end, or the first control bitstream is used to indicate that the transmitting end turns off a partial module in the physical layer circuit at the transmitting end, or the first control bitstream is used to indicate to the receiving end to turn off a partial module in the physical layer circuit at the receiving end. The bitstream detection circuit is further configured to indicate to the clock gating circuit to stop sending a clock signal to the partial module in the physical layer circuit at the receiving end. The clock gating circuit is configured to stop sending a clock signal to the partial module in the physical layer circuit at the receiving end. The bitstream detection circuit is further configured to receive a random bitstream via the serializer / deserializer.

[0016] In this way, upon receiving the first control bit stream, the receiving end knows that the transmitting end has no service data to transmit, and the receiving end may turn off a partial module in the physical layer circuit of the receiving end to reduce power consumption. In addition, to allow the CDR circuit of the serializer / deserializer of the receiving end to remain in a locked state, the serializer / deserializer of the receiving end may continue to receive a random bit stream after receiving the first control bit stream.

[0017] In one possible design, the partial module in the physical layer circuit of the transmitting end includes at least one of a forward error correction (FEC) encoding circuit or a scrambling circuit, and the partial module in the physical layer circuit of the receiving end includes at least one of an FEC decoding circuit or a descrambling circuit. For the beneficial effects of this design, see the description of the first aspect.

[0018] In one possible design, the high-speed serial interface further includes a data link layer at the receiving end, and the clock gating circuit is specifically configured to stop sending a clock signal to the partial module in the physical layer circuit at the receiving end when it is determined that the interval from the last time that the physical layer circuit at the receiving end transmits service data to the data link layer at the receiving end exceeds a preset time period. When it is determined that the interval from the last time that the physical layer circuit at the receiving end transmits service data to the data link layer at the receiving end exceeds a preset time period, it can be determined that no service data is currently being received and the received service data has been completely transmitted to the data link layer at the receiving end.

[0019] In one possible design, the bitstream detection circuit is further configured to control the serializer / deserializer to receive a second control bitstream, and to indicate to the clock gating circuit to send a clock signal to the partial module in the physical layer circuit of the receiving end when the second control bitstream is used to indicate that the transmitting end has turned on a partial module in the physical layer circuit of the transmitting end, or when the second control bitstream is used to indicate that the transmitting end turns on a partial module in the physical layer circuit of the transmitting end, or when the second control bitstream is used to indicate to the receiving end to turn on a partial module in the physical layer circuit of the receiving end. The clock gating circuit is further configured to send a clock signal to the partial module in the physical layer circuit of the receiving end. The bitstream detection circuit is further configured to send the service data received from the serializer / deserializer to the physical layer circuit of the receiving end. For beneficial effects of this design, please refer to the description of the first aspect.

[0020] In one possible design, the first control bit stream includes multiple repeat marker identifiers, a first marker end identifier, and a first bit stream content, where the first bit stream content is used to indicate that the transmitting end has turned off a partial module in the physical layer circuit of the transmitting end, or the first control bit stream is used to indicate the transmitting end to turn off a partial module in the physical layer circuit of the transmitting end, or the first control bit stream is used to indicate the receiving end to turn off a partial module in the physical layer circuit of the receiving end, and the first marker end identifier is used to indicate the position of an end bit of the first control bit stream. The second control bit stream includes a plurality of repeating marker identifiers, a second marker end identifier, and a second bit stream content, where the second bit stream content is used to indicate that the transmitting end has turned on a partial module in the physical layer circuit of the transmitting end, or the second control bit stream is used to indicate that the transmitting end turns on a partial module in the physical layer circuit of the transmitting end, or the second control bit stream is used to indicate the receiving end to turn on a partial module in the physical layer circuit of the receiving end, and the second marker end identifier is used to indicate a position of an end bit of the second control bit stream. The random bit stream is used to enable the clock and data recovery CDR circuit of the serializer / deserializer to remain in a locked state, and the random bit stream includes a balanced amount of 0s and 1s. The bit stream detection circuit is further configured to discard the random bit stream when the random bit stream is identified. For beneficial effects of this design, please refer to the description of the first aspect.

[0021] According to a third aspect, a data transmission method is provided, which is applied to a high-speed serial interface. The high-speed serial interface includes a physical layer circuit at a transmitting end. The method includes a step in which the transmitting end transmits a first control bit stream when the transmitting end does not transmit service data, and the first control bit stream is used to indicate that the transmitting end has turned off a partial module in the physical layer circuit of the transmitting end, or the first control bit stream is used to indicate that the transmitting end turns off a partial module in the physical layer circuit of the transmitting end, or the first control bit stream is used to indicate the receiving end to turn off a partial module in the physical layer circuit of the receiving end. The transmitting end turns off the partial module in the physical layer circuit of the transmitting end. The transmitting end transmits a random bit stream.

[0022] For the beneficial effects of the third aspect, please refer to the description of the first aspect.

[0023] In one possible design, a partial module in the physical layer circuit at the transmitting end includes at least one of a forward error correction (FEC) encoding circuit or a scrambling circuit, and a partial module in the physical layer circuit at the receiving end includes at least one of an FEC decoding circuit or a descrambling circuit.

[0024] In one possible design, the high-speed serial interface further includes a partial module in a data link layer of the transmitting end, and determining that the transmitting end is not transmitting service data includes determining that the transmitting end is not transmitting service data when the data link layer of the transmitting end is not transmitting service data to the physical layer circuit of the transmitting end.

[0025] In one possible design, the high-speed serial interface further includes a serializer / deserializer, and the method includes a step of the transmitting end sending a second control bit stream when the transmitting end resumes transmitting the service data, the second control bit stream is used to indicate that the transmitting end has turned on a partial module in the physical layer circuit of the transmitting end, or the second control bit stream is used to indicate that the transmitting end turns on a partial module in the physical layer circuit of the transmitting end, or the second control bit stream is used to indicate the receiving end to turn on a partial module in the physical layer circuit of the receiving end. The transmitting end turns on the partial module in the physical layer circuit of the transmitting end. The transmitting end controls the physical layer circuit of the transmitting end to transmit the service data to the serializer / deserializer.

[0026] In one possible design, the first control bitstream includes multiple repeated bitstream identifiers, a first marker end identifier, and a first bitstream content, where the first bitstream content is used to indicate that the transmitting end has turned off a partial module in the physical layer circuit of the transmitting end, or the first control bitstream is used to indicate the transmitting end to turn off a partial module in the physical layer circuit of the transmitting end, or the first control bitstream is used to indicate the receiving end to turn off a partial module in the physical layer circuit of the receiving end, and the first marker end identifier is used to indicate the position of an end bit of the first control bitstream. The second control bit stream includes a plurality of repeating bit stream identifiers, a second marker end identifier, and a second bit stream content, the second bit stream content is used to indicate that the transmitting end has turned on a partial module in the physical layer circuit of the transmitting end, or the second control bit stream is used to indicate that the transmitting end turns on a partial module in the physical layer circuit of the transmitting end, or the second control bit stream is used to indicate the receiving end to turn on a partial module in the physical layer circuit of the receiving end, and the second marker end identifier is used to indicate the position of the end bit of the second control bit stream. The random bit stream is used to enable the clock and data recovery CDR circuit of the serializer / deserializer to be in a locked state, and the random bit stream includes a balanced amount of 0s and 1s.

[0027] According to a fourth aspect, a data transmission method is provided, which is applied to a high-speed serial interface. The high-speed serial interface includes a physical layer circuit at a receiving end. The method includes a step of the receiving end receiving a first control bit stream, the first control bit stream being used to indicate that the transmitting end has turned off a partial module in the physical layer circuit of the transmitting end, or the first control bit stream being used to indicate that the transmitting end turns off a partial module in the physical layer circuit of the transmitting end, or the first control bit stream being used to indicate the receiving end to turn off a partial module in the physical layer circuit of the receiving end. The receiving end turns off the partial module in the physical layer circuit of the receiving end. The receiving end receives a random bit stream.

[0028] For the beneficial effects of the fourth aspect, please refer to the description of the second aspect.

[0029] In one possible design, some modules in the physical layer circuitry at the receiving end include at least one of a forward error correction (FEC) encoding circuit or a scrambling circuit, and a partial module in the physical layer circuitry at the receiving end includes at least one of an FEC decoding circuit or a descrambling circuit.

[0030] In one possible design, the high-speed serial interface further includes a serializer / deserializer, and the method further includes a step of the receiving end controlling the serializer / deserializer to receive a second control bit stream, where the second control bit stream is used to indicate that the transmitting end has turned on a partial module in the physical layer circuit of the transmitting end, or the second control bit stream is used to indicate that the transmitting end turns on a partial module in the physical layer circuit of the transmitting end, or the second control bit stream is used to indicate to the receiving end to turn on a partial module in the physical layer circuit of the receiving end. The receiving end turns on the partial module in the physical layer circuit of the receiving end. The receiving end controls the physical layer circuit of the receiving end to receive the service data transmitted through the serializer / deserializer.

[0031] In one possible design, the first control bit stream includes multiple repeat marker identifiers, a first marker end identifier, and a first bit stream content, where the first bit stream content is used to indicate that the transmitting end has turned off a partial module in the physical layer circuit of the transmitting end, or the first control bit stream is used to indicate the transmitting end to turn off a partial module in the physical layer circuit of the transmitting end, or the first control bit stream is used to indicate the receiving end to turn off a partial module in the physical layer circuit of the receiving end, and the first marker end identifier is used to indicate the position of an end bit of the first control bit stream. The second control bit stream includes a plurality of repeating marker identifiers, a second marker end identifier, and a second bit stream content, the second bit stream content is used to indicate that the transmitting end has turned on a partial module in the physical layer circuit of the transmitting end, or the second control bit stream is used to indicate that the transmitting end turns on a partial module in the physical layer circuit of the transmitting end, or the second control bit stream is used to indicate the receiving end to turn on a partial module in the physical layer circuit of the receiving end, and the second marker end identifier is used to indicate the position of the end bit of the second control bit stream. The random bit stream is used to enable the clock and data recovery CDR circuit of the serializer / deserializer to remain in a locked state, and the random bit stream includes a balanced amount of 0s and 1s. The method further includes discarding the random bit stream when the random bit stream is identified.

[0032] According to a fifth aspect, there is provided a communication apparatus, the communication apparatus including at least one processor, the at least one processor coupled to a memory, the at least one processor configured to read and execute a program stored in the memory, such that the apparatus performs a method corresponding to the third aspect or any one of the possible designs of the third aspect, or performs a method according to the fourth aspect or any one of the possible designs of the fourth aspect.

[0033] According to a sixth aspect, there is provided a chip, coupled to a memory and configured to read and execute program instructions stored in the memory to perform a method corresponding to the third aspect or any one of the possible designs of the third aspect, or to perform a method according to the fourth aspect or any one of the possible designs of the fourth aspect.

[0034] According to a seventh aspect, the present application provides a chip system, which is used in a cloud center. The chip system includes one or more interface circuits and one or more processors. The interface circuits and the processors are interconnected via lines. The interface circuits are configured to receive signals from a memory of the cloud center and transmit signals to the processor. The signals include computer instructions stored in the memory. When the processor executes the computer instructions, the cloud center performs a data transmission method provided in the first aspect or a corresponding possible design of the first aspect.

[0035] According to an eighth aspect, an embodiment of the present application provides a serial interface circuit. The circuit is included in an electronic device, and the device has a function to implement the behavior of the electronic device in any one of the above aspects or possible implementations of the above aspects. The function may be implemented by hardware or by hardware executing corresponding software.

[0036] According to a ninth aspect, a computer readable storage medium is provided, comprising computer instructions which, when executed on an electronic device, enable the electronic device to perform a method according to the third aspect or any one of the possible designs of the third aspect.

[0037] According to a tenth aspect, a computer readable storage medium is provided, comprising computer instructions which, when executed on an electronic device, enable the electronic device to perform a method according to the third aspect or any one of the possible designs of the third aspect.

[0038] It can be understood that the corresponding method provided above may be applied to any one of the high-speed serial interface, communication device, chip system, computer-readable storage medium, or computer program product provided above. Therefore, for the beneficial effects that can be achieved by the high-speed serial interface, communication device, chip system, computer-readable storage medium, or computer program product, please refer to the beneficial effects of the corresponding method. Details are not repeated here.

[0039] These and other aspects of the present application will become more clear and understandable from the following description. [Brief description of the drawings]

[0040] [Figure 1] FIG. 2 is a schematic diagram of an application architecture of a high-speed serial interface according to an embodiment of the present application. [Diagram 2] FIG. 2 is a schematic diagram of the signal flow in which the DL, PHY, and SerDes on one side communicate with the peer side of the link in the transmit and receive directions according to one embodiment of the present application. [Figure 3A] FIG. 2 is a schematic diagram of a circuit of a high-speed serial interface at a transmitting end according to an embodiment of the present application. [Figure 3B]FIG. 2 is a schematic diagram of a circuit of a high-speed serial interface at a transmitting end according to an embodiment of the present application. [Figure 4] FIG. 2 is a schematic diagram of a circuit of a high-speed serial interface at a receiving end according to an embodiment of the present application. [Diagram 5] FIG. 2 is a schematic diagram of a circuit of a high-speed serial interface at a transmitting end according to an embodiment of the present application. [Figure 6] FIG. 2 is a schematic diagram of a circuit of a high-speed serial interface at a receiving end according to an embodiment of the present application. [Figure 7] 4 is a schematic flowchart of a data transmission method applied at a transmitting end according to an embodiment of the present application; [Figure 8] 4 is a schematic flowchart of a data transmission method applied at a receiving end according to an embodiment of the present application; [Figure 9] 1 is a schematic flowchart of turning off PL_TX and PL_RX according to an embodiment of the present application. [Figure 10] 4 is a schematic flowchart of a data transmission method applied at a transmitting end according to an embodiment of the present application; [Figure 11] 4 is a schematic flowchart of a data transmission method applied at a receiving end according to an embodiment of the present application; [Figure 12] 1 is a schematic flowchart of turning on PL_TX and PL_RX according to an embodiment of the present application. [Figure 13] FIG. 2 is a schematic diagram of the structure of a network device according to an embodiment of the present application; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0041] For ease of understanding, some concepts related to the embodiments of the present application are described as examples for reference, as shown below.

[0042] Serializer / Deserializer (SerDes): Time-division multiplexing (TDM) and point-to-point (P2P) serial communication technology. Multiple low-speed parallel signals are converted into high-speed serial signals at the transmitting end of the SerDes. The high-speed serial signals pass through a transmission medium (optical cable or copper wire). Finally, the high-speed serial signals are converted back into low-speed parallel signals at the receiving end of the SerDes. This point-to-point serial communication technology fully utilizes the channel capacity of the transmission medium, reduces the number of transmission channels and device pins used, and increases the signal transmission speed, thus significantly reducing communication costs.

[0043] Peripheral Component Interconnect Express (PCIe): High-speed serial point-to-point dual-channel transmission with high bandwidth. Devices connected through PCIe are assigned exclusive channel bandwidth, and devices do not share bus bandwidth. PCIe primarily supports active power management, fault reporting, end-to-end reliable transmission, hot swapping, Quality of Service (QoS), and other features.

[0044] Hamming Code (Bose Ray-Chaudhuri Hocquenghem, BCH): A widely studied type of error-correcting code used to correct multiple random error patterns in multilevel, cyclic, error-correcting, and variable-length digital codes.

[0045] The following describes the technical solutions of the embodiments of the present application with reference to the accompanying drawings of the embodiments of the present application. In the description of the embodiments of the present application, " / " indicates "or" unless otherwise specified. For example, A / B may indicate A or B. The term "and / or" in this specification only describes the association relationship between related objects and indicates that three relationships may exist. For example, A and / or B may indicate the following three cases: only A exists, both A and B exist, and only B exists. In addition, in the description of the embodiments of the present application, "multiple" means two or more.

[0046] The terms "first" and "second" used hereinafter are intended for descriptive purposes only and should not be understood as an indication or implication of relative importance or of the quantity of the technical features indicated. Thus, a feature qualified by "first" or "second" may explicitly or implicitly include one or more features. In the description of the embodiments, "plurality" means two or more, unless otherwise specified.

[0047] The PCIe specification defines low power states such as L0s, L1, L2, etc. When no service packets are transmitted on the link for a certain period of time, the low power states are initiated to reduce the power consumption of the link.

[0048] Specifically, L0s indicates that a local transmitter (TX) and a peer receiver (RX) pair to enter or exit a low power state, and the delay of entering or exiting the low power state is several us. L1 indicates that the low power state is simultaneously exited in the TX direction and the RX direction, and the delay of entering or exiting the low power state is several tens of us. L1 reduces power consumption more than L0s, and L2 reduces power consumption more than L1. The L1 low power state is used as an example. The operation process of a link entering a low power state may be as follows:

[0049] (1) The PCIe power management module monitors whether a Transaction Layer Packet (TLP) is not transmitted in the transmit or receive direction of the link within a duration T.

[0050] (2) After determining that T is greater than a configured threshold, the PCIe power management module determines to initiate the process of entering an L1 low power state.

[0051] (3) The PCIe power management module sends a request to the PCIe physical layer to enter an L1 low power state.

[0052] (4) After receiving a request from the power management module, the PCIe physical layer negotiates with the peer device on entering the L1 low power state, in which the PCIe physical layer and the PCIe SerDes TX and RX are also in a power saving state.

[0053] (5) After determining that the process of negotiating with the peer device on entering the L1 low power state is complete, the PCIe physical layer reports to the PCIe power management module that the L1 low power state was successfully entered.

[0054] (6) After receiving an indication that the physical layer has entered the L1 state, the PCIe power management module indicates to the PCIe controller to enter an L1 low power state.

[0055] The L1 low power state is still used as an example. The operation process of exiting the low power state may be as follows.

[0056] (1) The PCIe power management module monitors whether a TLP request is sent in the transmit direction of the link.

[0057] (2) Upon detecting that a TLP has been sent, the PCIe power management module begins the process of exiting the L1 low power state.

[0058] (3) The PCIe power management module sends a request to the PCIe physical layer to exit the L1 low power state.

[0059] (4) After receiving a request from the PCIe power management module, the PCIe physical layer negotiates with the peer device to exit the L1 low power state. In this process, the PCIe physical layer controls both the TX and RX of the PCIe SerDes, which is equivalent to both the PCIe physical layer and the SerDes exiting the power saving state.

[0060] (5) After completing the process of negotiating with the peer device to exit the L1 low power state, the PCIe physical layer reports an indication to the power management module that it has successfully entered the L0 low power state.

[0061] (6) After receiving an indication that the PCIe physical layer has entered the L0 low power state, the PCIe power management module indicates the PCIe controller to also enter the L0 low power state.

[0062] First, from the process of entering and leaving the L1 low power state, it can be seen that before the PCIe physical layer and the PCIe controller, including SerDes, etc., enter the low power state, the transmission of service data on the link must stop for a certain period of time. The period is usually several us or several ms. However, if the interval for transmitting service data is shorter than this time, the low power mechanism cannot take effect, and the power consumption of the link still cannot be reduced.

[0063] In addition, in the PCIe protocol, when no service data is transmitted on the link within a short period of time, invalid IDLE data needs to be inserted in the TX direction for data padding. However, the IDLE data still passes through circuits such as the FEC circuit and the scrambling circuit of the physical layer, and the FEC circuit and the scrambling circuit of the physical layer still cause high power consumption, so the power consumption of the link still cannot be reduced.

[0064] In addition, in PCIe, when the PCIe controller enters a low power state when entering or exiting a low power state, the SerDes in the PCIe controller also enters a low power state. Therefore, the delay in entering and exiting a low power state is large, usually tens of us. In addition, when the link enters or exits a low power state, the service data is blocked. When frequently entering and exiting a low power state, the high-speed input / output (I / O) interface of the SerDes in the link is frequently used in the switching process, and the service data cannot be transmitted. This affects the performance of the high-speed I / O interface to a certain extent, and high-speed switching cannot be implemented.

[0065] Thus, the present application provides a high speed serial interface, which may be used, for example, in a PCIe, Ethernet, or other network architecture, among others.

[0066] In this application, when the transmitting end transmits service data, the monitor in the high-speed serial interface may monitor whether the service data is still being transmitted on the physical layer. When it determines that the service data is not being transmitted, the monitor triggers the clock gating circuit to stop sending a clock signal to the partial module in the physical layer circuit of the transmitting end. This is equivalent to the partial module in the physical layer circuit of the transmitting end being turned off. In addition, the control bit stream generating circuit is triggered to generate a first control bit stream. The first control bit stream corresponds to a switch to execute instructions to the partial module in the physical layer circuit of the remote end, i.e., the receiving end, and is used to indicate to turn off the partial module in the physical layer circuit of the receiving end. Upon detecting the first control bit stream, the bit stream detection circuit of the receiving end also triggers the clock gating circuit of the receiving end to turn off the partial module in the physical layer circuit of the receiving end. In this method in which the clock gating circuit and the control bit stream are used to put the partial module in the physical layer circuit of the transmitting end and the partial module in the physical layer circuit of the receiving end into a low power state, the response speed is usually several ns. Compared to conventional technologies in which the process of entering an L1 low power state or an L0s low power state in PCIe takes several us or even several ms, the response speed is significantly slower, resulting in a significant reduction in power consumption of the link.

[0067] Similarly, in the present application, the process of exiting the low power state and entering normal service data transmission can be implemented using a second control bit stream. In this way, the switching time spent exiting the low power state and entering normal service data transmission is shorter than the time spent exiting the L1 low power state or the L0s low power state in PCIe, and the response speed is faster.

[0068] In addition, in the high-speed serial interface in this application, when the clock gating circuit at the transmitting end does not send a clock signal to the physical layer circuit at the transmitting end, the partial module in the physical layer circuit at the transmitting end may be turned off. This includes that the FEC encoding circuit, the scrambling circuit, etc. in the physical layer circuit at the transmitting end are turned off and do not operate normally. When the clock gating circuit at the receiving end does not send a clock signal to the partial module in the physical layer circuit at the receiving end, the partial module in the physical layer circuit at the receiving end is turned off. This includes that the FEC decoding circuit, the descrambling circuit, etc. of the physical layer at the receiving end are turned off and do not operate normally. In the existing PCIe protocol, when service data is not transmitted in the low power state, IDLE data is still inserted in the transmission direction and passes through the FEC circuit, the scrambling / descrambling circuit, etc. This still causes high power consumption. However, in this application, the partial module in the physical layer circuit at the transmitting end and the partial module in the physical layer circuit at the receiving end cannot operate normally. This includes that the FEC circuit, the scrambling / descrambling circuit, etc. of the physical layer do not operate normally. Therefore, the power consumption of the link can be significantly reduced.

[0069] In addition, in the prior art PCIe, when the link enters a low-power operating state, the SerDes in the link also enters a low-power state. However, in the present application, after the first control bit stream is transmitted, when the physical layer circuit is turned off, the transmitter circuit of the SerDes is still in an operating state and may continue to transmit a random bit stream. Of course, the receiver circuit of the SerDes at the receiving end may also be in an operating state and continue to receive a random bit stream. This can ensure that the Clock and Data Recovery (CDR) circuit in the SerDes is in a stable locked state, and the impact on the performance of high-speed I / O can be reduced.

[0070] It should be understood that the high-speed serial interface in this application includes a receiver circuit and a transmitter circuit. When there are high-speed serial interfaces for transmitting service data on both sides, the transmitter circuit of the high-speed serial interface on one side can cooperate with the receiver circuit of the high-speed serial interface on the other side.

[0071] In some embodiments, as shown in Fig. 1, the high-speed serial interface on one side may be included in a System-on-a-Chip (SoC), and the high-speed serial interface on the other side may be included in a Network Interface Card, for example, an Ethernet Network Interface Card. The SoC may be connected to the Network Interface Card through the high-speed serial interface. Service data may be transmitted between the SoC and the Network Interface Card, and the SoC may communicate with an external network using the Network Interface Card.

[0072] As shown in Figure 1, the high-speed serial interface is integrated into the I / O controller of the SoC and connected to the system bus of the SoC. The central processing unit (CPU), direct memory access controller (DMAC), memory, and other components are further connected to the system bus.

[0073] In some embodiments, in this application, the high-speed serial interface of the SoC is regarded as a high-speed serial interface of the transmitting end, which is equivalent to improving the physical layer circuit in the high-speed serial interface. On the basis that the high-speed serial interface of the SoC includes application layer (AP) / transport layer (TL) / data link layer (DL), physical layer (PHY) and SerDes circuits, monitors, clock gating circuits, control bitstream generating circuits and other circuits are added to the high-speed serial interface.

[0074] Similarly, the network interface card also includes a high-speed serial interface, and the high-speed serial interface is integrated into the I / O controller of the SoC. The high-speed serial interface in the network interface card may be considered as a high-speed serial interface at the receiving end, and the high-speed serial interface at the receiving end is also improved. Based on the high-speed serial interface controller in the network interface card including AP / TL / DL, PHY, and SerDes, a clock gating circuit, a bitstream detection circuit, etc. are added.

[0075] The high-speed serial interface in the SoC may be connected to an external network interface card via a SerDes in the high-speed serial interface to configure a chip system having a high-speed I / O interface.

[0076] It should be understood that the high-speed serial interface in the SoC may alternatively function as a high-speed serial interface at a receiving end, and the high-speed serial interface in the network interface card may alternatively function as a high-speed serial interface at a transmitting end. Specifically, the high-speed serial interface of the SoC not only includes a high-speed serial interface at a transmitting end, but also includes a high-speed serial interface at a receiving end, and the high-speed serial interface of the network interface card not only includes a high-speed serial interface at a transmitting end, but also includes a high-speed serial interface at a receiving end.

[0077] The following further describes a system framework including DL and PHY in the high-speed serial interface of the transmitting end and DL and PHY in the high-speed serial interface of the receiving end. Please refer to FIG. 2. It should be understood that the transmitting end also includes a receiver circuit, and the receiving end also includes a transmitter circuit. FIG. 2 shows the signal flow in which the DL, PHY, and SerDes of one side communicate with the peer side of the link in the transmitting and receiving directions. The data path of the DL includes two directions DL_TX and DL_RX. The data path of the PHY also includes two directions PL_TX and PL_RX. The PHY includes high-power circuits such as FEC circuits and scrambling / descrambling circuits. The DL_TX may be a partial module of the data link layer of the transmitting end, specifically the transmitter circuit of the data link layer of the transmitting end. The DL_RX may be a partial module of the data link layer of the receiving end, specifically the receiver circuit of the data link layer of the receiving end. The PL_TX may be a partial module in the physical layer circuit of the transmitting end, specifically the transmitter circuit of the physical layer circuit of the transmitting end. The PL_RX is a partial module in the physical layer circuit of the receiving end, and may be specifically a receiver circuit in the physical layer circuit of the receiving end. The PL_TX may receive data from the DL_TX, the data is encoded by an FEC encoding circuit, a scrambling circuit, etc. in the PHY, and then the encoded data is sent to the SerDes. The PL_RX may receive data from the SerDes on the peer side, the data is decoded by a descrambling circuit, etc. in the PHY, and then the decoded data is sent to the DL_RX on the peer side for further processing.

[0078] It should be noted that in this application, the transmitter circuit (PL_TX) in the physical layer circuit of the transmitting end is not limited to only include an FEC encoding circuit and a scrambling circuit, and may further include another power-consuming transmitter circuit. Similarly, in this application, the receiver circuit (PL_RX) in the physical layer circuit of the receiving end is not limited to only include an FEC decoding circuit and a descrambling circuit, and may further include another power-consuming receiver circuit. For example, the transmitter circuit in the physical layer circuit of the transmitting end may further include a data distribution circuit, and the receiver circuit in the physical layer circuit of the receiving end may further include a symbol lock circuit, a deskew circuit, etc.

[0079] This application corresponds to an improvement of the peripheral circuits of the PHY. A monitor, a clock gating circuit, a control bit stream generating circuit, etc. are added to the periphery of the PHY at the transmitting end. A bit stream detection circuit, a clock gating circuit, etc. are added to the periphery of the PHY at the receiving end.

[0080] In some embodiments, a random bit stream generating circuit is further added around the PHY at the transmitting end and configured to generate a random bit stream.

[0081] In the following, the high-speed serial interface at the transmitting end in this application is described first. The high-speed serial interface includes a data link layer circuit at the transmitting end, a physical layer circuit at the transmitting end, a monitor, a clock gating circuit, a control bit stream generating circuit, a random bit stream generating circuit, and a serializer / deserializer, and further includes the following circuits: Figure 3A is a schematic diagram of the structure of the high-speed serial interface at the transmitting end.

[0082] The monitor is configured as shown in the clock gating circuit to stop sending clock signals to the partial modules in the physical layer circuit of the transmitting end when the transmitting end is not sending service data.

[0083] The clock gating circuit is configured to stop sending a clock signal to a partial module in the physical layer circuit at the transmitting end.

[0084] The control bitstream generating circuit is configured to transmit a first control bitstream through the serializer / deserializer when it is determined that the clock gating circuit has stopped transmitting the clock signal, and the first control bitstream is used to indicate that the transmitting end has turned off a partial module in the physical layer circuit of the transmitting end, or the first control bitstream is used to indicate that the transmitting end turns off a partial module in the physical layer circuit of the transmitting end, or the first control bitstream is used to indicate that the receiving end turns off a partial module in the physical layer circuit of the receiving end. This is equivalent to the first control bitstream not passing through the partial module in the physical layer circuit of the transmitting end after the partial module in the physical layer circuit of the transmitting end is turned off.

[0085] The random bit stream generating circuit is configured to send a random bit stream to the serializer / deserializer, which is equivalent to the random bit stream not passing through the partial module in the physical layer circuit of the transmitting end after the partial module in the physical layer circuit of the transmitting end is turned off.

[0086] In this way, when the transmitting end does not transmit service data, the partial module in the physical layer circuit of the high-speed serial interface of the transmitting end is turned off, and the transmitting end also transmits a first control bit stream to indicate that the transmitting end has turned off the partial module in the physical layer circuit of the transmitting end, or the first control bit stream is used to indicate that the transmitting end turns off the partial module in the physical layer circuit of the transmitting end, or the first control bit stream is used to indicate the receiving end to turn off the partial module in the physical layer circuit of the receiving end. This is equivalent to the receiving end also being able to turn off the physical layer circuit of the receiving end when it determines that there is no service data to be transmitted to the transmitting end, in order to reduce power consumption at the transmitting end and the receiving end. In the present application, a random bit stream may further be transmitted so that the serializer / deserializer, i.e., SerDes, in the high-speed serial interface is in an operating state.

[0087] For example, as shown in FIG. 3B, a sub-module in the physical layer circuit of the transmitting end is a transmitter circuit in the physical layer circuit of the transmitting end, namely PL_TX.

[0088] In this case, the monitor monitors whether the DL_TX is transmitting service data to the PL_TX, and when it is determined that the DL_TX is not transmitting service data to the PL_TX, the monitor is configured to stop transmitting a clock signal to the PL_TX, as shown in the clock gating circuit (CLK_GAT); the clock gating circuit is configured to stop sending a clock signal to the PL_TX; The control bitstream generating circuit (marker insert) is configured to send a first control bitstream when it is determined that the clock gating circuit has stopped sending the clock signal, and the first control bitstream is used to indicate to the receiving end of the service data to turn off PL_RX.

[0089] In some embodiments, a multiplexer circuit (MUX) is further included and configured to select to output the service data or select to output the first control bitstream upon receiving an instruction indicating to output the first control bitstream.

[0090] When the clock gating circuit is configured to stop sending the clock signal to the PL_TX, this is equivalent to stopping the sending of the pulse signal used to transmit the service data to the PL_TX. If the PL_TX does not receive the clock signal, the FEC encoding circuit and the scrambling circuit in the PL_TX cannot operate normally, and the PL_TX will not output the service data to the MUX.

[0091] Therefore, when it is determined that the DL_TX is not transmitting service data to the PL_TX, the high-speed serial interface at the generating end may use a clock gating circuit to turn off the PL_TX. In addition, the control bitstream generating circuit may also generate a first control bitstream indicating to turn off the PL_RX at the receiving end.

[0092] It should be noted that in this application, the sending of the clock signal may be stopped to turn off some corresponding modules. In other words, stopping the sending of the clock signal to a partial module is equivalent to turning off the partial module.

[0093] For example, the clock gating circuit stops sending a clock signal to turn off a partial module in the physical layer circuit of the transmitting end. In other words, the clock gating circuit stops sending a clock signal to a partial module in the physical layer circuit of the transmitting end, which is equivalent to turning off the partial module in the physical layer circuit of the transmitting end.

[0094] Correspondingly, the high-speed serial interface at the receiving end in this application is further described.

[0095] At the receiving end, as shown in (a) of Fig. 4, the high-speed serial interface includes a data link layer circuit at the receiving end, a physical layer circuit at the receiving end, a bitstream detection circuit, a clock gating circuit, and a serializer / deserializer. The bitstream detection circuit is configured to receive a first control bitstream through the serializer / deserializer, and the first control bitstream is used to indicate that the transmitting end has turned off a partial module in the physical layer circuit at the transmitting end, or the first control bitstream is used to indicate that the transmitting end turns off a partial module in the physical layer circuit at the transmitting end, or the first control bitstream is used to indicate the receiving end to turn off a partial module in the physical layer circuit at the receiving end.

[0096] The bitstream detection circuit is further configured as shown in the clock gating circuit to stop sending a clock signal to the partial module in the physical layer circuit of the receiving end.

[0097] The clock gating circuit is configured to stop sending a clock signal to a partial module in the physical layer circuit at the receiving end.

[0098] The bitstream detection circuit is further configured to receive the random bitstream via the serializer / deserializer.

[0099] For example, as shown in (b) of FIG. 4, a partial module in a physical layer circuit in a high-speed serial interface at a receiving end includes a PL_RX at the receiving end, and the high-speed serial interface further includes a DL_RX, a bitstream detection circuit (marker check), and a clock gating circuit at the receiving end.

[0100] The bitstream detection circuit is configured as shown in the clock gating circuit to stop sending a clock signal to the PL_RX when the first control bitstream is received and the first control bitstream is used to indicate that the PL_RX should be turned off.

[0101] The clock gating circuit is configured to stop sending a clock signal to PL_RX.

[0102] The bitstream detection circuit is further configured to receive the random bitstream via the SerDes, where the random bitstream does not pass through the PL_RX at the receiving end.

[0103] Specifically, when a first control bit stream indicating to turn off PL_RX is received at the high-speed serial interface of the receiving end, the clock gating circuit no longer sends a clock signal to PL_RX. When the clock gating circuit stops sending a clock signal to PL_RX, this is equivalent to skipping sending a pulse signal used to receive service data to PL_RX. If PL_TX does not receive a clock signal, the FEC decoding circuit and the descrambling circuit in PL_RX cannot operate normally, and PL_RX will no longer output service data to DL_RX.

[0104] It should be noted that in this application, the sending of the clock signal may be stopped to turn off some corresponding modules. In other words, stopping the sending of the clock signal to a partial module is equivalent to turning off the partial module.

[0105] For example, the clock gating circuit stops sending a clock signal to turn off a partial module in the physical layer circuit of the receiving end. In other words, the clock gating circuit stops sending a clock signal to a partial module in the physical layer circuit of the receiving end, which is equivalent to turning off the partial module in the physical layer circuit of the receiving end.

[0106] Thus, in the present application, when it is determined that there is no service data to be transmitted on the link within a short period of time, the high-speed serial interface may control the PL_TX of the transmitting end and the PL_RX of the receiving end to be turned off. For example, high-power circuits such as FEC circuits and scrambling circuits in the PL_TX and high-power circuits such as FEC circuits and descrambling circuits in the PL_RX are turned off. This reduces the power consumption of the link.

[0107] In addition, in the present application, when the first control bit stream is used to indicate that PL_RX should also be turned off based on the PL_TX of the transmitting end being turned off, the first control bit stream corresponds to a switch for indicating to turn off the circuit. Compared with the existing PCIe protocol, etc., in which the delay of entering or exiting a low power state is several us or several ms, the response speed of the switch used in the present application can be several ns, and the response speed is fast.

[0108] Figure 5 shows a high-speed serial interface at a transmitting end based on the high-speed serial interfaces shown in Figures 3A, 3B, and 4. The high-speed serial interface at the transmitting end further includes a SerDes TX, i.e., a SerDes transmitter circuit, configured to output service data or a first control bit stream.

[0109] In some embodiments, after the transmitting end completes the transmission of the first control bit stream, in order to ensure that the SerDes transmits data continuously and does not fail, the high-speed serial interface of the transmitting end may further include a random bit stream generating circuit configured to generate a random bit stream, so that the CDR circuit in the SerDes is in a locked state. The random bit stream includes 0s and 1s with balanced quantities.

[0110] In the present application, the CDR circuit in the SerDes being in a locked state may be understood as the CDR circuit in the SerDes remaining in a data transmission state and not entering a low power state. In the case of the transmitting end, the CDR circuit in the SerDes being in a locked state may be understood as the CDR circuit in the SerDes being configured to continuously transmit data, for example, to transmit service data, a first control bit stream, or a random bit stream. In the case of the receiving end, the CDR circuit in the SerDes being in a locked state may be understood as the CDR circuit in the SerDes being configured to continuously receive data, for example, to receive service data, a first control bit stream, or a random bit stream.

[0111] Specifically, as shown in FIG. 5 , the first end a of DL_TX is coupled to the first end b of PL_TX, the second end c of PL_TX is coupled to the first end d of the MUX circuit, the first end e of the monitor is coupled between the first end a and the first end b, the second end f of the monitor is coupled to the first end g of the clock gating circuit, the second end h of the clock gating circuit is coupled to the third end i of PL_TX, the first end j of the control bit stream generation circuit is coupled to the second end k of the MUX circuit, the first end l of the random bit stream generation circuit is coupled to the third end m of the MUX circuit, the third end n of the monitor is coupled to the fourth end o of the MUX, and the fifth end p of the MUX is coupled to the first end q of the SerDes TX, and a link is established between the output end of the SerDes TX and the SerDes RX of the receiving end.

[0112] DL_TX is a transmit directional circuit in the data link layer, configured to transmit service data to PL_TX.

[0113] The PL_TX is a transmit direction circuit of the physical layer, configured to receive service data from the DL_TX, encode the service data using an FEC circuit and a scrambling circuit, etc. in the PL_TX, and then transmit the encoded service data to the SerDes TX through a MUX circuit.

[0114] The clock gating circuit is configured to perform gating on the clock input to each module in PL_TX. For example, when the enable value of the input clock signal is 1, it indicates that the clock gating circuit should be turned on, or when the enable value of the input clock signal is 0, it indicates that the clock gating circuit should be turned off.

[0115] The monitor is configured to monitor whether the DL_TX is transmitting service data to the PL_TX.

[0116] The control bitstream generation circuit is configured to, when it is determined that the PL_TX is turned off, insert a marker indicating that the circuitry is off into the data to be transmitted, or, when it is determined that the PL_TX is turned on, insert a marker indicating that the circuitry is on into the data to be transmitted, and transmit data to the SerDes TX via the MUX circuit so that the receiving end identifies the operation of turning the physical layer circuitry on or off.

[0117] The random bitstream generation circuit is configured to send an invalid random bitstream to the SerDes TX via the MUX when it is determined that the local PL_TX is turned off.

[0118] The SerDes TX is the transmit direction circuit of the SerDes and is configured to convert the parallel data transmitted by the PL_TX into a serial bit stream and transmit the serial bit stream onto the link.

[0119] Based on the above description of the high-speed serial interface at the transmitting end, the process of transmitting data through the high-speed serial interface at the transmitting end includes the following processes.

[0120] (1) DL_TX transmits service data to PL_TX.

[0121] (2) The PL_TX performs physical layer coding, such as FEC coding and byte distribution, on the service data, scrambles the service data using a scrambling circuit, and then sends the processed service data to the MUX circuit, so that the MUX circuit sends the processed service data to the receiving end via the SerDes TX.

[0122] (3) When the monitor determines that the DL_TX is not transmitting service data, the monitor indicates to the clock gating circuit to stop sending a clock signal to the PL_TX and triggers the control bitstream generation circuit to send a first control bitstream to the SerDes TX via the MUX circuit.

[0123] (4) Upon determining that the transmission of the first control bit stream is completed, the monitor triggers the random bit stream generating circuit to transmit a random bit stream, specifically, transmits the random bit stream to the SerDes TX via the MUX.

[0124] Correspondingly, based on the high-speed serial interfaces shown in Figures 3 and 4, Figure 6 shows a high-speed serial interface at a receiving end. The high-speed serial interface at the receiving end further includes a SerDes RX, i.e., a SerDes receiver circuit, configured to receive service data, a first control bit stream, a random bit stream, etc.

[0125] Specifically, as shown in FIG. 6 , a first end a' of the SerDes RX is coupled to a first end b' of the bitstream detection circuit, a second end c' of the bitstream detection circuit is coupled to a first end d' of the PL_RX, a second end e' of the PL_RX is coupled to a first end f' of the DL_RX, a third end g' of the bitstream detection circuit is coupled to a first end h' of the clock gating circuit, and a second end i' of the clock gating circuit is coupled to a third end j' of the PL_RX.

[0126] The SerDes RX is configured to receive serial data from the link, perform serial-to-parallel conversion, and send the parallel data to the PL_RX via the bitstream detection circuit.

[0127] The bitstream detection circuit is configured to detect whether the bitstream output by the SerDes RX includes a control bitstream indicating to turn the circuit on or off, and determine whether to turn the PL_RX on or turn the PL_RX off based on the control bitstream.

[0128] The clock gating circuit is configured to perform gating on a clock signal input to each module in the PL_RX, and the clock signal indicates whether to turn the PL_RX on or off, for example, when the enable value of the input clock signal is 1, it indicates that the PL_RX circuit should be turned on, or when the enable value of the input clock signal is 0, it indicates that the PL_RX circuit should be turned off.

[0129] PL_RX is a physical layer receive direction module, configured to receive service data sent by SerDes RX through a bitstream detection circuit, perform physical layer decoding, descrambling, etc. on the service data, and then send the processed service data to DL_RX.

[0130] DL_RX is a receive direction module in the data link layer, configured to receive and process the service data output by PL_RX.

[0131] Based on the above description of the high-speed serial interface at the receiving end, the process of receiving data by the high-speed serial interface at the receiving end includes the following processes.

[0132] (1) The SerDes RX receives the serial data sent by the transmitting end, converts the serial data into parallel data, and sends the parallel data to the bit stream detection circuit.

[0133] (2) The bitstream detection circuit detects the received data and, if service data is detected, sends service data to the PL_RX circuit; if the first control bitstream is detected, triggers the clock gating circuit to stop sending a clock signal to the PL_RX circuit; or, if a random bitstream is detected, discards the random bitstream.

[0134] (3) The bitstream detection circuit transmits the service data to the PL_RX circuit, which performs descrambling and FEC decoding on the service data and transmits the processed data to the DL_RX.

[0135] Therefore, in the present application, when no service data is currently being transmitted on the link, the high-speed serial interface may control the PL of the transmitting end and the PL of the receiving end to be turned off to reduce the power consumption of the link. In addition, in the present application, a control bit stream is used to indicate the circuit to be turned on or off, so that the response speed can be enhanced. In addition, in the present application, after the transmission of the control bit stream is completed, a random bit stream may be further transmitted to ensure that the CDR in the transmitting end SerDes and the receiving end SerDes in the high-speed serial interface are in a stable lock state, so that there is no possibility of interface bit errors and other problems occurring.

[0136] When a first control bit stream is sent to turn off the physical layer circuit of the peer end corresponding to the process of reducing power consumption, a second control bit stream can be further sent to turn on the physical layer circuit of the peer end when the transmission of service data is resumed. With reference to the embodiment of the transmitting end and receiving end circuits of the high-speed serial interface in the present application, the following further describes the process of turning off PL_TX and PL_RX, and the process of turning on PL_TX and PL_RX in the present application.

[0137] A: This application provides a data transmission method. As shown in Figure 7, the method is applied to a high-speed serial interface at a transmitting end. The high-speed serial interface includes a physical layer circuit. The method includes the following steps:

[0138] 701: When the transmitting end does not transmit service data, the transmitting end transmits a first control bit stream, and the first control bit stream is used to indicate that the transmitting end has turned off a partial module in the physical layer circuit of the transmitting end, or the first control bit stream is used to indicate that the transmitting end turns off a partial module in the physical layer circuit of the transmitting end, or the first control bit stream is used to indicate the receiving end to turn off a partial module in the physical layer circuit of the receiving end.

[0139] For a specific implementation of step 701, please refer to the following description of steps (1), (2), and (5) in FIG.

[0140] 702: The transmitting end turns off a partial module in the physical layer circuit of the transmitting end.

[0141] For a specific implementation of step 701, please refer to the following description of steps (3) and (4) in FIG.

[0142] It should be noted that the sequence of turning off the partial module in the physical layer circuit of the transmitting end by the transmitting end and sending the first control bit stream by the transmitting end is not limited in the present application. Specifically, optionally, the transmitting end sends the first control bit stream after the transmitting end turns off the partial module in the physical layer circuit of the transmitting end, or optionally, the transmitting end turns off the partial module in the physical layer circuit of the transmitting end in the process of the transmitting end sending the first control bit stream, or optionally, the transmitting end turns off the partial module in the physical layer circuit of the transmitting end after the transmitting end completes sending the first control bit stream.

[0143] 703: The transmitting end transmits a random bit stream.

[0144] For a specific implementation of step 703, please refer to the following description of step (6) in FIG.

[0145] The sequence of turning off the partial module in the physical layer circuit of the transmitting end by the transmitting end and sending the random bit stream by the transmitting end is also not limited in the present application. Specifically, optionally, the transmitting end sends the random bit stream after the transmitting end turns off the partial module in the physical layer circuit of the transmitting end, or optionally, the transmitting end turns off the partial module in the physical layer circuit of the transmitting end in the process of the transmitting end sending the random bit stream, or optionally, the transmitting end turns off the partial module in the physical layer circuit of the transmitting end after the transmitting end completes sending the random bit stream.

[0146] Correspondingly, for a high-speed serial interface, the high-speed serial interface includes a physical layer circuit at the receiving end. As shown in Figure 8, the method includes the following steps:

[0147] 801: A receiving end receives a first control bit stream, where the first control bit stream is used to indicate that the transmitting end has turned off a partial module in the physical layer circuit of the transmitting end, or the first control bit stream is used to indicate that the transmitting end turns off a partial module in the physical layer circuit of the transmitting end, or the first control bit stream is used to indicate the receiving end to turn off a partial module in the physical layer circuit of the receiving end.

[0148] For a specific implementation of step 801, please refer to the following description of step (7) in FIG.

[0149] 802: The receiving end turns off a partial module in the physical layer circuit of the receiving end.

[0150] For a specific implementation of step 802, please refer to the following description of steps (8) and (9) in FIG.

[0151] 803: The receiving end receives the random bit stream.

[0152] The random bit stream does not pass through any partial module in the physical layer circuitry at the receiving end.

[0153] The sequence of turning off the partial module in the physical layer circuit of the receiving end by the receiving end and receiving the random bit stream by the receiving end is also not limited in the present application. Specifically, optionally, the receiving end receives the random bit stream after the receiving end turns off the partial module in the physical layer circuit of the receiving end, or optionally, the receiving end turns off the partial module in the physical layer circuit of the receiving end in the process of receiving the random bit stream, or optionally, the receiving end turns off the partial module in the physical layer circuit of the receiving end after the receiving end completes receiving the random bit stream.

[0154] For a specific implementation of step 803, please refer to the following description of step (10) in FIG.

[0155] It should be noted that the manner of turning off a partial module in a physical layer circuit includes turning off the power of the associated module, turning off the clock of the associated module, or stopping the transmission of a clock signal to the associated module, etc., so that the partial module in the physical layer circuit is in an inoperative state.

[0156] For example, in the circuit structure shown in Figure 9, the partial module in the physical layer circuit of the transmitting end is PL_TX, and the partial module in the physical layer circuit of the receiving end is PL_RX. The process of turning off PL_TX and PL_RX may be as follows:

[0157] (1) After completing the transmission of the service data, the DL_TX stops transmitting the service data to the PL_TX.

[0158] (2) The monitor detects that DL_TX is not transmitting service data.

[0159] Each time the DL_TX transmits service data to the PL_TX, the monitor receives a first signal, where the first signal indicates that the DL_TX is transmitting service data to the PL_TX.

[0160] When the time during which the DL_TX does not receive the first signal exceeds a preset time period, the monitor determines that the DL_TX is not transmitting service data to the PL_TX. For example, the preset time period here may be 1 μs or 1 ns.

[0161] (3) After waiting until the PL_TX completes transmitting the service data output by the DL_TX, the monitor sends a request to the first clock gating circuit to turn off the partial circuit of the PL_TX.

[0162] When the monitor determines that the DL_TX has not transmitted service data to the PL_TX, the PL_TX may not have completed transmission of the service data received from the PL_TX to the MUX. Thus, after waiting until the PL_TX has completed transmission of the service data output by the DL_TX, for example, after waiting until the interval from the time when the PL_TX completed transmission of the last service data exceeds a time period, the monitor determines that the PL_TX has completed transmission of the service data output by the DL_TX. In this case, the monitor initiates a process of entering a low power state and transmits a request to the first clock gating circuit to turn off the partial circuit of the PL_TX. The partial circuit of the PL_TX here may include a high power circuit such as an FEC circuit or a scrambling circuit.

[0163] (4) The first clock gating circuit turns off a partial circuit of PL_TX.

[0164] It should be understood that the PL_TX may be triggered by continuously receiving a clock signal from the first clock gating circuit to transmit service data, and upon receiving a request to turn off the partial circuit of the PL_TX, the first clock gating circuit may turn off the partial circuit of the PL_TX by ceasing to send a clock signal to the partial circuit of the PL_TX.

[0165] For example, the first clock gating circuit updates the enable value of the clock signal output to the partial circuit of PL_TX from 1 to 0 to indicate that the partial circuit of PL_TX is to be turned off.

[0166] (5) The control bitstream generating circuit sends a first control bitstream to the SerDes TX, where the first control bitstream indicates to turn off the partial circuit of the PL_RX. The SerDes TX converts the parallel data of the first control bitstream into serial data, and then sends the serial data to the link.

[0167] In some embodiments, when the monitor determines that the first clock gating circuit turns off the partial circuit of the PL_TX, the monitor may trigger the control bitstream generating circuit to generate a first control bitstream to control the partial circuit of the PL_RX to be turned off at the receiving end. For example, the monitor sends a second signal to the control bitstream generating circuit, and the second signal is used to indicate to the control bitstream generating circuit to send the first control bitstream. In this case, the monitor is coupled to the control bitstream generating circuit. The monitor may trigger the MUX circuit to select the first control bitstream to be sent to the SerDes TX.

[0168] In some embodiments, a global control circuit operates in the high-speed serial interface of the transmitting end to control the high-speed serial interface. When the control circuit determines that the first clock gating circuit turns off the partial circuit of the PL_TX, the control circuit can trigger the control bitstream generating circuit to generate a first control bitstream, and the control circuit triggers the MUX circuit to select the first control bitstream to be sent to the SerDes TX.

[0169] (6) The random bit stream generation circuit sends the random bit stream to the SerDes TX. The SerDes TX converts the parallel data of the random bit stream into serial data, and then sends the serial data to the link.

[0170] In some embodiments, when the control bitstream generating circuit determines that the first control bitstream has been transmitted, the monitor may trigger the random bitstream generating circuit to generate a random bitstream, so that the SerDes TX transmits the random bitstream to the link. For example, when the control bitstream generating circuit determines that the first control bitstream has been transmitted, the monitor may transmit a third signal to the random bitstream generating circuit, and the third signal may be used to indicate to the random bitstream generating circuit to transmit the random bitstream. In this case, the monitor is coupled to the random bitstream generating circuit. The monitor may trigger the MUX circuit to select the random bitstream to be transmitted to the SerDes TX.

[0171] In some embodiments, when the control bitstream generation circuit determines that it has completed transmitting the first control bitstream, the control circuit may trigger the random bitstream generation circuit to generate a random bitstream, and the control circuit triggers the MUX circuit to select the random bitstream for transmission to the SerDes TX.

[0172] (7) The SerDes RX converts the serial data of the received first control bit stream into parallel data, and then sends the parallel data to the bit stream detection circuit.

[0173] (8) Upon identifying the first control bitstream as a bitstream indicating to turn off the partial circuit of the PL_RX, the bitstream detection circuit sends an instruction to the second clock gating circuit indicating to turn off the partial circuit of the PL_RX.

[0174] In some embodiments, the first control bitstream includes multiple repeat marker identifiers, a first marker end identifier, and a first bitstream content, and the first bitstream content indicates the receiving end to turn off a partial circuit of the PL_RX. For a specific implementation of the first control bitstream, please refer to the detailed description of the first control bitstream below. The first marker end identifier is used to indicate the position of the end bit of the first control bitstream. The multiple repeat marker identifiers are used to indicate that the first control bitstream is a control bitstream different from the service data bitstream.

[0175] It can be understood that the bitstream detection circuit continuously detects the bitstream output by the SerDes RX. When the first control bitstream is received and the first control bitstream is identified as a request to turn off the partial circuit of the PL_RX, the bitstream detection circuit can immediately send an instruction to the second clock gating circuit to turn off the partial circuit of the PL_RX.

[0176] (9) Upon receiving an instruction to turn off the partial circuit of the PL_RX, the second clock gating circuit waits until the PL_RX completes service data processing, and then turns off the partial circuit of the PL_RX.

[0177] When the second clock gating circuit receives an instruction to turn off the partial circuit of the PL_RX, the PL_RX may not have completed transmitting the service data received from the SerDes RX to the DL_RX. Thus, when the second clock gating circuit determines that the interval from the last time that the PL_RX transmits the service data to the DL_RX exceeds a preset time period, the second clock gating circuit stops transmitting the clock signal to the PL_RX. For example, the preset time period may be 1 ns or 2 ns.

[0178] When the subcircuitry of the PL_RX is turned off, the subcircuitry of the PL_RX enters a low power state.

[0179] (10) (not shown in FIG. 9) SerDes RX receives the random bit stream and sends the random bit stream to the bit stream detection circuit. After the bit stream detection circuit identifies the random bit stream, it discards the random bit stream.

[0180] B: When turning on the physical layer circuit, in the process of the transmitting end, as shown in FIG. 10, the method may further include the following steps:

[0181] 101: When the transmitting end resumes transmitting service data, send a second control bit stream, and the second control bit stream is used to indicate that the transmitting end has turned on a partial module in the physical layer circuit of the transmitting end, or the second control bit stream is used to indicate that the transmitting end turns on a partial module in the physical layer circuit of the transmitting end, or the second control bit stream is used to indicate the receiving end to turn on a partial module in the physical layer circuit of the receiving end.

[0182] For a specific implementation of step 101, please refer to the following description of steps (1), (2), and (6) in FIG.

[0183] 102: The transmitting end turns on a partial module in the physical layer circuit of the transmitting end.

[0184] For a specific implementation of step 102, please refer to the following description of steps (3) and (4) in FIG.

[0185] The sequence of turning on the physical layer circuit of the transmitting end and sending the second control bit stream by the transmitting end is also not limited in the present application. Specifically, optionally, the transmitting end sends the second control bit stream after the transmitting end turns on the physical layer circuit of the transmitting end, optionally, the transmitting end turns on the physical layer circuit of the transmitting end in the process of the transmitting end sending the second control bit stream, or optionally, the transmitting end turns on the physical layer circuit of the transmitting end after the transmitting end completes sending the second control bit stream.

[0186] 103: The transmitting end controls a physical layer circuit of the transmitting end to transmit service data to the serializer / deserializer.

[0187] For a specific implementation of step 102, please refer to the following description of steps (5) and (7) in FIG.

[0188] Correspondingly, as shown in FIG. 11, in the process at the receiving end, the method may further include the following steps:

[0189] 111: The receiving end controls the serializer / deserializer to receive a second control bit stream, where the second control bit stream is used to indicate that the transmitting end has turned on a partial module in the physical layer circuit of the transmitting end, or the second control bit stream is used to indicate that the transmitting end turns on a partial module in the physical layer circuit of the transmitting end, or the second control bit stream is used to indicate the receiving end to turn on a partial module in the physical layer circuit of the receiving end.

[0190] For a specific implementation of step 111, please refer to the following description of step (9) in FIG.

[0191] 112: The receiving end turns on a partial module in the physical layer circuit of the receiving end.

[0192] For a specific implementation of step 112, please refer to the following description of step (10) in FIG.

[0193] 113: The receiving end controls a physical layer circuit of the receiving end to receive the service data transmitted through the serializer / deserializer.

[0194] For a specific implementation of step 113, please refer to the following description of steps (8), (11), and (12) in FIG.

[0195] It should be noted that the manner of turning on a partial module in a physical layer circuit includes turning on the clock of the corresponding module, turning on the power supply of the corresponding module, or controlling the clock circuit to send a clock signal to the corresponding module so that the physical layer module is in an operational state.

[0196] For example, in the circuit structure shown in Figure 12, the partial module in the physical layer circuit of the transmitting end is PL_TX, and the partial module in the physical layer circuit of the receiving end is PL_RX. The process of turning on PL_TX and PL_RX may be as follows:

[0197] (1) DL_TX receives service data sent by the upper layer and starts sending the service data to PL_TX.

[0198] Specifically, DL_TX is restored to the service data transmission state.

[0199] (2) The monitor detects that DL_TX has started transmitting service data.

[0200] When the DL_TX starts to send service data to the PL_TX, the DL_TX also sends a first signal to the monitor. The monitor receiving the first signal means that the monitor detects that the DL_TX resumes sending service data to the PL_TX.

[0201] (3) The monitor indicates to the first clock gating circuit to turn on a subcircuit of PL_TX.

[0202] Specifically, the monitor initiates the process of exiting the low power state.

[0203] (4) The first clock gating circuit turns on a partial circuit of PL_TX.

[0204] Specifically, the first clock gating circuit starts transmitting a clock signal to the partial circuit of PL_TX. For example, the enable value of the clock signal is updated from 0 to 1.

[0205] (5) The random bit stream generating circuit stops transmitting the random bit stream.

[0206] In some embodiments, after sending the instruction to the first clock gating, the monitor may send a fourth signal to the random bit stream generating circuit to indicate to the random bit stream generating circuit to stop sending the random bit stream, which is also equivalent to the random bit stream generating circuit determining that the first clock gating circuit starts sending a clock signal to the subcircuit of PL_TX.

[0207] In addition, the monitor indicates to the MUX circuitry to stop selecting to transmit the random bit stream and to start selecting to transmit the service data.

[0208] (6) The control bitstream generating circuit sends a second control bitstream, and the second control bitstream is used to indicate the receiving end to turn on PL_RX.

[0209] In some embodiments, when indicating to the first clock gating circuit to begin transmitting the clock signal, the monitor may further indicate to the control bitstream generation circuit to transmit a second control bitstream.

[0210] In some embodiments, the second control bitstream includes multiple repeat marker identifiers, a second marker end identifier, and a second bitstream content, where the second bitstream content indicates to the receiving end to turn on PL_RX. The second bitstream content is used to indicate to turn off the physical layer circuitry. The second marker end identifier is used to indicate the position of the end bit of the second control bitstream. The multiple repeat marker identifiers are used to indicate that the second control bitstream is a different control bitstream from the service data bitstream.

[0211] (7) Upon determining that the transmission of the second control bitstream is complete, the monitor indicates to the MUX circuit to begin transmitting the service data.

[0212] In some embodiments, the monitor determines that the transmission of the second control bitstream is complete when the control bitstream generation circuit determines that the interval from the time that the control bitstream generation circuit completed the transmission of the last data piece of the second control bitstream exceeds a certain time period. In this case, the monitor may indicate to the MUX circuit to select the service data received from PL_RX to be transmitted to the SerDes TX. The SerDes TX converts the parallel service data to serial data and then transmits the serial data to the link.

[0213] (8) The SerDes RX converts the received serial service data into parallel data, and then sends the parallel data to the bitstream detection module.

[0214] (9) The bitstream detection module continuously detects the bitstream output by the SerDes RX, and when a second control bitstream is identified, indicates to the second clock gating circuit to send a clock signal to the PL_RX.

[0215] Specifically, the bitstream detection module indicates to the second clock gating circuit to turn on a subcircuit of PL_RX.

[0216] (10) The second clock gating circuit starts sending the clock signal to PL_RX.

[0217] (11) The bitstream detection circuit sends the service data received after the second control bitstream to PL_RX.

[0218] (12) The PL_RX performs physical layer decoding, descrambling, and the like on the received service data, and then outputs the processed service data to the DL_RX.

[0219] In this way, in the present application, the monitor, the clock gating circuit, the control bitstream generating circuit, the bitstream detecting circuit, and other circuits cooperate with each other to avoid the waste of power that occurs when the physical layer circuit is still working when the high-speed serial interface does not transmit service data within a short period of time. In the present application, during the period when no service data is transmitted on the link within a short period of time, the transmitter circuit of the PL at the transmitting end can be controlled to be turned off, and the receiver circuit of the PL at the receiving end can be controlled to be turned off, so as to reduce the power consumption of the link. The first control bitstream and the second control bitstream correspond to a switch for controlling the PL layer circuit. The response speed of the switch is usually several ns, which is much faster than the switching speed of low power states such as L0s, L1, or L2 in PCIe. This solves the problem that the entry and exit process takes a long time when the power is switched by the high-speed serial interface.

[0220] In addition, in this application, assuming that the transmitting end and the receiving end in the embodiment are respectively the SoC and the network interface card, it should be understood that in the direction in which the SoC transmits data to the network interface card, the transmitter circuit of the PL in the SoC may be controlled to be off or on, and the receiver circuit of the PL in the network interface card may be controlled to be off or on. In addition, the SoC may alternatively function as the receiving end, and the network interface card functions as the transmitting end. In this application, in the direction in which the network interface card transmits data to the SoC, the transmitter circuit of the PL in the network interface card may also be controlled to be off or on, and the receiver circuit of the PL in the SoC may also be controlled to be off or on. Specifically, in this application, the architecture and process of turning on or off the physical layer circuit in the transmitting direction are completely independent from those in the receiving direction on one side. In this application, in the task execution phase, the service data transmission status in the transmitting direction and the receiving direction on one side may be distinguished. Specifically, the transmitting direction and the receiving direction in the link may be independently monitored, and the physical layer circuit in the transmitting direction or the receiving direction may be independently controlled. In other words, the transmit and receive directions of a link can be enabled or disabled in parallel and independently without affecting each other. However, with conventional physical layer power switching, the directions cannot be distinguished. Specifically, in conventional schemes, turning on or off physical layer circuitry is equivalent to turning off both the transmitter and receiver circuitry at one side of the physical layer.

[0221] The following further describes the implementation of the first control bitstream, the second control bitstream and the random bitstream in the present application.

[0222] Control Bitstream From the above description, it can be understood that the first control bit stream in this application can be used to indicate to the receiving end that the transmission of service data is completed, and the receiving end can turn off the partial circuit of PL_RX. When the transmitting end resumes the transmission of service data, the second control bit stream is used to indicate to the receiving end that the transmitting end has started or will start transmitting the service data, and the receiving end can turn on the partial circuit of PL_RX.

[0223] In this application, the first control bit stream and the second control bit stream may be uniquely identified by the physical layer and have a certain bit error tolerance capability after being transmitted over the link, ensuring that the bit stream can still be accurately identified when a bit error occurs. In addition, the bit stream includes an instruction to turn on or off a partial circuit of the physical layer. The structure and content of the control bit stream are not limited in this application.

[0224] It is noted that the first control bit stream and the second control bit stream in the present application may further have error detection and error correction capabilities to ensure that the receiving end can correctly identify the first control bit stream and the second control bit stream when bit errors occur during transmission over the link.

[0225] In addition, it should be understood that the first control bitstream and the second control bitstream in this application need to be distinguished from service data.

[0226] In some embodiments, a structure of a control bitstream that meets the above requirements may be shown in Table 1.

[0227] [Table 1]

[0228] Specifically, the control bitstream includes multiple fields: N+1 repeat marker identifiers, a marker end identifier, and a bitstream content (marker payload), where N is an integer equal to or greater than 0.

[0229] The N+1 repeat marker identifiers are marker identifier 0, marker identifier 1, ..., and marker identifier N in Figure 9. The N+1 repeat marker identifiers are used to identify whether the current data is a control bitstream.

[0230] In order to ensure that the control bitstream has a certain error tolerance capability, the marker identifier may be constructed using a Hamming code. At the receiving end, a bitstream detection circuit may perform error detection and error correction on the received control bitstream according to the detection and error correction principles of the Hamming code to ensure that the control bitstream is distinguished from multiple bitstreams.

[0231] The marker end identifier is used to indicate that the control bitstream has ended. When the receiving end receives the marker end identifier, the receiving end will end receiving the control bitstream after it next receives the bitstream content.

[0232] The bitstream content is used to indicate that the current control bitstream is used to turn off the physical layer circuitry or to turn on the physical layer circuitry. The bitstream content may be constructed using Hamming codes. Different Hamming codes indicate turning on or off partial circuits of the physical layer, for example turning on or off the FEC circuitry and the scrambling / descrambling circuitry.

[0233] For example, when the eBCH (extended Bose Ray-Chaudhuri Hocquenghem) code is used in this application, it is assumed that eBCH-16 is specifically used. eBCH-16 includes BCH(15,5) and 1 parity check bit. The payload part of BCH(15,5) includes 5 bits, and the code length is 15 bits. The generating polynomial of the eBCH code is g BCH(15,5) (x)=x 10 +x 8 +x 5 +x 4 +x 2 +x+x+1. The full eBCH codeword set contains a total of 32 codewords. Table 2 shows the BCH(15,5) codeword set.

[0234] [Table 2A] [Table 2B]

[0235] During the transmission of the first control bit stream or the second control bit stream, the balance between 0 and 1 (the number of 0 and the number of 1 in the data transmitted in a unit time are balanced) needs to be further considered. After the encoding result is obtained using the BCH(15,5) codeword set, a codeword with balanced 0 and 1 can be determined based on the codeword set that satisfies the DC balance in Table 3.

[0236] [Table 3]

[0237] When the control bit stream generating circuit generates a code similar to the original BCH Code, in order to balance the number of 0s and the number of 1s in the encoded data, the balance adjustment between 0s and 1s can be performed using a Non-Return to Zero (NRZ) or Level Pulse Amplitude Modulation (PAM) 4 code pattern. Each symbol of the PAM4 code pattern represents 2 bits. For example, when NRZ is used, if the pre-modulation code word is 01000111_10101100, the modulation code word obtained by adjustment based on the position correspondence between (43275160_75432160) and (76543210_76543210) in NRZ is 00100111_11011000.

[0238] The following provides an example of a control bitstream, see Table 4.

[0239] [Table 4]

[0240] Referring to Table 4, Symbol Number indicates the number of symbols occupied by each type of descriptive information. In this example, the following is written. The codewords used for Marker identify, i.e., marker identifier, are CW21 and CW28 in Table 2, the codewords used for Marker END, i.e., marker end identifier, are CW22 and CW3, and the codewords used for Marker Payload, i.e., marker content, are CW3 and CW8. When the content of the control bitstream indicates that the physical layer circuit is turned off (closed), the codewords used for the marker content are CW23 and CW3. When the content of the control bitstream indicates that the physical layer circuit is turned on (open), the codewords used for the marker content are CW28 and CW8. After the codewords used for the control bitstream are determined, the positions of 0 and 1 in the codewords can be adjusted based on the modulation codeword set shown in Table 3, in which 0 and 1 are balanced.

[0241] Random Bit Stream From the above description, it can be seen that the random bit stream is sent after the transmitting end sends the first control bit stream to ensure that the SerDes in the link continues to input a bit stream after the PL_TX stops sending service data. This can avoid an exception occurring when the SerDes at the receiving end receives data if the SerDes does not send a bit stream. In this way, the CDR in the SerDes remains in a locked state.

[0242] In this application, for the generation of random bit streams, randomness needs to be guaranteed and the amount of 0's and 1's needs to be balanced.

[0243] In some embodiments, the random bit stream generation circuitry is configured to generate a random bit stream based on a polynomial G(X)=X 23 +X 21 +X 16 +X8 +X 5 +X 2 +1 may be used to generate a pseudorandom bit stream. A segment of data within the pseudorandom bit stream is considered to be the random bit stream transmitted in this application.

[0244] Of course, the control bitstream and the random bitstream in this application may alternatively be implemented in other manners, which is not a limitation of this application.

[0245] To implement the aforementioned functions, it can be understood that the high-speed serial interface includes corresponding hardware and / or software modules for performing the functions. With reference to the algorithms and steps in the examples described in the embodiments disclosed herein, the present application may be implemented in the form of hardware or a combination of hardware and computer software. Whether the functions are implemented by hardware or by hardware driven by computer software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the functions described for each specific application with reference to the embodiments. However, the implementation should not be considered to go beyond the scope of the present application.

[0246] In an embodiment, the high-speed serial interface may be divided into functional modules based on the above-mentioned method example. For example, each functional module may be obtained by dividing the corresponding function, or two or more functions may be integrated into one processing module. The integrated module may be implemented in the form of hardware. It should be noted that in the embodiment, the division into modules is an example, and is merely a logical division of functions. In actual implementation, another division method may be used.

[0247] When each functional module is obtained by dividing the corresponding function, FIG. 13 is a schematic diagram of a possible configuration of the network device 130 in the above embodiment. The network device may include a serial interface circuit. As shown in FIG. 13, when the network device includes a transmitting end and a receiving end for transmitting a bit stream, for example, the transmitting end is a SoC in the above description, and the receiving end is a network interface card in the above description. The network device 130 may include a determining unit 1301, a bit stream generating unit 1302, a first control unit 1303, a sending unit 1304, a receiving unit 1305, a detecting unit 1306, and a second control unit 1307.

[0248] The determining unit 1301 may be configured to support the network device 130 in performing the above process of determining that the high-speed serial interface stops or resumes transmitting service data and / or another process of the techniques described herein. The determining unit 1301 corresponds to the function of a monitor in this application.

[0249] The bitstream generation unit 1302 may be configured to support the network device 130 in performing the aforementioned processes of generating a first control bitstream, a second control bitstream, a random bitstream, etc., and / or another process of the techniques described herein. The bitstream generation unit 1302 equivalently includes the functions of a control bitstream generation circuit and a random bitstream generation circuit in this application.

[0250] The first control unit 1303 may be configured to support the network device 130 in performing the aforementioned processes, such as generating and transmitting a clock signal at the transmitting end, and / or other processes of the techniques described herein. The first control unit 1303 equivalently includes the function of a clock gating circuit at the transmitting end in this application.

[0251] The transmitting unit 1304 may be configured to support the network device 130 in performing the aforementioned process of transmitting the first control bit stream, the second control bit stream, the random bit stream, service data, etc., and / or another process of the techniques described herein. The transmitting unit 1304 includes the functionality of a transmitter circuit of a SerDes in this application.

[0252] The receiving unit 1305 may be configured to support the network device 130 in performing the aforementioned process of receiving a first control bit stream, a second control bit stream, a random bit stream, service data, etc., and / or another process of the techniques described herein. The receiving unit 1305 includes the functionality of a receiver circuit of a SerDes in this application.

[0253] The detection unit 1306 may be configured to support the network device 130 in performing the aforementioned processes of detecting the first control bit stream, the second control bit stream, the random bit stream, and the like.

[0254] The second control unit 1307 may be configured to support the network device 130 in performing the aforementioned processes, such as generating and transmitting a clock signal at the receiving end, and / or other processes of the techniques described herein. The second control unit 1307 equivalently includes the function of a clock gating circuit at the receiving end in this application.

[0255] It should be noted that all the relevant contents of the steps in the above method embodiments can be cited in the functional description of the corresponding functional modules, and the details are not repeated here.

[0256] The network device 130 provided in this embodiment is configured to perform the aforementioned data transmission method, and can thus achieve the same effects as the method of the aforementioned embodiment.

[0257] When an integrated unit is used, the network device 130 may include a processing module, a storage module, and a communication module. The processing module may be configured to control and manage the operation of the network device 130. For example, the processing module may be configured to support the network device 130 in performing steps performed by the determining unit 1301, the bitstream generating unit 1302, the first control unit 1303, the detecting unit 1306, and the second control unit 1307. The storage module may be configured to support the network device 130 in storing program code, data, etc. The communication module may be configured to support communication between a transmitting end and a receiving end in the network device 130. In the present application, the communication module may be configured to support the network device 130 in performing steps performed by the transmitting unit 1304 and the receiving unit 1305.

[0258] The processing module may be a processor or a controller. The processing module may implement or execute various exemplary logic blocks, modules, and circuits described with reference to the disclosed subject matter of this application. The processor may alternatively be a combination of processors implementing computing functions, such as a combination including one or more microprocessors, or a combination of a digital signal processing (DSP) and a microprocessor. The storage module may be a memory. The communication module may specifically be a circuit, such as a SerDes.

[0259] An embodiment of the present application further provides an electronic device including one or more processors and one or more memories. The one or more memories are coupled to the one or more processors. The one or more memories are configured to store computer program code, and the computer program code includes computer instructions. When the one or more processors execute the computer instructions, the electronic device is enabled to perform the relevant method steps described above to implement the data transmission method in the above embodiment.

[0260] An embodiment of the present application further provides a computer storage medium, which stores computer instructions, which, when executed on an electronic device, enable the electronic device to perform the relevant method steps described above to implement the data transmission method in the above embodiment.

[0261] An embodiment of the present application further provides a computer program product, which, when executed on a computer, enables the computer to execute the relevant steps described above to implement the data transmission method performed by the electronic device including the high-speed serial interface in the above embodiment.

[0262] In addition, an embodiment of the present application further provides an apparatus. The apparatus may specifically be a chip, a component, or a module. The apparatus may include a processor and a memory connected to each other. The memory is configured to store computer-executable instructions. When the apparatus operates, the processor may execute the computer-executable instructions stored in the memory, so that the chip executes the data transmission method executed by the electronic device including the high-speed serial interface in the embodiment of the method described above.

[0263] The electronic device, computer storage medium, computer program product, or chip provided in the embodiment is configured to execute the corresponding method provided above. Therefore, for the beneficial effects that can be achieved by the electronic device, computer storage medium, computer program product, or chip, please refer to the beneficial effects of the corresponding method provided above. Details are not repeated here.

[0264] Based on the description of the above embodiments, those skilled in the art can understand that for the purpose of convenient and concise description, the above division into functional modules is only used as an example for illustration. In actual application, the above functions can be assigned to different functional modules and implemented as needed. In other words, the internal structure of the device is divided into different functional modules to implement all or part of the functions described above.

[0265] In the embodiments provided in this application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the described apparatus embodiments are merely examples. For example, the division into modules or units is merely a logical division of functions, and may be divided in other ways in actual implementation. For example, multiple units or components may be combined or integrated into another apparatus, and some features may be ignored or not implemented. In addition, the illustrated or described mutual couplings or direct couplings or communication connections may be implemented through some interfaces. Indirect couplings or communication connections between apparatuses or units may be implemented in electrical, mechanical, or other forms.

[0266] The units described as separate parts may or may not be physically separated, and the parts shown as units may be one or more physical units, i.e., located in one place or distributed in multiple different places. Some or all of the units may be selected according to actual requirements to achieve the objectives of the solutions of the embodiments.

[0267] In addition, the functional units in the embodiments of the present application may be integrated into one processing unit, and each of the units may exist physically alone, or two or more units may be integrated into one unit. The integrated unit may be implemented in the form of hardware or in the form of a software functional unit.

[0268] When the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, the integrated unit may be stored in a readable storage medium. Based on such understanding, the technical solutions in the embodiments of the present application essentially, or the part contributing to the prior art, or all or part of the technical solutions may be implemented in the form of a software product. The software product is stored in a storage medium and includes some instructions for instructing a device (which may be a single-chip microcomputer, chip, etc.) or a processor to execute all or part of the steps of the method of the embodiments of the present application. The storage medium includes any medium that can store program code, such as a USB flash drive, a removable hard disk drive, a read only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0269] The above description is merely a specific embodiment of the present application, and is not intended to limit the scope of protection of the present application. Any variations or replacements that are easily conceived by those skilled in the art within the technical scope disclosed in the present application shall be within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be subject to the scope of protection of the claims. [Explanation of symbols]

[0270] 130 Network Devices 1301 Judgment Unit 1302 Bitstream Generation Unit 1303 First Control Unit 1304 Transmitter Unit 1305 receiving unit 1306 Detection Unit 1307 Second Control Unit

Claims

1. A high-speed serial interface, comprising: a physical layer circuit at a transmitting end; a monitor; a clock gating circuit; a control bit stream generating circuit; a random bit stream generating circuit; and a serializer / deserializer; The monitor is configured to indicate to the clock gating circuit that the clock signal is stopped from being sent to a partial module in the physical layer circuit of the transmitting end when the transmitting end is not sending service data; The clock gating circuit is configured to stop transmission of the clock signal to the partial module in the physical layer circuit of the transmitting end; the control bitstream generating circuit is configured to transmit a first control bitstream through the serializer / deserializer when it is determined that the clock gating circuit has stopped transmitting the clock signal, and the first control bitstream is used to indicate that the transmitting end has turned off the partial module in the physical layer circuit of the transmitting end, or the first control bitstream is used to indicate that the transmitting end should turn off the partial module in the physical layer circuit of the transmitting end, or the first control bitstream is used to indicate that the receiving end should turn off the partial module in the physical layer circuit of the receiving end; the random bit stream generation circuit is configured to transmit a random bit stream to the serializer / deserializer; High speed serial interface.

2. The partial module in the physical layer circuit of the transmitting end includes at least one of a forward error correction (FEC) encoding circuit or a scrambling circuit; The partial module in the physical layer circuit of the receiving end includes at least one of an FEC decoding circuit or a descrambling circuit; 2. The high speed serial interface of claim 1.

3. The high-speed serial interface further includes a data link layer at the transmitting end, and the monitor further includes: monitoring whether the data link layer of the transmitting end transmits service data to the physical layer circuit of the transmitting end; If it is determined that the data link layer of the transmitting end does not transmit the service data to the physical layer circuit of the transmitting end, it is determined that the transmitting end does not transmit the service data.

3. A high-speed serial interface according to claim 1 or 2, specially adapted for:

4. The monitor, When it is determined that the clock gating circuit has stopped transmitting the clock signal to a partial module in the physical layer circuit of the transmitting end, a first signal is sent to the control bitstream generating circuit, and the first signal is used to indicate the control bitstream generating circuit to send the first control bitstream; sending a second signal to the random bit stream generation circuit when it is determined that the control bit stream generation circuit has completed transmitting the first control bit stream, the second signal being used to indicate to the random bit stream generation circuit to transmit the random bit stream.

4. A high-speed serial interface according to claim 1, further configured to:

5. The monitor is further configured to, when the transmitting end resumes transmitting the service data, indicate to the clock gating circuit to transmit the clock signal to the partial module in the physical layer circuit of the transmitting end; The clock gating circuit is further configured to transmit the clock signal to the partial module in the physical layer circuit of the transmitting end; the random bit stream generation circuit is further configured to stop transmitting the random bit stream when it is determined that the clock gating circuit has started transmitting the clock signal; The control bitstream generating circuit is further configured to, when it is determined that the transmitting end resumes transmitting the service data, send a second control bitstream through the serializer / deserializer, and the second control bitstream is used to indicate that the transmitting end has turned on the partial module in the physical layer circuit of the transmitting end, or the second control bitstream is used to indicate that the transmitting end turns on the partial module in the physical layer circuit of the transmitting end, or the second control bitstream is used to indicate the receiving end to turn on the partial module in the physical layer circuit of the receiving end; the physical layer circuit of the transmitting end is configured to initiate transmission of the service data through the serializer / deserializer; 5. A high-speed serial interface according to any one of claims 1 to 4.

6. the first control bit stream includes a plurality of repeated bit stream identifiers, a first marker end identifier, and a first bit stream content, the first bit stream content is used to indicate that the transmitting end has turned off the partial module in the physical layer circuit of the transmitting end, or the first control bit stream is used to indicate that the transmitting end turns off the partial module in the physical layer circuit of the transmitting end, or the first control bit stream is used to indicate the receiving end to turn off the partial module in the physical layer circuit of the receiving end, and the first marker end identifier is used to indicate the position of an end bit of the first control bit stream; the second control bit stream includes a plurality of repeat bit stream identifiers, a second marker end identifier, and a second bit stream content, the second bit stream content is used to indicate that the transmitting end has turned on the partial module in the physical layer circuit of the transmitting end, or the second control bit stream is used to indicate that the transmitting end turns on the partial module in the physical layer circuit of the transmitting end, or the second control bit stream is used to indicate the receiving end to turn on the partial module in the physical layer circuit of the receiving end, and the second marker end identifier is used to indicate the position of an end bit of the second control bit stream; The random bit stream is used to enable a clock and data recovery CDR circuit in the serializer / deserializer to be in a locked state, the random bit stream containing a balanced amount of 0's and 1's.

6. The high speed serial interface according to claim 5.

7. A high-speed serial interface, comprising: a physical layer circuit at a receiving end; a bit stream detection circuit; a clock gating circuit; and a serializer / deserializer; The bitstream detection circuit is configured to receive a first control bitstream through the serializer / deserializer, and the first control bitstream is used to indicate that a transmitting end has turned off a partial module in a physical layer circuit of the transmitting end, or the first control bitstream is used to indicate that the transmitting end turns off a partial module in the physical layer circuit of the transmitting end, or the first control bitstream is used to indicate the receiving end to turn off a partial module in the physical layer circuit of the receiving end; The bitstream detection circuit is further configured to indicate to the clock gating circuit that the bitstream detection circuit stops sending a clock signal to the partial module in the physical layer circuit of the receiving end; The clock gating circuit is configured to stop transmission of the clock signal to the partial module in the physical layer circuit of the receiving end; the bitstream detection circuit is further configured to receive a random bitstream via the serializer / deserializer. High speed serial interface.

8. The partial module in the physical layer circuit of the transmitting end includes at least one of a forward error correction (FEC) encoding circuit or a scrambling circuit; The partial module in the physical layer circuit of the receiving end includes at least one of an FEC decoding circuit or a descrambling circuit; 8. The high speed serial interface of claim 7.

9. the high speed serial interface further comprises a data link layer at the receiving end; The clock gating circuit is specifically configured to stop sending the clock signal to the partial module in the physical layer circuit of the receiving end when it is determined that an interval from the last time that the physical layer circuit of the receiving end transmits service data to the data link layer of the receiving end exceeds a preset time period.

9. A high-speed serial interface according to claim 7 or 8.

10. The bitstream detection circuit is further configured to control the serializer / deserializer to receive a second control bitstream, and when the second control bitstream is used to indicate that the transmitting end has turned on the partial module in the physical layer circuit of the transmitting end, or when the second control bitstream is used to indicate that the transmitting end turns on the partial module in the physical layer circuit of the transmitting end, or when the second control bitstream is used to indicate the receiving end to turn on the partial module in the physical layer circuit of the receiving end, indicate to the clock gating circuit to send the clock signal to the partial module in the physical layer circuit of the receiving end; The clock gating circuit is further configured to transmit the clock signal to the partial module in the physical layer circuit of the receiving end; The bitstream detection circuit is further configured to send the service data received from the serializer / deserializer to the physical layer circuit at the receiving end.

10. A high-speed serial interface according to any one of claims 7 to 9.

11. the first control bit stream includes a plurality of repeat marker identifiers, a first marker end identifier, and a first bit stream content, the first bit stream content is used to indicate that the transmitting end has turned off the partial module in the physical layer circuit of the transmitting end, or the first control bit stream is used to indicate that the transmitting end turns off the partial module in the physical layer circuit of the transmitting end, or the first control bit stream is used to indicate the receiving end to turn off the partial module in the physical layer circuit of the receiving end, and the first marker end identifier is used to indicate the position of an end bit of the first control bit stream; The second control bit stream includes a plurality of repeat marker identifiers, a second marker end identifier, and a second bit stream content, the second bit stream content is used to indicate that the transmitting end has turned on the partial module in the physical layer circuit of the transmitting end, or the second control bit stream is used to indicate that the transmitting end turns on the partial module in the physical layer circuit of the transmitting end, or the second control bit stream is used to indicate the receiving end to turn on the partial module in the physical layer circuit of the receiving end, and the second marker end identifier is used to indicate the position of an end bit of the second control bit stream; the random bit stream is used to enable a clock and data recovery CDR circuit in the serializer / deserializer to remain in a locked state, the random bit stream containing a balanced amount of 0's and 1's; the bitstream detection circuitry is further configured to discard the random bitstream when the random bitstream is identified.

11. The high speed serial interface of claim 10.

12. A data transmission method applied to a high-speed serial interface, the high-speed serial interface having a physical layer circuit at a transmitting end, the method comprising: sending a first control bit stream by the transmitting end when the transmitting end does not transmit service data, the first control bit stream being used to indicate that the transmitting end has turned off a partial module in the physical layer circuit of the transmitting end, or the first control bit stream being used to indicate that the transmitting end turns off a partial module in the physical layer circuit of the transmitting end, or the first control bit stream being used to indicate the receiving end to turn off a partial module in the physical layer circuit of the receiving end; turning off, by the transmitting end, the partial module in the physical layer circuit of the transmitting end; transmitting a random bit stream by the transmitting end; A data transmission method comprising:

13. The partial module in the physical layer circuit of the transmitting end includes at least one of a forward error correction (FEC) encoding circuit or a scrambling circuit; The partial module in the physical layer circuit of the receiving end includes at least one of an FEC decoding circuit or a descrambling circuit; The method of claim 12.

14. the high-speed serial interface further comprises a data link layer at the transmitting end; The transmitting end does not transmit service data. When the data link layer of the transmitting end does not transmit the service data to the physical layer circuit of the transmitting end, the transmitting end determines that the transmitting end does not transmit the service data. The method of claim 12 or 13, comprising:

15. the high speed serial interface further comprising a serializer / deserializer, sending a second control bit stream by the transmitting end when the transmitting end resumes transmitting the service data, the second control bit stream being used to indicate that the transmitting end has turned on the partial module in the physical layer circuit of the transmitting end, or the second control bit stream being used to indicate that the transmitting end turns on the partial module in the physical layer circuit of the transmitting end, or the second control bit stream being used to indicate the receiving end to turn on the partial module in the physical layer circuit of the receiving end; turning on, by the transmitting end, the partial module in the physical layer circuit of the transmitting end; controlling, by the transmitting end, the physical layer circuit of the transmitting end to transmit the service data to the serializer / deserializer; 15. The method of any one of claims 12 to 14, further comprising:

16. the first control bit stream includes a plurality of repeated bit stream identifiers, a first marker end identifier, and a first bit stream content, the first bit stream content is used to indicate that the transmitting end has turned off the partial module in the physical layer circuit of the transmitting end, or the first control bit stream is used to indicate that the transmitting end turns off the partial module in the physical layer circuit of the transmitting end, or the first control bit stream is used to indicate the receiving end to turn off the partial module in the physical layer circuit of the receiving end, and the first marker end identifier is used to indicate the position of an end bit of the first control bit stream; the second control bit stream includes a plurality of repeat bit stream identifiers, a second marker end identifier, and a second bit stream content, the second bit stream content is used to indicate that the transmitting end has turned on the partial module in the physical layer circuit of the transmitting end, or the second control bit stream is used to indicate that the transmitting end turns on the partial module in the physical layer circuit of the transmitting end, or the second control bit stream is used to indicate the receiving end to turn on the partial module in the physical layer circuit of the receiving end, and the second marker end identifier is used to indicate the position of an end bit of the second control bit stream; The random bit stream is used to enable a clock and data recovery CDR circuit in the serializer / deserializer to be in a locked state, the random bit stream containing a balanced amount of 0's and 1's. The method of claim 15.

17. A data transmission method applied to a high-speed serial interface, the high-speed serial interface having a physical layer circuit at a receiving end, the method comprising: receiving a first control bit stream by the receiving end, the first control bit stream being used to indicate that the transmitting end has turned off a partial module in the physical layer circuit of the transmitting end, or the first control bit stream being used to indicate that the transmitting end turns off a partial module in the physical layer circuit of the transmitting end, or the first control bit stream being used to indicate the receiving end to turn off a partial module in the physical layer circuit of the receiving end; turning off, by the receiving end, the partial module in the physical layer circuit of the receiving end; receiving a random bit stream by the receiving end; A data transmission method comprising:

18. The partial module in the physical layer circuit of the transmitting end includes at least one of a forward error correction (FEC) encoding circuit or a scrambling circuit; The partial module in the physical layer circuit of the receiving end includes at least one of an FEC decoding circuit or a descrambling circuit; 20. The method of claim 17.

19. the high speed serial interface further comprising a serializer / deserializer, controlling, by the receiving end, the serializer / deserializer to receive a second control bit stream, wherein the second control bit stream is used to indicate that the transmitting end has turned on the partial module in the physical layer circuit of the transmitting end, or the second control bit stream is used to indicate that the transmitting end turns on the partial module in the physical layer circuit of the transmitting end, or the second control bit stream is used to indicate the receiving end to turn on the partial module in the physical layer circuit of the receiving end; turning on, by the receiving end, the partial module in the physical layer circuit of the receiving end; controlling, by the receiving end, the physical layer circuit of the receiving end to receive the service data transmitted through the serializer / deserializer; 19. The method of claim 17 or 18, further comprising:

20. the first control bit stream includes a plurality of repeat marker identifiers, a first marker end identifier, and a first bit stream content, the first bit stream content is used to indicate that the transmitting end has turned off the partial module in the physical layer circuit of the transmitting end, or the first control bit stream is used to indicate that the transmitting end turns off the partial module in the physical layer circuit of the transmitting end, or the first control bit stream is used to indicate the receiving end to turn off the partial module in the physical layer circuit of the receiving end, and the first marker end identifier is used to indicate the position of an end bit of the first control bit stream; The second control bit stream includes a plurality of repeat marker identifiers, a second marker end identifier, and a second bit stream content, the second bit stream content is used to indicate that the transmitting end has turned on the partial module in the physical layer circuit of the transmitting end, or the second control bit stream is used to indicate that the transmitting end turns on the partial module in the physical layer circuit of the transmitting end, or the second control bit stream is used to indicate the receiving end to turn on the partial module in the physical layer circuit of the receiving end, and the second marker end identifier is used to indicate the position of an end bit of the second control bit stream; the random bit stream is used to enable a clock and data recovery CDR circuit in the serializer / deserializer to be in a locked state, the random bit stream containing a balanced amount of 0's and 1's; The method further comprises discarding the random bit stream when the random bit stream is identified.

20. The method of claim 19.

21. 17. A computer readable storage medium comprising computer instructions which, when executed on an electronic device, enable the electronic device to perform the method of any one of claims 12 to 16.

22. 21. A computer readable storage medium comprising computer instructions which, when executed on an electronic device, enable the electronic device to perform the method of any one of claims 17 to 20.

Images