DC Series RF Parallel PIN Diode Switch

Abstract

The present disclosure describes systems, methods, and apparatus for a PIN diode switch comprising: series connected PIN diodes comprising two or more PIN diodes connected in series, each having a first node and a second node; an internal node located where a first node of a first PIN diode connects to a second node of a second adjacent PIN diode; an RF bypass capacitor connected between a reference node and a first end of the series connected PIN diodes, the second end of the series connected PIN diode being connected to the reference node; an RF circuit connected between the reference node and the internal node; and a PIN diode driver connected across the RF bypass capacitor.

Description

[Technical field]

[0001] (Claim of priority under 35 U.S.C. Section 119) This application for patent claims priority to Provisional Application No. 63 / 297,071, filed January 6, 2022, and entitled "DC SERIES RF PARALLEL PIN DIODE SWITCH," which is assigned to the assignee of the present application and is expressly incorporated by reference herein.

[0002] The present disclosure relates generally to diode switch circuits and, more particularly, but not by way of limitation, to PIN diode switch circuits that utilize a DC series RF parallel arrangement of two or more PIN diodes. [Background technology]

[0003] Description of Related Art A PIN diode is an electrical device that has an undoped or lightly doped intrinsic (I) semiconductor region sandwiched between heavily doped regions and has a variety of uses, for example, as a switching device in impedance matching networks, particularly radio frequency (RF) matching networks.

[0004] The "PIN" designation comes from the diode's three-part "sandwich" structure, i.e., a lightly doped intrinsic region (I) located between a heavily doped p-type semiconductor (P) and a heavily doped n-type semiconductor (N). In general, PIN diodes follow conventional diode behavior for low frequency input signals, but for higher frequency input signals, they operate as a resistor in the forward bias or on state and as a capacitor in the reverse bias or off state. Thus, PIN diodes are often utilized in radio frequency (RF) applications, for example, in attenuators and high speed switches where high isolation and low loss are desired. In some situations, PIN diodes can be turned on with a DC current that is a small fraction of the RF current being switched, and turned off by reverse biasing the PIN diode. PIN diodes are attractive switches because they combine low on-state resistance with very low off-state losses. In some cases, a PIN diode driver circuit may be used to turn a PIN diode on and off by conducting a DC current through the PIN diode and applying a reverse bias voltage across the PIN diode, respectively. In the off state, the PIN diode may be subjected to a high RF voltage. In a conventional PIN diode switch circuit, an RF blocking device (or RF choke) is placed between the PIN diode and the PIN diode driver circuit. Ideally, this RF blocking device should be designed to conduct DC current and withstand the high RF voltage applied across the PIN diode.

[0005] In one implementation, PIN diodes are used in an impedance matching network configured to match the varying load impedance of a plasma load to a desired impedance (e.g., 50 ohms) into which a high-power RF generator can deliver power. In such an implementation, the PIN diodes serve to rapidly modify the nature of the matching network by connecting or disconnecting a reactive component of the impedance matching network, typically a capacitor, switching reactive elements in and out of the network.

[0006] A major difficulty is to design an effective RF blocking device between the PIN diode driver and the PIN diode. The RF blocking device should carry high DC current, charge and discharge the PIN diode quickly, and provide low RF losses when subjected to high levels of RF voltage. For a new class of high speed drivers with energy recovery, the RF blocking device is a major impediment to PIN diode switch circuit performance. Thus, there is a need for an elaborated PIN diode switch circuit that does not require an RF blocking device to be subjected to high levels of RF voltage.

[0007] A description provided in the Description of Related Art section should not be considered prior art merely because it is mentioned in or associated with this section. The Description of Related Art section may include information that describes one or more aspects of the present technology. Summary of the Invention [Means for solving the problem]

[0008] The following presents a simplified summary related to one or more aspects and / or embodiments disclosed herein. As such, the following summary should not be considered an extensive overview related to all envisioned aspects and / or embodiments, nor should the following summary be considered to identify key or critical elements related to all envisioned aspects and / or embodiments or to delimit the scope associated with any particular aspect and / or embodiment. Thus, the following summary has the sole purpose of presenting certain concepts related to one or more aspects and / or embodiments related to the mechanisms disclosed herein in a simplified form prior to the detailed description presented below.

[0009] Aspects of the present disclosure relate generally to systems, methods, and apparatus for radio frequency (RF) switching circuits, and more specifically, for PIN diode switch circuits for high speed, high repetition rate, and / or high power applications. In one embodiment, the PIN diode switch circuit includes two or more PIN diodes connected in series between a first node and a reference node, and an RF bypass capacitor connected between the first node and the reference node. In some cases, a PIN diode driver is connected across the RF bypass capacitor. In some embodiments, the remainder of the RF circuitry is connected between an internal node of the series-connected PIN diodes (i.e., one that is intrinsic to the string of series-connected PIN diodes, e.g., a node between a first PIN diode and a second adjacent PIN diode) and the reference node.

[0010] In another embodiment, the PIN diode switch circuit includes two or more PIN diodes connected in series between a first node and a second node, a first RF bypass capacitor connected between the first node and a reference node, and a second RF bypass capacitor connected between the second node and the reference node. In addition, a first PIN diode driver is connected across the first RF bypass capacitor and a second PIN diode driver is connected across the second RF bypass capacitor. In some embodiments, the remainder of the RF circuitry (e.g., RF circuitry 318, 328, 338 of FIGS. 3A, 3B, and 3C, respectively) is connected between an internal node of the series-connected PIN diodes (i.e., one that is intrinsic to the string of series-connected PIN diodes, e.g., a node between a first PIN diode and a second adjacent PIN diode) and the reference node. In some embodiments, for example, with respect to a PIN diode driver circuit incorporating multiple PIN diode drivers, a DC-passing RF blocking circuit may be connected between an internal node (e.g., internal node 365 of FIG. 3F) and a reference node (e.g., reference node 367) to compensate for differences (if any) between the PIN diodes and / or PIN diode drivers. The PIN diode drivers may be selected from a class of two-stage PIN diode drivers with energy recovery, which may facilitate recovery of energy stored in the PIN diodes and / or RF bypass capacitors. In some cases, the PIN diode drivers may further incorporate one or more lower voltage reverse bias power supplies and associated switches to further limit losses, for example, associated with charge removal from the intrinsic region of the PIN diode when switching from an on state to an off state.

[0011] In some cases, aspects of the present disclosure help eliminate the need for RF blocking devices between the PIN diode driver and the PIN diode, and in other cases, reduce the requirements imposed on the RF blocking devices between the PIN diode driver and the PIN diode. The need for these RF blocking devices makes PIN diode switch-based matching networks unattractive in many applications because the RF blocking devices are an obstacle to high-speed drivers, are typically bulky, and are a major source of RF losses and therefore efficiency. By eliminating or dramatically reducing the design requirements imposed on the RF blocking devices (e.g., reducing the voltage across the RF blocking device by a factor of 30 or less and / or reducing the RF losses by a factor of 900 or less), tuning range and efficiency can be improved for PIN diode switch-based matching networks compared to prior art techniques.

[0012] Some other embodiments of the present disclosure can be characterized as variable impedance matching networks that include a variable reactance element, the variable reactance element including at least a PIN diode coupled to a capacitor.

[0013] In some aspects, the techniques described herein relate to an apparatus including series-connected PIN diodes, the series-connected PIN diodes comprising two or more PIN diodes connected in series between first ends and second ends and an internal node positioned between two of the two or more PIN diodes; a first radio frequency (RF) bypass capacitor connected between a reference node and the first ends of the series-connected PIN diodes, the second ends of the series-connected PIN diodes being connected to the reference node; an RF circuit connected between the reference node and the internal node; and a first PIN diode driver connected across the first RF bypass capacitor.

[0014] In some aspects, the techniques described herein relate to an apparatus in which the series-connected PIN diodes include an equal number of PIN diodes on either side of an internal node.

[0015] In some aspects, the techniques described herein relate to an apparatus in which a first PIN diode driver is configured to do one or more of: provide a current through the series-connected PIN diodes to turn on two or more PIN diodes; and provide a reverse bias voltage across the series-connected PIN diodes to turn off two or more PIN diodes. In some implementations of the apparatus, the magnitude of impedance presented to an RF circuit is greater when two or more PIN diodes are off compared to when two or more PIN diodes are on.

[0016] In some aspects, the techniques described herein relate to an apparatus, wherein the apparatus is connected to an RF impedance matching network that includes one or more reactive elements, in some implementations, the apparatus is further configured to connect or disconnect at least one of the one or more reactive elements to or from the remainder of the RF impedance matching network.

[0017] In some aspects, the techniques described herein relate to an apparatus in which a first PIN diode driver is a two-stage driver including a first resonant stage having a power supply, one or more switches and reactive elements for charging and discharging one or more of a first RF bypass capacitor, a series-connected PIN diode, and one or more capacitive elements in an RF circuit from and to a power supply, and a second holding stage. In some implementations, the second holding stage is configured to do one or more of: hold a reverse bias voltage across the series-connected PIN diode and supply a current through the series-connected PIN diode. In some examples, the series-connected PIN diode is in an off state when a reverse bias voltage is applied. In addition, the series-connected PIN diode is in an on state when a current is supplied through the series-connected PIN diode.

[0018] In some aspects, the techniques described herein relate to an apparatus including a second PIN diode driver, a second end of the series-connected PIN diode connected to a reference node through a second RF bypass capacitor, the apparatus further including a second PIN diode driver connected across the second RF bypass capacitor.

[0019] In some aspects, the techniques described herein relate to an apparatus in which the second PIN diode driver is a complementary PIN diode driver that produces a voltage and current of opposite polarity to the first PIN diode driver.

[0020] In some aspects, the techniques described herein relate to an apparatus further including a device (e.g., a DC-passing RF blocking device) connected between the internal node and the reference node, the DC-passing RF blocking device presenting low resistance to DC current and a large magnitude of impedance to RF current. In some examples, the device (i.e., the DC-passing RF blocking device) is selected from the group consisting of an inductor, a parallel combination of an inductor and a capacitor, and a quarter RF wavelength long transmission line. Other types of DC-passing RF blocking devices are also contemplated in different embodiments, and the examples listed herein are not intended to be limiting.

[0021] In some aspects, the techniques described herein relate to an apparatus in which the first RF bypass capacitor includes a plurality of capacitors connected in series, the apparatus further including a plurality of DC-passing RF blocking devices connected between an internal node of the plurality of series-connected capacitors and an internal node of the series-connected PIN diodes. In some implementations, one or more of the plurality of DC-passing RF blocking devices present a low resistance to DC current and a large magnitude of impedance to RF current. Some non-limiting examples of such devices (i.e., DC-passing RF blocking devices) include inductors, parallel combinations of inductors and capacitors, and quarter RF wavelength long transmission lines (i.e., λ / 4 transmission lines).

[0022] In some aspects, techniques described herein relate to a method for driving series-connected PIN diodes (also referred to as PIN diodes in series), including two or more PIN diodes connected in series between a first end and a second end, in a PIN diode switch, the method including: providing a current through the series-connected PIN diodes to forward bias and turn on the series-connected PIN diodes, where RF circuitry is coupled between a reference node and an internal node, a first RF bypass capacitor is connected between a first end of the series-connected PIN diodes and the reference node, and the internal node is positioned between two of the two or more PIN diodes; and providing a reverse bias voltage across the series-connected PIN diodes to turn off the series-connected PIN diodes. In some implementations of the method, when the series-connected PIN diodes are on, a first impedance is presented to the RF circuitry, and when the series-connected PIN diodes are off, a second impedance is presented to the RF circuitry. In some implementations of the method, the magnitude of the second impedance is greater than the magnitude of the first impedance.

[0023] In some aspects, the techniques described herein relate to a method in which the second ends of the series-connected PIN diodes are coupled to a reference node.

[0024] In some aspects, the techniques described herein relate to a method in which a second end of the series-connected PIN diode is coupled to a reference node via a second RF bypass capacitor.

[0025] In some aspects, the techniques described herein relate to a method in which a first PIN diode driver is connected across a first RF bypass capacitor and a second PIN diode driver is connected across a second RF bypass capacitor.

[0026] In some aspects, the techniques described herein relate to methods in which the second PIN diode driver is a complementary PIN diode driver that produces a voltage and a current with an opposite polarity to the first PIN diode driver.

[0027] In some aspects, the techniques described herein relate to methods that further include charging and discharging one or more of a first RF bypass capacitor, a series connected PIN diode, and one or more capacitive elements in the RF circuitry from and to a power supply of a first resonant stage of a two-stage driver that is coupled across the first RF bypass capacitor.

[0028] In some aspects, the techniques described herein relate to a method further including holding a reverse bias voltage across the series connected PIN diodes via a holding stage of a two-stage driver, which is connected across the first RF bypass capacitor.

[0029] In some aspects, the techniques described herein relate to a method further including providing current through a series-connected PIN diode via a holding stage of a two-stage driver, the series-connected PIN diode being connected across the first RF bypass capacitor.

[0030] In some aspects, the techniques described herein relate to methods that further include disconnecting at least one reactive element in the impedance matching network when the series-connected PIN diode is off.

[0031] In some aspects, the techniques described herein relate to a non-transitory, tangible, computer-readable storage medium encoded with processor-readable instructions for implementing a method for switching two or more PIN diodes on and off from an impedance matching network, the method including: providing a current through two or more PIN diodes to forward bias and turn on the two or more PIN diodes, where RF circuitry is coupled between a reference node and an internal node, a first RF bypass capacitor is connected between first ends of the two or more PIN diodes and the reference node, and the internal node is positioned between two of the two or more PIN diodes; and providing a reverse bias voltage across the two or more PIN diodes to turn off the two or more PIN diodes. In some implementations of the non-transitory tangible computer-readable storage medium described above, when two or more PIN diodes are on, a first impedance is presented to the RF circuitry and when two or more PIN diodes are off, a second impedance is presented to the RF circuitry, the magnitude of the second impedance being greater than the magnitude of the first impedance.

[0032] In some aspects, the techniques described herein relate to a non-transitory, tangible, computer-readable storage medium, where providing a reverse bias voltage includes providing a first voltage to remove charge from a specific region of each of the two or more PIN diodes, and providing a reverse bias voltage to keep the two or more PIN diodes off, where a magnitude of the first voltage is less than a magnitude of the reverse bias voltage.

[0033] These and other features and characteristics of the present technology, and the method of operation and function of the associated elements of structure, and combination with economies of parts and manufacture, will become more apparent upon consideration of the following description and appended claims, with reference to the accompanying drawings, all of which form a part of this specification and in which like reference numerals designate corresponding parts in the various views. It is to be expressly understood, however, that the drawings are for purposes of illustration and description only and are not intended as a definition of the limits of the invention. As used in this specification and claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. [Brief description of the drawings]

[0034] Various objects and advantages of the present disclosure and a more complete understanding will become apparent and will be more readily understood by reference to the following detailed description and appended claims, when considered in conjunction with the accompanying drawings.

[0035] [Figure 1A] FIG. 1A illustrates a schematic diagram of a dual-source PIN diode driver circuit that drives a single PIN diode, according to one or more implementations.

[0036] [Figure 1B] FIG. 1B illustrates another schematic diagram of a dual-source PIN diode driver circuit driving a single PIN diode, according to one or more implementations.

[0037] [Figure 1C] FIG. 1C illustrates a schematic diagram of a PIN diode driver circuit that drives a single PIN diode, according to one or more implementations.

[0038] [Figure 2A] FIG. 2A illustrates a schematic diagram of an equivalent circuit for a PIN diode in an on state, according to one or more implementations.

[0039] [Figure 2B] FIG. 2B illustrates a schematic diagram of an equivalent circuit for a PIN diode in an off state, according to one or more implementations.

[0040] [Figure 2C] FIG. 2C illustrates a schematic diagram of series-connected PIN diodes, according to one or more implementations.

[0041] [Figure 3A] FIG. 3A is a block diagram illustrating an example of a PIN diode driver that drives two PIN diodes in series, where the two PIN diodes are in RF parallel, in accordance with various aspects of the disclosure.

[0042] [Figure 3B] FIG. 3B is a block diagram illustrating an embodiment of a PIN diode driver that drives multiple strings of PIN diodes in series, where the strings of PIN diodes are in RF parallel, in accordance with various aspects of the disclosure.

[0043] [Figure 3C] FIG. 3C is a block diagram illustrating an example of a multiple PIN diode driver driving multiple PIN diodes, where the multiple PIN diodes are in series and in RF parallel, in accordance with various aspects of the disclosure.

[0044] [Figure 3D] FIG. 3D is a block diagram illustrating an embodiment of a multiple PIN diode driver driving multiple strings of PIN diodes in series, where the multiple strings of PIN diodes are in RF parallel, in accordance with various aspects of the disclosure.

[0045] [Figure 3E]FIG. 3E is a block diagram illustrating an embodiment of a multiple PIN diode driver driving multiple PIN diodes in series, where the multiple PIN diodes are in RF parallel, in accordance with various aspects of the disclosure.

[0046] [Figure 3F] FIG. 3F is a block diagram illustrating an embodiment of a multiple PIN diode driver driving multiple strings of PIN diodes in series, where the multiple strings of PIN diodes are in RF parallel, in accordance with various aspects of the disclosure.

[0047] [Figure 3G] FIG. 3G is a block diagram illustrating an example of a PIN diode driver that drives multiple strings of PIN diodes in series, where the multiple strings of PIN diodes are in RF parallel, in accordance with various aspects of the disclosure.

[0048] [Figure 3H] FIG. 3H is a block diagram illustrating an embodiment of a multiple PIN diode driver driving multiple strings of PIN diodes in series, where the multiple strings of PIN diodes are in RF parallel, in accordance with various aspects of the disclosure.

[0049] [Figure 4A] FIG. 4A is a block diagram of a two-supply half-bridge driver driving multiple PIN diodes in accordance with various aspects of the present disclosure.

[0050] [Figure 4B] FIG. 4B is a block diagram of a two-supply half-bridge driver driving multiple strings of PIN diodes in accordance with various aspects of the disclosure.

[0051] [Diagram 5] FIG. 5 illustrates an embodiment of a two-stage driver for driving multiple PIN diodes in accordance with various aspects of the present disclosure.

[0052] [Figure 6] FIG. 6 illustrates one embodiment of a two-stage driver for driving multiple PIN diodes in accordance with various aspects of the present disclosure.

[0053] [Figure 7] FIG. 7 illustrates an embodiment of a plurality of two-stage drivers for driving a plurality of PIN diodes in accordance with various aspects of the present disclosure.

[0054] [Figure 8] FIG. 8 illustrates an example of a method for driving multiple PIN diodes according to various aspects of the disclosure.

[0055] [Figure 9] FIG. 9 illustrates an example of a method for driving multiple PIN diodes using multiple PIN diode drivers in accordance with various aspects of the disclosure.

[0056] [Figure 10A] FIG. 10A illustrates an example of a method for driving multiple PIN diodes using multiple PIN diode drivers according to various aspects of the disclosure.

[0057] [Figure 10B] FIG. 10B illustrates an example of a method for driving series-connected PIN diodes in a PIN diode switch according to various aspects of the disclosure.

[0058] [Figure 11] FIG. 11 illustrates a block diagram of a computer system that can be used to implement one or more aspects of the disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0059] (Detailed Description) Prior to describing the embodiments in detail, it is convenient to define certain terms as used in this disclosure.

[0060] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

[0061] Preliminary Note: The flow charts and block diagrams in the following figures illustrate the functionality and operation of possible implementations of a PIN diode switch in which two or more PIN diodes are driven in series by one or more PIN diode drivers while two or more PIN diodes appear in parallel with respect to RF current, according to various embodiments of the present disclosure. It should be noted that in some alternative implementations, the functions described in each block may occur out of the order described in the figures. For example, two blocks shown in succession may in fact be performed substantially in parallel, or the blocks may sometimes be performed in reverse order, depending on the functionality involved. For example, the operation of connecting the second end of the series-connected PIN diode to a reference node can be replaced with or performed in parallel with connecting an RF bypass capacitor between the reference node and the first end of the series-connected PIN diode.

[0062] As used herein, the term "PIN diode" refers to any two-terminal device that acts like a PIN diode in the sense that it acts like a small resistor (e.g., less than 0.2 ohms) to RF current when a forward bias current flows through the device, and acts like a small capacitor (e.g., less than 10 pF) to RF current when a reverse bias voltage is applied across the device.

[0063] As used herein, the term "series-connected PIN diodes," such as series-connected PIN diodes 200-c of FIG. 2C, refers to PIN diodes connected in series with the anode of one PIN diode connected to the cathode of an adjacent PIN diode as shown in FIG. 2C. The term "first end" 201 of the series-connected PIN diodes refers to either the anode or cathode of either the last or first PIN diode in the series-connected PIN diodes. The term "second end" 203 of the series-connected PIN diodes refers to the anode or cathode of the last or first diode in the series-connected PIN diodes that is not the "first end." The term "internal node of the series-connected PIN diodes" or "internal node," such as internal node 202 of FIG. 2C, refers to any PIN diode anode / PIN diode cathode connection in series-connected PIN diodes 200-c. With one of the intermediate nodes of the series-connected PIN diodes (e.g., one of the internal nodes 202 in FIG. 2c) designated as an “internal node” (e.g., internal node 323 in FIG. 3B), the series-connected PIN diodes are divided into two strings of series-connected PIN diodes (e.g., PIN diode strings 324 and 326 in FIG. 3B), with one string consisting of all PIN diodes between the “first end” and the “internal node” and a second string consisting of all diodes between the “internal node” and the “second end.”

[0064] As used herein, the terms “diode string” and “PIN diode string” may be used interchangeably throughout this disclosure and may be used to refer to multiple PIN diodes connected in series (e.g., PIN diode string 324 of FIG. 3B comprising multiple PIN diodes 367 connected in series).

[0065] As described above, a PIN diode is an electrical diode device with an undoped or lightly doped intrinsic (I) semiconductor region sandwiched between a heavily doped p-type semiconductor region (P) and a heavily doped n-type semiconductor region (N), hence the name "PIN diode". In general, PIN diodes follow conventional diode behavior for low frequency input signals. However, for higher frequency input signals (e.g., >10 MHz), PIN diodes behave as a small resistor (e.g., as a 0.15-ohm resistor) in the forward bias or on state and as a small capacitor (e.g., a 4 pF capacitor) in the reverse bias or off state. Thus, PIN diodes are often utilized in radio frequency (RF) applications, such as attenuators and high speed switches, where high isolation and low loss are desired. In one particular implementation, PIN diodes are used in an impedance matching network configured to match the changing (or fluctuating) load impedance of a plasma load to a desired impedance (e.g., 50 ohms or 70 ohms, to name two non-limiting examples) so that a high power RF generator can efficiently deliver power. In such an implementation, the PIN diode serves to connect or disconnect reactive components of the impedance matching network, typically capacitors, to rapidly alter the nature of the matching network by switching reactive elements on and off the network.

[0066] PIN diodes in switching circuits typically have an associated PIN diode driver circuit or switch driver that provides controlled forward bias current and reverse bias voltage. For example, FIGS. 1A and 1B illustrate dual-source PIN diode driver circuits 100-a and 100-b, respectively. The dual-source PIN diode driver circuit 100-a includes a PIN type diode 103 that is connected to an RF circuit, while the dual-source PIN diode driver circuit 100-b includes a PIN type diode 104 that is connected to another RF circuit. Each PIN diode 103, 104 is driven by two power supplies (e.g., power supplies 110 and 114 for the PIN diode driver circuit 100-a, and power supplies 112 and 116 for the PIN diode driver circuit 100-b) that serve to provide forward bias current and reverse bias voltage to the individual PIN diodes 103, 104. For example, in circuit 100-a, a low-voltage forward bias current source 110 is connected in series with a first switch 118, while a high-voltage reverse bias voltage source 114 is connected in series with a second switch 120. When the first switch 118 is closed (and the second switch 120 is open), the forward bias current source 110 provides a forward bias current to the PIN diode 103. In addition, when the second switch 120 is closed (and the first switch 118 is open), the reverse bias voltage source 114 provides a reverse bias voltage across the PIN diode 103. Similarly, in circuit 100-b, a high voltage reverse bias voltage supply 116 is connected in series with a first switch 122 to provide a reverse bias voltage across the PIN diode 104 when the first switch 122 is closed, and a low voltage forward bias current supply 112 is connected in series with a second switch 124 to provide a forward bias current to the PIN diode 104 when the second switch 124 is closed. It should be noted that although Figures 1A and 1B show elements 106, 108 as inductors, any other elements (or circuitry) that pass direct current (DC) at low frequencies and suppress RF signals applied by the RF circuitry to the PIN diodes 103, 104 may be utilized in different embodiments.Some non-limiting examples of types of elements and / or circuits that may be utilized in place of the inductors 106, 108 include an RF choke, a parallel resonant LC tank or tanks, a quarter wavelength transmission line (at the frequency of the applied RF signal), etc.

[0067] FIG. 1C illustrates a schematic diagram of a PIN diode driver circuit 100-c including a driver 126, a PIN diode 105, an RF network connected to the PIN diode 105, and an inductor 128 (or another applicable element that passes DC at low frequencies and suppresses the RF frequency applied to the PIN diode 105 by the RF network) according to one or more implementations. As can be seen, the driver 126 is used to drive a single PIN diode 105. Here, FIG. 1C represents a generalization of FIG. 1B. However, it should be noted that reversing the polarity of the PIN diode 105 in FIG. 1C would represent a generalization of FIG. 1A. In a conventional PIN diode circuit, a PIN diode driver (e.g., driver 126) is placed in series with an RF blocking DC passing device such as inductor 128. A series combination of a PIN diode driver (e.g., driver 126) and an RF blocking DC passing device such as inductor 128 is connected across the PIN diode 105. Inductor 128 is used to isolate driver 126 from high RF voltages that the RF circuitry may impose across PIN diode 105. In a typical application, the RF blocking device (e.g., inductor 128) may see voltages in excess of 1,000V RMS at RF frequencies, e.g., 13.56 MHz. In such cases, the RF blocking device should be designed to have low RF losses when subjected to high RF voltages and be able to handle high currents (e.g., above a predetermined threshold such as 5A) when the PIN diode is toggled between forward bias (on state) and reverse bias (off) states.

[0068] The operation of the PIN diode driver circuit will now be described in more detail, again referring to circuit 100-a as an example. To forward bias the PIN diode 103, switch 118 is closed and switch 120 is open. A low voltage current source 110 provides a forward bias current to the PIN diode 103. When the PIN diode 103 is forward biased, if the "I" region is sandwiched between (or adjacent to or located between) the "P" and "N" region materials, holes from the "P" region material and electrons from the "N" region material of the diode 103 are injected into the "I" region material. Because the charge in the diode 103 does not recombine instantly, the net charge is stored in the "I" region, which, if not continually replenished, decays exponentially with a time constant known as the carrier lifetime. An amount of charge equal to the product of the forward bias current and the carrier lifetime accumulates in the intrinsic region. As long as the charge that any RF current flowing through the PIN diode can remove in one-half of an RF cycle is significantly less than the stored charge, the PIN diode will conduct RF current in either direction and act as a small resistor in a forward biased state. Thus, in some aspects, the PIN diode 103 acts as a resistor with an effective "on" resistance value at RF frequencies. An equivalent forward bias circuit 200-a for a PIN diode such as PIN diode 103 is illustrated in FIG. 2A. A typical value for the resistor in FIG. 2A is 0.15 ohms and a typical value for the inductor in FIG. 2A is 1 nH, although other resistance and inductance values ​​are contemplated in different embodiments.

[0069] To reverse bias the PIN diode 103, switch 118 is opened and switch 120 is closed to provide a reverse bias voltage from the high voltage reverse bias voltage source 114 to the PIN diode 103. During reverse bias operation, the PIN diode 103 has an equivalent circuit (e.g., as shown by the equivalent reverse bias circuit 200-b of FIG. 2B) of a large resistor (i.e., several times larger than the resistance value in the equivalent forward bias circuit 200-a) shunted by a small capacitance. For example, typical capacitance, resistance, and inductance values ​​for the circuit 200-b of FIG. 2B at 13.56 MHz may be approximately 4 pF for the capacitor, 1 megaohm for the resistor, and 1 nH for the inductor. Depending on the various aspects of the PIN diode 103, various forward bias resistances and reverse bias capacitances may be achieved for specific applications in various situations.

[0070] One of the potential performance challenges associated with conventional PIN diode circuits (e.g., PIN diode circuits 100-a, 100-b) is that the RF blocking devices (e.g., inductors 106, 108, 128) may be bulky, contribute to RF losses, and allow high voltages to develop across the PIN diode when used in high speed, high repetition rate, and / or high power applications. In some non-limiting examples, when a PIN diode is used in a high power application with frequencies ranging from 3 to 30 MHz, the PIN diode may be forward biased at 1 amp from a forward bias current source and reverse biased at 1,500 V from a reverse bias voltage source. The carrier lifetime for a typical diode in such an application may be about 12 μs. To switch rapidly (e.g., in a time period shorter than the carrier lifetime) from a forward biased (on) state to a reverse biased (off) state, the charge to be removed from the PIN is based at least in part on the forward current and the carrier lifetime (e.g., the product of the forward current and the carrier lifetime). In the above referenced example, a charge of 12 μC may need to be removed to switch from a forward biased state to a reverse biased state. If this charge is removed by a high voltage power supply (e.g., high voltage power supply 114 of FIG. 1A), the energy expended may be calculated as the product of the power supply voltage and the charge, i.e., 1,500 V×12 μC=18 mJ. If the operation is performed at a high repetition rate, the power required may be prohibitive for many types of applications. For example, if the operation of forward and reverse biasing a PIN diode (e.g., PIN diode 103) is to be performed at a repetition rate of 10 kHz, in this example, the power drawn from the high voltage power supply 114 may be calculated as 18 mJ×10 kHz=180 W. In one non-limiting example, an impedance matching network for matching a 3 kW RF generator to a load may contain 50 PIN diodes.If half of the PIN diodes in the impedance matching network each consume 180 W, then the total power consumption for an impedance matching network matching a 3 kW RF generator to a load can be calculated as 25 x 180 W = 4.5 kW. In some situations, the relatively high power consumption of the impedance matching network negates much of the benefit of having the impedance matching network in the first place. Furthermore, a significant percentage (e.g., more than half) of the power drawn from the high voltage power supply 114 (e.g., about 180 W) can be dissipated in the PIN diodes during their reverse recovery, which is more than a typical PIN diode can safely dissipate.

[0071] To reduce the power spent in removing charge from the "I" region, reactive circuitry can be used to either reduce the energy spent or recover the stored energy. For example, inductors 106 and 108 can be used in combination with switches 118 and 120 (or switches 122 and 124) to reduce the energy spent or recover the stored energy. However, in some circumstances, when reactive circuitry is used, the PIN diode may snap off when charge is being extracted from the "I" region. This sudden switching off of the PIN diode (or sudden reduction in current through the PIN diode), as is typical for energy recovery, can result in a high voltage drop across the PIN diode (e.g., above the breakdown voltage of the PIN diode) if it is driven through an inductor (e.g., inductor 106 or inductor 108), which can lead to PIN diode failure.

[0072] One solution to the high power consumption and rapid off switching of PIN diodes and overvoltages is to use RF parallel DC series connected PIN diodes and RF bypass capacitors across the PIN diode driver. In other words, two sets of series connected PIN diodes can be arranged to appear in series with the PIN diode driver, while these same two sets of series connected PIN diodes can appear in parallel to the RF network. At the same time, the arrangement across the PIN diode driver, in addition to the appropriate selection of the capacitance value of the RF bypass capacitor, helps to reduce the maximum RF voltage that may develop across the PIN diode driver compared to the prior art. By reducing the maximum RF voltage across the PIN diode driver, aspects of the present disclosure allow DC passing RF blocking devices (e.g., inductors 106, 108, 128) to be eliminated or replaced by RF blocking devices that handle a small fraction (e.g., 5%) of the RF voltage applied across the PIN diode. In addition to reducing or eliminating the possibility of the PIN diode accidentally snapping off, the elimination of the DC passing RF blocking device (e.g., inductor 106) also allows for a smaller PIN diode switch or system (e.g., 300, 301, 302, 303, 304, 305, 400, 401). Additionally, the use of an RF bypass capacitor to block the PIN diode driver current (DC current) in combination with another DC blocking device (e.g., a series capacitor) in the RF circuitry creates a DC current path that flows through the PIN diode driver and the series connected diode.Both ends of the series-connected PIN diodes are connected (through an RF bypass capacitor on one end and either directly or through a second RF bypass capacitor on the other end if a second driver is used) to a reference node with low RF impedance, so that neither end of the series-connected PIN diodes can be disconnected from the reference node at RF frequencies by reverse biasing the PIN diodes, but the internal node of the series-connected PIN diodes can be disconnected from the reference node by reverse biasing the PIN diodes. By connecting the remainder of the RF network between the internal node and the reference node, the circuit can function as an RF switch. The effect of connecting the RF network between the internal node and the reference node is that the PIN diode between the internal node and one end of the series-connected diodes is in RF parallel to the PIN diode connected between the internal node and the other end of the series-connected PIN diodes.

[0073] Additionally or alternatively, a two-stage (or dual-stage) driver circuit comprising a resonant stage (e.g., shown as resonant stage 502 in FIG. 5 ) for energy recovery followed by a holding stage (e.g., shown as holding stage 504) may be employed to mitigate the high power consumption and rapid off-switching and overvoltage of PIN diodes found in the prior art. Such a two-stage driver circuit simultaneously achieves 1) fast switching, 2) energy recovery, and 3) avoidance of dangerous voltage spikes when the PIN diode snaps off. The use of a first (resonant) stage followed by a second (holding) stage provides the ability to drive the PIN diode (e.g., PIN diodes 508, 514) at high speed without using excessive power because energy is recovered within the system. The holding stage serves both to limit the voltage when the PIN diode snaps off and to hold the high reverse voltage and supply current in the on-state. In the voltage limiting process, the energy is transferred to a high voltage supply (e.g., V in FIG. 5 ) in the holding stage, which is connected to a holding network. high). Because the recovered energy generally exceeds the energy input to the system via the high voltage supply, the excess recovered energy can optionally be passed back to the resonant stage via a power converter (not shown in FIG. 5). This excess recovered energy can also be passed to other sources besides the resonant stage, or dissipated as heat (although this is typically not desired).

[0074] FIG. 3A is a block diagram 300 illustrating one example of a PIN diode driver 310 that drives two PIN diodes 314, 316 in series, where the two PIN diodes 314, 316 are in RF parallel, according to various aspects of the disclosure. FIG. 3A illustrates one non-limiting example of a PIN diode circuit (or PIN diode switch) that may be employed to avoid the need for an RF blocking DC passing device (e.g., an inductor) between the PIN diode driver 310 and the PIN diodes. As seen in FIG. 3A, in some embodiments, multiple PIN diodes (two in this example) may be connected such that they appear in series with respect to the PIN driver current 306 and in parallel with respect to the RF current 307. In some examples, the RF circuitry (not shown in detail) may include a DC blocking device, typically a series capacitor (e.g., shown as capacitor C2 in the RF circuitry 510 and / or 610 of FIG. 5 and / or 6, respectively), that prevents DC current from flowing through the RF circuitry. In this manner, the PIN diodes may appear to be in DC series with the driver 310 because the PIN driver current (i.e., DC current) is blocked from flowing through the RF bypass capacitor 312 and the RF circuitry (i.e., due to a DC blocking device such as a series capacitor in the RF circuitry). Additionally, there is minimal to no flow of RF current through the PIN diode driver 310; i.e., the combination of the low voltage across the PIN diode driver 310 combined with the relatively high impedance of the PIN diode driver 310 to RF current causes negligible RF current through the driver 310.

[0075] As used herein, the term "RF bypass capacitor" may refer to a capacitor having a capacitance sufficient (i.e., large enough) to allow the RF voltage developed across the capacitor (e.g., when the maximum possible RF current is flowing through the capacitor) to be a small fraction (i.e., less than a predetermined threshold) of the maximum RF voltage that may be present across the PIN diode switch. As an example, in a PIN diode switch where a 1000V RMS RF voltage may be developed across the PIN diode switch and a maximum RF current of 10A RMS may flow through the RF bypass capacitor, the RF bypass capacitor may be selected such that the voltage drop across the RF bypass capacitor is less than 50V RMS (e.g., less than 5% of the maximum RF voltage developed across the PIN diode switch). In this example, when the RF frequency is 13.56 MHz, the capacitance of the RF bypass capacitor may be selected to be at least 2.35 nF. In other words, the RF bypass capacitor is: [ka] (In the formula, V RF_PIN is the maximum RF voltage that may exist across the PIN diode switch, and V RF_Cap is the RF voltage developed across the RF bypass capacitor. [ka] is, or [ka] It is.

[0076] In the PIN switch block diagram 300 shown in FIG. 3A, two PIN diodes 314 and 316 are connected in series (referred to herein as series-connected PIN diodes 314, 316), and an RF bypass capacitor 312 is connected between a reference node 311 and a first end 395-a of the series-connected PIN diodes 314, 316. In addition, a second end 396-b of the series-connected PIN diodes 314, 316 is connected to the reference node. In this embodiment, an RF network 318 is connected between the reference node 311 and an internal node 313 between the series-connected PIN diodes 314, 316, and a driver 310 is connected across the RF bypass capacitor 312. Alternatively, it may be said that the driver 310 is connected between the first end 395-a of the series-connected PIN diodes 314, 316 and the reference node 311. Specifically, RF circuitry 318 is connected between reference node 311 and internal node 313, which is connected to one end of each of PIN diodes 314, 316. Here, the internal node is connected to a second end 396-a of first PIN diode 314 and a first end 395-b of second PIN diode 316. The first end of first PIN diode 314 is also the first end 395-a of series-connected PIN diodes 314, 316, and the second end of second PIN diode 316 is the second end 396-b of series-connected PIN diodes 314, 316.

[0077] With the design of the PIN switch shown in FIG. 3A, the PIN diode driver 310 does not experience high RF voltages, which allows conventional RF blocking devices between the driver and the PIN diode (e.g., shown as inductors 106, 108, and 128 in FIGS. 1A-1C) to be eliminated, reduced in size, and / or significantly simplified. In this arrangement, the driver 310 is connected across the RF bypass capacitor 312. In one non-limiting example, the PIN diodes 314 and / or 316 may be designed to safely handle a maximum RF current of 10 A RMS. In this example, if the PIN diode switch is operating at 13.56 MHz and the capacitance of the RF bypass capacitor 312 is about 5 nF, the voltage developed across the RF bypass capacitor 312 is about 23 V RMS when the PIN diode is conducting the maximum RF current of 10 A RMS that it can safely conduct. As can be seen, this RMS voltage (e.g., 23V RMS) developed across the RF bypass capacitor 312 is small compared to the off-state RMS voltage (e.g., 1,000V RMS) that the PIN diode driver 310 may experience in a typical PIN diode switch circuit. As a result, an RF blocking device (e.g., an inductor) between the driver 310 and the PIN diode can be eliminated.

[0078] Although not required, in some embodiments, an RF filter may be employed to protect the driver 310 against low RF voltages (e.g., 23V RMS) developed across the RF bypass capacitor 312. However, this RF filter (optional) can be significantly smaller than the RF blocking devices (e.g., inductors) used in conventional PIN diode switch circuits (e.g., as described above in connection with FIGS. 1A-C). Due to its compact nature, this optional RF filter may also be incorporated into the driver circuit 310 in some embodiments. Alternatively, the RF blocking capacitor 312 may be placed in series with a small inductor such that the series combination of the RF blocking capacitor 312 and the inductor resonates at the RF frequency, which further serves to reduce the RF voltage across the driver 310. For example, with a 5nF RF bypass capacitor and an RF frequency of 13.56MHz, the value of the inductor is 27nH - the parasitic inductance of the selected 5nF capacitor.

[0079] FIG. 3A also shows the current paths for the PIN diode driver current (current path 306, shown as a dashed dotted line) and the RF current (current path 307, shown as a dashed line). As shown by the current path 306 through the PIN diode driver 310, the two PIN diodes 314 and 316 appear in series with respect to the PIN diode driver current. The PIN diode driver current in the depicted direction is for forward biasing the PIN diodes 314, 316. In some cases, the current can also flow in the opposite direction, briefly, when the driver 310 switches the PIN diodes 314, 316 from a forward bias (on) state to a reverse bias (off) state. Additionally or alternatively, the current may increase (for a short duration) above the nominal forward bias on state current when the driver 310 switches the PIN diodes 314, 316 from a reverse bias (off) state to a forward bias (on) state. In comparison to an RF current (shown by current path 307) that oscillates at an RF operating frequency, e.g., 13.56 MHz, the PIN diode driver current can be considered to be a DC current. In such a case, the RF bypass capacitor 312 blocks or substantially blocks the PIN diode driver current. In some cases, the RF bypass capacitor 312 may not block all of the PIN diode driver current, for example, when the driver 310 is switching the PIN diode between an on state and an off state (e.g., when the driver 310 is charging and discharging one or more of the RF bypass capacitor 312, the PIN diode, and / or a capacitor that is part of the RF circuitry 318).

[0080] 3A shows that the two diodes 314, 316 appear in parallel with respect to RF current. In some cases, the RF bypass capacitor 312 may cause RF current to flow preferentially through the diode 316 when the PIN diodes 314, 316 are in an on-state because the on-state resistance of the PIN diode is small compared to the impedance of the RF bypass capacitor 312. In some cases, an optional resonant inductor (not shown) may be placed in series with the RF bypass capacitor 312, which helps to reduce the RF current imbalance between the diodes 316 and 314 as well as the RF voltage across the driver.

[0081] 3B is a block diagram 301 illustrating an embodiment of a PIN diode driver 320 that drives multiple strings 324, 326 of PIN diodes in series, where the strings of PIN diodes are in RF parallel, according to various aspects of the disclosure. As can be seen, each string of PIN diodes comprises multiple PIN diodes 367 arranged in series. Furthermore, multiple ones (two in this example) of the strings of PIN diodes are arranged in series, similar to the two PIN diodes 314, 316 of FIG. 3A. The PIN diode switch of FIG. 3B illustrates that the PIN diodes 314 and 316 of the PIN diode switch of FIG. 3A are replaced by diode strings 324 and 326, while retaining the basic characteristics of FIG. 3A. Compared to the arrangement of FIG. 3A, in which an RF bypass capacitor is connected between the reference node and the anode of the series-connected PIN diodes, in this embodiment, an RF bypass capacitor 322 is connected between the reference node 321 and the cathode of the PIN diode string 324 (also described as the cathode of the last PIN diode in the string 324). In addition, the anode of the PIN diode string 326 (also described as the anode of the first PIN diode in the string 326) is connected to the reference node 321. The different orientations of the PIN diodes in FIGS. 3A and 3B illustrate that either orientation may be implemented throughout the embodiments of the present disclosure without departing from the scope and spirit of the present disclosure and without undue experimentation. For simplicity, most embodiments will be shown with the diode orientations shown in FIGS. 3A and 3C, but this does not preclude the implementation of the orientation shown in FIG. 3B. An RF network 328 is connected between the reference node 321 and an internal node 323 of the series-connected PIN diode string. Specifically, RF circuitry 328 is coupled at one end to reference node 321 and at another end to an internal node 323 between PIN diode string 324 and PIN diode string 326. In other words, internal node 323 is connected to one end of each of PIN diode strings 324 and 326.

[0082] 3C is a block diagram illustrating an embodiment of a PIN diode switch 302 in accordance with various aspects of the disclosure, where the PIN diode switch 302 comprises multiple PIN diode drivers 330, 331 and multiple PIN diodes 334, 336. As can be seen, multiple PIN diode drivers 330, 331 are used to drive multiple PIN diodes, where the multiple PIN diodes are in series (in terms of PIN diode driver current) and in parallel (in terms of RF current).

[0083] The PIN diode switch 302 of FIG. 3C uses two complementary drivers 330 and 331 with two RF bypass capacitors 332 and 333. Such a design creates two parallel RF paths, one path through the PIN diode 334 and the RF bypass capacitor 332, and the other path through the PIN diode 336 and the RF bypass capacitor 333, and these two RF paths are symmetrical. The symmetrical RF paths help minimize or reduce the possibility of imbalance of high RF current through the two PIN diodes 334, 336. In this case, the RF bypass capacitors 332 and 332 may not be placed in series with the resonant inductor to ensure current balance. Instead, an optional RF filter may be incorporated into one or more of the drivers 330 and 331 to further protect the PIN diode drivers 330 and 331, for example. In some cases, the impedance of this optional filter may be selected so that the impedance seen by RF bypass capacitor 332 or 333 is high compared to the impedance of the RF bypass capacitor at RF frequencies (eg, 13.56 MHz).

[0084] 3C, the PIN diode driver current 319 flows through the PIN diode driver 330, the PIN diode 334, the PIN diode 336, and the PIN diode driver 331. That is, the two PIN diodes 334 and 336 are in series with respect to the PIN diode driver current 319. Furthermore, the RF current 339 flows through the RF circuitry 338 and then splits into two parallel paths, one RF current path comprising the series combination of the PIN diode 334 and the RF bypass capacitor 332, while the other RF current path comprises the series combination of the PIN diode 336 and the RF bypass capacitor 333. Thus, the two PIN diodes 334 and 336 are in parallel with respect to the RF current 339.

[0085] The term "complementary," as it relates to PIN diode drivers, indicates that the two drivers produce voltages and currents of opposite polarity. For example, to forward bias PIN diodes 334 and 336, driver 330 (i.e., driver A) produces a positive voltage at the node connected to the PIN diodes with respect to reference node 337. This causes a positive current to flow from driver A from the node where driver A 330 connects to the PIN diodes, toward the PIN diodes. Similarly, driver 331 (i.e., driver B) produces a negative voltage at the node connected to the PIN diodes with respect to reference node 337, which causes a positive current to flow from the PIN diodes to driver B at the node where the PIN diodes connect to driver B 331.

[0086] 3D is a block diagram illustrating an embodiment of a PIN diode switch 303 according to various aspects of the disclosure. Specifically, according to various aspects of the disclosure, the block diagram of FIG. 3D illustrates multiple PIN diode drivers (e.g., PIN diode drivers 340, 341) driving multiple strings of PIN diodes (e.g., PIN diode strings 344, 346) in series, where the multiple strings of PIN diodes are in RF parallel. The PIN diode switch 303 implements one or more aspects of the PIN diode switches described herein, including at least PIN diode switches 300, 301, and / or 302.

[0087] PIN diode switch 303 of FIG. 3D illustrates that the PIN diodes (eg, PIN diodes 334, 336) of switch circuit 302 of FIG. 3C can be replaced by strings of PIN diodes 344 and 346 without altering the basic properties of switch 302.

[0088] In the PIN diode switch 303 of FIG. 3D , PIN diode strings 344, 346 are connected in series, a first RF bypass capacitor 342 is connected between a reference node 347 and a first end (anode) of the series-connected PIN diodes (i.e., all of the PIN diodes in strings 344 and 346), a second RF bypass capacitor 343 is connected between the reference node 347 and a second end (cathode) of the series-connected PIN diodes (i.e., all of the PIN diodes in strings 344 and 346), an RF network 348 is connected between the reference node 347 and an internal node 345 of the series-connected PIN diodes (i.e., all of the PIN diodes in strings 344 and 346), a first PIN diode driver 340 is connected across the first RF bypass capacitor 342, and a second or complementary PIN diode driver 341 is connected across the second RF bypass capacitor 343. In some cases, the first PIN diode driver 340 (i.e., driver A) and the second PIN diode driver 341 (i.e., driver B) may be complementary, meaning that they produce voltages and currents of opposite polarity.

[0089] 3E is a block diagram illustrating an example of a PIN diode switch 304 according to various aspects of the disclosure. In this example, multiple PIN diode drivers 350, 351 are used to drive multiple PIN diodes, and multiple PIN diodes 354, 356 appear in series with respect to the PIN diode driver current and in RF parallel (i.e., in parallel with respect to the RF current) according to one or more implementations.

[0090] As seen in FIG. 3E, an RF blocking DC passing circuit or device 358 is connected between an internal node 355 of the series connected PIN diodes (e.g., a node between series connected PIN diodes 354 and 356) and a reference node 357. In addition, an RF network 359 is also connected between the internal node 355 and the reference node 357. In some examples, as depicted in FIG. 3E, the RF blocking DC passing device 358 (hereinafter, “RF blocking device 358”) may be an inductive device such as an inductor, although other types of circuits or devices are also contemplated in different embodiments. For example, a parallel combination of an inductor and a capacitor or a ¼ wave transmission line may be utilized in place of an inductor in some embodiments. As described above, this RF blocking device 358 (e.g., an inductor) may be configured to withstand the same RF voltages as the RF blocking devices 106, 108, and 128 described in connection with FIG. 1. However, the RF blocking device 358 may be simpler (e.g., less bulky) to design since it does not need to conduct the peak driver current and / or peak forward bias current. The addition of the RF blocking device 358 helps to compensate for the difference (or minute variations) between the PIN diodes 354 and 356. As an example, when switching from a forward biased on state to a reverse biased off state, if the diode 354 recovers (meaning all charge is removed from the inherent, i.e., "I" region, of the PIN diode) before the diode 356, a high, potentially damaging voltage (e.g., a voltage above a safety threshold) may develop across the diode 354, which may remain in a partially recovered state if no RF blocking device 358 is employed. Some aspects of the present disclosure are directed to mitigating the effects of such a scenario through the use of an RF blocking device 358 (or RF choke), such as an inductor.In such a case, RF blocking device 358 allows both PIN diodes 354 and 356 to recover to a fully off state more quickly, based at least in part on their DC passing and RF blocking characteristics, reducing the voltage spike that would otherwise develop across the first recovering PIN diode.

[0091] 3F is a block diagram illustrating an embodiment of a PIN diode switch 305 in accordance with various aspects of the disclosure. In this embodiment, the PIN diode switch 305 includes multiple PIN diode drivers 360, 361 that drive multiple strings of PIN diodes (e.g., PIN diode strings 364, 366), where the PIN diode strings appear in series (in terms of PIN diode driver current) and RF parallel (in terms of RF current).

[0092] 3F illustrates that the PIN diodes (e.g., PIN diodes 354, 356) of switch circuit 304 may be replaced by strings of PIN diodes 364 and 366 without altering the basic properties of switch 304. In switch circuit 305, an RF blocking device 368, such as an inductor, may be utilized to compensate for differences (if any) between PIN diode strings 364 and 366.

[0093] In the PIN diode switch circuit 305 of FIG. 3F, PIN diode strings 364 and 366 are connected in series, a first RF bypass capacitor 362 is connected between a reference node 367 and a first end (anode) of PIN diode string 364, a second RF bypass capacitor 363 is connected between the reference node 367 and a second end (cathode) of PIN diode string 366, RF circuitry 369 is connected between the reference node 367 and an internal node 365 of PIN diode strings 364 and 366, a PIN diode driver 360 is connected across the first RF bypass capacitor 362, a complementary PIN diode driver 361 is connected across the second RF bypass capacitor 363, and a DC passing RF blocking device or circuit 368 (e.g., an inductor) is connected between the internal node 365 and the reference node 367.

[0094] FIG. 3G is a block diagram 300-g illustrating an embodiment of a PIN diode driver 370 that drives multiple strings 374, 376 of PIN diodes in series, where the strings of PIN diodes are in RF parallel, according to various aspects of the disclosure. As can be seen, each string of PIN diodes comprises multiple PIN diodes 373 arranged in series. RF circuitry 379 is connected between a reference node 377 and an internal node 375 of the series-connected PIN diode strings 374, 376. An RF bypass capacitor assembly 372, comprising multiple capacitors 371 connected in series, is connected between a first end of the series-connected PIN diodes 373 and the reference node 377. A plurality of DC passing and RF blocking devices 378 (e.g., inductors, parallel combinations of inductors and capacitors, and quarter RF wavelength long transmission lines) are connected between the intermediate node of the series-connected capacitors 371 and the intermediate node of the series-connected PIN diodes 373. Capacitor 371 may be shunted by a large resistor (e.g., a 10 megohm resistor, not shown) to ensure that the voltage across capacitor 371 remains balanced at DC, or an additional driver (not shown) may be connected between reference node 377 and the intermediate node of series connected capacitors 371 to maintain a balanced DC voltage across capacitor 371. This arrangement of capacitor 371 and DC passing RF blocking device 378 compensates for differences in the properties of PIN diodes 373. For example, during reverse biasing of PIN diodes 373, if one of PIN diodes 373 turns off before another of PIN diodes 373, current can flow through DC passing RF blocking device 378 and turn off the rest of PIN diodes 373.

[0095] 3H is a block diagram 300-h illustrating an embodiment of a plurality of PIN diode drivers 380, 381 driving a plurality of strings 384, 386 of PIN diodes in series, where the strings of PIN diodes are in RF parallel, according to various aspects of the disclosure. As can be seen, each string of PIN diodes comprises a plurality of PIN diodes 393 arranged in series. RF circuitry 389 is connected between a reference node 387 and an internal node 385 of the series-connected PIN diode string. A first RF bypass capacitor assembly 382 comprising a plurality of capacitors 391 connected in series is connected between a first end of the series-connected PIN diodes 393 and the reference node 387. A plurality of DC passing and RF blocking devices 398 (e.g., inductors, parallel combinations of inductors and capacitors, and quarter RF wavelength long transmission lines) are connected between the intermediate node of the series-connected capacitors 391 and the intermediate node of the series-connected PIN diodes 393. A second RF bypass capacitor assembly 383 comprising a plurality of capacitors 392 connected in series is connected between a second end of the series connected PIN diode 393 and a reference node 387. A plurality of DC pass and RF blocking devices 398 are connected between the intermediate node of the series connected capacitors 392 and the intermediate node of the series connected PIN diode 393. One of the DC pass and RF blocking devices 398 may be connected between the internal node 385 and the reference node 387. The capacitors 391 and 392 may be shunted by a large resistor (e.g., a 10 megohm resistor) to ensure that the voltage across the capacitors 391 and 392 remains balanced at DC, or an additional driver (not shown) may be connected between the reference node 387 and the intermediate node of the series connected capacitors 391 and 392 to maintain a balanced DC voltage across the capacitors 391 and 392. This arrangement of the capacitors 391 and 392 and the DC pass RF blocking device 398 compensates for the difference in the properties of the PIN diode 393.For example, during reverse biasing of the PIN diodes 393, if one of the PIN diodes 393 turns off before another of the PIN diodes 393, current can flow through the DC passing RF blocking device 398 and turn off the rest of the PIN diodes 393.

[0096] In some circumstances, DC voltage excursions may damage equipment (e.g., network analyzers) connected to circuits incorporating PIN diode switches (e.g., PIN diode matching networks). The advantage of the PIN switch circuits 302, 303, 304, 305, and 300-h of Figures 3C, 3D, 3E, 3F, and 3H, respectively, using complementary drivers, is that because the drivers are complementary, the individual internal nodes 335, 345, 355, 365, and 385 remain at 0 volts relative to the individual reference nodes 337, 347, 357, 367, and 387, except for small disturbances due to the PIN diodes and PIN diode drivers that are not identical. This means that the RF circuitry is not subject to DC voltage excursions. Aspects of the present disclosure thus help prevent DC voltages at internal nodes (e.g., nodes between adjacent PIN diodes or PIN diode strings) from drifting / straying relative to the DC voltage of a reference node, which can adversely affect RF circuit performance and / or cause damage to susceptible equipment.

[0097] 4A is a block diagram 400 of a two-source half-bridge driver driving multiple PIN diodes 403, 404 in accordance with various aspects of the disclosure. Specifically, but not by way of limitation, the PIN diode switch of FIG. 4A illustrates a particular implementation of the PIN diode switch previously described in connection with FIG. 3A. As can be seen, in place of driver 310, FIG. 4A depicts a two-source PIN diode driver consisting of a low-voltage forward-biased current source 410, a high-voltage reverse-biased power source 414, and two switches 418 and 420 arranged as a half-bridge circuit.

[0098] 4B is a block diagram 401 of a two-supply half-bridge driver driving multiple strings of PIN diodes (e.g., shown as PIN diode strings 423, 424) in accordance with various aspects of the disclosure. Specifically, but not by way of limitation, the PIN diode switch of FIG. 4B illustrates a particular implementation of switch 301 of FIG. 3B. In FIG. 4B, a two-supply PIN diode driver is used to implement driver 320 of PIN diode switch 301, which includes a low-voltage forward-biased current source 430, a high-voltage reverse-biased power source 444, and two switches 448 and 440 arranged as a half-bridge circuit.

[0099] FIG. 5 illustrates an example of a PIN diode switch 500 according to various aspects of the disclosure, where the PIN diode switch 500 includes a two-stage driver that drives multiple PIN diodes. Specifically, but not by way of limitation, the PIN diode switch 500 of FIG. 5 illustrates an example implementation of the switch 300 of FIG. 3A. In one non-limiting example, the driver 310 of the PIN diode switch 300 may be implemented as a two-stage driver consisting of a first resonant stage 502 and a second holding stage 504. As can be seen, the PIN diode switch 500 comprises a first (resonant) stage 502, a second (holding) stage 504, an RF blocking device 506 comprising an inductor (L2) and a capacitor (C3) arranged in parallel, a bypass capacitor 516 (C4) coupled to one end of the RF blocking device 506 and another end of a reference node 512, a first PIN diode 508, a second PIN diode 514, and an internal node 518. As can be seen, the RF circuitry 510 comprises at least one capacitor (C2), which is coupled between the internal node 518 and the reference node 512. In this embodiment, the capacitor (C2) of the RF circuitry 510 is coupled to the internal node 518 between the PIN diode 508 and the PIN diode 514. In some embodiments, a power supply (V mid, which may charge and discharge one or more of the RF bypass capacitor 516, the PIN diodes 508, 518, the capacitor C1 in the resonant stage 502, and any other capacitors that are part of the RF circuitry 510. The capacitors may be connected to the same voltage (e.g., V mid ), it is theoretically possible to do so without consuming power. However, some (but minimal) power is lost in this process due to the non-ideal switches. Additionally or alternatively, some power is also lost in the PIN diodes 508, 518 during their reverse recovery.

[0100] In one non-limiting embodiment, V mid = 1,300V (or -1,300V if the polarity is reversed in Figure 5), and V high = 3,000V (or -3,000V if the polarity is reversed in FIG. 5), L1 = 100 μH, C1 = 5 nF, C2 = 60 pF, L2 = 1.5 μH, C3 = 22.96 pF, and C4 = 5 nF, although other values ​​are also contemplated in different embodiments and the example values ​​listed herein are not intended to be limiting.

[0101] FIG. 6 illustrates an example of a PIN diode switch 600 according to various aspects of the disclosure. Here, the PIN diode switch 600 utilizes a two-stage driver for driving multiple PIN diodes and includes a low-voltage reverse-bias power supply and associated switch 620 in addition to a first (resonant) stage 602 and a second (holding) stage 604. In some embodiments, in switching from an ON state to an OFF state, the PIN diode is reverse-biased first, i.e., after disconnecting the forward-bias supply (by opening S4 in the holding stage 604) and before operating the first (resonant) stage 602, with a lower reverse-bias voltage. This helps to reduce the energy used to switch the PIN diode from an ON state to an OFF state, for example, by removing charge from the PIN diode at a lower voltage. Note that the polarity of the PIN diode in FIG. 6 is reversed compared to that shown in FIG. 5.

[0102] FIG. 6 also serves to illustrate that to construct a PIN diode switch in which the polarity of the PIN diode is reversed (by comparison with FIG. 5), the polarity of the supply voltage in the PIN diode driver and the polarity of the switch in the PIN diode driver are also reversed. For example, a switch (including a diode) that can reserve a voltage of one polarity (i.e., conducts only a low current, e.g., 1 microamp, when a voltage of that polarity is applied) can be replaced by a switch that can reserve a voltage of the opposite polarity. A controlled switch, such as, but not limited to, a field effect transistor (FET), can only reserve a voltage in the OFF state. In other words, for a controlled switch, reserving a voltage of one polarity implies reserving a voltage of that polarity in the OFF state.

[0103] In one non-limiting embodiment, V mid = 1,400 V, and V high= 3,000V, L1 = 100 μH, C1 = 5 nF, C2 = 60 pF, L2 = 1.5 μH, C3 = 22.96 pF, and C4 = 5 nF, although other values ​​are also contemplated in different embodiments and the example values ​​listed herein are not intended to be limiting.

[0104] FIG. 7 illustrates an example of a PIN diode switch 700 in accordance with various aspects of the disclosure. In this example, the PIN diode switch 700 employs multiple two-stage drivers (e.g., PIN driver 702, complementary PIN driver 704) to drive multiple PIN diodes (e.g., PIN diodes 714, 716). In some aspects, the PIN diode switch 700 of FIG. 7 is an example implementation of the PIN diode switch 304 of FIG. 3E using complementary PIN diode drivers. As can be seen, the PIN diode switch 700 comprises a first driver 702 (e.g., similar to or substantially similar to driver 351 or driver B of FIG. 3E ), a second or complementary driver 704 (e.g., similar to or substantially similar to driver 350 or driver A of FIG. 3E ), an RF blocking device 718 (also shown as RF blocking device 358), an RF bypass capacitor 708 (also shown as RF bypass capacitor 353), and an RF bypass capacitor 724 (also shown as RF bypass capacitor 352). In this implementation, the drivers 702 and 704 each include an RF filter (shown as RF filters 712-a and 712-b, respectively) within the driver. In addition, the driver 702 includes an inductor (L1) 706 and an RF bypass capacitor (C1) 708, as well as an RF bypass capacitor (C2) 706 that is connected to the same power supply (e.g., V mid ) to the capacitor 708, PIN diodes 714 and 716, and elements in the RF filter 712-a that allow other capacitances in the RF network 710 to be charged and discharged. As can be seen, the complementary driver 704 contains a resonant network similar to that of the driver 702. For example, the complementary driver 704 includes an inductor (L1B ) and RF bypass capacitor 724 (C 1B ) and complementary driver 704 is connected to a power supply (e.g., V midB 7. The resonant circuit comprises a resonant circuit consisting of a resonant frequency .DELTA.F. 712-b that allows the resonant frequency .DELTA.F. 712-c to be charged and discharged from the resonant frequency .DELTA.F. 712-b to the capacitor 724, PIN diodes 714 and 716, and other capacitances in the RF network 710.

[0105] Capacitor C2 presents a low impedance to the RF current, which improves the effectiveness of the RF filter 712-a. Additionally, capacitor C2, along with L1 (706) and C1 (708) (and to a lesser extent L2 and C3), form part of the resonant circuit of the first resonant stage of the driver 702. Similarly, capacitor C 2B L 1B and C 1B (724) (To a lesser extent, L 2B and C 3B ) forms part of the resonant circuit of the first resonant stage of the complementary driver 704. In some embodiments, the capacitor C 2B is selected to present a low impedance to the RF currents, which serves to improve the effectiveness / performance of the RF filter 712-b.

[0106] In one non-limiting embodiment, V mid = 700V, V high = 1,500V, and L1 and L 1B = 100 μH, C1 and C 1B = 5 nF, C (of RF filter 712-a) = 1 nF, C (of RF network 710) = 60 pF, and C 2B = 1nF, and L2 and L 2B = 1.5 μH, and C3 and C 3B = 22.96 pF, C4 = 4.3 pF, L3 = 8 μH, and V highB = 1,500V (-1,500V if the polarity is reversed in FIG. 7), and V midB=700V (-700V if the polarity is reversed in FIG. 7B), although other values ​​are also contemplated in different embodiments and the example values ​​listed herein are not intended to be limiting.

[0107] FIG. 8 illustrates an example of a method 800 for operating a PIN diode switch (e.g., a PIN diode switch as described in connection with FIGS. 3A-7) according to various aspects of the disclosure. The method 800 begins with connecting at least two PIN diodes in series (operation 802). Then, an RF bypass capacitor is connected between a reference node and a first end of the series-connected PIN diodes (operation 804). In some embodiments, in operation 806, a second end of the series-connected PIN diodes is connected to the reference node. Furthermore, operation 808 includes connecting an RF network between the reference node and an internal node of the series-connected PIN diodes. Finally, a PIN diode driver is connected across the RF bypass capacitor (operation 810).

[0108] FIG. 9 illustrates an example of a method 900 for operating a PIN diode switch (e.g., a PIN diode switch described in connection with FIGS. 3A-7) according to various aspects of the disclosure. The method 900 begins with connecting at least two PIN diodes in series (operation 902). At operation 904, the method 900 includes connecting a first RF bypass capacitor between a reference node and a first end (e.g., an anode) of the series-connected PIN diodes (operation 904). In some embodiments, operation 906 includes connecting a second RF bypass capacitor between the reference node and a second end (e.g., a cathode) of the series-connected PIN diodes. In some cases, RF circuitry is connected between the reference node and an internal node of the series-connected PIN diodes (operation 908). Then, at operation 910, a first PIN diode driver is connected across the first bias capacitor. Additionally, at operation 912, a second or complementary PIN diode driver is connected across the second RF bypass capacitor. As described above, two PIN diode drivers are said to be "complementary" when they generate currents and voltages of opposite polarity. For example, in FIG. 3D, PIN diode driver 340 (driver A) and PIN diode driver 341 (driver B) are complementary, implying that drivers A and B produce currents and voltages that are opposite in polarity. In some embodiments, using complementary PIN diode drivers helps prevent the voltage at an internal node (e.g., internal node 345) from drifting or straying from the DC voltage at a reference node (e.g., reference node 347).

[0109] 10A illustrates an example of a method 1000-a for operating a PIN diode switch according to various aspects of the disclosure. The method 1000-a begins with connecting at least two PIN diodes in series (operation 1002). Then, a first RF bypass capacitor (e.g., first RF bypass capacitor 362 of FIG. 3F) is connected between a reference node (e.g., reference node 367) and a first end of the series-connected PIN diodes (operation 1004). Then, a second RF bypass capacitor (e.g., second RF bypass capacitor 363) is connected between the reference node and a second end of the series-connected PIN diodes (operation 1006). In operation 1008, an RF network (e.g., RF network 369) is connected between the reference node and an internal node (e.g., internal node 365) of the series-connected PIN diodes (operation 1008). A PIN diode driver (e.g., driver A in FIG. 3F) is then connected across the first bias capacitor (operation 1010). Additionally, a complementary PIN diode driver (e.g., driver B in FIG. 3F) is connected across the second RF bypass capacitor (operation 1012). In some cases, operation 1014 includes connecting a DC passing RF blocking circuit or device (e.g., inductor 368) between the internal node and the reference node (operation 1014).

[0110] From an application standpoint, when a DC series RF parallel PIN diode switch (e.g., the PIN diode switch described in connection with any of FIGS. 3A-7) is implemented in conjunction with a solid-state matcher, multiple PIN diodes may be switched within the time window of a pulse (power state) of an RF generator. In one non-limiting example, it is envisioned that a solid-state matcher implemented in conjunction with a PIN diode switch (e.g., PIN diode switch 301 of FIG. 3B, PIN diode switch 305 of FIG. 3F, etc.) can tune a state up to 50 microseconds in duration by allowing a PIN diode (or PIN diode string) to switch between an OFF state and an ON state within 10 microseconds or less.

[0111] 10B illustrates an example of a method 1000-b for driving series-connected PIN diodes in a PIN diode switch in accordance with various aspects of the present disclosure. Additionally or alternatively, FIG. 10B relates to a method for switching two or more PIN diodes on and off from an impedance matching network in accordance with various aspects of the present disclosure.

[0112] In some cases, the series-connected PIN diodes comprise two or more PIN diodes connected in series between a first end and a second end. Operation 1016 includes providing a current through the series-connected PIN diodes to forward bias and turn on the series-connected PIN diodes. Operation 1018 includes providing a reverse bias voltage across the series-connected PIN diodes to turn off the series-connected PIN diodes. Operation 1020 includes connecting a first RF bypass capacitor between the reference node and a first end of the series-connected PIN diodes. Operation 1022 includes connecting RF circuitry between the reference node and an internal node of the series-connected PIN diodes. Operation 1024 includes connecting a second end of the series-connected PIN diodes to the reference node. In some embodiments, when the two or more PIN diodes are on, a first impedance is presented to the RF circuitry, and when the two or more PIN diodes are off, a second impedance is presented to the RF circuitry. In some cases, the magnitude of the second impedance exceeds the magnitude of the first impedance.

[0113] 10B and described in conjunction therewith, it should be noted that operations 1016-1024 need not occur in the order shown. For example, two or more operations shown in succession (e.g., operations 1020, 1022, 1024) may in fact be performed substantially in parallel. Additionally or alternatively, operations may be performed in reverse order (e.g., operations 1020, 1022, and 1024 may be performed prior to operations 1016 and 1018).

[0114] FIG. 11 illustrates a block diagram of a computer system 1100 that may be used to implement one or more aspects of the disclosure, including at least a method for switching two or more PIN diodes on and off from an impedance matching network (e.g., as described above in connection with FIG. 10B). As shown, in this embodiment, a display 1112 and a non-volatile memory 1129 are coupled to a bus 1122 that is also coupled to a random access memory ("RAM") 1124, a processing portion 1126 (including N processing components), a field programmable gate array (FPGA) 1127, and a transceiver component 1128, including N transceivers. Although the components depicted in FIG. 11 represent physical components, FIG. 11 is not intended to be a detailed hardware diagram, and thus many of the components depicted in FIG. 11 may be realized by common construction or distributed among additional physical components. Other existing and yet to be developed physical components and architectures may also be utilized to implement the functional components described with reference to FIG. 11.

[0115] The display 1112 generally operates to provide a user interface for a user, and in some implementations, the display 1112 is realized by a touch screen display. For example, the display 1112 can be used to control and interact with the components described herein. In general, the non-volatile memory 1129 is a non-transient memory that functions to store (e.g., persistently store) data and machine-readable (e.g., processor-executable) code (including executable code associated with performing the methods described herein). In some embodiments, for example, the non-volatile memory 1129 includes boot loader code, operating system code, file system code, and non-transient processor-executable code to facilitate execution of the methods described herein, such as the method 1000 of FIGS. 10A-B.

[0116] In some implementations, non-volatile memory 1129 may be realized by flash memory (e.g., NAND or ONENAND memory). In other embodiments, other memory types may be utilized as well. While some embodiments may execute code from non-volatile memory 1129, in other embodiments, executable code in non-volatile memory may typically be loaded into RAM 1124 and executed by one or more of the N processing components in processing portion 1126.

[0117] In operation, the N processing components associated with the RAM 1124 may generally operate to execute instructions stored in the non-volatile memory 1129 to implement the functionality of the PIN diode switch system described herein. For example, non-transient processor-executable instructions for performing the methods described herein may be persistently stored in the non-volatile memory 1129 and executed by the N processing components associated with the RAM 1124. The processing portion 1126 may include a video processor, a digital signal processor (DSP), a graphics processing unit (GPU), and other processing components.

[0118] Additionally, or in other embodiments, a field programmable gate array (FPGA) 1127 may be configured to perform one or more aspects of the methodologies described herein. For example, non-transient FPGA configuration instructions may be persistently stored in non-volatile memory 1129 and accessed by FPGA 1127 (e.g., during power-up) to configure FPGA 1127.

[0119] The input component 1131 may generally operate to receive signals (e.g., the frequency of a radio frequency or RF signal, the magnitude of the current to be provided through the series-connected PIN diodes, the magnitude of the reverse bias voltage to be provided across the series-connected PIN diodes, to name a few). The output component 1132 may generally operate to provide one or more digital and / or analog signals (e.g., to a control module, to a PIN diode driver, etc.) for effecting operational aspects of the PIN diode switch systems and / or other systems described herein. In some embodiments, the computer system 1100 may be used in conjunction with one or more of the PIN diode switches described herein to drive the series-connected PIN diodes within the PIN diode switch. Additionally or alternatively, the computer system 1100 may be configured to implement a method for switching two or more PIN diodes on and off from an impedance matching network.

[0120] The depicted transceiver component 1128 includes N transceiver chains that may be used to communicate with external devices (e.g., an external controller) over a wireless or wired network. Each of the N transceiver chains may represent a transceiver associated with a particular communication scheme (e.g., WiFi, Ethernet, Profibus, etc.).

[0121] Methods 1000-a and 1000-b and other methods of the present disclosure may include other steps or variations in various other embodiments. Some or all of any of method 1000 may be performed by or embodied in hardware in controlling other associated hardware, devices, systems, or products in performing, implementing, or embodying various subject matter of the methods, and / or performed or executed by a measurement and control multiprocessor system-on-chip (MPSoC) that may include a controller, CPU, FPGA, system-on-chip (SoC), both a CPU and FPGA, and other elements together within one integrated SoC or other processing or computing device processing executable instructions. Additional Embodiments

[0122] Some embodiments of the present disclosure may be characterized as a method for driving PIN diodes in a PIN diode switch including providing series connected PIN diodes, connecting two or more PIN diodes in series; connecting a first radio frequency (RF) bypass capacitor between a reference node and a first end of the series connected PIN diodes; connecting a second RF bypass capacitor between the reference node and a second end of the series connected PIN diodes; connecting an RF circuit between the reference node and an internal node of the series connected PIN diodes, the internal node being positioned between the first end of the first PIN diode of the two or more PIN diodes and the second end of the second PIN diode of the two or more PIN diodes, the first PIN diode being adjacent to the second PIN diode; connecting a first PIN diode driver across the first RF bypass capacitor; and connecting a second PIN diode driver across the second RF bypass capacitor.

[0123] In some embodiments of the methods described above, the first PIN diode driver and the second PIN diode driver are complementary to each other and are configured to generate currents and voltages of opposite polarity.

[0124] In some embodiments of the methods described above, the first PIN diode driver and the second PIN diode driver are configured to provide a current through the series-connected PIN diodes to switch the series-connected PIN diodes to an on state, provide a reverse bias voltage across the series-connected PIN diodes to switch the series-connected PIN diodes to an off state, and a magnitude of impedance presented to an RF circuit connected between the internal node and the reference node is higher when the series-connected PIN diodes are in an off state compared to when the series-connected PIN diodes are in an on state.

[0125] In some embodiments of the methods described above, the PIN diode switch is connected to an RF impedance matching network comprising one or more reactive elements, and the PIN diode switch is further configured to connect or disconnect at least one of the one or more reactive elements to or from the remainder of the RF impedance matching network.

[0126] In some embodiments of the method described above, the first PIN diode driver and the second PIN diode driver are each a two-stage driver including: (1) a first resonant stage having a power supply and one or more of a switch and a reactive element for charging and discharging respective ones of the first and second RF bypass capacitors, the series-connected PIN diodes, and the one or more capacitive elements in the RF circuit from the power supply, and (2) a second holding stage for either holding a reverse bias voltage across the series-connected PIN diodes or supplying a current through the series-connected PIN diodes. In some cases, the PIN diodes are in an off state when a reverse bias voltage is applied and are in an on state when a current is supplied through the PIN diodes.

[0127] Some embodiments of the methods described above further include connecting an RF choke (e.g., an inductor) between the internal node and the reference node, the RF choke being configured to block RF signals and pass DC signals.

[0128] As used herein, the term "radio frequency" or "RF" should also be understood to encompass "alternating current" or "AC." For example, AC bypass capacitors may be used in place of RF bypass capacitors. Similarly, AC circuitry may be used in place of RF circuitry in some embodiments.

[0129] As used herein, the recitation of "at least one of A, B, and C" is intended to mean "any of A, B, C, or any combination of A, B, and C." The foregoing description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments without departing from the spirit or scope of the present disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0130] Terms such as "first," "second," "third," and the like may be used herein to describe various elements, components, regions, layers, and / or sections, but it should be understood that these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, component, region, layer, or section discussed below may also be referred to as a second element, component, region, layer, or section without departing from the teachings of the present disclosure.

[0131] Spatially relative terms such as "below," "below," "below side," "down," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures for ease of description. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures were turned over, elements described as being "below," or "below," or "below" the other element or feature would therefore be oriented "above" the other element or feature. Thus, the exemplary terms "below" and "below" can encompass both "upper" and "lower" orientations. The device may be oriented differently (e.g., rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein may be interpreted accordingly. Additionally, it should also be understood that when a layer is referred to as being "between" two layers, this may be the only layer between the two layers, or one or more intervening layers may also be present.

[0132] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It is further understood that the terms "comprises" and / or "comprising", as used herein, specify the presence of the stated features, integers, steps, operations, elements, components, and / or groups, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any combination of one or more of the associated listed items and may be abbreviated as " / ".

[0133] When an element or layer is referred to as being "on", "connected to", "coupled to", or "adjacent to" another element or layer, it is understood that it may be "directly on", "connected to", "coupled to", or "adjacent to" the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly connected to", "directly coupled to", or "directly adjacent to" another element or layer, no intervening elements or layers are present.

[0134] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this disclosure belongs. It is further understood that terms such as those defined in commonly used dictionaries should be interpreted to have a meaning consistent with their meaning in the relevant field and / or in the context of this specification, and will not be interpreted in an idealized or overly formal sense unless expressly defined as such in this specification.

Claims

1. An apparatus comprising: A series-connected PIN diode, the series-connected PIN diode comprising: two or more PIN diodes connected in series between a first end and a second end; an internal node located between two of the two or more PIN diodes; a series-connected PIN diode comprising: a first radio frequency (RF) bypass capacitor connected between a reference node and a first end of the series-connected PIN diode, a second end of the series-connected PIN diode being connected to the reference node; an RF circuit connected between the reference node and the internal node; a first PIN diode driver connected across the first RF bypass capacitor; An apparatus comprising:

2. 2. The apparatus of claim 1, wherein the series-connected PIN diodes comprise an equal number of PIN diodes on either side of the internal node.

3. The first PIN diode driver providing a current through the series connected PIN diodes to turn on the two or more PIN diodes; providing a reverse bias voltage across the series connected PIN diodes to turn off the two or more PIN diodes, wherein a magnitude of impedance presented to the RF circuit is higher when the two or more PIN diodes are off compared to when the two or more PIN diodes are on; The apparatus of claim 1 , configured to do one or more of the following:

4. 4. The apparatus of claim 3, wherein the apparatus is connected to an RF impedance matching network comprising one or more reactive elements, the apparatus being further configured to connect or disconnect at least one of the one or more reactive elements to or from a remainder of the RF impedance matching network.

5. The first PIN diode driver comprises a two-stage driver, the two-stage driver comprising: a first resonant stage having a power supply; one or more switches and reactive elements for charging and discharging one or more of the first RF bypass capacitor, the series connected PIN diode, and one or more capacitive elements in the RF circuit from and to the power supply; a second holding stage, maintaining a reverse bias voltage across the series connected PIN diodes, the series connected PIN diodes being in an off state when the reverse bias voltage is applied; providing a current through the series connected PIN diode, the series connected PIN diode being in an on state when a current is provided through the series connected PIN diode; a second holding stage configured to perform one or more of: The apparatus of claim 3 , comprising:

6. 2. The apparatus of claim 1 , wherein a second end of the series-connected PIN diode is connected to the reference node through a second RF bypass capacitor, the apparatus further comprising a second PIN diode driver connected across the second RF bypass capacitor.

7. 7. The apparatus of claim 6, wherein the second PIN diode driver is a complementary PIN diode driver that produces a voltage and current of opposite polarity to that of the first PIN diode driver.

8. 7. The apparatus of claim 6, further comprising a DC-passing RF blocking device connected between the internal node and the reference node, the DC-passing RF blocking device presenting a low resistance to DC current and a large magnitude impedance to RF current, the DC-passing RF blocking device being selected from the group consisting of an inductor, a parallel combination of an inductor and a capacitor, and a quarter RF wavelength long transmission line.

9. The first radio frequency (RF) bypass capacitor comprises a plurality of capacitors connected in series, and the apparatus further comprises: a plurality of DC-passing RF blocking devices connected between an intermediate node of the plurality of series-connected capacitors and an intermediate node of the series-connected PIN diodes, the plurality of DC-passing RF blocking devices presenting a low resistance to DC current and a large magnitude impedance to RF current. The apparatus of claim 1 , comprising:

10. 1. A method for driving series-connected PIN diodes in a PIN diode switch, the series-connected PIN diodes comprising two or more PIN diodes connected in series between a first end and a second end, the method comprising: providing a current through the series connected PIN diodes to forward bias and turn on the series connected PIN diodes, wherein an RF network is coupled between a reference node and an internal node, a first RF bypass capacitor is connected between a first end of the series connected PIN diodes and the reference node, and the internal node is located between two of the two or more PIN diodes; providing a reverse bias voltage across the series connected PIN diode to turn off the series connected PIN diode; a first impedance is presented to the RF circuitry when the series connected PIN diode is on and a second impedance is presented to the RF circuitry when the series connected PIN diode is off; The magnitude of the second impedance is greater than the magnitude of the first impedance. A method comprising:

11. The method of claim 10 , wherein a second end of the series-connected PIN diode is coupled to the reference node.

12. The method of claim 11 , wherein a second end of the series-connected PIN diode is coupled to the reference node through a second RF bypass capacitor.

13. 13. The method of claim 12, wherein a first PIN diode driver is connected across the first RF bypass capacitor and a second PIN diode driver is connected across the second RF bypass capacitor.

14. 14. The method of claim 13, wherein the second PIN diode driver is a complementary PIN diode driver that produces a voltage and a current with an opposite polarity to that of the first PIN diode driver.

15. 11. The method of claim 10, further comprising charging and discharging one or more of the first RF bypass capacitor, the series connected PIN diode, and one or more capacitive elements in the RF network from and to a power supply of a first resonant stage of a two-stage driver coupled across the first RF bypass capacitor.

16. 16. The method of claim 15, further comprising holding the reverse bias voltage across the series connected PIN diodes via a holding stage of the two-stage driver connected across the first RF bypass capacitor.

17. 16. The method of claim 15, further comprising: providing the current through the series connected PIN diode via a holding stage of the two-stage driver connected across the first RF bypass capacitor.

18. The method of claim 10 , further comprising disconnecting at least one reactive element in an impedance matching network when the series connected PIN diode is off.

19. 1. A non-transitory, tangible computer readable storage medium encoded with processor readable instructions for implementing a method for switching two or more PIN diodes on and off from an impedance matching network, the method comprising: providing a current in a forward bias through the two or more PIN diodes to turn on the two or more PIN diodes, wherein an RF network is coupled between a reference node and an internal node, a first RF bypass capacitor is connected between a first end of the two or more PIN diodes and the reference node, and the internal node is located between two of the two or more PIN diodes; providing a reverse bias voltage across the two or more PIN diodes to turn off the two or more PIN diodes; when the two or more PIN diodes are on, a first impedance is presented to the RF circuitry, and when the two or more PIN diodes are off, a second impedance is presented to the RF circuitry; The magnitude of the second impedance is greater than the magnitude of the first impedance.

1. A non-transitory tangible computer readable storage medium comprising:

20. Providing the reverse bias voltage comprises: providing a first voltage to remove charge from a specific area of ​​each of the two or more PIN diodes; providing the reverse bias voltage and maintaining the two or more PIN diodes off, the magnitude of the first voltage being less than the magnitude of the reverse bias voltage; 20. The non-transitory, tangible computer readable storage medium of claim 19, comprising:

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