Control of grain growth for bonding and bonded structures with controlled grain growth

Abstract

Disclosed is an element including a conductive feature at a contact surface of the element and a non-conductive region at the contact surface in which the conductive feature is at least partially embedded, the contact feature including a conductive material and an amount of impurities at grain boundaries of the conductive material, the impurities including a non-alloying material that does not form an alloy with the conductive material at a bonding temperature.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority under 35 U.S.C. § 119 to U.S. Provisional Patent Application No. 63 / 293,300, filed December 23, 2021, and entitled “CONTROLLED GRAIN GROWTH FOR BONDING AND BONDED STRUCTURE WITH CONTROLLED GRAIN GROWTH,” the contents of which are incorporated herein by reference in their entirety for all purposes.

[0002] This field relates to grain growth controlled conductive features. [Background technology]

[0003] Semiconductor elements, such as integrated device dies or chips, can be mounted or stacked on other elements. For example, the semiconductor elements can be mounted on a carrier, such as a package substrate, an interposer, a reconstituted wafer, or an element. As another example, a semiconductor element can be stacked on another semiconductor element, such as a first integrated device die on a second integrated device die. Each semiconductor element can have conductive pads for mechanically and electrically coupling the semiconductor elements to each other. There is a continuing need to improve the method of forming the conductive pads for reliable coupling. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Pat. No. 9,564,414 [Patent Document 2] U.S. Pat. No. 9,391,143 [Patent Document 3] U.S. Pat. No. 10,434,749 [Patent Document 4] U.S. Pat. No. 9,716,033 [Patent Document 5] U.S. Pat. No. 9,852,988 Summary of the Invention [Means for solving the problem]

[0005] The detailed description will now be made with reference to the accompanying drawings, in which the use of the same reference numbers in different drawings indicates similar or identical items.

[0006] In this description, the devices and systems illustrated in the figures are depicted as having multiple components. Various implementations of the devices and / or systems described herein can include fewer components and still depart from the scope of the disclosure. Alternatively, other implementations of the devices and / or systems can include additional components or different combinations of the components described and still depart from the scope of the disclosure.

[0007] These and other aspects will become apparent from the following description of the preferred embodiments and the accompanying drawings which are intended to illustrate, but not to limit, the invention. [Brief description of the drawings]

[0008] [Figure 1A] 1 is a schematic image of impurities in a metal (e.g., copper) grain structure exhibiting a conductive feature after plating having a relatively low or minimal impurity concentration, according to one embodiment. [Figure 1B] 1B is a representation of the grain structure shown in FIG. 1A immediately prior to annealing, according to one embodiment. [Figure 1C] 1B is a representation of the grain structure shown in FIG. 1A after annealing, according to one embodiment. [Figure 2A] 1 is an image showing schematic impurity images of a metal (e.g., copper) grain structure exhibiting conductive features after plating with impurity concentrations selected to manage grain growth, according to one embodiment. [Figure 2B] 2B is a representation of the grain structure shown in FIG. 2A immediately prior to annealing, according to one embodiment. [Figure 2C] 2B is a representation of the grain structure shown in FIG. 2A after annealing, according to one embodiment. [Figure 3A] 1 is a schematic image of impurities in a metal (e.g., copper) grain structure exhibiting a conductive feature after plating having a relatively high impurity concentration, according to one embodiment. [Figure 3B] 3B is a representation of the grain structure shown in FIG. 3A immediately prior to annealing, according to one embodiment. [Figure 3C] 3B is a representation of the grain structure shown in FIG. 3A after annealing, according to one embodiment. [Figure 4A-4D] 1A-1C are a series of schematic cross-sectional side views illustrating a multi-step method by which a device may be formed according to one embodiment. [Figure 4E] FIG. 2 is a schematic cross-sectional side view of a first and second element prepared to be directly bonded, according to one embodiment. [Figure 4F] FIG. 4F is a schematic cross-sectional side view of the first and second elements of FIG. 4E after being directly bonded together, according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] This disclosure describes a method for controlling metal grain growth of conductive features (e.g., conductive pads, through-substrate vias (TSVs), etc.) in devices, such as microelectronic devices. Various embodiments disclosed herein can be advantageous for direct metal bonding, such as direct hybrid bonding. For example, as shown generally in FIG. 4E and FIG. 4F, two or more semiconductor devices 102, 152 (such as integrated device dies, wafers, etc.) can be stacked or bonded together to form a bonded structure 100. A conductive feature 206 of one device 102 can be electrically connected to a corresponding conductive feature 156 of another device (e.g., a second device 156). Any suitable number of devices can be stacked in the bonded structure 100. The methods and conductive feature structures described herein can be useful in other contexts as well.

[0010] In some embodiments, the elements (e.g., the first element 102 and the second element 152) are directly bonded to each other without the use of adhesive. In various embodiments, the non-conductive (e.g., semiconductor or inorganic dielectric) region 130 of the first element 102 can be directly bonded to the corresponding non-conductive (e.g., semiconductor or inorganic dielectric) region 160 of the second element 152 without the use of adhesive. Although not shown, the non-conductive layer can be provided on a bulk device such as a semiconductor substrate in which devices are formed. In various embodiments, the conductive features 206 (e.g., metal pads, contact pads, TSVs, etc.) of the first element 102 can be directly bonded to the corresponding conductive features 156 (e.g., metal pads, contact pads, TSVs, etc.) of the second element 152 without the use of adhesive. The non-conductive region 130 can be referred to as a non-conductive bonding region or bonding layer of the first element 102. In some embodiments, the non-conductive regions 130 of the first element 102 can be directly bonded to the corresponding non-conductive regions 160 of the second element 152 without the use of adhesives using direct bonding techniques as disclosed in at least U.S. Patent Nos. 9,564,414, 9,391,143, and 10,434,749, the contents of each of which are incorporated herein by reference in their entirety for all purposes. In other applications, the bonded structure 100 can directly bond the non-conductive regions 130 of the first element 102 to the conductive features 156 of the second element 152 such that the conductive features 206 of the first element 102 closely mate with the non-conductive regions 160 of the second element 152.

[0011] In various embodiments, direct bonding can be formed without the use of an intermediate adhesive. For example, the semiconductor or dielectric bonding surfaces (e.g., the nonconductive surface 136 of the first nonconductive region 130 of the first element 102 and the nonconductive surface 146 of the second nonconductive region 160 of the second element 152) can be polished to a high degree of smoothness. The nonconductive bonding surfaces can be cleaned and exposed to a plasma to activate the surfaces. In some embodiments, the nonconductive bonding surfaces can be terminated with chemical species after or during activation (e.g., in a plasma). Without being limited by theory, in some embodiments, an activation process can be performed to break chemical bonds at the nonconductive bonding surfaces, and the termination process can provide the nonconductive bonding surfaces with additional chemical species that increase the bond energy during direct bonding. In some embodiments, activation and termination are performed in the same step, such as activating and terminating the nonconductive surfaces with a plasma or a wet etchant. In other embodiments, the nonconductive bonding surfaces can be terminated in a separate process to provide additional chemical species for direct bonding. In various embodiments, the terminating species can include nitrogen. Additionally, in some embodiments, the non-conductive bonding surface can be exposed to fluorine. For example, there can be one or more fluorine peaks near the layers and / or the non-conductive bonding interface. Thus, in a direct bond structure, the bonding interface between the two non-conductive regions 130, 160 can include a very smooth interface with high nitrogen content and / or fluorine peaks at the bonding interface. Further examples of activation and / or termination treatments are described in U.S. Patent Nos. 9,564,414, 9,391,143, and 10,434,749, the contents of each of which are incorporated herein by reference in their entirety for all purposes.

[0012] In various embodiments, the conductive contact features 206 (e.g., contact pads, TSVs, etc.) of the first element 102 may also be directly bonded to corresponding conductive features 156 (e.g., contact pads, TSVs, etc.) of the second element 152. For example, direct hybrid bonding techniques may be used to provide conductor-conductor direct bonding along a bonding interface that includes covalently directly bonded dielectric-dielectric surfaces (e.g., the non-conductive surface 136 of the first non-conductive region 130 of the first element 102 and the non-conductive surface 146 of the second non-conductive region 160 of the second element 152) prepared as described above. In various embodiments, direct bonding techniques disclosed in at least U.S. Patent Nos. 9,716,033 and 9,852,988 can be used to form conductor-conductor (e.g., conductive feature 206-conductive feature 156) direct bonds (e.g., bonds between the conductive surface 138 of the first conductive feature 206 of the first element 102 and the conductive surface 148 of the second conductive feature 156 of the second element 152) and dielectric-dielectric hybrid bonds, the contents of each of which are incorporated herein by reference in their entirety for all purposes. The bonded structures 100 described herein are also useful for direct metallurgical bonds or other bonding techniques that do not involve non-conductive region bonding.

[0013] In some embodiments, the inorganic dielectric bonding surfaces (e.g., non-conductive surfaces 136, 146) can be prepared to bond directly to each other without the use of an intermediary adhesive as described above. The conductive contact pads, such as the first and second conductive features 206, 156 (which can be surrounded by non-conductive dielectric field regions, such as the first and second non-conductive regions 130, 160) can also be bonded directly to each other without the use of an intermediary adhesive. In some embodiments, the respective conductive surfaces 138, 148 of the contact pads (e.g., the first and second conductive features 206, 156) can be recessed downward from the outer (e.g., upper) non-conductive surfaces 136, 146 of the dielectric field regions or non-conductive regions 130, 160 by, for example, less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, for example, within a range of 2 nm to 20 nm, or within a range of 4 nm to 10 nm. In some embodiments, the non-conductive regions 130, 160 can be bonded directly to each other without the use of an adhesive at room temperature, after which the bonded structure 100 can be annealed. Upon annealing, the conductive features 206, 156 (which may be, for example, contact pads, TSVs, etc.) may expand relative to the non-conductive regions 130, 160 and contact one another to form metal-metal direct bonds. The use of hybrid bonding techniques, such as Direct Bond Interconnect (DBI®), available from Adeia, Inc., San Jose, Calif., may advantageously allow for a high density (e.g., small or fine pitch for regular arrays) of pads (e.g., conductive features 206, 156) connected across the direct bond interface. In various embodiments, the conductive features 206, 156 may include copper, although other metals may be suitable.

[0014] Thus, in a direct bonding process, the first element 102 may be directly bonded to the second element 152 without the use of an intermediary adhesive. In some configurations, the first element 102 may include a singulated element, such as a singulated integrated device die. In other configurations, the first element 102 may include a carrier or substrate (e.g., a wafer) that includes multiple (e.g., tens, hundreds, or more) element regions that upon singulation form multiple integrated device dies. Similarly, the second element 152 may also include a singulated element, such as a singulated integrated device die. In other arrangements, the second element 152 may include a carrier or substrate (e.g., a wafer).

[0015] As described herein, the first and second elements 102, 152 can be directly bonded to each other without the use of adhesives, which is different from a deposition process. Thus, the first and second elements 102, 152 can include non-deposited elements. Additionally, a directly bonded structure (e.g., bonded structure 100), unlike a deposited layer, can include defect regions along the bond interface where nanovoids exist. The nanovoids can form due to activation (e.g., exposure to plasma) of the bonded surfaces. As discussed above, the bond interface can include concentrations of materials from the activation and / or last chemical treatment process. For example, in an embodiment utilizing a nitrogen plasma for activation, a nitrogen peak can form at the bond interface. In an embodiment utilizing an oxygen plasma for activation, an oxygen peak can form at the bond interface. In some embodiments, the bond interface can include silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride, and prior to direct bonding, a level of nitrogen is present at the bond interface indicative of nitrogen termination of at least one of these elements. In some embodiments, the bond interface can be free of nitrogen and nitrogen related moieties. As described herein, the direct bonds can include covalent bonds that are stronger than van der Waals bonds. The bond layer can also include a polished surface that is highly smooth and planarized.

[0016] In various embodiments, metal-metal bonds between contact pads (e.g., conductive features 206, 156) can be bonded such that copper grains 116 grow into one another across the bond interface. In some embodiments, the copper can have grains 116 oriented perpendicularly along the 111 crystal planes to enhance diffusion of copper across the bond interface. In some embodiments, misorientation of the orientation of the 111 crystal planes in the conductive material can be within ±30° relative to the perpendicular direction from the conductive surface of the conductive material (e.g., conductive surfaces 138, 148 of the conductive features 206, 156 of the first and second elements 102, 152). In some embodiments, the crystal misorientation can be within ±20° relative to the perpendicular direction, or within ±15°. The bonding interface can extend substantially all the way to at least a portion of the bonded contact pads (e.g., conductive features 206, 156) such that there are substantially no gaps between the bonded contact pads (e.g., conductive features 206, 156) or the non-conductive bonding areas (e.g., non-conductive areas 130, 160) nearby. In some embodiments, a barrier layer (e.g., which may include copper or a copper alloy) can be provided below the conductive features 206, 156. However, in other embodiments, there can be no barrier layer below the conductive features 206, 156, as described, for example, in U.S. Patent Application Publication No. 2019 / 0096741, which is incorporated herein by reference in its entirety for all purposes.

[0017] The annealing temperature (also referred to herein as the "bonding temperature") and annealing time for forming a metal-metal direct bond (e.g., a direct bond between the conductive surface 138 of the first conductive feature 206 of the first element 102 and the conductive surface 148 of the second conductive feature 156 of the second element 152) can affect the thermal budget consumption of the annealing process. The bonding temperature can be, for example, in the range of 100°C to 250°C, 100°C to 200°C, 150°C to 200°C, or 100°C to 150°C. To minimize the thermal (energy) budget consumption, it may be desirable to reduce the annealing temperature and / or annealing time. The 111 crystal plane ( <111> ) can be 3-4 orders of magnitude faster than diffusion along 100 or 110 crystal planes. Also, metals (e.g., Cu) with grains oriented along 111 crystal planes can have higher surface mobility than conventional back end of line (BEOL) copper. Furthermore, creep of the nanotextured surface of Cu on the 111 crystal planes allows for low temperature direct metal-metal bonding (which can include bonding occurring at bonding temperatures below 250° C.). Thus, to reduce annealing times and / or annealing temperatures for direct bonding (e.g., direct hybrid bonding), it can be advantageous to have 111 crystal planes on the bonding surfaces (e.g., contact surfaces 104, 154). In some embodiments, the benefits of having 111 crystal planes can be especially pronounced at low temperatures, since metal surface diffusion (e.g., Cu surface diffusion) also slows as annealing temperatures are reduced. Thus, in various embodiments disclosed herein, the crystal structure can have grains oriented vertically along the 111 crystal planes to enhance metal diffusion (e.g., Cu diffusion) during direct bonding.

[0018] The metal layer can be formed using a process selected to plate a copper (Cu) layer with Cu in the 111 crystal orientation. For example, the Cu layer can be deposited from a non-superfilling or super-filling electroplating bath where the plating chemistry is selected to optimize efficient filling of voids (e.g., vias, trenches) in the substrate rather than optimizing the direct metal-metal bond that occurs during direct hybrid bonding. Subsequent metal processing, as described later in this specification, can facilitate subsequent bonding and allow any desired plating chemistry to be employed to optimize other considerations such as filling as described above. The microstructure (e.g., grain size) of the deposited or coated metal layer (e.g., conductive elements 206, 156) can be stabilized prior to a metal planarization process (e.g., chemical mechanical polishing, or CMP). The microstructure of the metal layer (e.g., conductive elements 206, 156) can be stabilized, for example, by an annealing step separate from the subsequent annealing step of direct hybrid bonding. In some embodiments, the plated metal may be partially stabilized prior to the CMP operation that forms the bonding surface (e.g., contact surface 104, 154). In other embodiments, the plated metal may be fully stabilized prior to the CMP operation.

[0019] As discussed above, the contact pads (e.g., conductive features 206, 156) can expand relative to the non-conductive bonding regions (e.g., non-conductive regions 130, 160) and contact one another to form a direct metal-metal bond (e.g., bond between contact surfaces 104, 154). For example, the expansion of the contact pads (e.g., conductive features 206, 156) can be caused primarily by thermal expansion of the material (e.g., copper) of the contact pads relative to the non-conductive bonding regions (e.g., non-conductive regions 130, 160). Grain growth of the contact pads (e.g., conductive features 206, 156) can at least partially cause the expansion of the contact pads. It is believed that grain growth beneficially occurs when the contact pads (e.g., conductive features 206, 156) are annealed to expand and bond the contact pads together, for example, by bonding the contact surfaces 104, 154. However, grain growth of the contact pads (e.g., conductive features 206, 156) can also occur prior to bonding or annealing. For example, in a material such as copper, grain growth may occur at room temperature due to diffusion between the copper grains 116. If the grains 116 grow at room temperature, a higher annealing temperature may be required to induce further grain growth than would be required if the grains 116 did not grow at room temperature. This is because the grown grains may be in a more stable state. The grain growth and / or expansion of the contact pads (e.g., conductive features 206, 156) may be temperature driven. For reliable bonding between the contact pads (e.g., conductive features 206, 156), it may be beneficial to minimize grain growth prior to bonding or annealing to conserve potential energy of the contact pad material until bonding or annealing, so that the material expands sufficiently during bonding or annealing. In other words, direct hybrid bonding may be performed by expanding the contact pads (e.g., conductive features 206, 156) during annealing, which may be partially driven by grain growth.One way to complete this anneal with less impact on the thermal budget is to reduce or minimize the grain growth (and corresponding release of potential energy) that occurs at room temperature. This reduction in grain growth at room temperature preserves the potential energy of the conductive material 108 until annealing at the bonding temperature. In such a configuration, the potential energy released from grain growth can contribute to promoting direct bonding between the contact pads (e.g., conductive features 206, 156) during the anneal, rather than being released and lost at ambient conditions prior to annealing.

[0020] The above phenomenon can be expressed, at least in part, by the following equation:

number

[0021] Various embodiments disclosed herein relate to forming an element (e.g., element 102) that includes a conductive pad (e.g., conductive feature 206) having a direct bond surface (e.g., contact surface 104) with impurities 120 present at grain boundaries 118 of the conductive material 108 (e.g., copper) of the conductive pad (e.g., contact surface 104) to prevent or minimize grain growth of the conductive material 108 (e.g., copper) prior to bonding or annealing. The impurities 120 may be located at the grain boundaries 118 within the conductive material 108 (e.g., copper) of the contact pad (e.g., conductive feature 206).

[0022] 1A-1C show the morphology evolution of the contact surface microstructure of a conductive feature 106 of a device (e.g., a semiconductor device) immediately after plating when there are relatively low or minimal levels of impurities 120 at the grain boundaries 118. FIG. 1A-1C show how the contact surface microstructure evolves as the conductive feature 106 is processed during a direct hybrid bonding procedure. FIG. 1A shows the contact surface microstructure (e.g., size and shape of grains 116) of the conductive feature 106 immediately after plating. FIG. 1B shows the microstructure of the same contact surface of the conductive feature 106 but immediately before an annealing process after partial room temperature grain growth has occurred. FIG. 1C also shows the microstructure of the same contact surface of the conductive feature 106 after an annealing process at a bonding temperature. The bonding temperature can be in the range of, for example, 100° C. to 250° C., 100° C. to 200° C., 150° C. to 200° C., or 100° C. to 150° C. It is understood that the difference between the microstructures of Figure 1A and 1B is at least partially a result of the conductive features 106 being exposed to ambient conditions (e.g., room temperature) between plating and annealing, and the difference between the microstructures of Figure 1B and 1C is at least partially a result of the conductive features 106 being annealed at the bonding temperature.

[0023] 1A-1C, the conductive feature 106 can include a conductive material 108 and a non-alloy material 110. The non-alloy material 110 does not form an alloy with the conductive material 108 at the bonding temperature. The conductive material 108 can include copper, gold, silver, or alloys thereof. The conductive material 108 can form grains 116. At interfaces between the grains 116 of the conductive material 108, grain boundaries 118 can occur. The non-alloy material 110 can include, for example, metal compounds, metal oxides, non-metal compounds, non-metal oxides, chemical compounds, and / or refractory materials, as further described herein. The non-alloy material 110 can form impurities 120 in the conductive material 108 of the conductive feature 106. Each impurity 120 can diffuse or migrate throughout the conductive material 108 and can reside within the grains 116 or along the grain boundaries 118 or accumulate around the grain boundaries 118. When a sufficient amount of impurities 120 accumulates along the grain boundaries 118, the impurities 120 can "pin" the grains 116 and inhibit grain growth. An additional amount of energy can also be introduced to induce growth of the pinned grains 116. For example, this can include annealing the microstructure of the grains 116 with the impurities 120 accumulated to an additional high temperature for an appropriate time. The additional high temperature increases the mobility of atoms within the grains 116, particularly along the grain boundaries 118. The increased mobility of the grain boundaries 118 causes the grains 116 to grow and increase in size. The word "pinning" does not mean that the pinned grain boundaries 118 are completely immobile, but rather the impurities 120 can exert a force (e.g., a drag force or pinning force) that can slow down grain growth by inhibiting the mobility of the grain boundaries 118. In essence, the more impurities 120 present along the grain boundaries 118, the more pinning can be increased and the grain growth can be reduced.

[0024] In Figures 1A-1C, the conductive feature 106 includes a minimal level of impurities 120, i.e., the grains 116 of the conductive material 108 are minimally pinned. Figure 1A shows very fine grains 116 of the conductive material 108 as seen immediately after plating. Figure 1A also shows a minimal amount of impurities 120 in the conductive material 108. Due in part to the minimal level of impurities 120, the grains 116 in the conductive feature 106 are not pinned and are allowed to grow even at ambient conditions (e.g., room temperature) prior to annealing, as shown in Figure 1B. This grain growth that may occur at ambient temperatures may be referred to as "natural annealing" and is distinct from annealing at the bonding temperature. Figure 1C shows that the grains 116 in the conductive feature 106 are allowed to continue to grow during annealing at the bonding temperature.

[0025] 2A-2C show the morphology change of the microstructure of the contact surface 104 of the conductive feature 206 in the element 102 (shown in FIG. 4D) when an amount of impurities 120 selected to manage grain growth is present at the grain boundaries 118 immediately after plating, according to various embodiments. The amount of impurities 120 at the grain boundaries 118 shown in FIG. 2A is greater than the amount shown in FIG. 1A. FIGS. 2A-2C show how the microstructure of the contact surface 104 (shown in FIG. 4D) can evolve as the conductive feature 206 is processed, according to various embodiments. FIG. 2A shows the microstructure (e.g., size and shape of grains 116) of the contact surface 104 of the conductive feature 206 (shown in FIG. 4D) immediately after plating, according to various embodiments. FIG. 2B shows the microstructure of the same contact surface 104 (shown in FIG. 4D) but immediately before annealing, according to various embodiments. And FIG. 2C shows the microstructure of the same contact surface 104 (shown in FIG. 4D) after annealing at the bonding temperature, according to various embodiments. The bonding temperature can be, for example, in the range of 100° C. to 350° C., 100° C. to 250° C., 100° C. to 200° C., 150° C. to 200° C., or 100° C. to 150° C. It is understood that the difference between the microstructures of FIG. 2A and FIG. 2B is at least partially a result of the conductive features 206 being exposed to ambient conditions (e.g., room temperature) between plating and annealing. It is understood that the difference between the microstructures of FIG. 2B and FIG. 2C is at least partially a result of the conductive features 206 being annealed at the bonding temperature.

[0026] 2A-2C, the conductive feature 206 can include a conductive material 108 and a non-alloy material 110. The non-alloy material 110 does not form an alloy with the conductive material 108 at the bonding temperature. According to various embodiments, the conductive material 108 can include copper, gold, silver, or alloys thereof. The conductive material 108 can form grains 116. At interfaces between the grains 116 of the conductive material 108, grain boundaries 118 can occur. According to various embodiments, the non-alloy material 110 can include, for example, metal compounds, metal oxides, non-metal compounds, non-metal oxides, chemical compounds, and / or refractory materials, as further described herein. The non-alloy material 110 can form impurities 120 in the conductive material 108 of the conductive feature 206. Each impurity 120 can diffuse or migrate throughout the conductive material 108 and typically accumulate along the grain boundaries 118. When a sufficient amount of impurities 120 accumulates along the grain boundaries 118 or around the grains 116, the impurities 120 can "pin" the grains 116 and inhibit the growth of the various grains 116. An additional amount of energy can also be introduced to cause the pinned grains 116 to grow. One example method for de-pinning the grains 116 can include exposing the pinned microstructure to an additional high temperature for a suitable time. The additional high temperature increases the mobility of atoms within the grains 116, particularly along the grain boundaries 118. The increased mobility of the grain boundaries 118 de-pins the pinned grains, thus allowing the grains 116 to grow and increase in size. In essence, the presence of more impurities 120 along the grain boundaries 118 can increase pinning and reduce grain growth.

[0027] In Figures 2A-2C, the conductive feature 206 includes a first level of impurities 120 selected to manage grain growth, i.e., to selectively pin the grains 116 of the conductive material 108, according to various embodiments. Figure 2A shows very fine grains 116 of the conductive material 108 as seen immediately after plating. Figure 2A also shows an amount of impurities 120 in the conductive material 108 selected to manage grain growth. The amount of impurities can be selected to pin the grains 116 from growing before bonding and annealing (e.g., at ambient conditions) as shown in Figure 2B, but allow grain growth during annealing at the bonding temperature (e.g., 100°C-250°C) as shown in Figure 2C. Due in part to the level of impurities 120 selected to manage grain growth, at ambient conditions (e.g., room temperature) before annealing as shown in Figure 2B, the grains 116 in the conductive feature 206 are sufficiently pinned to prevent or minimize grain growth. The presence of an amount of impurities 120 selected to manage grain growth can prevent or minimize "spontaneous annealing." Figure 2C shows that grains 116 in conductive feature 206 can grow during annealing at the bonding temperature.

[0028] The amount of impurities 120 along the grain boundaries 118 selected to manage grain growth can be balanced such that at ambient conditions (e.g., room temperature), there can be enough impurities 120 along the grain boundaries 118 to cause enough pinning to reduce or minimize grain growth, but at the bonding temperature, which can be in the range of, for example, 100° C.-250° C., 100° C.-200° C., 150° C.-200° C., or 100° C.-150° C., there is not enough impurities 120 along the grain boundaries 118 to prevent or minimize grain growth. As described herein, the impurities 120 in an amount selected to manage such grain growth can facilitate direct hybrid bonding by allowing grain growth that can help form a reliable direct bond between two conductive features 206, 156 of two elements 102, 152 (as shown in FIG. 4F) at a bonding temperature (e.g., in the range of 100° C. to 250° C., 100° C. to 200° C., 150° C. to 200° C., or 100° C. to 150° C.) after maintaining the potential energy of the conductive material 108 at ambient conditions.

[0029] 3A-3C show the morphology change of the microstructure of the contact surface 104 (shown in FIG. 4D) of the conductive feature 306 in the element 102 (shown in FIG. 4D) when high levels of impurities 120 are present at the grain boundaries 118 immediately after plating, according to various other embodiments. The amount of impurities 120 at the grain boundaries 118 shown in FIG. 3A is higher than that shown in FIG. 2A. FIGS. 3A-3C show how the microstructure of the contact surface 104 (shown in FIG. 4D) can evolve as the conductive feature 306 is processed, according to various embodiments. FIG. 3A shows the microstructure (e.g., size and shape of grains 116) of the contact surface 104 of the conductive feature 306 (shown in FIG. 4D) immediately after plating, according to various embodiments. FIG. 3B shows the microstructure of the same contact surface 104 of the conductive feature 306 (shown in FIG. 4D) but immediately before annealing, according to various embodiments. FIG. 3C also shows the microstructure of the same contact surface 104 (shown in FIG. 4D) of the conductive feature 306 after annealing at a bonding temperature, according to various embodiments. The bonding temperature can be in the range of, for example, 100° C. to 400° C., 100° C. to 250° C., 100° C. to 200° C., 150° C. to 200° C., or 100° C. to 150° C. It is understood that the difference between the microstructure of FIG. 3A and the microstructure of FIG. 3B is at least partially a result of the conductive feature 306 being exposed to ambient conditions (e.g., room temperature) between plating and annealing. It is understood that the difference between the microstructure of FIG. 3B and the microstructure of FIG. 3C is at least partially a result of the conductive feature 306 being annealed at the bonding temperature.

[0030] 3A-3C, the conductive feature 306 can include a conductive material 108 and a non-alloy material 110. The non-alloy material 110 does not form an alloy with the conductive material 108 at the bonding temperature. According to various embodiments, the conductive material 108 can include copper, gold, silver, or alloys thereof. The conductive material 108 can form grains 116. At interfaces between the grains 116 of the conductive material 108, grain boundaries 118 can occur. According to various embodiments, the non-alloy material 110 can include, for example, a material that does not dissolve in the conductive material 108 at the bonding temperature, and can include metal compounds, metal oxides, non-metal compounds, non-metal oxides, chemical compounds, and / or heat resistant materials as further described herein. The non-alloy material 110 can form impurities 120 in the conductive material 108 of the conductive feature 306. Each impurity 120 can diffuse or migrate throughout the conductive material 108 and can be present within the grains 116 or along the grain boundaries 118. If a sufficient amount of impurities 120 are present along the grain boundaries 118, the impurities 120 can "pin" the grains 116 and inhibit grain growth. In short, the more impurities 120 present along the grain boundaries 118, the more pinning tends to decrease grain growth. In some embodiments, the non-alloy material 110 can include a material that has limited solubility in the conductive material 108 at the bonding temperature. For example, the solubility of the non-alloy material 110 in the conductive material 108 can be less than 20% at the bonding temperature and less than 5%, or less than 1%, or less than 0.05% at room temperature.

[0031] 3A-3C, the conductive feature 306 includes a second high level of impurities 120, i.e., can substantially completely pin the grains 116 of the conductive material 108. FIG. 3A shows very fine grains 116 of the conductive material 108 as seen immediately after plating. FIG. 3A also shows a relatively high amount of impurities 120 in the conductive material 108. The amount of impurities 120 can be selected to be high enough to cause sufficient pinning to prevent or minimize grain growth in the conductive feature 306, both at ambient conditions (e.g., room temperature) prior to bonding and annealing as shown in FIG. 3B, and during annealing at bonding temperatures (e.g., in the range of 100° C.-400° C., 100° C.-250° C., 100° C.-200° C., 150° C.-200° C., or 100° C.-150° C.) as shown in FIG. 3C. The presence of high levels of impurities 120 in the conductive features 306 can reduce or minimize both the "natural anneal" and the anneal at the bonding temperature. In short, Figure 3B shows that at room temperature the size of the grains 116 can remain similar to that shown in Figure 3A, and Figure 3C shows that even after annealing at the bonding temperature the size of the grains 116 can remain similar to that shown in Figures 3A and 3B. Thus, if grain growth is not desired, a high enough impurity content can be introduced to prevent grain growth.

[0032] The impurities 120 used in FIGS. 1A-3C may include non-alloyed impurities 120 that do not form an alloy with the conductive material 108 (e.g., copper) of the conductive feature 206. The non-alloyed impurities 120 may include materials that do not dissolve with the conductive material 108 (e.g., copper) of the conductive feature 206 at the annealing temperature of interest (e.g., bonding temperature). In some embodiments utilizing copper as the conductive material 108 of the conductive feature 206, the non-alloyed impurities 120 may include metal compounds. In some embodiments, the non-alloyed impurities 120 may include metal oxides. In some embodiments, the non-alloyed impurities 120 may include non-metal compounds. In some embodiments, the non-alloyed impurities 120 may include non-metal oxides. In some embodiments, the non-alloyed impurities 120 may include other compounds, such as ceramic materials, i.e., two or more combined chemical elements. In some embodiments, the non-alloyed impurities 120 may include refractory materials. A non-exhaustive list of such materials can include aluminum nitride, tantalum particles and nanoparticles, tantalum nitride particles and nanoparticles, titanium nitride particles and nanoparticles, aluminum oxide, nickel oxide particles and nanoparticles, magnesium oxide particles and nanoparticles, manganese oxide particles and nanoparticles, glass, ceramic or glass-ceramic particles and nanoparticles, silicon carbide (SiC), silicon nitride (SiN), silicon carbide-silicon nitride (SiCN), silicon oxide, tantalum (Ta), zirconium (Zr), molybdenum (Mo), and tungsten (W).

[0033] In some embodiments, the impurities 120 can be introduced by co-deposition sputtering the impurities 120 and the conductive material 108 into the cavity 122 of FIG. 4B to form the structure of FIG. 4C. In some embodiments, a sputtering target including the impurities 120 and the conductive material 108 can be sputtered into the cavity 122 to form the structure of FIG. 4C. In some embodiments, the impurities 120 can be introduced into the electroplating bath as a particulate material and co-deposited into the conductive material 108 during the plating step to form the conductive material 108 of FIG. 4C. In some embodiments, the impurities 120 can include silicon oxide (or other non-metallic oxide) particles or silicon carbide (or other non-metallic compounds). In some embodiments, the non-alloy material can be introduced into the conductive material 108 of the conductive feature 206 as very fine particles (e.g., particles having linear lateral dimensions of less than 200 nm, less than 100 nm, less than 50 nm, or less than 20 nm) of non-alloy impurities 120 into an electroplating bath and co-deposited with the conductive material 108 on the substrate of interest, for example, by galvanostatic or potentiostatic techniques, pulse plating, or various combinations thereof.

[0034] The conductive features 106 shown in Figures 1A-1C can have less than 20 ppm of impurities 120, such as 2 parts per million (ppm) or 3 ppm of impurities 120. For example, the conductive features 106 of Figure 1A can have 2 ppm to 20 ppm, 5 ppm to 20 ppm, 2 ppm to 15 ppm, or 5 ppm to 15 ppm of impurities 120. In such conductive features 106, the grains 116 of the conductive material 108 of the conductive features 106 can grow at room temperature. The grown grains 116 shown in Figure 1B, which have a lower potential energy compared to the fine grains 116 shown in Figure 1A, can be in a relatively stable state that may require a relatively high bonding temperature for the tight interlocking of the multiple conductive features 106 of the multiple elements directly bonded to each other. In some applications, a relatively low direct bonding or annealing temperature (low thermal budget) may be preferred due to some limitations or constraints imposed by one of the bonded elements 102, 152 (shown in FIG. 4F). One example of a limitation that reduces the thermal budget of a bonded structure is when a relatively high annealing temperature (e.g., greater than 250° C.) is used to bond two elements with a relatively large difference in coefficient of thermal expansion (CTE). Such thermal expansion mismatch between the two elements may cause defects in the bonded structure, stress-related cracks, or device degradation. In some embodiments, the CTE difference between the materials of the first and second elements 102, 152 may be greater than 2 ppm / ° C. or 5 ppm / ° C., and in other applications may be greater than 10 ppm / ° C. The use of conductive features 206 having dopant amounts selected to manage grain growth (e.g., as shown in Figures 2A-2C) can facilitate the use of elements (e.g., first and second elements 102, 152) having CTE differences greater than 2 ppm / °C, 5 ppm / °C, or 10 ppm / °C, elements that are typically susceptible to heat-related damage as discussed above. This is believed to be because the use of such conductive features 206 reduces the thermal effects of the bonding process, e.g., by reducing the annealing bonding temperature, bonding time, or both.In some embodiments, a smaller die may be bonded to a larger die, such that the bonding surface area of ​​the first element 102 (not shown) may be smaller than the bonding surface area of ​​the second element 152 (not shown).

[0035] In the conductive feature 206 of FIGS. 2A-2C, the first amount of impurities 120 can be sufficient to retard grain growth of the conductive material 108 of the conductive feature 206 such that the stored potential energy of the conductive material 108, e.g., due to the relatively small grains 116 having a relatively high atomic vacancy, is maintained until an annealing process bonds the conductive feature 206 to another conductive feature (e.g., the conductive feature 156 of the second element 152 shown in FIG. 4E). The retardation of grain growth can be due to an increase in the drag coefficient (ks in the above equation). In some embodiments, the first amount of impurities 120 can enable the conductive material 108 of the conductive feature 206 to prevent or minimize grain growth at room temperature.

[0036] In the conductive feature 306 of FIGS. 3A-3C, the second amount of impurities 120 can be a sufficient amount of impurities 120 that can retard grain growth of the conductive material 108 of the conductive feature 306 such that the stored potential energy of the conductive material 108 is maintained until an annealing process that bonds the conductive feature 306 to another conductive feature (e.g., the conductive feature 156 of the second element 152 shown in FIG. 4E). The second amount of impurities 120 (i.e., the amount of impurities 120 in FIGS. 3A-3C) is greater than the first amount (i.e., the amount of impurities 120 in FIGS. 2A-2C). In some embodiments, the conductive material 108 with the second amount of impurities 120 can retard grain growth of the conductive material 108 for a longer time than the conductive material 108 with the first amount of impurities 120. In some embodiments, the second amount of impurities 120 can enable the conductive material 108 of the conductive feature 306 to prevent or minimize grain growth at room temperature.

[0037] The conductive features disclosed herein (e.g., the first conductive feature 206 of the first element 102 and the second conductive feature 156 of the second element 152) may be replaced with any suitable conductive feature or structure. The conductive feature 206 may include a contact pad configured to directly couple to another conductive feature 156 on the opposing element. The conductive feature 206 may include a contact pad that is connected to an underlying circuit or trace, a through substrate via (TSV) that extends at least partially through the substrate, or any other conductive material configured to directly couple to and contact the opposing conductive feature 156.

[0038] 4A-4F are schematic cross-sectional side views illustrating various steps of a process for fabricating the bonded structure 100 after fabricating the first element 102. In FIG. 4A, a non-conductive region 130 may be provided. The non-conductive region 130 may include a non-conductive material (e.g., a dielectric material 132), such as silicon oxide, silicon nitride, silicon oxynitride, or other similar material. In FIG. 4B, an opening 122 may be formed in a non-conductive surface 136 of the non-conductive region 130. The opening 122 may have any suitable shape and size for receiving the conductive material 108 (shown in FIG. 4C) to form a conductive feature 206 (shown in FIG. 4D), such as a contact pad or a via, such as a through substrate via (TSV) or through substrate trench (TSG). The non-conductive surface 136 may include a contact surface that may be bonded to a non-conductive surface 148 of the second element 152 in some embodiments, as shown in FIGS. 4E and 4F.

[0039] In FIG. 4C, a barrier layer 126, a seed layer (not shown), and a conductive material 108 may be provided within the opening 122 and on the surface of the dielectric material 132. The barrier layer 126 may include a nitride, such as titanium nitride (TiN) or tantalum nitride (TaN). Also, the seed layer (not shown) may be a metal (e.g., copper) seed that is deposited on the barrier layer 126 and used as a seed for an electroplating process to fill the opening 122 with the conductive material 108. In FIG. 4C, an impurity 120 (not shown) may be provided within the conductive material 108 of the conductive feature 206. In some embodiments, the impurity 120 (not shown) may be provided as a seed layer (not shown), for example, sputtered into the opening 122. In some other embodiments, the impurity 120 may be provided by a physical vapor deposition (PVD) process or by sputtering. For example, the impurities 120 can be provided through a method of co-depositing a concentration of the impurities 120 with the conductive material 108 using a doped conductive material target or co-sputtering, or co-plating the impurities 120 with the conductive material 108 from one or more electroless or electrolytic plating baths. Multiple types of plating baths can be applied to fill the openings 122 in the dielectric material 132. After a seed layer coating step, a first bath including a superfilling can be used to form the conductive material 108 (e.g., a void-free or substantially void-free conductive material) in the majority of the openings 122. For example, the first bath can be used to fill less than 90% (not shown) of the depth of the openings 122. A second coating step can be applied to fill and overfill the openings 122 in the dielectric material 132. The second coating can include size modulated particles. In some embodiments, the impurities 120 (not shown) can include nanoparticles. In some embodiments, the impurities 120 may be provided by atomic layer deposition (ALD) techniques.The amount of impurity 120 can be selected to maintain the stored potential energy of the conductive material 108 at ambient conditions (e.g., room temperature) prior to the annealing process. The conductive feature 206 is configured such that the grains 116 (not shown) of the conductive material 108 grow slower at room temperature than the conductive material 108 without the impurity 120 (not shown).

[0040] In FIG. 4D, the element 102 can be formed. In FIG. 4D, at least a portion of the conductive material 108 can be removed. The portion of the conductive material 108 can be removed by chemical mechanical polishing (CMP). In some embodiments, a CMP process can also remove a small portion of the non-conductive surface 136 of the dielectric material 132 to form the contact surface 104. Polishing the non-conductive surface 136 of the dielectric material 132 can cause dielectric rounding to be present in the area of ​​the contact surface 104 adjacent the barrier layer 126 or conductive material 108 in the opening 122 (shown in FIG. 4B) of the dielectric material 132. The presence of impurities 120 (not shown) can reduce the size (not shown) of the grains 116 of the conductive material 108 in the conductive feature 206 of the opening 122. Small grains tend to be mechanically harder than large grains, and therefore the presence of impurities in the conductive material 108 can reduce the polishing rate of polishing the conductive material 108. The reduced polish rate of the small grain conductive material 108 coincidentally minimizes dielectric rounding. Although not shown in Figures 4A-4D, it is understood that the depicted dielectric material 132 (e.g., non-conductive regions 130) and conductive features 206 (which may include conductive material 108 embedded with impurities 120 (not shown)) may be formed over a larger semiconductor device region (not shown), such as a silicon region or layer. Each element 102 may include multiple conductive features 206 formed in the contact surface 104.

[0041] 4E illustrates an element 102 (first element 102) and another element (second element 152) before being bonded together to form bonded structure 100 (shown in FIG. 4F). In some embodiments, the second element 152 can have a structure similar to the first element 102. In some embodiments, as described above, each of the first and second elements 102, 152 can include a conductive feature 206, 156 at least partially embedded in a non-conductive region 130, 160. As described above, the conductive feature 206, 156 can include a conductive material 108 (e.g., shown in FIGS. 2A-2C) and an impurity 120 (e.g., shown in FIGS. 2A-2C). The conductive material 108 may include grains 116 (e.g., as shown in FIGS. 2A-2C) and grain boundaries 118 (e.g., as shown in FIGS. 2A-2C), and may have impurities 120 embedded in the grains 116 or along the grain boundaries 118 (e.g., as shown in FIGS. 2A-2C) within the conductive features 206, 156. In some embodiments, each of the elements 102 and 152 may include a seed layer (not shown) and / or a barrier layer 126, 126a disposed between the conductive features 206, 156 and the dielectric material 132, 132a of each element.

[0042] The bonded structure 100 (shown in FIG. 4F) can be formed by bonding a contact surface 104 of a first element 102 to a contact surface 154 of a second element 156. The contact surface 104, 154 of each element 102, 152 can include a non-conductive portion (e.g., a non-conductive surface 136, 146, which can be a surface of a non-conductive region 130, 160) and a conductive portion (e.g., a conductive surface 138, 148, which can be a surface of a conductive feature 206, 156). The conductive surface 138, 148 can be recessed downward from the non-conductive surface 136, 146, for example by less than 30 nm. These recesses are not shown in the figures.

[0043] FIG. 4F illustrates a bonded structure 100 in which the first and second elements 102, 152 shown in FIG. 4E are directly bonded to one another along contact surfaces 104, 154. During this direct bonding process, the elements 102, 152 (shown in FIG. 4F) can be brought together to form a direct bond between adjacent non-conductive regions 130, 160, and the conductive features 206, 156 can be annealed to provide expansion and form electrical contacts between opposing conductive features 206, 156. Prior to bonding, the potential energy of the conductive material (e.g., copper) of the conductive features 206, 156 can be advantageously maintained by providing non-alloy impurities 120 (e.g., shown in FIGS. 2A-2C) that migrate to the grain boundaries 118 of the conductive material. Maintaining the potential energy can advantageously reduce the thermal budget of the direct bonding process by reducing the temperature at which the elements 102, 152 can be annealed to form metallic contacts between the opposing conductive features 206, 156.

[0044] The non-conductive (e.g., dielectric) material 132 of the non-conductive region 130 of the first element 102 can be bonded to the non-conductive (e.g., dielectric) material 132a of the non-conductive region 160 of the second element 152. The dielectric material 132 of the first element 102 can be bonded directly to the dielectric material 132a of the second element 152 without the use of an intermediary adhesive. Because the conductive surfaces 138, 148 can be recessed below the contact surfaces 104, 154, respectively, in some embodiments, when the non-conductive surface 136 of the first element 102 is directly bonded to the non-conductive surface 146 of the second element 152, the first and second conductive features 206, 156 can still have some separation therebetween. After the non-conductive regions 130, 160 of the first and second elements 102, 152 are bonded to each other, the bonded elements 102, 152 can be annealed to form the bonded structure 100. The conductive features 206, 156 can expand and bond directly to one another during annealing. When the first and second conductive features 206, 156 bond directly to one another, they can form a single component, bonded conductive feature 162.

[0045] In some embodiments, the bonded elements 102, 152 can be annealed at a relatively low temperature. For example, the bonded elements can be annealed at a bonding temperature of less than 250° C., or at a temperature in the range of 100° C. to 250° C., 100° C. to 200° C., 150° C. to 200° C., or 100° C. to 150° C. As described herein, the impurities 120 (e.g., as shown in FIGS. 2A-2C ) can include a non-alloying material that does not form an alloy with the conductive material 108 at the bonding temperature.

[0046] In some embodiments, the impurities 120 (e.g., as shown in FIGS. 2A-2C) can be provided to cover, for example, 5%-75%, 5%-40%, 5%-30%, 15%-75%, 15%-40%, or 15%-30% of the grain boundaries 118 (e.g., as shown in FIGS. 2A-2C) of the conductive material 108 (e.g., as shown in FIGS. 2A-2C). In some embodiments, the conductive feature 206 can include, for example, 20 parts per million (ppm) to 5000 ppm, 20 ppm to 1000 ppm, 50 ppm to 1000 ppm, 100 ppm to 5000 ppm, 200 ppm to 2000 ppm, 50 ppm to 500 ppm, 100 ppm to 500 ppm, 200 ppm to 1000 ppm, or 200 ppm to 500 ppm of the non-alloy impurities 120. In some embodiments, the concentration or amount of impurities 120 is not uniform throughout the conductive feature 206. For example, in some embodiments, the concentration or amount of impurities 120 may be higher near the bonding surface (e.g., contact surface 104 shown in FIG. 4E) than in the bulk. The concentration or amount of impurities 120 may be measured by secondary ion mass spectrometry (SIMS) and / or transmission electron microscopy (TEM), such as high resolution TEM (HRTEM). The impurities 120 may be present both at the grain boundaries 118 and within the grains 116 (e.g., shown in FIGS. 2A-2C) of the conductive material 108 of the conductive feature 206 both before and after the annealing process.

[0047] overview In one embodiment, an element includes a conductive feature at a contact surface of the element and a non-conductive region at the contact surface in which the conductive feature is at least partially embedded, the conductive feature including a conductive material and an amount of impurities at grain boundaries of the conductive material, the impurities including a non-alloy material that does not form an alloy with the conductive material at a bonding temperature.

[0048] In some embodiments, the impurities can include metal compounds. In some embodiments, the impurities can include metal oxides. In some embodiments, the impurities can include non-metal compounds. In some embodiments, the impurities can include non-metal oxides. In some embodiments, the impurities can include chemical compounds. In some embodiments, the conductive material can include copper. In some embodiments, the impurities can include refractory materials. In some embodiments, the impurities can include tantalum. In some embodiments, the impurities can include zirconium. In some embodiments, the impurities can include molybdenum. In some embodiments, the conductive feature can be configured such that the grains of the conductive material grow slower at room temperature than the conductive material without the impurities. In some embodiments, the impurities can be disposed to cover between 5% and 75% of the grain boundaries of the conductive material. In some embodiments, the impurities can be disposed to cover between 5% and 40% of the grain boundaries of the conductive material. In some embodiments, the conductive feature can include between 20 parts per million (ppm) and 5000 ppm of impurities. In some embodiments, the conductive feature can include between 200 parts per million (ppm) and 1000 ppm of impurities. In some embodiments, the amount of impurities can be configured such that the potential energy of the conductive material is maintained at room temperature. In some embodiments, the conductive feature can include between 20 parts per million (ppm) and 5000 ppm of impurities near the contact surface. In some embodiments, the conductive feature can include between 200 parts per million (ppm) and 1000 ppm of impurities near the contact surface. In some embodiments, the conductive feature can include a contact pad. In some embodiments, the conductive feature can include a through-substrate via (TSV). In some embodiments, the bonding temperature can be in the range of 100° C. to 250° C.

[0049] In another embodiment, the coupling structure can include a first element including a first conductive feature and a first non-conductive region at a first contact surface of the first element. The coupling structure can also include a second element including a second conductive feature directly bonded to the first conductive feature to define a coupling conductive feature and a second non-conductive region directly bonded to the first non-conductive region. In some embodiments, the coupling conductive feature can include a conductive material and a concentration of impurities, the impurities having a non-alloying material that does not form an alloy with the conductive material.

[0050] In some embodiments, the impurities can include metal compounds. In some embodiments, the impurities can include metal oxides. In some embodiments, the impurities can include non-metal compounds. In some embodiments, the impurities can include non-metal oxides. In some embodiments, the impurities can include chemical compounds. In some embodiments, the conductive material can include copper. In some embodiments, the impurities can include refractory materials. In some embodiments, the impurities can include tantalum. In some embodiments, the impurities can include zirconium. In some embodiments, the impurities can include molybdenum. In some embodiments, the conductive feature can be configured such that grains of the conductive material grow slower at room temperature than a conductive material without the impurities. In some embodiments, the conductive feature can include between 20 parts per million (ppm) and 5000 ppm of impurities. In some embodiments, the conductive feature can include between 200 parts per million (ppm) and 1000 ppm of impurities. In some embodiments, the amount of impurities can be configured such that the potential energy of the conductive material is maintained at room temperature.

[0051] In another embodiment, an element can be formed by forming an opening in a dielectric material, providing a conductive material in the opening, providing non-alloying impurities at grain boundaries of the conductive material, and polishing surfaces of the dielectric material and the conductive material.

[0052] In some embodiments, providing the non-alloy impurities can include providing a seed layer including the non-alloy impurities. In some embodiments, providing the non-alloy impurities can include co-depositing the non-alloy impurities with the conductive material. In some embodiments, providing the non-alloy impurities can include co-sputtering the non-alloy impurities with the conductive material. In some embodiments, the impurities can include metal compounds. In some embodiments, the impurities can include metal oxides. In some embodiments, the impurities can include non-metal compounds. In some embodiments, the impurities can include non-metal oxides. In some embodiments, the impurities can include chemical compounds. In some embodiments, the conductive material can include copper. In some embodiments, the impurities can include a refractory material. In some embodiments, the impurities can include tantalum. In some embodiments, the impurities can include zirconium. In some embodiments, the impurities can include molybdenum.

[0053] In another embodiment, the bonded structure can be formed by providing a first element having a first conductive feature and a first non-conductive region on a first contact surface and a second element having a second conductive feature and a second non-conductive region on a second contact surface, directly bonding the first non-conductive region to the second non-conductive region without the use of an intermediary adhesive, and bonding the first conductive feature to the second conductive feature by an annealing process to form a bonded conductive feature. In some embodiments, the bonded conductive feature includes a conductive material and a concentration of impurities, where the impurities can include a non-alloying material that does not form an alloy with the conductive material.

[0054] In some embodiments, the impurities can include metal compounds. In some embodiments, the impurities can include metal oxides. In some embodiments, the impurities can include non-metal compounds. In some embodiments, the impurities can include non-metal oxides. In some embodiments, the impurities can include chemical compounds. In some embodiments, the conductive material can include copper. In some embodiments, the impurities can include refractory materials. In some embodiments, the impurities can include tantalum. In some embodiments, the impurities can include zirconium. In some embodiments, the impurities can include molybdenum. In some embodiments, the conductive features can be configured such that grains of the conductive material grow slower at room temperature than a conductive material without the impurities. In some embodiments, the combined conductive features can include between 20 parts per million (ppm) and 1000 ppm of impurities. In some embodiments, the combined conductive features can include between 200 parts per million (ppm) and 1000 ppm of impurities.

[0055] In another embodiment, the bonding structure can include a first element and a second element, the first element including a first conductive feature and a first non-conductive region at a first contact surface of the first element, and the second element including a second conductive feature directly bonded to the first conductive feature to define a bonding conductive feature and a second non-conductive region directly bonded to the first non-conductive region. In some embodiments, the bonding surface area of ​​the first element can be smaller than the bonding surface area of ​​the second element, and a coefficient of thermal expansion (CTE) difference between the material of the first element and the material of the second element can be greater than 5 ppm / °C.

[0056] In some embodiments, the first conductive feature can include an impurity.

[0057] Unless the context clearly requires otherwise, words such as "comprise, comprising, include, including" and the like are to be construed in an inclusive sense, i.e., "including, but not limited to," rather than an exclusive or exhaustive sense. The word "coupled," as generally used herein, means two or more elements that may be connected directly or through one or more intermediate elements. Similarly, the word "connected," as generally used herein, means two or more elements that may be connected directly or through one or more intermediate elements. Additionally, when the application uses words such as "herein," "above," "below," and words of similar import, these words are intended to refer to the application as a whole and not to any particular portion of the application. Furthermore, when a first element is described herein as being "on" or "over" a second element, the first element can be directly on or over the second element such that the first and second elements are in direct contact with each other, or indirectly on or over the second element such that there are one or more intervening elements between the first and second elements. Words using the singular or plural in the above detailed description can also include the plural or singular, respectively, where the context allows. The word "or" when referring to a list of two or more items covers all interpretations of the word, such as any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0058] Additionally, as used herein, inter alia, conditional terms such as "can, could, might, may" and "eg, for example, such as" are generally intended to convey that some embodiments include certain features, elements and / or conditions and other embodiments do not include them, unless expressly stated otherwise or understood otherwise within the context of use. Thus, such conditional terms are generally not intended to imply that features, elements and / or conditions are in any way required for one or more embodiments.

[0059] Although several embodiments have been described, these embodiments are presented as examples only and are not intended to limit the scope of the present disclosure. Indeed, the novel apparatus, method and system described herein may be embodied in various other forms, and various omissions, substitutions and modifications of the forms of the methods and systems described herein may be made without departing from the spirit of the present disclosure. For example, although blocks are shown in a given arrangement, another embodiment may perform similar functions using different components and / or circuit topologies, and some blocks may be deleted, moved, added, subdivided, combined and / or modified. Each of these blocks may be implemented in a variety of different ways. Any suitable combination of elements and acts of the various embodiments described above may be combined to provide further embodiments. The appended claims and their equivalents are intended to cover such forms or modifications as fall within the scope and spirit of the present disclosure. [Explanation of symbols]

[0060] 102 First semiconductor element 104 Contact surface 126 Barrier Layer 126a Barrier layer 130 Non-conductive area 132 Dielectric Materials 132a Dielectric Materials 136 Non-conductive surfaces 138 Conductive Surface 146 Non-conductive surfaces 148 Conductive Surface 152 Second semiconductor element 154 Contact surface 156 Conductive Features 206 Conductive Characteristics

Claims

1. An element comprising: a conductive feature on a contact surface of the element; a non-conductive region of the contact surface in which the conductive features are at least partially embedded; the conductive feature comprises a conductive material and an amount of impurities at grain boundaries of the conductive material, the impurities comprising non-alloyed materials that do not form an alloy with the conductive material at a bonding temperature. A device characterized in that

2. The impurities include metal compounds. The device of claim 1 .

3. The impurities include metal oxides. The element of claim 2.

4. The impurities include non-metallic compounds. The element according to claim 1.

5. The impurities include non-metal oxides. The element according to claim 4.

6. The impurities include chemical compounds. The element according to claim 1.

7. the conductive material comprises copper; The device of claim 1 .

8. The impurities include refractory materials; The device of claim 7.

9. The impurities include tantalum. The device of claim 7.

10. The impurities include zirconium. The element according to claim 7.

11. The impurities include molybdenum. The element according to claim 7.

12. the conductive feature is configured such that grains of the conductive material grow slower at room temperature than those of the conductive material without the impurity; The device of claim 1 .

13. The impurities are disposed so as to cover 5% to 75% of the grain boundaries of the conductive material. The device of claim 1 .

14. The impurities are arranged to cover 5% to 40% of the grain boundaries of the conductive material. The device of claim 1 .

15. the conductive feature contains between 20 parts per million (ppm) and 5000 ppm of the impurity; The device of claim 1 .

16. the conductive feature contains between 200 parts per million (ppm) and 1000 ppm of the impurity; The device of claim 1 .

17. The amount of impurities is configured to maintain the potential energy of the conductive material at room temperature. The device of claim 1 .

18. the conductive feature contains between 20 parts per million (ppm) and 5000 ppm of the impurity near the contact surface; The device of claim 1 .

19. the conductive feature contains between 200 parts per million (ppm) and 1000 ppm of the impurity near the contact surface; The device of claim 1 .

20. the conductive features include contact pads; The device of claim 1 .

21. the conductive features include through-substrate vias (TSVs); The device of claim 1 .

22. The bonding temperature is in the range of 100°C to 250°C. The device of claim 1 .

23. A bonding structure comprising: A first element; and A second element; and Including, the first element includes a first conductive feature and a first non-conductive region on a first contact surface of the first element; the second element includes a second conductive feature directly coupled to the first conductive feature to define a coupled conductive feature and a second non-conductive region directly coupled to the first non-conductive region; the bonded conductive feature includes a conductive material and a concentration of impurities, the impurities comprising a non-alloying material that does not form an alloy with the conductive material; A bonding structure characterized by:

24. The impurities are present at grain boundaries of the conductive material. The bond structure of claim 23.

25. The impurities include metal compounds. The bond structure of claim 23.

26. The impurities include metal oxides. The bond structure of claim 24.

27. The impurities include non-metallic compounds. The bond structure of claim 23.

28. The impurities include non-metal oxides.

28. The bond structure of claim 27.

29. The impurities include chemical compounds. The bond structure of claim 23.

30. the conductive material comprises copper; The bond structure of claim 23.

31. The impurities include refractory materials; The bond structure of claim 30.

32. The impurities include tantalum. The bond structure of claim 30.

33. The impurities include zirconium. The bond structure of claim 30.

34. The impurities include molybdenum. The bond structure of claim 30.

35. the conductive feature is configured such that grains of the conductive material grow slower at room temperature than those of the conductive material without the impurity; The bond structure of claim 23.

36. the bonded conductive feature contains between 20 parts per million (ppm) and 5000 ppm of the impurity; The bond structure of claim 23.

37. the bonded conductive feature contains between 200 parts per million (ppm) and 1000 ppm of the impurity; The bond structure of claim 23.

38. The amount of impurities is configured to maintain the potential energy of the conductive material at room temperature. The bond structure of claim 23.

39. 1. A method of forming a device, comprising: forming an opening in a dielectric material; providing a conductive material within the opening; providing non-alloying impurities at grain boundaries of the conductive material; polishing a surface of the dielectric material and the conductive material; The method according to claim 1, further comprising:

40. providing the non-alloying impurities includes providing a seed layer including the non-alloying impurities; 40. The method of claim 39.

41. providing the non-alloying impurities includes co-depositing the non-alloying impurities with the conductive material; 40. The method of claim 39.

42. providing the non-alloying impurities includes co-sputtering the non-alloying impurities with the conductive material; 40. The method of claim 39.

43. The impurities include metal compounds.

40. The method of claim 39.

44. The impurities include metal oxides.

44. The method of claim 43.

45. The impurities include non-metallic compounds.

40. The method of claim 39.

46. The impurities include non-metal oxides.

46. ​​The method of claim 45.

47. The impurities include chemical compounds.

40. The method of claim 39.

48. the conductive material comprises copper; 40. The method of claim 39.

49. The impurities include refractory materials; 49. The method of claim 48.

50. The impurities include tantalum.

49. The method of claim 48.

51. The impurities include zirconium.

49. The method of claim 48.

52. The impurities include molybdenum.

49. The method of claim 48.

53. A method for forming a bonded structure, comprising the steps of: Providing a first element having a first conductive feature and a first non-conductive region on a first contact surface and a second element having a second conductive feature and a second non-conductive region on a second contact surface; directly bonding the first non-conductive region to the second non-conductive region without the use of an intermediary adhesive; bonding the first conductive feature to the second conductive feature by an annealing process to form a bonded conductive feature; Including, the bonded conductive feature includes a conductive material and a concentration of impurities, the impurities comprising a non-alloying material that does not form an alloy with the conductive material; A method comprising:

54. The impurities include metal compounds.

54. The method of claim 53.

55. The impurities include metal oxides.

55. The method of claim 54.

56. The impurities include non-metallic compounds.

54. The method of claim 53.

57. The impurities include non-metal oxides.

57. The method of claim 56.

58. The impurities include chemical compounds.

54. The method of claim 53.

59. the conductive material comprises copper; 54. The method of claim 53.

60. The impurities include refractory materials; 60. The method of claim 59.

61. The impurities include tantalum.

60. The method of claim 59.

62. The impurities include zirconium.

60. The method of claim 59.

63. The impurities include molybdenum.

60. The method of claim 59.

64. the conductive feature is configured such that grains of the conductive material grow slower at room temperature than those of the conductive material without the impurity; 54. The method of claim 53.

65. the bonded conductive feature contains between 20 parts per million (ppm) and 1000 ppm of the impurity; 54. The method of claim 53.

66. the bonded conductive feature contains between 200 parts per million (ppm) and 1000 ppm of the impurity; 54. The method of claim 53.

67. A bonding structure comprising: A first element; and A second element; and Including, the first element includes a first conductive feature and a first non-conductive region on a first contact surface of the first element; the second element includes a second conductive feature directly coupled to the first conductive feature to define a coupled conductive feature and a second non-conductive region directly coupled to the first non-conductive region; a bonding surface area of ​​the first element is smaller than a bonding surface area of ​​the second element, and a coefficient of thermal expansion (CTE) difference between a material of the first element and a material of the second element is greater than 5 ppm / °C; A bonding structure characterized by:

68. the first conductive feature comprises an impurity; 68. The bond structure of claim 67.

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