Fault injection attack countermeasures
A hardware comparator circuit and MCU-based interrupt system enhance security by ensuring authorized access to computer resources, mitigating fault injection attacks through robust parameter comparisons.
Patent Information
- Application Number
- JP2024540686
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2022-06-29
- Filing Date
- 2023-01-03
- Publication Date
- 2025-01-24
AI Technical Summary
Existing software encoding implementations are insufficiently robust against well-synchronized fault injection attacks, which can bypass authentication mechanisms and expose device resources to unauthorized access.
Implementing a hardware comparator circuit to perform comparisons of access parameters in a hardware comparator circuit, followed by a microcontroller unit (MCU) to assert success or failure interrupts based on these comparisons, ensuring that only authorized access is granted to computer resources.
Enhances security by separating the condition check for resource access from the actual enabling process, reducing the likelihood of unauthorized access due to fault injection attacks.
Smart Images
Figure 2025502020000001_ABST
Abstract
Claims
1. 1. A method for providing access to a computer resource, the method comprising: programming the first and second values and the first compare enable command into respective first operand, second operand, and first compare enable command registers within the hardware comparator circuit; determining that a first match exists corresponding to the first and second values; programming a third value into the first operand register and a fourth value into the second operand register; programming a second compare enable command into a second compare enable command register in the hardware comparator circuit; asserting a success interrupt signal in response to determining that there is a second match corresponding to the third and fourth values; programming a fifth value into the first operand register and a sixth value into the second operand register by a successful interrupt service routine (ISR); programming a second compare enable command into a second compare enable command register in the hardware comparator circuit according to the successful ISR; A method comprising:
2. 2. The method of claim 1, further comprising programming a scratchpad register in the hardware comparator circuit with a scratchpad value corresponding to the computer resource.
3. 3. The method of claim 2, further comprising determining that a match exists corresponding to the fifth value and the sixth value, which causes the scratchpad register in the hardware comparator circuit to be readable.
4. The method of claim 3, further comprising: reading said scratchpad value from said scratchpad register by said success ISR; enabling the computer resource corresponding to the scratchpad value according to the successful ISR; A method comprising:
5. The method of claim 3, further comprising: providing the scratchpad value from the scratchpad register to a signal generator within the hardware comparator; enabling, by said signal generator, said computer resource corresponding to said scratchpad value; A method comprising:
6. 2. The method of claim 1, further comprising: asserting a fail interrupt signal by the hardware comparator circuit in response to the second compare enable command being programmed into the second compare enable command register before the first compare enable command is programmed into the first compare enable command register.
7. 2. The method of claim 1, further comprising: in response to determining that the first match corresponding to the first and second values does not exist or the second match corresponding to the third and fourth values does not exist, asserting a fail interrupt by the hardware comparator circuit.
8. 2. The method of claim 1, further comprising enabling the hardware comparator circuit to perform a comparison corresponding to the third and fourth values in response to the determining that the first match exists.
9. 1. An integrated circuit (IC), comprising: Computer resources, a hardware comparator circuit including a first operand register, a second operand register, a first compare enable command register, a second compare enable command register, a third compare enable command register, and a scratch pad register; and a microcontroller unit (MCU) coupled to said hardware comparator circuit; Including, The MCU, writing a first value to the first operand register, writing a second value to the second operand register, writing a first compare enable command to the first compare enable command register, and writing a scratchpad value to the scratchpad register, the scratchpad value identifying the computer resource; determining that a first match exists corresponding to the first and second values; writing a third value to the first operand register and a fourth value to the second operand register; writing a second compare enable command to the second compare enable command register; in response to receiving a success interrupt signal from the hardware comparator circuit indicating there is a second match corresponding to the third and fourth values, writing a fifth value to the first operand register, a sixth value to the second operand register, and a second compare enable command to the second compare enable command register; 4. The method of claim 3, IC.
10. 10. The IC of claim 9, wherein the hardware comparator circuit is configured to enable the scratchpad register to be readable upon detection of the presence of the second match.
11. 11. The IC of claim 10, wherein the MCU is configured to read the scratchpad register and to enable the computer resource based on the scratchpad value.
12. 11. The IC of claim 10, wherein the hardware comparator circuit is configured to enable the computer resource based on the scratchpad value.
13. 10. The IC of claim 9, wherein the MCU is configured to implement a first pseudo-random time value before writing the first value to the first operand register, and to implement a second pseudo-random time value before writing the third value to the first operand register.
14. 10. The IC of claim 9, wherein the hardware comparator circuit is configured to assert a failure interrupt signal in response to a failure of the first match corresponding to the first and second values or a failure of the second match corresponding to the third and fourth values.
15. 1. An integrated circuit (IC), comprising: controller, a digital comparator having a first comparator input, a second comparator input, and a digital comparator output; a first latch having a first latch input, a first latch output, and a first enable input, the first latch input coupled to the digital comparator output and the first enable input coupled to a controller; a first AND gate having a first AND gate input, a second AND gate input, and a first AND gate output, the first AND gate input coupled to the first latch output and the second AND gate input coupled to the controller; and a second latch having a second latch input, a second latch output, and a second enable input, the second latch input coupled to the digital comparator output and the second enable input coupled to the first AND gate output; Including, IC.
16. 16. The IC of claim 15, further comprising: a first operand register coupled to the first comparator input; a second operand register coupled to the second comparator input; Including, IC.
17. 17. The IC of claim 16, further comprising: a first compare enable command register coupled to the controller; a second compare enable command register coupled to the controller; Including, The controller: enabling the first latch in response to a first value from the first compare enable command register; asserting a signal to the second AND gate input in response to a second value from the second compare enable command register; It is configured as follows: IC.
18. 17. The IC of claim 16, further comprising an event generator having a first event generator input and a second event generator input, the first event generator input coupled to the first latch output and the second event generator input coupled to the second latch output.
19. 20. An IC as claimed in claim 18, wherein the event generator has a first interrupt signal output and a second interrupt signal output, the event generator comprising: asserting the first interrupt signal output in response to both the first and second latch outputs being in a first predetermined state; asserting said second interrupt signal output in response to said first and second latch outputs being in a second predetermined state; An IC configured as follows.
20. 17. The IC of claim 16, further comprising: a third latch having a third latch input and a third latch output, the third latch input coupled to the digital comparator output; a scratch pad register having a read enable input coupled to the third latch output; Including, IC.