High-Throughput Scanning Architecture

Abstract

A method, system, and apparatus for a high throughput scan architecture. The scan architecture may include a clock controller, a decompressor, a scan chain, and a compressor. In some embodiments, a set of values ​​representing a particular data pattern is received. A first data signal is generated using at least a portion of the values ​​in the set of values, the first data signal having a first frequency. A first latch sequence and a second latch sequence are used to extract alternating values ​​of at least a portion of the values ​​from the first data signal, the first latch sequence and the second latch sequence extracting the alternating values ​​at a second frequency that is a fraction of the first frequency. The outputs of the first latch sequence and the second latch sequence are combined to generate a second data signal, the second data signal having the first frequency.

Description

[Technical field]

[0001] This specification relates to scan architectures and techniques for using scan architectures. [Background technology]

[0002] Mobile computing devices such as smartphones, personal digital assistants, electronic tablets, and laptops all rely on circuits that function as designed. Some integrated circuits do not function as designed due to defects in the manufacturing process. Manufacturing or production tests may be performed to verify that the circuits have been manufactured correctly and to identify defective circuits. Since these tests often need to be performed on thousands or even millions of chips or chipsets, significant power and processing resources are expended in performing the tests. Thus, inefficiencies in the testing process result in substantial losses in the form of wasted power and processing resources. The time required for testing and quality assurance can also become a bottleneck in the production line. Summary of the Invention

[0003] Described herein are techniques for high throughput scan architectures for testing digital devices. The techniques may be particularly useful for performing quality assurance and testing of integrated circuits at the end of manufacturing. The scan architectures may be implemented in electronic devices, such as computer processors, and used to determine whether the electronic devices are functioning properly or if the electronic devices are defective.

[0004] The scan architecture may include multiple scan chains, each including multiple latch series. For example, each scan chain of the high throughput scan architecture may include a first latch series constituting a first series and a second latch series constituting a second series. The first and second latch series may operate simultaneously (e.g., in parallel), with each latch series storing alternating values ​​of the scan-in data signal. As a result, the first and second series record different sets of values ​​of a test pattern provided by the test system. For example, both latch series may be coupled to an input line that provides the test pattern as a sequence of values. Each latch series may be configured to store every other value that occurs in the sequence, alternating which latch series stores the next value. A delay element may be used in one of the latch series, and an offset may be provided such that each of the two latch series stores a different portion of the input test pattern. In other words, the first latch series stores a first input value, the second latch series stores a second input value, the first latch series stores a third input value, the second latch series stores a fourth input value, etc. In this way, the test pattern sequence is distributed to the two latch series during the scan-in phase.

[0005] Then, after the test is performed, the values ​​of the two latch series are output from the two latch series in the scan-out phase, and the values ​​from the two latch series are interspersed or interleaved with each other to form an output sequence for the scan-out phase. For example, the output sequence may be constructed by a selector taking values ​​from different latch series in sequence and switching between the two series of values ​​each time an output value is added to the sequence. In other words, the output sequence may be a first value from a first latch series, a first value from a second latch series, a second value from the first latch series, a second value from the second latch series, etc. In this way, an output sequence is formed by (1) distributing the input sequence of the scan chain among different latch series during scan-in to alternately store values ​​in the different latch series, and (2) interleaving the outputs of the different latch series during scan-out.

[0006] The latch series may operate at a lower frequency than other components of the scan architecture. For example, the first latch series and the second latch series may operate at a clock rate that is half the data rate of the scan-in data signal during a test mode or a shift mode. In this mode, both of the latch series may operate by storing a value, such as a value obtained from the scan-in data signal (e.g., receiving a value during scan-in or shift-in), and emitting a value (e.g., outputting during scan-out or shift-out) at a divided-down clock rate.

[0007] A test system may select a test pattern to provide as an input to a scan architecture during testing of an electronic device. The test pattern may include one or more bit streams used to load data into latches of scan chains in the scan architecture. The test pattern may also include or be part of a test program that provides inputs of the scan chains and timing parameters for the inputs. For example, when performing a test on a device, the test system may select a test pattern to load latches of the scan chains in the device and a program to use to perform the test. The program may specify scan enable (SE) inputs of the latches of the scan chains (e.g., switching between shift mode and functional or capture mode of latch series in the scan chains) and timing for providing the inputs. After providing the test pattern as an input and enabling the capture or functional mode for one or more clock cycles, the test system may return the latch series to shift mode to shift out the stored value. The shift-out value may be a test output that the test system may compare to a reference output to determine whether the electronic device is functioning properly or whether the electronic device is defective. For example, if the test output does not match the reference output, the test system may determine that the electronic device is defective or requires further analysis.

[0008] In one general aspect, an electronic device includes a clock system providing a plurality of clock signals including a first clock signal at a first frequency and a second clock signal at a second frequency lower than the first frequency; a decompressor configured to receive the first clock signal and provide a scan-in input value at a first data rate based on the first frequency of the first clock signal; and a scan chain including two separate sets of latches provided as a first latch series and a second latch series, operating using the second clock signal, the scan chain being configured to (i) distribute the scan-in input value between the first latch series and the second latch series, and (ii) combine values ​​from the first latch series and the second latch series to provide a scan-out output value, and the electronic device further includes a compressor configured to receive the first clock signal and obtain the scan-out output value from the scan chain.

[0009] In another general aspect, an electronic device includes a clock controller providing a plurality of clock signals including a first clock signal at a first frequency and a second clock signal at a second frequency lower than the first frequency; and a decompressor configured to receive the first clock signal and provide a first data signal having a set of values, the decompressor configured to output values ​​of the first data signal at a first data rate based on the first frequency of the first clock signal, the electronic device further including a scan chain including two separate sets of latches provided as a first series of latches and a second series of latches, the first series of latches and the second series of latches both receiving the first data signal but outputting values ​​from the first data signal. the first latch series and the second latch series are both configured to receive a second clock signal to capture values ​​from the first data signal at a second data rate based on a second frequency of the second clock signal; the scan chain is configured to generate the second data signal by combining an output of the first latch series with an output of the second latch series; the electronic device further includes a compressor configured to receive the first clock signal and to obtain the second data signal from the scan chain, the compressor configured to obtain the second data signal from the scan chain at the first data rate according to the first frequency using the first clock signal.

[0010] Implementations include one or more of the following features. For example, in some implementations, extracting a subset of distinct values ​​of the set of values ​​from the first data signal includes, for each value in the set of values, alternating which of two series of latches captures the value.

[0011] In some embodiments, extracting a subset of distinct values ​​of the set of values ​​from the first data signal includes capturing, by a first latch series, every other value of the first data signal and capturing, by a second latch series, other values ​​of the first data signal that were not captured by the second latch series.

[0012] In some embodiments, generating the second data signal includes interleaving an output of the first latch series with an output of the second latch series.

[0013] In some embodiments, the electronic device includes a multiplexer configured to receive an output of the first latch series, an output of the second latch series, and a first clock signal, and generating the second data signal includes controlling the multiplexer to alternately sample the output of the first latch series and the output of the second latch series at a first frequency of the first clock signal.

[0014] In some embodiments, the scan chain includes an element in one of the latch series that introduces a timing difference between when a first latch series can capture a value from the first data signal and when a second latch series can capture a value from the first data signal.

[0015] In some embodiments, the timing difference corresponds to one cycle of the first clock signal.

[0016] In some embodiments, the element is a lock-up latch and the other latches of the first series of latches and the second series of latches are flip-flops.

[0017] In some embodiments, the element is a first latch in a first latch series such that any value captured by the first latch series is loaded into or passes through the element before any other latch in the first latch series, or the element is a first latch in a second latch series such that any value captured by the second latch series is loaded into or passes through the element before any other latch in the second latch series.

[0018] In some embodiments, the element is a first type flip-flop and the other latches of the first latch series and the second latch series are second type flip-flops.

[0019] In some embodiments, the first type flip-flop is a master-slave flip-flop with a master bypass and the second type flip-flop is a master-slave flip-flop without a master bypass.

[0020] In some embodiments, the element introduces a timing offset between the first latch series and the second latch series, and the scan chain includes a second element that removes the timing offset between the first latch series and the second latch series.

[0021] In some embodiments, the element and the second element are both part of a first latch series, or the element and the second element are both part of a second latch series.

[0022] In some embodiments, the second element is the last latch in the first latch series, such that any value captured by the first latch series must pass through each of the other latches in the first latch series before reaching the second element, or the second element is the last latch in the second latch series, such that any value captured by the second latch series must pass through each of the other latches in the second latch series before reaching the second element.

[0023] In some embodiments, the second frequency is a division of the first frequency such that the second frequency is equal to the first frequency divided by an integer power (greater than zero) of two.

[0024] In some embodiments, the integer is 1 and the second frequency is one-half the first frequency.

[0025] In some embodiments, the integer is 2 and the second frequency is one-quarter the first frequency.

[0026] In some embodiments, the clock controller includes a frequency divider that receives a first clock signal and outputs a second clock signal based on the first clock signal.

[0027] In some embodiments, the divider is a programmable divider configured to output a variable clock signal at a frequency determined by a programmed state of the programmable divider, and the second clock signal is a variable clock signal having a second frequency based on the programmed state of the programmable divider.

[0028] In some embodiments, the decompressor provides the first data signal in response to the electronic device receiving one or more inputs that enable a shift mode of the electronic device.

[0029] In some embodiments, the electronic device receives one or more second inputs that disable a shift mode of the electronic device, and the scan chain is configured to generate a second data signal in response to the electronic device receiving one or more third inputs that re-enable the shift mode of the electronic device.

[0030] In another general aspect, an electronic device includes a clock controller providing a plurality of clock signals including a first clock signal at a first frequency, a second clock signal at a second frequency lower than the first frequency, and a third clock signal at a third frequency lower than the first and second frequencies; and a decompressor configured to receive the first clock signal and provide a first data signal having a set of values, the decompressor configured to output values ​​of the first data signal at a first data rate based on the first frequency of the first clock signal, the electronic device further including a scan chain including four separate latch groups provided as a first latch group, a second latch group, a third latch group, and a fourth latch group, each of the four separate latch groups having a first latch series and a second latch series, the first latch series and the second latch series of the first latch group both receiving the first data signal but capturing different subsets of values ​​from the first data signal; and a decompressor configured to receive a second clock signal and output values ​​of the first data signal at a second data rate based on the second frequency of the second clock signal. and capturing a value from the output of the second latch series of the first latch group at a third data rate based on a third frequency of the third clock signal, and both the first latch series and the second latch series of the second latch group are configured to receive an output of the second latch series of the first latch group and receive a third clock signal to capture a value from the output of the second latch series of the first latch group at a third data rate based on a third frequency of the third clock signal, and both the first latch series and the second latch series of the third latch group are configured to receive an output of the first latch series of the first latch group and receive a third clock signal to capture a value from the output of the second latch series of the first latch group at a third data rate based on a third frequency of the third clock signal. and capturing a value from an output of the first series of latches of the first group of latches at a third data rate based on a third frequency of the third clock signal, the first series of latches and the second series of latches of the fourth group of latches are both configured to receive a second data signal including the output of the second group of latches and the output of the third group of latches, and to receive the second clock signal and capture a value from the second data signal at a second data rate based on a second frequency of the second clock signal,The electronic device is configured to generate a third data signal by combining an output of the first latch series of the fourth latch group with an output of the second latch series of the fourth latch group, and the electronic device further includes a compressor that receives the first clock signal and obtains the third data signal from the scan chain, the compressor being configured to obtain the third data signal from the scan chain at a first data rate according to the first frequency using the first clock signal.

[0031] In another general aspect, a method includes receiving a set of values ​​representing a particular data pattern and generating a first data signal using at least some of the values ​​in the set of values, the first data signal having a first frequency, the method further includes extracting alternating values ​​of at least some of the values ​​from the first data signal using a first latch sequence and a second latch sequence, the first latch sequence and the second latch sequence extracting the alternating values ​​at a second frequency that is a fraction of the first frequency, and the method further includes combining an output of the first latch sequence with an output of the second latch sequence to generate a second data signal, the second data signal having the first frequency.

[0032] Other embodiments of these aspects include corresponding systems and devices configured to perform the actions of the methods.

[0033] The subject matter described herein may be implemented in particular embodiments to realize one or more of the following advantages. For example, the described scan architecture may achieve improved dynamic power consumption. This advantage is achieved, at least in part, through the design of the scan chains and clock networks used in the scan architecture. By using scan chains that include two or more latch series and reducing the frequency at which the latch series operate (e.g., the frequency at which the latches store and release bits), the dynamic power used by the scan architecture during test modes (e.g., shift mode rather than functional mode) is reduced.

[0034] The dynamic power savings provided by the scan architecture are achieved at least through a reduction in the dynamic power used by the clock network and the latches of the scan chains of the scan architecture. First, the frequency at which the latches in the scan architecture operate can be a division(s) of the frequency at which other components of the scan architecture operate. As a result, the dynamic power of the clock network is effectively divided. Second, because the latches of the scan chains in the scan architecture operate at a divided frequency or frequencies, the clock-related dynamic power used internally by the latches is reduced.

[0035] In using multiple latch series in each scan chain, the scan architecture may achieve a reduction in dynamic power without increasing test time. More specifically, using multiple latch series that operate at a frequency that is a division of the frequency at which other components of the scan architecture operate counters the increase or significant increase in test time that would normally be expected from lowering the frequency at which the latches operate. This is because the bits of the input data signal are split among two or more latch series of the scan chains. For example, if the latches in the scan architecture operate at half the undivided clock rate of the clock controller, the scan architecture may continue to generate an output data signal at the undivided clock rate by using scan chains that each include two latch series. As a result, the scan architecture provides the additional benefit of reducing dynamic power without increasing or significantly increasing test time, thereby improving test efficiency. [Brief description of the drawings]

[0036] [Figure 1] FIG. 1 is a diagram of an exemplary system for testing electronic devices having a high throughput scan architecture. [Diagram 2] FIG. 1 is a diagram of an exemplary high throughput scanning architecture. [Diagram 3] 1A-B are diagrams of an example scan chain for a high-throughput scan architecture and timing diagrams for various modes of the scan chain; [Figure 4] 1 is a diagram of an exemplary scan chain in a high throughput scan architecture and a timing diagram of the scan chain in use; [Diagram 5] 1A-D are diagrams of various latches that may be used in the scan chains of a high throughput scan architecture. [Figure 6A] 1 is a diagram of an exemplary scan chain in a high throughput scan architecture and a timing diagram of the scan chain in use; [Figure 6B] 1 is a diagram of an exemplary scan chain in a high throughput scan architecture and a timing diagram of the scan chain in use; [Figure 7] 1 is a flow chart of an exemplary process for using a high-throughput scanning architecture. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0037] Like reference symbols and designations in the various drawings indicate like elements. FIG. 1 is a diagram of an exemplary system 100 for performing testing of electronic devices. These electronic devices may be circuits. For example, the electronic devices may be or include processing devices such as a processor (CPU), a processor core (CPU core), or a microprocessor. The system 100 may include a test system 110 that can access a data storage device 112. The system 100 may also include a device test queue 120 that includes one or more electronic devices 122a-122c to be tested by the test system 110. Each of the electronic devices 122a-122c in the device test queue 120 includes a high-throughput scan architecture 130 that includes at least one scan chain, a decompressor, a compressor, and a clock controller. For example, the electronic device 122a includes a scan chain 132, a decompressor 134, a compressor 136, and a clock controller 138.

[0038] The scan architecture 130 may be implemented in an electronic device, such as a computer processor, and used to determine whether the electronic device is functioning properly or if the electronic device is defective. The scan architecture 130 may include multiple scan chains, each including multiple latch series. For example, each scan chain of the high-throughput scan architecture 130 may include a first latch series constituting a first series and a second latch series constituting a second series. The first latch series and the second latch series may operate simultaneously (e.g., in parallel) by shifting in alternate sets of values ​​from the scan-in data signal such that the first latch series and the second latch series record different data sets from the test pattern provided by the test system 110. These latch series may operate at a lower frequency than other components of the scan architecture. For example, the first latch series and the second latch series may operate at a clock rate that is a division of the data rate of the scan-in data signal during a test mode or a shift mode. Specifically, the clock rate may be equal to the data rate divided by an integer (nonzero) power of two. In this test or shift mode, both of the latch series may operate by storing (e.g., scanning in or shifting in) values, such as values ​​obtained from a scan-in data signal, and emitting (e.g., scanning out or shifting out) values ​​at the divided clock rate.

[0039] More specifically, one or more components of the scan architecture 130 may receive a first clock signal having a first frequency. These one or more components may provide inputs to the first and second latch series at, for example, the first frequency. The first and second latch series may receive a second clock signal having a second frequency that is a division of the first frequency. The second frequency may be equal to the first frequency divided by an integer (non-zero) power of two. For example, the second frequency may be equal to one-half the first frequency, one-quarter the first frequency, or one-eighth the first frequency. The first and second latch series may operate at the second frequency to capture alternating inputs provided by the one or more components.

[0040] The scan architecture 130 of an electronic device may provide many advantages for improving testing of the electronic device. These advantages may include reduced dynamic power consumption during electronic device testing, and are achieved, at least in part, through the design of the scan chains and clock networks used in the scan architecture 130. As described in more detail below with respect to Figures 2 and 4, each scan chain in the scan architecture 130 may include two or more latch series that operate at a lower frequency than other components of the scan architecture 130. By lowering the frequency at which the latch series operate (e.g., the frequency at which the latches store and release bits), the dynamic power used by the scan architecture 130 during a test mode (e.g., a shift mode rather than a functional mode) is reduced.

[0041] The dynamic power savings provided by the scan architecture 130 are achieved at least through a reduction in the dynamic power used by the clock network and the latches of the scan chains of the scan architecture 130. First, the frequency at which the latch series in the scan architecture 130 operate can be a division (or multiple) of the frequency at which other components of the scan architecture 130 operate, such as the decompressor 134 and the compressor 136. If each of the scan chains of the scan architecture 130 has two latch series, the operating frequency of the clock network is divided by a factor of two during the shift mode. As a result, the dynamic power of the clock network is effectively halved. Second, since the latches of the scan chains in the scan architecture 130 operate at a divided frequency or frequencies, the clock-related dynamic power used within the latches is reduced.

[0042] In using multiple latch series in each scan chain, scan architecture 130 may achieve dynamic power reduction without increasing test time. More specifically, using multiple latch series operating at a frequency that is a division of the frequency at which other components of scan architecture 130 operate counters the increase or substantial increase in test time that would normally be expected from lowering the frequency at which the latches operate (e.g., an increase of one, two, or more cycles in the output data rate of decompressor 134, which may be equal to the undivided clock rate D of clock controller 138). This is because the bits of the input data signal are split between two or more latch series of scan chains. For example, a first series of scan chains 132 may receive, store, and release all bits provided by decompressor 134 as a data signal in the even positions of the data signal, and a second series of scan chains 132 may receive, store, and release all remaining bits. That is, the second series of scan chains 132 may receive, store, and release all bits provided by compressor 136 as a data signal in the odd positions of the data signal. If the latches in scan architecture 130 operate at half the undivided clock rate D of clock controller 138 (e.g., operate at a clock rate of D / 2), scan architecture 130 may continue to generate output data signals at the undivided clock rate D by using scan chains that each include two series of latches. As a result, scan architecture 130 provides the added advantage of reducing dynamic power without increasing or significantly increasing test time, thereby improving test efficiency.

[0043] Scan architecture 130 includes various components. As shown, scan architecture 130 includes scan chain 132, and decompressor 134 designed to drive the loading of values ​​into the scan chains of scan architecture 130. Decompressor 134 may be an on-chip decompressor located on the device being tested, here electronic device 122a. Each of the other electronic devices in device test queue 120 may include a decompressor similar to decompressor 134 of electronic device 122a.

[0044] As described in more detail below, test system 110 may initiate scan chain testing by providing test patterns, such as a test input bitstream, to electronic devices in device test queue 120. The test patterns provided by test system 110 are used to initialize scan chains in the scan architecture. That is, the test patterns are used to set data states of certain portions of electronic device 122a during a scan-in phase or shift-in mode of electronic device 122a. As described in more detail below, the test patterns may also control the modes of electronic device 122a to perform scan chain testing, and switching between different modes.

[0045] More specifically, when electronic device 122a receives a test pattern from test system 110 on a scan-in line of scan architecture 130, decompressor 134 may use the test pattern to load values ​​into the scan chains of scan architecture 130, including scan chain 132. To load the values, decompressor 134 may be used to generate data signals that are provided to the scan-in lines of the scan chains. For example, decompressor 134 may receive a first clock signal from clock controller 138 and use this signal to generate data signal(s) from the test pattern and provide the data signals at a data rate equal to the clock rate of the first clock signal or a data rate that is a division of the clock rate. For example, decompressor 134 may receive a non-divided clock signal from clock controller 138 having a clock rate of D. Decompressor 134 may proceed to output a test input bitstream of the test pattern at a clock rate of D such that each scan chain of scan architecture 130 is provided one bit per clock cycle at clock rate D.

[0046] Scan chain 132 includes memory elements, such as latches (e.g., flip-flops), that are chained together to form a scan chain. These memory elements are represented as registers R1, R2, and R3. Scan chain 132 may also include logic components represented as L1, L2, and L3. Scan chain 132 may operate in a test or shift mode (e.g., a scan-in state) in which it follows scan path 142, and in a functional mode (e.g., a capture state) in which it follows a functional path. As described in more detail below with respect to FIGS. 2, 4, and 6A-6B, the scan chain of scan architecture 130 may include a first latch series that constitutes a first latch series, and a second latch series that constitutes a second latch series. The first and second latch series may operate simultaneously by shifting in alternating sets of values ​​from the scan-in data signal (e.g., driven by decompressor 134) such that the first and second latch series record different data sets from the test pattern provided by test system 110. For example, the first latch series may store every other bit of the data signal provided by decompressor 134, while the second latch series stores all of the remaining bits of the data signal.

[0047] The scan chain 132 may receive a second clock signal from a clock controller 138 having a clock rate that is a division of the clock rate D provided to the decompressor 134 and the compressor 136. The clock rate of the second clock signal is D / 2. N where N is any integer greater than 0. The latches of the scan chain 132 may receive and operate at this lower clock rate. N When operating at D / 2, the first and second series of latches store (e.g., scan in or shift in) values, such as values ​​obtained from a scan-in data signal driven by the decompressor 134, and NThe CLKIN pin emits (e.g., scans out or shifts out) values ​​at the clock rate.

[0048] The scan chains in scan architecture 130 may receive multiple clock signals from clock controller 138. For example, different components of scan chain 132 may receive and operate on different clock signals provided by clock controller 138. More specifically, one or more first components of scan chain 132 may receive a first clock signal having a clock rate D, and one or more other components of scan chain 132 may receive a first clock signal having a clock rate D / 2. N For example, the clock controller 138 may provide a first clock signal having a clock rate D to a multiplexer (MUX) of the scan chain 132 and a second clock signal having a clock rate D / 2 to two latch series of the scan chain 132. N The latch series may provide a second clock signal at a rate of D / 2. N at a rate of 100 ms, while the MUX may operate at a rate D to combine the values ​​shifted out from both series to generate the output data signal of scan chain 132. In combining the outputs of the two latch series, the MUX may interleave the output of the first latch series with the output of the second latch series, such that every other bit of the output signal is taken from the first latch series and the remaining bits of the output signal are taken from the second latch series.

[0049] The scan chains in scan architecture 130 may use multiple divided clock rates. As described in more detail below with respect to FIGS. 6A-6B, the scan chains of scan architecture 130 may in some cases include more than two latch series. For example, scan architecture 130 may include scan chains each including eight latch series. Four of the latch series may receive and operate at a clock rate of D / 2, while the remaining four latch series may receive and operate at a lower clock rate, such as a clock rate of D / 4.

[0050] Compressor 136 may receive the outputs of the scan chains of scan architecture 130 and combine them to generate a test output. For example, compressor 136 may take values ​​representing the outputs of the scan chains in scan architecture 130 and combine them to generate a signal on a scan-out line of the scan architecture that represents a test output or that can be used by test system 110 to extract a test output. Compressor 136 may operate at a higher clock rate than the latches of scan chains 132. For example, compressor 136 may operate at clock rate D by receiving a clock signal from clock controller 138 having a clock rate of D and reading the output value of each scan chain in scan architecture 130 on the rising edge of the clock signal having clock rate D. Compressor 136 may receive the same clock signal as decompressor 134 and operate at the same clock rate as decompressor 134. The test output generated by compressor 136 may be a bit stream provided to a scan-out line of scan architecture 130.

[0051] The test outputs are based on a test pattern provided by the test system 110. For example, each bit of the test pattern may have a corresponding bit in a test output. An input bit may correspond to an output bit, for example, based on the position of the input bit in the test pattern and the position of the output bit in the test output. For example, an input bit may correspond to an output bit based on the particular bit stream of the test pattern in which the input bit is located (e.g., which may indicate which scan chain the input bit is loaded into), the position of the input bit in the respective bit stream (e.g., which may indicate which latch in the scan chain the input bit is loaded into when the functional mode is enabled), the particular bit stream of the test output in which the output bit is located (e.g., which may indicate which scan chain the output bit is shifted out of), and the position of the output bit in the respective bit stream (e.g., which may indicate which latch in the scan chain the output bit is shifted out of upon switching from the functional mode to the shift mode). Also, each bit stream of the test pattern may have a corresponding bit stream in a test output. An input bitstream of test patterns may have a corresponding bitstream of test outputs, for example, based on a particular scan chain in scan architecture 130 that was loaded with the input bitstream and converted it into an output bitstream.

[0052] The clock controller 138 may be an on-chip clock controller configured to provide one or more clock signals to different components of the scan architecture 130. For example, the clock controller 138 may provide a first clock signal having a clock rate D to the decompressor 134 and the compressor 136, and a second clock signal having a clock rate D / 2 to the decompressor 134 and the compressor 136. N A second clock signal having a divided clock rate of 1 / 2 may be provided to the latches of the scan chain 132.

[0053] Test system 110 may include one or more computers or other computing devices such as desktop computer(s), laptop computer(s), server(s), or mobile device(s) such as smartphone(s) or tablet(s). Test system 110 may be part of a cloud computing environment. Test system 110 may include or have access to data storage 112.

[0054] Data storage 112 may be local to test system 110, such as an internal memory, or may be remote, such as part of a cloud computing environment that test system 110 can access.

[0055] Test system 110 may test electronic devices to determine whether the electronic devices function as designed or were properly manufactured. Test system 110 may begin testing on electronic devices in device test queue 120 after the electronic devices are placed in test location 124. For example, test system 110 may begin testing electronic device 122a in response to being placed in or assigned to test location 124.

[0056] When beginning testing of the electronic device, the test system 110 may select a test pattern to provide as an input to the scan architecture of the electronic device. The test pattern may include one or more bit streams used to load latches of scan chains in the scan architecture. Each of these bit streams may be represented as a vector. The test pattern may also include or be part of a test program that provides inputs to the scan chains and timing parameters for the inputs. For example, when performing a test on the electronic device 122a, the test system 110 may select a test pattern to load into latches of scan chains on the electronic device 122a, including the scan chain 132. The test system 110 may also select a test program to use to perform the test. The program may specify scan enable (SE) inputs of the scan chain latches (e.g., to switch between shift and functional modes of the latch series in the scan chain) and the timing for providing the inputs. After providing the test pattern as an input and enabling the functional mode for a number of clock cycles, the test system 110 may switch the latch series back to the shift mode to shift out the stored values. The shift out value may represent a test output that the test system 110 may obtain from a scan out line of the scan architecture 130. After obtaining the test output, the test system 110 may compare the test output to a reference output from the reference output 118 to determine whether the electronic device is functioning properly or is defective. For example, if the test output does not match the reference output or deviates from the reference output by more than an acceptable amount, the test system 110 may determine that the electronic device 122a is defective or requires further analysis.

[0057] The test system 110 may select a particular test pattern from the test patterns 116 based on one or more factors. These factors may include structural parameters of the electronic device being tested. For example, the test system 110 may select a particular test pattern based on the design of the scan architecture of the electronic device being tested. As another example, the test system 110 may select a particular test pattern based on the particular electronic device being tested or the type of electronic device being tested (which may indicate, for example, the scan architecture design used by the electronic device being tested). More specifically, the test system 110 may select test pattern A for the electronic device 122a based on a model of the electronic device 122a. The model of the electronic device 122a may indicate, for example, that the scan chains of the scan architecture 130 have a bit size of 8 (e.g., each scan chain of the scan architecture 130 includes eight latches, each configured to store one bit of a value at a time), and therefore the number of bits required to load the scan chains with a value for testing. Based on this, test system 110 may select test pattern A from test patterns 116 that includes a bit stream having a required bit size (e.g., 8 bits) and enable loading bit values ​​from test pattern A into all latches of the scan chains of scan architecture 130.

[0058] The factors may include the type of error, the type of defect, or the performance area for which the electronic device is to be tested. For example, the test system 110 may select a particular test pattern from the test patterns 116 based on a determination that stuck-at test should be performed on the electronic device 122a. The particular test pattern may be designed to test the electronic device 122a for either stuck-at-1 or stuck-at-0 logic behaviors, which indicate a defective gate. As another example, the test system may select a different test pattern from the test patterns 116 based on a determination that at-speed testing should be performed on the electronic device 122a. The test pattern may be designed to test the electronic device 122a for node timing defects, such as rising transition faults and falling transition faults. Other test patterns in test patterns 116 may be designed for other tests, such as path delay testing (e.g., to test these critical paths by performing at-speed testing on certain designated paths), IDDQ testing (e.g., to test CMOS integrated circuits for the presence of manufacturing faults indicated by the presence of excessive current draw), N-detection testing and embedded multiple-detection testing (e.g., to test multiple faults that are randomly targeted), deterministic bridging testing (e.g., to identify net pairs that have faults that may be bridging and are not detected by other test patterns), small-delay defect testing (e.g., to test the longest path to detect small-delay defects), etc. In some embodiments, a test pattern may be designed or applicable for multiple types of tests.

[0059] Test system 110 may determine the error type, defect type, or performance area for which the electronic device is to be tested and, based on the determination, select a test pattern from test patterns 116. For example, a user of test system 110 may specify all defect test types to be performed on all model X electronic devices. In response to determining that electronic device 122a is a model X electronic device, test system 110 may examine a data object of the model X electronic device that provides that each model X device should undergo at-speed testing. Based on the model X device having a scan architecture with a scan chain of bit size 4 and an indication that at-speed testing should be performed, test system 110 may load 4 bits into the scan chain and select test pattern B from test patterns 116 designed to reveal whether the electronic device being tested has a stuck-at-1 or stuck-at-0 logic behavior.

[0060] As another example, the test system 110 may determine the type of errors, types of defects, or performance areas for which the electronic device is to be tested based on attributes of the electronic device, such as structural attributes of the electronic device. These attributes may include the node size of the electronic device, defects historically common for the model or manufacturer of the electronic device, the intended use or acceptable quality level of the electronic device, etc. For example, by default, the test system 110 may perform stuck-at-speed testing and at-speed testing for all electronic devices in the device test queue 120. However, if the electronic device includes a design node of 90 nm or smaller, the test system 110 may determine that low-delay defect testing also needs to be performed. Before testing the electronic device, the test system 110 may refer to a lookup table to identify the test pattern to use, the type of test to perform, the type of defect or error to be identified, or rules for identifying any of the foregoing.

[0061] In some embodiments, test system 110 selects multiple test patterns to use when testing a single electronic device. For example, when testing electronic device 122a, test system 110 may select a first test pattern from test patterns 116 to test electronic device 122a for proper timing performance and may select a second test pattern from test patterns 116 to test electronic device 122a for stuck-at-1 or stuck-at-0 logic behavior. In response to running a test with two different test patterns, test system 110 may obtain two test outputs.

[0062] In some embodiments, the test system 110 selects multiple reference outputs for use when testing a single electronic device. Continuing with the previous example, the test system 110 may select a first reference output from the reference outputs 118 based on a first test pattern and a second reference from the output of the reference outputs 118 based on a second test pattern. The test system 110 may compare the first reference output to the first test output (e.g., to see if they match) and may compare the second reference output to the second test output (e.g., to see if they match). If the first comparison reveals that the first test output did not match the first reference output or was not sufficiently similar to the first reference output, the test system 110 may determine that the timing performance of the electronic device 122a is defective. If the second comparison reveals that the second test output did not match the second reference output or was not sufficiently similar to the second reference output, the test system 110 may determine that the logical operation of the electronic device 122a is defective.

[0063] In selecting a test pattern to use to test the electronic devices in test queue 120, test system 110 may access data storage 112 to select a test pattern from test patterns 116. As mentioned above, the test pattern selected by test system 110 may be based on attributes of the electronic device being tested, the type of test to be performed, or the defects to be identified.

[0064] In selecting a reference output to use for comparison with the test output, the test system 110 may access the data storage device 112 to select a reference output from the reference outputs 118. The reference output selected by the test system 110 may depend on the selected test pattern. For example, a particular test pattern may have a corresponding reference output or a set of corresponding reference outputs (e.g., the selection from among the set depends on other factors such as the model of the electronic device being tested). The reference output selected may also depend on the electronic device being tested. For example, the reference output selected by the test system 110 may be specific to the type of electronic device in which the electronic device 122a is, the model of the electronic device 122a, the bit size of the scan chain 132 (e.g., the number of latches in the scan chain 132), the manufacturer or designer of the electronic device 122a, or other attributes of the electronic device 122a.

[0065] Instead of selecting a test pattern, the test system 110 may automatically generate the test pattern. For example, the test system 110 may use automatic test pattern generation to test the electronic device 122a. The method that the test system 110 uses to generate the test pattern may depend on the type of test(s) to be performed on the electronic device 122a or the type of defects to be ruled out for the electronic device 122a.

[0066] If the test system 110 automatically generates the test patterns, the test system 110 may automatically generate corresponding reference outputs based on the test patterns. For example, using the generated test patterns and attributes of the electronic device 122a, the test system 110 may generate an array or vector of values ​​that represent expected test outputs of the electronic device 122a, assuming that the electronic device 122a is functioning properly.

[0067] The test system 110 may obtain the test output by capturing a value detected on the scan-out line of the scan architecture 130 after a threshold time or number of clock cycles (e.g., based on the clock rate) has elapsed since a test pattern was provided as an input to the scan-in line or since the mode of the scan chain was switched from functional mode to shift mode. For example, if the scan architecture 130 includes a scan chain with an 8-bit size, after the test system 110 disables the functional mode (e.g., by setting a scan enable of a latch of the scan chain to 1) and enables the shift mode, the test system 110 may obtain the test output of the electronic device 122a by storing the value read on the scan-out line of the scan architecture 130 for 8 clock cycles at the clock rate D. Alternatively, after the test system 110 reads the first value, the test system 110 may obtain the test output of the electronic device 122a by storing the value read on the scan-out line of the scan architecture 130 for 8 clock cycles at the clock rate D.

[0068] In comparing the test output to the reference output to determine whether the electronic device is defective, the test system 110 may apply one or more rules that indicate whether the device passed or failed the test. The rules may require an exact match between the reference output and the test output. The rules may additionally or alternatively define an acceptable deviation between the reference output and the test output. The rules may use a percentage threshold or an absolute threshold to define an acceptable deviation between the reference output and the test output. For example, the test output obtained by the test system 110 may include an array of values ​​[0;0;1;0;1;1;0;1], and the reference output identified by the test system 110 may include an array of values ​​[0;1;0;0;1;1;0;0]. The test system 110 determines that the second value, the third value, and the eighth value of the test output differ from the reference pattern, but the other values ​​match corresponding values ​​of the reference pattern. As a result, the test system 110 may conclude that the electronic device 122a does not function as designed or contains a defect, and therefore fails the test.

[0069] The rules applied to the comparison results may depend on the parameters of the test or the attributes of the electronic device being tested. For example, the rules applied to determine whether the electronic device 122a passed or failed the test may be selected by the test system 110 based on the test pattern used for the test, the type of test performed on the electronic device 122a (e.g., at-speed test, stuck-at test, etc.), or the intended use or acceptable quality level of the electronic device 122a. More specifically, the test system 110 may apply a first set of rules that require an exact match between the test output of the electronic device 122a and the reference output if the test performed was a path delay test. However, if the test system 110 performs an at-speed test on the electronic device 122a, the test system 110 may apply a different set or rules that require that only 95% of the values ​​in the test output match a positionally related value in the reference output.

[0070] After determining that the electronic device has failed the test, the test system 110 may notify one or more users of the test system 110 that the test has failed. For example, the test system 110 may generate a notification indicating that the electronic device 122a has failed the test, or more generally, that the electronic device in the first position 124 of the test queue 120 has failed the test. The notification may include additional information, such as the results of the test. The results may include, for example, an indication of the test pattern used and an indication of the reference output used. The results may include the test output. The results may additionally or alternatively include information related to a comparison of the test output to the reference output. The test system 110 may transmit this notification to a user of the test system 110, for example, via a dashboard, an email notification, a text message, etc. In response to receiving this notification, the user may instruct the defective electronic device to be discarded. For example, in response to receiving a notification from the test system 110 indicating that the electronic device 122a has failed a test, a user may provide instructions to the test system 110 to place the electronic device 122a in a waste container 126. The test system 110 may proceed by sending instructions to one or more robotic devices to discard the electronic device 122a.

[0071] After determining that the electronic device fails the test, the test system 110 may generate instructions to discard the electronic device. For example, the test system 110 may generate instructions to have a robotic device, such as a robotic arm, place the electronic device 122a in an area containing the defective device or toss the electronic device 122a into a waste container 126. Before generating the instructions or sending the instructions for disposal, the test system 110 may ask an administrator or other user for confirmation of the disposal. If the electronic device 122a is on a wafer with other electronic devices, the test system 110 may avoid sending instructions to move or discard the electronic device 122a until other devices on the same wafer have been tested.

[0072] In response to determining that the electronic device failed the test, the test system 110 may provide an indication that the tested electronic device failed the test or should be discarded. For example, in response to determining that the electronic device 122a failed the test, the test system 110 may update a data object that stores data related to the electronic device 122a to reflect that the electronic device 122a is defective. The test system 110 may also generate and transmit a notification that includes the indication. For example, the test system 110 may generate an electronic message indicating that the electronic device 122a failed the test and is defective. The electronic message may be transmitted electronically by the test system 110 to a manager, manufacturer, or designer of the electronic device 122a. The electronic message may include additional information regarding the results of the test, such as the test pattern used, the test output received, the results of a comparison of the test output to a reference output, or parameters used to determine whether the electronic device passed or failed the test. The electronic message may include a report on all electronic devices that share one or more attributes, such as all electronic devices on the same wafer.

[0073] Test system 110 may take other actions if it determines that the electronic device has passed the test. For example, as shown, in response to determining that electronic device 122a has passed the test, test system 110 may generate instructions that cause device 122a to be placed in area 128 with other properly functioning devices. If electronic device 122a is on a wafer with other electronic devices, test system 110 may avoid placing device 122a in area 128 until the other devices on the wafer have been tested.

[0074] In response to determining that the electronic device passed the test, the test system 110 may provide an indication that the tested electronic device passed the test or that the device should be moved to an area for properly functioning devices. For example, in response to determining that the electronic device 122a passed the test, the test system 110 may update a data object that stores data related to the electronic device 122a to reflect that the electronic device 122a functions properly. The test system 110 may also generate and transmit a notification that includes the indication. For example, the test system 110 may generate an electronic message indicating that the electronic device 122a passed the test and functions properly. The electronic message may be transmitted electronically by the test system 110 to a manager, manufacturer, or designer of the electronic device 122a. The electronic message may include additional information regarding the results of the test, such as the test pattern used, the test output received, the results of a comparison of the test output to a reference output, or parameters used to determine whether the electronic device passed or failed the test. The electronic message may include a report on all electronic devices that share one or more attributes, such as all electronic devices on the same wafer.

[0075] Test system 110 may store all or a portion of the results of each test performed or each test performed that ended in failure. Test system 110 stores all or a portion of these results in data storage 112 as part of collected data 114. For example, test results for an electronic device that failed a test may be stored by test system 110 as part of collected data 114 for further analysis because they may provide insight into which part of the electronic device is not functioning as designed, which step or steps in the manufacturing process are likely to have caused the defect in the electronic device, or which manufacturing machine is most likely to have introduced a defect in the electronic device during manufacturing.

[0076] Each electronic device in device test queue 120 may include an interface that test system 110 uses to provide test patterns to and receive test results from the electronic device. For example, test system 110 may use a test interface or test access port (TAP) of electronic device 122a to provide test patterns as input to scan architecture 130 of electronic device 122a and receive test results from electronic device 122a in response to the test patterns. The test interface of the electronic device may take advantage of the scan architecture described herein by providing data transfer to and from the electronic device at an undivided clock rate, for example, while power is conserved as a result of the latch design of scan architecture 130.

[0077] The test interface of the electronic device may be a standard interface, such as an interface with test structures of IEEE Standard 1149.1. The ability to use a standard test interface may further improve the efficiency of the test system 110 testing the electronic device. For example, the test system 110 may not need customized test parameters to test the electronic device with the scan architecture 130 when a standard test interface is used. This may provide the advantage of reducing or eliminating the time spent determining test parameters and not having to change the test parameters, thereby reducing the test time of the electronic device (e.g., for the device with the scan architecture and other devices, or for each of the devices with the scan architecture). The ability to use a standard test interface may also provide additional advantages. These advantages may include reduced design time and manufacturing time of the electronic device with the scan architecture 130. For example, a circuit designer of the electronic device with the scan architecture 130 may not need to provide user-inserted test structures for scan testing when a standard test interface is used, and thus may be transparent (e.g., hidden or invisible) to the circuit designer.

[0078] Test system 110 may place electronic devices in device test queue 120. Test system 110 may place electronic devices in device test queue 120 when it receives the electronic devices, e.g., when it manufactures the electronic devices, or when it is scheduled for testing. Alternatively, test system 110 may place electronic devices in device test queue 120 according to an electronic device hierarchy, or a combination of hierarchy and order in which it receives the electronic devices. For example, test system 110 may be programmed to assign a higher priority to certain models or types of electronic devices than all other electronic devices (e.g., because they are more important to meet quotas at a particular time, because they are new designs to reduce waste if the manufacturing process is producing more than an acceptable rate of defective devices, etc.). After an electronic device assigned the highest priority, or an electronic device assigned a higher priority than any other electronic device in test queue 120, is manufactured, test system 110 may place the electronic device in the first position 124 for devices to be tested, or in the next position for devices to be tested (e.g., when testing of the electronic device in current position 124 has already begun).

[0079] Electronic devices 122a-122c may represent three CPUs on a silicon wafer that was recently manufactured and contains 597 other CPUs. Device 122a may be, for example, the first CPU on the silicon wafer selected for testing.

[0080] The order of electronic devices in test queue 120 may depend on their location relative to the location of the first electronic device selected for testing and / or their location relative to the wafer (e.g., edge of the wafer, first row of devices on the wafer, first column of devices on the wafer, etc.). For example, electronic devices 122a-122c may all be found in the first, top row of electronic devices on the wafer. After electronic device 122a is selected for testing first, test system 110 may place electronic device 122b in the test queue next because electronic device 122b is the next CPU in the top CPU row after electronic device 122a. Similarly, test system 110 may place electronic device 122c in the test queue next because electronic device 122c is the next CPU in the top CPU row after electronic device 122b.

[0081] Additionally, the order of the electronic devices in device test queue 120 may be predetermined, for example, based on the location of the electronic devices on the wafer. For example, test system 110 may follow a location order, such that any electronic devices located at a first location are tested first, any electronic devices located at a second location are tested second, and so on.

[0082] 1 includes a flow chart of an exemplary process 150 for testing electronic devices using a high-throughput scan architecture. Process 150 may be performed, at least in part, using test system 110 described herein.

[0083] The process 150 includes testing 152 the device with the test pattern. For example, the test system 110 may obtain a test pattern from the test pattern generator 116 to provide as an input to a scan-in line of the scan architecture 130 of the electronic device 122a. The test pattern selected by the test system 110 may be based on the particular electronic device being tested or the type of electronic device being tested. For example, the test system 110 may select a test pattern to use to test the electronic device 122a based on the make and model of the electronic device 122a.

[0084] Process 150 includes obtaining a test output in response to the test pattern (154). For example, test system 110 may provide the test pattern as an input on a scan-in line and then read the test output on a scan-out line of scan architecture 130.

[0085] The process 150 includes comparing 156 the obtained test output to a reference. For example, the test system 110 may select a reference output from the reference outputs 118 based on the test pattern used to test the electronic device 122a. The reference output selected by the test system 110 may also depend on the particular device being tested or the type of device being tested.

[0086] The process 150 includes determining 158 whether the device meets criteria for passing the test based on the comparison. The criteria may define the extent to which the test output is allowed to deviate from a selected reference output. For example, the criteria for testing the electronic device 122a may specify that the test output must exactly match the reference output. The criteria used by the test system 110 may depend on different factors. For example, a manufacturer may set a first criterion for a first model of a processor and a second criterion for a second model of the processor that is different from the first criterion. As another example, a manufacturer may set different criteria for the same model of a processor based on the intended use of the individual processor or a third party that ordered the individual processor. If one processor of model A is to be installed in a consumer laptop and a second processor of the same model (model A) is to be installed in a satellite, test system 110 may select first criteria to use when testing the first processor set for use in the consumer laptop and may select second, more stringent criteria to use when testing the second processor set for use in the satellite.

[0087] Process 150 includes generating 160 a label for the device that indicates whether the device meets or does not meet the criteria. For example, in response to determining that electronic device 122a passed the test, test system 110 may update a data object for electronic device 122a to indicate that electronic device 122a passed the test. Test system 110 may provide this updated data object to one or more other devices, such as a robotic arm, which may use the updated data object to determine that electronic device 122a should be moved to region 128.

[0088] 2 is a diagram of a high-throughput scan architecture 130. In addition to the previously described decompressor 134, compressor 136, and clock controller 138, the scan architecture 130 may include a deserializer 210, a serializer 214, a mask 218, and multiple scan chains 202. As an example, the scan architecture 130 may be implemented on the electronic device 122a described in more detail above with respect to FIG.

[0089] The deserializer 210 is connected to an input line of the deserializer 210, through which the deserializer 210 may receive a test pattern provided by the test system 110. The deserializer 210 includes N serial load latches 212 (e.g., flip-flops). Using these serial load latches 212, the deserializer 210 may organize the input test pattern into N bit streams that are provided to the decompressor 134. Each bit stream may ultimately be passed by the decompressor 134 to a particular scan chain of the scan chains 202 at a particular data rate.

[0090] The deserializer 210 may also control the mask 218. For example, the deserializer 210 may enable or disable the mask 218 using an additional latch that controls the mask 218. If the latch stores a bit having a value of 1, the mask 218 may be enabled. However, if the latch stores a bit having a value of 0, the mask 218 may be disabled.

[0091] The clock controller 138 is configured to provide different clock signals to different components of the scan architecture. The clock controller 138 may include a clock network 250 that provides a clock signal having a clock rate D. The clock controller 138 may also include a divider 252 that can divide the clock signal provided by the clock network 250. For example, the divider 252 may divide the clock signal by two to generate a second clock signal having a clock rate of D / 2. The divider 252 may be a frequency divider.

[0092] In some embodiments, the divider 252 is a programmable divider. For example, the divider 252 may be a programmable divider configured to output a variable clock signal at a frequency determined by the program state of the programmable divider. Thus, the divided clock signal may be a variable clock signal having a frequency based on the program state of the programmable divider. As an example, the test system 110 may provide an input to control the divider to set the range to which the frequency of the undivided clock signal should be divided. More specifically, based on the electronic device 122a having a scan architecture in which each scan chain includes two latch series, the test system 110 may provide an input to set the divider 252 to divide the frequency of the undivided clock signal by two. However, if the electronic device 122a instead has a scan architecture in which each scan chain includes eight latch series (e.g., as shown in FIG. 6A), the test system 110 may provide different inputs that set a first divider to divide the frequency by two and a second divider to divide the frequency by four.

[0093] The clock controller 138 may include a multiplexer 254 or other electronic switch to control which clock signal is provided to the latches of the scan chain 202. The clock signal provided, e.g., a non-divided clock signal with a clock rate D or a divided clock signal with a clock rate D / 2, depends on the current mode of the scan architecture 130. For example, when the scan architecture 130 is in a shift mode (e.g., a scan enabled state), the multiplexer 254 of the clock controller 138 is used to provide a divided clock signal with a clock rate D / 2 to the latches of the scan chain 202. However, when the scan architecture 130 is in a functional mode (e.g., a scan disabled state), the multiplexer 254 of the clock controller 138 is used to switch the output signal from the divided clock signal with the clock rate D to the non-divided clock signal. That is, the multiplexer 254 may be used to function as a bypass for the divider 252 when the scan chain 202 is operating in a functional state.

[0094] In some embodiments, the clock controller 138 provides multiple divided clock signals using multiple dividers or additional controls. For example, the scan architecture may include scan chains each having eight latch series. In each scan chain, four of the eight series may operate at a D / 2 clock rate in shift mode, and the remaining four series may operate at a D / 4 clock rate. The clock controller 138 may use a first divider to generate a first divided clock signal having a rate of D / 2 and a second divider to generate a second divided clock signal having a rate of D / 4. To achieve this, the scan architecture may use multiple switching devices. For example, the scan architecture may include two multiplexers, a first multiplexer that receives and switches between the undivided clock signal from the clock network 250 and the first divided clock signal, and a second multiplexer that receives and switches between the undivided clock signal from the clock network 250 and the second divided clock signal.

[0095] The decompressor 134 may receive an undivided clock signal from the clock network 250 of the clock controller 138. The decompressor 134 may use the clock signal to provide the bit stream obtained or received from the deserializer 210 to the scan chain 202 at a particular data rate. The data rate may be equal to the clock rate D of the undivided clock signal. For example, in response to detecting a rising edge of the undivided clock signal, the decompressor 134 may read the values ​​of all bits in the serial load latch 212 of the serializer 214 and provide these values ​​as inputs to the scan chain. More specifically, if the bit value of the latch A of the serial load latch 212 is 0 when the rising edge of the undivided clock signal is detected, the decompressor 134 may obtain a bit value of 0 and provide it to the first scan of the scan chain 202. The decompressor 134 may continue to obtain and provide a bit value as an input to the scan chain 202 for each clock cycle of the undivided clock signal.

[0096] The data rate provided by the decompressor 134 may be a division of the clock rate of the undivided clock signal. For example, the data rate may be a division of the clock rate D (e.g., D / 2), and the operating rate of the latches of the scan chain 202 may be a further division of the clock rate (e.g., D / 4).

[0097] In some embodiments, decompressor 134 and compressor 136 receive a divided clock signal from clock controller 138, where clock controller 138 may provide a further divided clock signal to the latches of scan chain 202. For example, clock controller 138 may provide a clock signal having a clock rate of D / 2 to decompressor 134 and compressor 136, as well as provide a second clock signal having a clock rate of D / 4 to the latches of scan chain 202.

[0098] The decompressor 134 may be a set of logic components used to reduce scan chain length. For example, the decompressor 134 may fan out the input bit stream received from the deserializer 210 across more scan chains than the bit stream. Each of these scan chains may be shorter than the original bit stream requires. For example, if each bit stream is 16 bits long, but the internal scan chains 202 are limited to a bit size of 4, the decompressor 134 may be used to split the original bit stream into four bit streams of 4 bits each and continue to provide each of the smaller bit streams to a different scan chain of the scan chains 202.

[0099] Each of the scan chains 202 may include a first latch series 220 and a second latch series 230. For example, the first scan chain includes a first latch series 220a and a second latch series 230a, the second scan chain includes a first latch series 220b and a second latch series 230b, and the third scan chain includes a first latch series 220c and a second latch series 230c.

[0100] Each latch series in the scan chain may include the same number of memory elements. These memory elements may include flip-flop latches, such as master-slave flip-flops, as described in more detail with respect to FIG. 5A. For example, in the illustrated 4-bit configuration, each of the scan chains 202 includes two flip-flop latches 222 and 224 in the first latch series 220 and two flip-flop latches 234 and 236 in the second latch series 230. Various other configurations are possible. For example, in an 8-bit configuration, each of the scan chains may include four flip-flop latches in the first series and four flip-flop latches in the second series. As another example, in a 16-bit configuration, each of the scan chains may include eight flip-flop latches in the first series and eight flip-flop latches in the second series.

[0101] The scan chains 202 may also include a component or set of components that allows different latch series to store different bits driven by the decompressor 134. For example, each scan chain in the scan chains 202 may include a component or set of components that prevents the first latch series 220 and the second latch series 230 from storing the same bit driven by the decompressor 134. As described in more detail below with respect to Figures 5B-5D, this component or set of components may include memory components such as specialized flip-flop latches. However, other or additional components may be used. For example, each of the scan chains 202 may include a lock-up latch 232 (e.g., a transparent latch) that prevents the first latch series 220 and the second latch series 230 from storing the same bit driven by the decompressor 134 by introducing a hold window in the second latch series 230.

[0102] The lock-up latch 232 may receive and operate on a divided clock signal, and thus introduce a hold window that is equal to or longer than a full cycle of the undivided clock signal used by the decompressor 134 and the compressor 136. For example, the lock-up latch 232 may receive and operate on a divided clock signal having a clock rate D / 2, and thus introduce a hold window that is a full cycle of the undivided clock signal used by the decompressor 134 and the compressor 136. The lock-up latch 232 may be a positive lock-up latch 232 (e.g., a positive level sensitive lock-up latch) that functions transparently when the divided clock signal is high, and thus provides a hold window when the divided clock signal is low.

[0103] More specifically, the decompressor 134 may drive bits into the scan chain 202 at a data rate equal to the data rate of the clock rate D. When the decompressor 134 drives the first bit A in response to detecting a first positive edge of the undivided clock signal, the lock-up latch 232 may capture the first bit A as triggered by a first positive edge of the divided clock signal coinciding with the first positive edge of the undivided clock signal. As will be described in more detail below with respect to FIGS. 5A and 6A-6B, the first flip-flop 222a of the first latch series 220a is prevented from capturing the first bit A because the flip-flop 222a may be a master-slave flip-flop where the master contains old data and the slave is not activated until a half cycle of the divided clock signal has passed. That is, the flip-flop 222a must wait to move new data to the master until it can move old data to the slave when the divided clock signal goes low. For this same reason, the second flip-flop 234a is also prevented from capturing the first bit A when the divided clock signal is high and the lock-up latch 232b functions transparently. By the time a half cycle of the divided clock signal has elapsed, e.g., by the time the divided clock signal goes low, a full cycle of the undivided clock signal has elapsed and the decompressor 134 begins to drive the second bit B. When the divided clock is low, the master and slave of the first flip-flop 222a are active and the flip-flop 222a can store the second bit B. However, because the lock-up latch 232a introduces a hold window when the divided clock signal goes low, the lock-up latch 232a maintains the first bit A for the second latch 234a. Similar to the first flip-flop 222a, in response to the divided clock signal going low, the master and slave of the second flip-flop 234a are activated and the flip-flop 234a may store the output from the lock-up latch 232a, including bit A.

[0104] The end of the hold window coincides with a third positive edge of the undivided clock signal, triggering the decompressor 134 to begin driving the third bit C, and the above process is repeated. For example, the lock-up latch 232a may capture the third bit C. By the time the flip-flops of the first series 220a and the second series 230a are able to shift new data (e.g., by the time both the master and slave elements in the flip-flops are active), the decompressor 134 will have driven the fourth bit D. After the divided clock signal goes low a second time, the first flip-flop 222a can release bit B which can be stored in the master of the third flip-flop 224a, the first flip-flop 222a can shift to the fourth bit D, the second flip-flop 234a can release bit A which can be stored in the fourth flip-flop 236a, and the second flip-flop 234a can shift to the third bit C due to the hold window provided by the lock-up latch 232a. As this process continues, the first latch series 220a and the second latch series 230a can be fully loaded with different bits such that no latch of the first latch series 220a stores the same bit as that of the second latch series 230a.

[0105] After the values ​​are loaded into the memory elements of the scan chain 202, the scan architecture 130 may be switched to a functional mode to test the logic of the electronic device using the loaded values. For example, the test system 110 may provide an input to each of the flip-flops in the scan chain 202 to set a scan enable (SE) to 0 to disable the shift mode. In the functional mode, the values ​​loaded into the memory elements of the scan chain 202 may be used to test the logic components of the electronic device.

[0106] Each scan chain may also include a multiplexer 240 or other switching component that generates a bitstream by combining bits of the first latch series 220 and the second latch series 230. For example, after the circuit logic is tested in functional mode, the test system 110 may return the scan architecture 130 to a shift mode by providing an input that sets a scan enable (SE) of each flip-flop in the scan chain 202 to 1. The new values ​​stored in the memory components of the scan chain 202 are then shifted out of the scan chain 202, for example, as a result of a logic test along a functional path. A switching component, such as a multiplexer 240, may then be used for each scan chain to combine the values ​​released from the first latch series 220 with the values ​​released from the second latch series 230 to generate a bitstream for each scan chain. Unlike other components of the scan chain 202, such as the latches of the scan chain 202, the switching components of the scan chain 202 may operate with an undivided clock signal in shift mode to generate a bitstream having a data rate that matches the clock rate D or the data rate of the bitstream previously driven by the decompressor 134.

[0107] As an example, multiplexer 240a may receive an undivided clock signal and operate to select a value for third flip-flop 224a and a value for fourth flip-flop 236a. In this example, multiplexer 240a operates at twice the frequency at which the flip-flops in scan chain 202 shift bits, so that multiplexer 240a may select a first bit to pass through from third flip-flop 224a and be switched to select a bit from fourth flip-flop 236a before a new bit is shifted into fourth flip-flop 236a. This difference in operating speed between bit shifting in the scan chain and bit combining by the switching component is important to prevent bits from being lost that are not included in the bit stream generated by the switching component, for example.

[0108] The multiplexer 240a may continue to combine the selected bits from the first latch series 220a with the bits obtained from the second latch series 230a until all captured bits (e.g., bits captured in the memory components of the first scan chain) have been shifted out of the memory components.

[0109] The switching components of the scan chains 202 may provide the generated bit streams to the mask 218. The mask 218 may be enabled to mask the outputs of the scan chains 202 that it receives from the corresponding switching components. Alternatively, the mask 218 may be disabled such that the outputs pass through the mask 218 to the compressor 136. For example, when enabled, the mask 218 may pass the bit streams for each of the scan chains to the compressor 136 after masking those bit streams. Alternatively, when the mask 218 is disabled, the bit streams for each of the scan chains 202 may pass through the mask 218 to the compressor 136 directly.

[0110] The compressor 136 may receive and operate on a non-divided clock signal. The compressor 136 may be synchronized with the decompressor 134 such that both the compressor 136 and the decompressor 134 receive and operate on the same clock signal. The compressor 136 may receive bit streams of different scan chains 202, for example, from switching components of the scan chains 202 or masks 218. The compressor 136 may proceed to provide the bits in the bit streams to the serializer 214.

[0111] Compressor 136 may be a set of logic components used to combine outputs from multiple scan chains to reduce the number of outputs. For example, compressor 136 may include XOR gates that compressor 136 uses to combine bit streams of different scan chains in scan chains 202. For example, compressor 136 may provide a 4X compressor by combining bit streams from every fourth scan chain such that the number of bit streams included on the output lines of serializer 214 is reduced by a factor of four to match the design scan output. More specifically, there may be 16 scan chains in scan chains 202, but only four serial unload latches in serializer 214's serial unload latches 216. Compressor 136 may combine the bit streams of the first four scan chains of scan chains 202 and provide the combined bit stream to serial unload latch A of serial unload latch 216, combine the bit streams of the next four scan chains and provide the second combined bit stream to serial unload latch B of serial unload latch 216 of decompressor 134, and so on.

[0112] The serializer 214 is connected to an output line of the scan architecture 130. Through this output line, the serializer 214 may use the bit stream it receives from the compressor 136 to generate test result data (e.g., test output) for the electronic device under test. The serializer 214 includes N serial unload latches 216 (e.g., flip-flops). Using these serial unload latches 216, the serializer 214 may organize the input bit stream into a test output.

[0113] 3A-3B are diagrams of a scan chain 132 of a high throughput scan architecture and timing diagrams 350 for various modes of the scan chain 132. As shown in FIG.

[0114] 3, the scan chain 132 may include several memory elements 310a, 310b, and 310c. Each of the memory elements 310a, 310b, and 310c may be a register, such as a shift register including one or more flip-flops. The flip-flops may be triggered by edges of a clock signal provided by the clock controller 138. The scan chain 132 may also include several logic components 320a, 320b, and 320c. The logic components 320a, 320b, and 320c may each represent a combinational logic block of the electronic device being tested, or may collectively represent a combinational logic block of the electronic device being tested. Each of the logic components 320a, 320b, and 320c may include one or more logic gates connected via a set of nodes.

[0115] Scan chain 132 may operate in a test or shift mode (e.g., scan-in state) following scan path 142, and in a functional mode (e.g., capture state) following functional path 343. At the start of a new test, scan chain 132 may receive an input at input 302 that switches scan chain 132 to shift mode, thereby allowing new values ​​to be shifted into memory components 310a, 310b, and 310c. For example, this input may set a scan enable (SE) of each of memory components 310a, 310b, and 310c high to disable the functional mode. In other configurations of scan chain 132, this input may set a scan enable (SE) of each of memory components 310a, 310b, and 310c low to disable the functional mode. In the shift mode, memory components 310a, 310b, and 310c receive a divided clock signal from clock controller 138 to operate. For example, in shift mode, memory components 310a, 310b, and 310c receive a divided clock signal with a clock rate of D / 2, where the undivided clock signal has a clock rate of D. In shift mode, a bit stream provided to the scan-in line is loaded into memory components 310a, 310b, and 310c according to scan path 142.

[0116] After the memory components 310a, 310b, and 310c are loaded with bits from the scan-in line, the scan chain 132 may receive a new input at the input 302 that switches the scan chain 132 from the shift mode to the functional mode. For example, this input may set the scan enable (SE) of each of the memory components 310a, 310b, and 310c low to enable the functional mode. In other configurations of the scan chain 132, this input may set the scan enable (SE) of each of the memory components 310a, 310b, and 310c high to enable the functional mode. In the functional mode, the memory components 310a, 310b, and 310c may receive different clock signals from the clock controller 138. For example, each of the memory components 310a, 310b, and 310c may receive and operate on a non-divided clock signal at a clock rate D.

[0117] In the functional mode, bits loaded into memory components 310a, 310b, and 310c follow a logic path 342. In following the logic path 342, the stored bits are released to logic components 310a, 320b, and 320c and undergo logic operations. These logic operations may modify the bits, for example, by changing their value. After the logic operations are performed on the bits, the bits may be stored in the memory component that immediately follows the memory component from which the bits were released, or may be provided as or as part of the output(s) 304. For example, as a result of bits being loaded into memory components 310a, 310b, and 310c during the shift mode, the first memory component 310a may store a third bit C having a value of 0, the second memory component may store a second bit B having a value of 0, and the third memory component may store a first bit A having a value of 1. In the functional mode, the third bit C may be released by the first memory component 310a to the first logic component 320a, which performs a series of logical operations on bit C. As a result of the logical operations, bit C may be changed to now have a value of 1. Bit C may then be stored in the second memory component 310b. At substantially the same time that the first bit C is released, the second bit B may be released by the second memory component 310b to the second logic component 320b, which also performs a series of logical operations on bit B. Despite having undergone the logical operations, bit B may retain its original value of 0. Bit B may then be stored in the third memory component 310c. At substantially the same time that the third bit C and the second bit B are released, the first bit A may be released by the third memory component 310c to a third logic component 320c, which also performs a series of logical operations on bit A. As a result of the logical operations, bit A may now be changed to have a value of 0. Bit A may be output as or as part of the output(s) 304.

[0118] After the logical operations are performed and the resulting values ​​are stored in the memory components of the scan chain 132 or provided at the output(s) 304, a final step of shifting out the bits from the memory components is performed. For example, to end the test, the scan chain 132 may receive a final input at input 302 that returns the scan chain 132 to a shift mode so that the stored bits can be shifted out onto the scan-out line. For example, this input may set the scan enable (SE) of each of the memory components 310a, 310b, and 310c high to disable the functional mode and enable the shift mode. In this shift mode, the memory components 310a, 310b, and 310c may again operate receiving a divided clock signal provided by the clock controller 138. As an example, this divided clock signal may release the modified bit B stored in the third memory component 310c onto the scan-out line during a first cycle, and release the modified bit C stored in the second memory component 310b to be shifted into the third memory component 310c. During the second cycle, the modified bit C, now stored in the third memory component 310c, may be released onto the scan out lines to complete the shift out operation.

[0119] The test results may include the values ​​read from the scan-out line and the output 304. For example, the test system 110 may generate a vector using the output(s) 304 and the values ​​read on the scan-out line. More specifically, the test system 110 may generate a vector that initially includes only the value of the modified bit A in the output 304. This value may be available to the test system 110 before the shift mode is entered for the second time. In a first cycle of the shift mode during shift-out, the test system 110 may read the value of the modified bit B on the scan-out line and add this value to the vector. In a second cycle of the shift mode during shift-out, the test system 110 may read the value of the modified bit A on the scan-out line and add this value to the vector. The resulting vector may be represented as [bit A; bit B; bit C] or [0; 0; 1]. This vector may represent a test output or a portion of a test output of the scan chain 132, e.g., a bit stream.

[0120] 3B illustrates various different operating modes 350 that an electronic device may be in. These operating modes 350 include a shift-in mode 352, a slow-speed capture mode 354, a real-speed capture mode 356, a functional mode 358, and a shift-out mode 360. Many of these operating modes, such as the shift-in mode 352, the slow-speed capture mode 354, the real-speed capture mode 356, and the shift-out mode 360, are intended for scan chain testing. In contrast, the functional mode 358 is used for normal operation of the device.

[0121] As shown, different clock signals 362 may be used in the different modes 350. These clock signals 362 may be generated by the clock controller 138. The clock controller 138 may control which of the clock signals 362 are provided to components of the electronic device for the different modes 350. For example, the clock signals 362 may represent clock signals provided by the clock controller 138 to latches of the electronic device for the different modes of the electronic device. More specifically, with respect to FIG. 2, the clock controller 138 may provide a divided clock signal for the shift-in mode 352 to latches in the scan architecture 130 of the electronic device when the electronic device is in the shift mode. However, in response to the shift mode being disabled and the functional mode being enabled, the clock controller 138 may provide a non-divided higher frequency clock signal for the capture mode to the latches.

[0122] The higher frequency clock signal may be used by the latches in functional mode 358 (e.g., when the frequency of the higher frequency clock signal is higher than the frequency of the clock signal used by the latches in the shift mode) and in at-speed capture mode 356 (e.g., when the frequency of the higher frequency clock signal is higher than the frequency of the clock signal used by the latches in the slow speed capture mode 354). In those modes, the higher frequency clock signal may be provided by clock controller 138 to the latches of the electronic device. The frequency of the clock signal provided to the latches may be the same in functional mode 358 and at-speed capture mode 356. As an example, the high frequency clock signal may be a non-divided clock signal generated by clock network 250.

[0123] In contrast, a lower frequency clock signal may be used by the latches in the shift modes (e.g., shift-in mode 352 and shift-out mode 360 ​​when the frequency of the lower frequency clock signal is lower than the frequency of the clock signal used by the latches in functional mode 358) and slow capture mode 354 (e.g., when the frequency of the lower frequency clock signal is lower than the frequency of the clock signal used by the latches in at-speed capture mode 356). In those modes, the lower frequency clock signal may be provided by clock controller 138 to the latches of the electronic device. The frequency of the clock signal provided to the latches may be the same in the shift modes and the slow capture mode 354. For example, as shown, the frequency of the clock signals shift-in mode 352, slow capture mode 354, and shift-out mode 360 ​​may each be the same as one-quarter the frequency of the clock signal used by the latches in functional mode 358.

[0124] When the electronic device is operating in functional mode 358, the electronic device is operating normally and no scan chain testing is occurring. However, functional mode pulses are used during scan chain testing to test logic elements of scan architecture 130. These pulses are provided during a capture mode, which is described in more detail below.

[0125] When the electronic device is set in the shift-in mode to begin scan chain testing, values ​​are loaded into latches of the scan architecture 130 that operate with a clock signal having a frequency that is a division of the frequency used by the latches in functional mode 358.

[0126] After the values ​​for scan chain testing are loaded into the latches, the electronic device may be placed in a capture mode. For example, the electronic device may be placed in a slow-speed capture mode 354 or a real-speed capture mode 356. In the capture mode, the latches of the electronic device are switched (e.g., scan enable is disabled) so that the data stored in the latches follows the data path 342 shown in FIG. 3A. In effect, the latches are placed in a functional mode 358 for a limited number of clock cycles to allow the data in the latches to pass through the logic elements 320a, 320b, and 320c. For example, the test system 110 may switch the latches back into the shift mode after a single pulse of one or two clock cycles.

[0127] In some embodiments, the electronic device is configured to use only one capture mode. For example, clock controller 138 may be configured to provide only the undivided clock signal to the latch when the shift mode is disabled to achieve real-speed capture mode 356. In other embodiments, the electronic device is configured to use both capture modes. For example, clock controller 138 may be configured to continue to provide the divided clock signal to the latch after the electronic device enters the slow-speed capture mode, but may instead be configured to provide the undivided clock signal to the latch when the electronic device enters the real-speed capture mode.

[0128] The capture mode used may depend on the type of test being performed by the test system 110 or on identifying the source of the error or defect. For example, if the test system 110 determines to test the electronic device 122a for defects that are not frequency or temperature dependent, the test pattern used by the test system 110 may provide for placing the electronic device 122a in a slow capture mode 354 after values ​​are loaded into the latches during the shift-in mode 352. The slower clock speed of the clock signal used during the slow capture mode 354 reduces the likelihood that an observed error is caused by the frequency or heat of the clock network 250 (e.g., because less heat is generated when components of the electronic device 122a operate at a slower clock speed).

[0129] In some implementations, both capture modes are used. For example, during testing of device 122a, test system 110 may provide a test pattern to load a first set of values ​​into the scan chain of device 122a during shift-in mode 352. Test system 110 may then provide a signal to switch device 122a to low-speed capture mode 354 before shifting values ​​out of the scan chain during shift-out mode 360. If these initial results indicate that device 122a fails testing despite low-speed capture mode 354 being used, test system 110 may (i) decide not to proceed with testing (e.g., test device 122a using at-speed capture mode 356), and / or (ii) determine that device 122a includes a frequency- or thermal-dependent defect. However, if the initial results of the tests indicate that device 122a performed as expected, test system 110 may proceed to place device 122a in at-speed capture mode 356 before placing device 122a in shift-out mode 360 ​​again (e.g., the latches may have already been loaded with new values ​​during the previous shift-out mode 360). If the new outputs then indicate that device 122a did not perform as expected, test system 110 may determine that the defect or error is temperature or frequency related.

[0130] 4 is a diagram of an exemplary scan chain 402 in a high throughput scan architecture and a timing diagram 450 of the scan chain 402 in use. The scan chain 402 includes a first family of memory components 410 and a second family of memory components 430. The memory components in the first family 410 and the second family 430 may receive a divided clock signal 454 and operate in a shift mode with the divided clock signal 454. The memory components may include flip-flops, such as master-slave flip-flops. The scan chain 402 may also include a dual edge sampling (DES) element 404 that combines the outputs of the first family 410 and the second family 430. The DES 404 may receive multiple clock signals. For example, the latching components of the DES 404 may operate on the divided clock signal 454, while the switching components of the DES 404 may operate on the undivided clock signal 452. The divided clock signal 454 may have a frequency that is half (or a further division) of the frequency of the undivided clock signal 452. Specifically, the frequency of the divided clock signal 454 may be represented by the following equation:

[0131]

number

[0132] In this formula, n can be any integer greater than 0. Scan chain 402 is shown having a 16-bit size, although various other configurations are possible. For example, scan chain 402 could alternatively have an 8-bit configuration in which first series 410 includes four flip-flops and series 430 includes an additional four flip-flops.

[0133] The first series 410 includes multiple memory elements. For example, the first series 410 may include eight flip-flops 412, 414, 416, 418, 420, 422, 424, and 426. Of these memory elements, the first series 410 may include a dedicated memory element that prevents the first series 410 and the second series 410 from storing the same bit driven by the decompressor 134. For example, the first series 410 may include a dedicated flip-flop 412 that is different from the other flip-flops 414, 416, 418, 420, 422, 424, and 426. Unlike the other flip-flops, the dedicated flip-flop 412 may be designed to allow immediate storage of any bit driven by the decompressor 134. For example, the dedicated flip-flop 412 may bypass the master components during shift mode and, unlike other flip-flops, may allow values ​​to be immediately shifted to the slave components without requiring a half-cycle delay of the divided clock signal 454. Accordingly, the dedicated flip-flop 412 may introduce a half-cycle advance in the bit shifting compared to the shifting performed in the second series 430.

[0134] The second series 430 also includes multiple memory elements. For example, the second series 430 may include eight flip-flops 432, 434, 436, 438, 440, 442, 444, and 446. Unlike the first series 410, each of the memory elements in the second series may be of the same type or design. For example, the flip-flops 432, 434, 436, 438, 440, 442, 444, and 446 may all share the same master-slave design, which is described in more detail below with respect to FIG. 5A.

[0135] The first series 410 and the second series 430 may be loaded with values ​​driven by the decompressor to begin testing of the electronic device. For example, the decompressor 134 may provide data 456 generated by the decompressor 134 to the scan chain 402 at the rate of the undivided clock signal 452. As described above, the dedicated flip-flop 412 of the first series 410 may store bit 0, as shown in data 458 captured by an even number of flops in the first series 410. The first flip-flop 432 of the second series 430 may be prevented from capturing the first bit 0 because old data is stored in the master component of the flip-flop 432 and the slave component of the flip-flop 432 is not enabled until the divided clock signal 454 goes low. However, when divided clock signal 454 goes low, the master and slave components of flip-flop 432 become active and flip-flop 432 may store the current bit in data 456 being driven by decompressor 134. As shown in data 456, the bit being driven by decompressor 134 when divided clock signal 454 goes from high to low is bit 1, and flip-flop 432 captures bit 1, as shown in data 460.

[0136] As this process continues, first series 410 is loaded with half the bits of data 456 and second series 430 is loaded with the remaining half of the bits of data 456. For example, when the loading is complete, first series 410 is loaded with data 458 and second series 430 is loaded with data 460. More specifically, when the loading is complete, flip-flop 426 stores bit 0, flip-flop 424 stores bit 2, flip-flop 422 stores bit 4, flip-flop 420 stores bit 6, flip-flop 418 stores bit 8, flip-flop 416 stores bit A, flip-flop 414 stores bit C, and flip-flop 412 stores bit E. In the second series 430, flip-flop 446 stores bit 1, flip-flop 444 stores bit 3, flip-flop 442 stores bit 5, flip-flop 440 stores bit 7, flip-flop 438 stores bit 9, flip-flop 436 stores bit B, flip-flop 434 stores bit D, and flip-flop 432 stores bit F. Once loaded, scan chain 402 is in functional mode so that a logical operation can be performed using the stored bits.

[0137] In the shift mode, the memory components in the first series 410 and the second series 430 store bits for a time equivalent to one full divided clock cycle or two undivided clock cycles before releasing them as the shifting occurs at the rate of the divided clock signal 454. This prevents the first series 410 and the second series 430 from capturing every bit of the data 456. More specifically, because the decompressor 134 provides the data 456 at a rate D of the undivided clock signal 452 and the first series 410 samples the data 456 at a rate D / 2, the first series 410 is limited to capturing only every other value in the data 456. For the same reason, the second series 430 is also limited to capturing only every other value in the data 456. Due to the sampling timing difference between the first series 410 and the second series 430, which corresponds to a half cycle of the divided clock signal 454 and a full cycle of the undivided clock signal 452, the second series 430 captures the bits that the first series 410 is prevented from capturing, and the first series captures the bits that the second series 430 is prevented from capturing, thereby capturing all bits of the data 456. As a result, the first series 410 and the second series 430 never capture the same bits driven by the decompressor 134.

[0138] When the shift mode is enabled to complete testing of the electronic device, the DES 404 may combine the outputs of the first series 410 and the second series 430 at the clock rate of the undivided clock signal 452. For example, in response to the scan enable 462 going high, the values ​​stored in the first series 410 and the series 430 may begin shifting out values ​​at a rate D / 2 of the divided clock signal 454. The DES 404 may continue combining the outputs of the first series 410 and the second series 430 at a clock rate D that is twice the clock rate of the divided clock signal 454 with the flip-flops 412, 414, 416, 418, 420, 422, 424, 426, 432, 434, 436, 438, 440, 442, 444, and 446 operating in the shift mode. By doing this, the DES 404 may generate a bitstream for the scan chain 402 that has a data rate of D when shifting values ​​out of the scan chain in shift mode.

[0139] The DES 404 may operate on an undivided clock signal 452 to switch between selecting an output from the first series 410 and an output from the second series 430. For example, when the undivided clock signal 452 is high, the DES 404 may select to provide the output of the flip-flop 426 in the first series 410. When the undivided clock signal 452 goes low, the DES 404 may switch to select the output of the flip-flop 446 in the second series 430. By doing this, the DES 404 may interleave the output of the first series 410 with the output of the second series 430. This effectively returns the bits to their original order, although the values ​​of the bits may have been modified during logical operations performed on the bits when the scan chain 402 was placed in a functional mode for device testing.

[0140] The DES 404 may be designed to account for the timing difference between the first series 410 and the second series 430. As discussed above, this timing difference may manifest as a delay of a half cycle of the divided clock signal 454 in the second series 430 compared to the first series 410. This timing difference is illustrated in the timing diagram 450 through a comparison of data captured by an even flop 458 in the first series 410 and data captured by an odd flop 460 in the second series 430. The DES 404 may account for the timing difference by introducing a delay of a half cycle of the divided clock signal 454 in the first series 410. For example, the DES 404 may include a lock-up latch component, such as a positive level sensitive lock-up latch, that introduces a half cycle hold window in the first series 410.

[0141] In some embodiments, the scan chain 402 does not include a DES 404. For example, the scan chain 402 may include a multiplexer that combines the outputs of the first series 410 and the second series 430, avoiding the need for a DES 404 by introducing a redundant half cycle into the scan shift.

[0142] 5A-5D are diagrams of various latches that may be used in the scan chains of a high throughput scan architecture.

[0143] FIG. 5A illustrates a diagram of a flip-flop latch 502 that can be used in the scan architecture 130. For example, flip-flops 414-426 and flip-flops 432-446 illustrated in FIG. 4 may share the design of flip-flop 502. Flip-flop 502 may be a master-slave flip-flop including a master component 506 and a slave component 508. Master component 506 may itself be or include a flip-flop. For example, master component 506 may be a positive level sensitive lock-up latch that introduces a half cycle hold window when the divided clock signal goes low. Slave component 508 may itself be or include a flip-flop. For example, slave component 508 may be a negative level sensitive lock-up latch that introduces a half cycle hold window when the divided clock signal goes high.

[0144] Flip-flop 502 also includes a switching component 504. Switching component 504 may be a multiplexer that switches between a functional path (data) in a functional mode and a scan path (scan) in a shift mode. The switching of switching component 504 may be controlled by an input at a scan enable (SE) node. For example, when SE is set high, switching component 504 may select the scan path, while when SE is set low, switching component 504 may select the functional path.

[0145] The flip-flop latch 502 may operate on a divided clock signal having a clock rate that is a division of the clock rate used by the decompressor 134 and compressor 136 in the scan architecture 130. In operation, the master component 506 may become active to capture a new value when the divided clock signal goes high and remain active until the clock goes high again. The master component 506 may then remain inactive until the clock goes high a third time, and the process repeats. The slave component 508 may become active to capture data from the master component 506 when the divided clock signal goes low and remain active until the clock goes low again. The slave component 508 may then remain inactive until the clock goes low a third time, and the process repeats. Thus, there is always a half cycle delay (e.g., a half cycle of the divided clock signal) between when the master component 506 becomes active and when the slave component 508 becomes active. Therefore, it takes either a half cycle of the divided clock signal, or a full cycle of the divided clock signal, to shift a new value into flip-flop latch 502 and an old value out of flip-flop latch 502 .

[0146] FIG. 5B illustrates a diagram of a dedicated flip-flop latch 510 that can be used in the scan architecture 130 at the input stage of a scan chain. For example, the flip-flop 412 illustrated in FIG. 4 can use the design of the flip-flop 510. The flip-flop 510 can be a master-slave flip-flop including a master component 514 and a slave component 516. The master component 514 itself can be or include a flip-flop. For example, the master component 514 can be a positive level sensitive lock-up latch. However, when the scan architecture 130 is set to a shift mode, the master component 514 is bypassed. The slave component 516 itself can be or include a flip-flop. For example, the slave component 516 can be a negative level sensitive lock-up latch that introduces a hold window of a half cycle when the divided clock signal goes high.

[0147] Flip-flop 510 also includes a switching component 512. Switching component 512 may be a multiplexer that switches between a functional path (data) in a functional mode and a scan path (scan) in a shift mode. The switching of switching component 512 may be controlled by an input at a scan enable (SE) node. For example, when SE is set high, switching component 512 may select the scan path, while when SE is set low, switching component 512 may select the functional path.

[0148] The flip-flop latch 510 may operate on a divided clock signal having a clock rate that is a division of the clock rate used by the decompressor 134 and compressor 136 in the scan architecture 130. During shift mode operation, the master component 514 is bypassed, allowing values ​​to be passed directly from the switching component 512 to the slave component 516. Thus, shifting a new value into the flip-flop latch 510 during shift mode requires virtually no delay.

[0149] FIG. 5C illustrates a diagram of a dedicated flip-flop latch 520 that can be used in the scan architecture 130. The flip-flop 520 can be used in the input stage of a scan chain. For example, the flip-flop 412 illustrated in FIG. 4 can use the design of the flip-flop 520. Alternatively, the flip-flop 520 can be used in a scan chain, where each flip-flop in the scan chain is or shares the design of the flip-flop 520. The flip-flop 520 can be a master-slave flip-flop including a master component 524 and a slave component 526. The master component 526 can itself be or include a flip-flop. For example, the master component 524 can be a positive level sensitive lock-up latch that introduces a hold window of a half cycle when the divided clock signal goes low. However, when the scan architecture 130 is set to a shift mode, the master component 514 can be bypassed. The slave component 516 can itself be or include a flip-flop. For example, the slave component 516 may be a negative level sensitive lock-up latch that introduces a half cycle hold window when the divided clock signal goes high.

[0150] Flip-flop 502 also includes two switching components 522a and 522b. The first switching component 522a may be a multiplexer that switches between a functional path (data) in a functional mode and a scan path (scan) in a shift mode. The switching of switching component 522a may be controlled by an input at a scan enable (SE) node. For example, when SE is set high, switching component 522a may select the scan path, while when SE is set low, switching component 522a may select the functional path.

[0151] The second switching component 522b may be a multiplexer that switches between the scan path (scan) and the output of the master component 524. The switching of the switching component 522b may be controlled by an input at a scan enable (SE) node. For example, when SE is set high, the switching component 522b may select the scan path, while when SE is set low, the switching component 522b may select the output of the master component 524.

[0152] Flip-flop latch 520 may operate with a divided clock signal having a clock rate that is a division of the clock rate used by decompressor 134 and compressor 136 in scan architecture 130. During shift mode operation, master component 514 is bypassed. However, unlike flip-flop latch 510, master component 524 of flip-flop 520 is loaded with a value from the scan path in shift mode. Bypassing master component 524 allows a value to be passed directly from switching component 522b to slave component 516. For example, in shift mode operation, bit A driven on the scan path is provided to master component 524 via switching component 522a and stored by master component 523. The same bit A is also provided to slave component 526 via switching component 522b and stored by slave component 526. Thus, shifting a new value into flip-flop latch 520 during shift mode requires virtually no delay.

[0153] 5D shows a diagram of a dual edge sampling (DES) element 530 that can be used in the scan architecture 130. For example, the DES 404 of FIG. 4 can share the design of the DES 530. The DES 530 can receive and use multiple clock signals, including a divided clock signal and a non-divided clock signal. The DES can include a latch 534 ("S") that is operated using the divided clock signal and a switching component 532 that is operated using the non-divided clock signal. The switching component 532 can be a multiplexer that switches between a first signal in-line ("SI1") and a second signal in-line ("SI2").

[0154] The DES 530 may be used to combine an output appearing on a first signal in line ("SI1") with a value appearing on a second signal in line ("SI2") to generate an output. For example, when incorporated into a scan architecture, during shift mode operation, the DES 530 may use switching component 532 to switch between a sampling output on the first signal in line and an output on the second signal in line to generate an output on the scan out line of the scan chain. The latch 534 may introduce a delay on the first signal in line, for example, to account for timing differences between the first and second signal in lines. The latch 534 may be a lock-up latch, such as a positive level sensitive lock-up latch that introduces a half cycle hold window on the first signal in line. As an example, this hold window helps align the timing of values ​​shifting through the first latch series 410 and the second latch series 430 shown in FIG. 4, taking into account a timing offset introduced by a dedicated flip-flop in the first latch series 410, such as flip-flop 510 or flip-flop 520.

[0155] The switching component 532 may operate at a higher frequency than the frequency at which new values ​​appear on the signal in line. For example, new outputs may appear on the first signal in line and the second signal in line at a rate of D / 2. However, the switching component 532 may switch between the two lines at a rate of D. This allows the DES 530 to sample the output of both lines while switching without incurring the risk of missing the output. Furthermore, the possibility of missing an output due to timing differences between the two lines is eliminated by using the latch 534. For example, the latch 534 may introduce a hold window to account for the timing differences, giving the switching component 532 additional time to sample the first signal in line.

[0156] 6A-6B are diagrams of an example scan chain 602 in a high throughput scan architecture and a timing diagram 650 of the scan chain in use.

[0157] As shown in FIG. 6A and with reference to the timing diagram of FIG. 6B, the scan chain 602 includes eight different latch series organized into four elements 610, 620, 630, and 640. Two of these elements, element 610 (base A) and element 640 (base D), operate on a first divided clock signal 660. The remaining two elements, element 620 (base B) and element 630 (base C), operate on a second divided clock signal 670 (also referred to as clock signal 680), which is a further division of the undivided clock signal. For example, the first divided clock signal 660 may have a clock rate of D / 2, which is half the rate D of the undivided clock signal 652 and the upsampling clock signal. The second divided clock signal 670 may have a clock rate of D / 4, which is a quarter of the rate D of the undivided clock signal 652. Scan chain 602 is shown having a bit size of 16 with elements 610, 620, 630, and 640 each containing four memory components, although various other configurations are possible. For example, scan chain 602 could have a bit size of 32 with elements 610, 620, 630, and 640 each containing eight memory components.

[0158] Each of the elements 610, 620, 630, and 640 includes a plurality of memory components and a lock-up latch. The memory components may be latches, such as master-slave flip-flops. The lock-up latches may be, for example, positive level sensitive lock-up latches that function transparently when the respective divided clock signal is high, thus providing a hold window when the respective divided clock signal is low. Each of the elements 610, 620, 630, and 640 also includes a first series of memory components and a second series of memory components. Individually, each of the elements 610, 620, 630, and 640 operates similarly to the scan chain 202 described in more detail above with respect to FIG. 2.

[0159] From the data 654 provided by the decompressor 134, the first series of memory components in the first element 610 may capture positionally odd bits of data. See, for example, data 662 captured by FF0 of the first element 610 and data 664 captured by FF2 of the first element 610. Thus, the first output of the first element 610 may include a bit stream having the following bits: 1, 3, 5, 7, 9, B, D, and F. However, during shift-in, bit D may stop shifting when it is loaded into memory component FF2 of the first element 610. Similarly, during shift-in, bit F may stop shifting when it is loaded into memory component FF0 of the first element 610.

[0160] From the data 654 provided by the decompressor 134, the second series of memory components in the first element 610 may capture positionally even bits of data. See, for example, data 661 captured by the lock-up latch of the first element 610, data 663 captured by FF1 of the first element 610, and data 665 captured by FF3 of the first element 610. Thus, the second output of the first element 610 may include a bit stream having the following bits: 0, 2, 4, 6, 8, A, C, and E. However, during shift-in, bit C may stop shifting when it is loaded into memory component FF3 of the first element 610. Similarly, during shift-in, bit E may stop shifting when it is loaded into memory component FF1 of the first element 610.

[0161] A first output of the first element 610, represented as data 664, is provided as input data to a signal in-line of a third element 630, which is operating at a further downsampled frequency (e.g., half the frequency at which the first element 610 is operating). A second output of the first element 610, represented as data 665, is provided as input data to a signal in-line of a second element 620, which is operating at a further downsampled frequency (e.g., half the frequency at which the first element 610 is operating). The shifting between the memory components in the second element 620 and the third element 630 is based on the second divided clock signal. Thus, the shifting between the memory components in the second element 620 and the third element 630 occurs every four cycles of the undivided clock signal. However, because elements 620 and 630 each use two latch series, there is no or substantially no delay in the shifting due to the slower shifting occurring in elements 620 and 630.

[0162] From the data 665 provided by the first element 610 to the input lines of the second element 620, a first series of memory components within the second element 620 may capture positionally odd bits of data. See, for example, data 672 captured by FF0 of the second element 620 and data 674 captured by FF2 of the second element 620. Thus, the output of the first series of the second element 620 may include a bitstream having the following bits: 2, 6, A, and E.

[0163] From the data 665 provided by the first element 610 to the input lines of the second element 620, a second series of memory components within the second element 620 may capture positionally even bits of data. See, for example, data 671 captured by the lock-up latch of the second element 620, data 673 captured by FF1 of the second element 620, and data 675 captured by FF3 of the second element 620. Thus, the output of the second series of the second element 620 may include a bit stream having the following bits: 0, 4, 8, and C.

[0164] The second element 620 may include a switching component, such as a multiplexer, that combines the output of the first series of memory components of the second element 620 with the output of the second series of memory components of the second element 620. The switching component may operate at a higher frequency than the memory components of the second element 620. For example, the switching component of the second element 620 may operate with the first divided clock signal 660 having a rate of D / 2 instead of the second divided clock signal 670 having a rate of D / 4. The output of the switching component is represented as data 676. This output is provided to a first signal in line (SI0) of the upsampler multiplexer 604.

[0165] From the data 664 provided by the first element 610 to the input lines of the third element 630, a first series of memory components within the third element 630 may capture positionally odd bits of data. See, for example, data 682 captured by FF0 of the third element 630 and data 684 captured by FF2 of the third element 630. Thus, the output of the first series of the third element 630 may include a bit stream having the following bits: 3, 7, B, and F.

[0166] From the data 664 provided by the first element 610 to the input lines of the third element 630, the second series of memory components within the third element 630 may capture positionally even bits of data. See, for example, data 681 captured by the lock-up latch of the third element 630, data 683 captured by FF1 of the third element 630, and data 685 captured by FF3 of the third element 630. Thus, the output of the second series of the third element 630 may include a bit stream having the following bits: 1, 5, 9, and D.

[0167] The third element 630 may include a switching component, such as a multiplexer, that combines the output of the first series of memory components of the third element 630 with the output of the second series of memory components of the third element 630. The switching component may operate at a higher frequency than the memory components of the third element 630. For example, the switching component of the third element 630 may operate with the first divided clock signal 660 having a rate of D / 2 instead of the second divided clock signal 670 having a rate of D / 4. The output of the switching component is represented as data 686. This output is provided to a second signal inline (SI1) of the upsampler multiplexer 604.

[0168] The upsampler multiplexer 604 is a switching component that upsamples the outputs of the third element 630 and the second element 620 to generate an input vector that is provided to the fourth element 640. For example, the multiplexer 604 may switch between sampling data 676 of the second element 620 and data 686 of the third element 630. The multiplexer 604 may operate with an undivided clock signal 652 (e.g., upsampling clock signal 656) having a clock rate D that is twice the rate at which the data 676 and data 686 are provided. By operating with an undivided clock rate D, the multiplexer may switch between and sample both the data 676 and data 686 without dropping any bits of data. The output of the multiplexer 604 is provided at an input line of the fourth element 640. The output of the multiplexer 604 is represented as upsampled input data 690.

[0169] From the data 690 provided by multiplexer 604 to the input lines of the fourth element 640, a first series of memory components of the fourth element 640 may capture positionally odd bits of data. See, for example, data 692 captured by FF0 of the fourth element 640 and data 694 captured by FF2 of the fourth element 640. Thus, the output of the first series of the fourth element 640 may include a bit stream having the following bits: 1, 3, 5, 7, and 9.

[0170] From the data 690 provided by multiplexer 604 to the input lines of the fourth element 640, the second series of memory components of the fourth element 640 may capture positionally even bits of data. See, for example, data 691 captured by the lock-up latch of the fourth element 640, data 693 captured by FF1 of the fourth element 640, and data 695 captured by FF3 of the fourth element 640. Thus, the output of the second series of the fourth element 640 may include a bit stream having the following bits: 0, 5, 4, 6, and 8.

[0171] The fourth element 640 may include a switching component, such as a multiplexer, that combines the output of the first series of memory components of the fourth element 640 with the output of the second series of memory components of the fourth element 640. The switching components may operate at a higher frequency than the memory components of the fourth element 640. For example, the switching components of the fourth element 640 may operate with a non-divided clock signal 652 having a rate of D instead of a first divided clock signal 660 having a rate of D / 2. The output of the switching components is represented as data 696. This output may be provided to the mask 218 or the compressor 136 and may be used, for example, to generate a test output.

[0172] Scan chain 602 may provide additional advantages. For example, the design of scan chain 602 may achieve further dynamic power savings by using slower shifts between memory components (e.g., shifts at a D / 4 shift rate in half of the memory components of the scan chain) without substantially increasing test time.

[0173] 7 is a flow chart of an example process 700 for using a high-throughput scan architecture. The process may be performed, at least in part, using test system 110 described herein with respect to FIG 1. Process 400 may be performed, at least in part, using the scan chain(s) of a device being tested, such as the scan chain(s) of device 120a described herein with respect to FIG 1.

[0174] Process 700 includes receiving a set of values ​​representing a particular data pattern, the data signal having a first frequency system (702). As an example, with reference to FIG. 1, the set of values ​​may represent a test pattern selected by test system 110 and provided by test system 110 at a scan-in line of scan architecture 130. The set of values ​​may include, for example, a plurality of bit streams that decompressor 134 provides as input to a plurality of scan chains 202 of scan architecture 130.

[0175] For example, the set of values ​​may include a first set of values ​​to be loaded into a first scan chain of scan architecture 130. The set of values ​​may also include a second set of values ​​to be loaded into a second scan chain of scan architecture 130, where the first set of values ​​and the second set of values ​​are different.

[0176] As noted above, the test pattern, and therefore the set of values ​​selected by test system 110, may be based on different factors. For example, with respect to FIGURE 1, the set of values ​​received at the scan-in line of electronic device 122a may be selected by test system 110 based on the model of electronic device 122a. Additionally or alternatively, test system 110 may select the set of values ​​based on other factors, such as the intended use or quality control parameters of electronic device 122a and / or the type of test being performed on electronic device 122a.

[0177] In some embodiments, the set of values ​​is obtained by test system 110. For example, with reference to Figure 1, test system 110 may access a particular test pattern from test patterns 116 in data storage device 112 for use in testing electronic device 122a.

[0178] In some embodiments, the set of values ​​is generated by test system 110. For example, with reference to FIGURE 1, test system 110 may generate a test pattern including a set of values ​​for testing electronic device 122a in response to electronic device 122a being placed in position 124 of device test queue 120.

[0179] The process 700 includes generating (704) a first data signal using at least some of the values ​​in the set of values. The first data signal may have a first frequency and may be driven at a first data rate, for example. For example, the set of values ​​may include a first set of values ​​to be loaded into a first scan chain of the scan architecture 130. A decompressor of an electronic device receiving the set of values ​​may generate the first data signal. For example, with reference to FIGS. 1-2, the decompressor 134 may generate the first data signal by driving a subset of bits obtained from the scan-in line into a first scan chain of the scan chains 202. In driving the subset of bits, the decompressor 134 may use a first clock signal from a clock controller 138 having a first clock rate. The first frequency of the first data signal may be the first clock rate.

[0180] As an example, the clock signal that the decompressor receives and uses to generate the first data signal may be at an undivided clock rate. This may mean that the clock signal received by the decompressor of the electronic device under test and the compressor of the electronic device is taken directly from a clock network of the clock controller of the device and / or is not passed through a divider of the clock controller. However, one or more other clock signals provided by the clock controller, such as clock signals provided to latches of scan chains in the scan architecture 130 of the electronic device, may be generated using dividers.

[0181] In some embodiments, the first data signal is generated in response to receiving an input that enables a shift mode. For example, with reference to Figures 2-3, decompressor 134 may begin driving bits into scan chain 202 in response to scan architecture 130 receiving an input that enables a shift mode to begin shifting bits into scan chain 202.

[0182] The process 700 includes extracting (706) alternating values ​​of at least a portion of the values ​​from the first data signal using a first latch series and a second latch series. The first latch series and the second latch series may extract the alternating values ​​at a second frequency that is a fraction of the first frequency. For example, the scan chain may be designed such that a first flip-flop of the first latch series captures positionally odd bits driven by the decompressor 134, while a second flip-flop of the second latch series captures positionally even bits driven by the decompressor 134. This may be accomplished by placing an additional component in one of the latch series, such as a lock-up latch (e.g., lock-up latch 232a shown in FIG. 2) or a dedicated latch (e.g., flip-flop 510 shown in FIG. 5B or flip-flop 520 shown in FIG. 5C).

[0183] The additional components may ensure that the first and second latch series do not capture the same bit driven by the decompressor, for example, by introducing a time difference in when the first and second latch series can load the value driven by the decompressor. For example, if a typical memory component of the scan chain 202 in the scan architecture 130, such as flip-flop 222a, requires a half cycle of time (e.g., of a divided clock signal) before it can load a new value driven by the decompressor 134, both the lock-up latch 232a and the flip-flop 510 allow the new value to be loaded substantially immediately, without requiring a half cycle of time. One half cycle of time on this divided clock signal corresponds to a full cycle of time on the undivided clock signal used by the decompressor 134. Thus, in the scan chain of the described scan architecture 130, a latch series that includes an additional component can load a first new value driven by the decompressor 134, while other latch series must wait a full cycle of the undivided clock signal before they can load a value, and can only load a value after the decompressor 134 starts driving a second new value.

[0184] Continuing the example, because the scan chain operates at a second frequency that is a fraction of the first frequency, the latch series that includes the additional component is not free to load another value until the decompressor 134 drives a third new value. Similarly, the latch series that does not include the additional component is not free to load another value until the decompressor 134 drives a fourth new value.

[0185] The process 700 includes combining the output of the first latch series with the output of the second latch series to generate a second data signal (708). For example, a switching component such as a multiplexer can be used to sample between the first and second latch series. The switching component can operate at a frequency that is a multiple of the frequency at which the latches are shifting. As an example, the multiplexer can operate at a first frequency that the decompressor of the scan architecture 130 uses to drive at least a portion of the values ​​into a scan chain that includes the first and second latch series. With the latches shifting at this lower frequency and the switching component switching and sampling at this higher frequency (e.g., twice the shift frequency of the latches), the switching component can ensure that all bits released by the first and second latch series are sampled. The switching component can alternate between the first and second latch series to interleave the output of the first latch series with the output of the second latch series.

[0186] In some embodiments, the second data signal is generated in response to receiving an input enabling the shift mode a second time. For example, with reference to FIGS. 2-3, after the decompressor 134 loads the set of bits into the memory components of the scan chain 202, the scan architecture 130 may receive an input from the test system 110 that disables the shift mode and enables the functional mode such that the bits pass through the logic components of the electronic device under test and are at least partially reloaded into the memory components of the scan chain 202. The scan chain 202 may begin shifting logically operative bits out of the memory components of the scan chain 202 in response to the scan architecture 130 receiving an input enabling the shift mode that begins shifting bits into the scan chain 202.

[0187] In addition to the above embodiments, the following embodiments are also inventive. A first embodiment of the present invention relates to an electronic device, the electronic device comprising: a clock controller providing a plurality of clock signals, the clock controller comprising a first clock signal having a first frequency and a second clock signal having a second frequency lower than the first frequency; and a decompressor configured to receive the first clock signal and provide a first data signal having a set of values, the decompressor configured to output values ​​of the first data signal at a first data rate based on the first frequency of the first clock signal; the electronic device further comprising a scan chain including two separate sets of latches provided as a first latch series and a second latch series, the first latch series and the second latch series both receiving the first data signal but outputting different values ​​from the first data signal. the first latch series and the second latch series are both configured to receive a second clock signal and capture values ​​from the first data signal at a second data rate based on a second frequency of the second clock signal; the scan chain is configured to generate the second data signal by combining an output of the first latch series with an output of the second latch series; and the electronic device further comprises a compressor configured to receive the first clock signal and obtain the second data signal from the scan chain, the compressor being configured to obtain the second data signal from the scan chain at the first data rate according to the first frequency using the first clock signal.

[0188] Example 2 is the electronic device of example 1, wherein extracting a distinct subset of the set of values ​​from the first data signal includes, for each value in the set of values, alternating which of the two series of latches captures the value.

[0189] A third embodiment is an electronic device according to any one of the first and second embodiments, wherein extracting a subset of distinct values ​​of the set of values ​​from the first data signal includes capturing, by a first latch series, every other value of the first data signal, and capturing, by a second latch series, other values ​​of the first data signal that were not captured by the second latch series.

[0190] A fourth embodiment is the electronic device according to any one of the first to third embodiments, in which generating the second data signal includes interleaving an output of the first latch series with an output of the second latch series.

[0191] Embodiment 5 is an electronic device according to any one of embodiments 1 to 4, comprising a multiplexer configured to receive an output of a first latch series, an output of a second latch series, and a first clock signal, and generating a second data signal includes controlling the multiplexer to alternately sample the output of the first latch series and the output of the second latch series at a first frequency of the first clock signal.

[0192] A sixth embodiment is an electronic device according to any one of the first to fifth embodiments, in which the scan chain includes an element in one of the latch series that introduces a timing difference between when a first latch series can capture a value from a first data signal and when a second latch series can capture a value from the first data signal.

[0193] Embodiment 7 is the electronic device as in embodiment 6, wherein the timing difference corresponds to one cycle of the first clock signal.

[0194] An eighth embodiment is the electronic device according to any one of the sixth to seventh embodiments, in which the element is a lock-up latch, and the other latches of the first and second latch series are flip-flops.

[0195] Embodiment 9 is an electronic device described in any one of embodiments 6 to 8, wherein the element is a first latch of a first latch series, such that any value captured by the first latch series is loaded into or passes through the element before any other latch of the first latch series, or the element is a first latch of a second latch series, such that any value captured by the second latch series is loaded into or passes through the element before any other latch of the second latch series.

[0196] A tenth embodiment is an electronic device according to any one of the sixth to ninth embodiments, in which the element is a first type flip-flop, and the other latches of the first latch series and the second latch series are second type flip-flops.

[0197] Example 11 is the electronic device of example 10, wherein the first type flip-flop is a master-slave flip-flop with a master bypass and the second type flip-flop is a master-slave flip-flop without a master bypass.

[0198] Embodiment 12 is an electronic device described in any one of embodiments 6 to 11, wherein the element introduces a timing offset between the first latch series and the second latch series, and the scan chain includes a second element that removes the timing offset between the first latch series and the second latch series.

[0199] Example 13 is the electronic device of example 12, wherein the element and the second element are both part of a first latch series, or the element and the second element are both part of a second latch series.

[0200] Embodiment 14 is an electronic device described in any one of embodiments 12 to 13, wherein the second element is the last latch in the first latch series, and therefore any value captured by the first latch series must pass through each of the other latches in the first latch series before reaching the second element, or the second element is the last latch in the second latch series, and therefore any value captured by the second latch series must pass through each of the other latches in the second latch series before reaching the second element.

[0201] Embodiment 15 is an electronic device according to any one of embodiments 1 to 14, wherein the second frequency is obtained by dividing the first frequency so that the second frequency is equal to the first frequency divided by a power of two that is an integer (greater than zero).

[0202] Embodiment 16 is the electronic device of embodiment 15, wherein the integer is 1 and the second frequency is half the first frequency.

[0203] Embodiment 17 is the electronic device of embodiment 15, wherein the integer is 2 and the second frequency is a quarter of the first frequency.

[0204] An eighteenth embodiment is the electronic device according to any one of the first to seventeenth embodiments, in which the clock controller includes a frequency divider that receives a first clock signal and outputs a second clock signal based on the first clock signal.

[0205] Embodiment 19 is the electronic device of embodiment 18, wherein the divider is a programmable divider configured to output a variable clock signal at a frequency determined by a program state of the programmable divider, and the second clock signal is a variable clock signal having a second frequency based on the program state of the programmable divider.

[0206] Embodiment 20 is an electronic device described in any one of embodiments 1 to 19, wherein the decompressor provides the first data signal in response to the electronic device receiving one or more inputs that enable a shift mode of the electronic device.

[0207] Embodiment 21 is an electronic device as described in embodiment 20, wherein the electronic device is configured to receive one or more second inputs that disable a shift mode of the electronic device, and the scan chain is configured to generate a second data signal in response to the electronic device receiving one or more third inputs that re-enable the shift mode of the electronic device.

[0208]

[0031] Embodiment 22 is an electronic device comprising: a clock controller providing a plurality of clock signals including a first clock signal at a first frequency, a second clock signal at a second frequency lower than the first frequency, and a third clock signal at a third frequency lower than the first frequency and the second frequency; and a decompressor receiving the first clock signal and providing a first data signal having a set of values, the decompressor being configured to output values ​​of the first data signal at a first data rate based on the first frequency of the first clock signal; The device further comprises a scan chain including four separate latch groups provided as a first latch group, a second latch group, a third latch group, and a fourth latch group, each of the four separate latch groups having a first series of latches and a second series of latches, the first series of latches and the second series of latches of the first series of latches both receiving a first data signal but capturing a different subset of values ​​from the first data signal, and receiving a second clock signal and clocking the first data signal at a second data rate based on a second frequency of the second clock signal. and capturing a value from the output of the second latch series of the first latch group at a third data rate based on a third frequency of the third clock signal, and both the first latch series and the second latch series of the second latch group are configured to receive an output of the second latch series of the first latch group and receive a third clock signal to capture a value from the output of the second latch series of the first latch group at a third data rate based on a third frequency of the third clock signal, and both the first latch series and the second latch series of the third latch group are configured to receive an output of the first latch series of the first latch group and receive a third clock signal to capture a value from the output of the second latch series of the first latch group at a third data rate based on a third frequency of the third clock signal. and capturing a value from an output of the first series of latches of the first group of latches at a third data rate based on a third frequency of the third clock signal, the first series of latches and the second series of latches of the fourth group of latches are both configured to receive a second data signal including the output of the second group of latches and the output of the third group of latches, and to receive the second clock signal and capture a value from the second data signal at a second data rate based on a second frequency of the second clock signal,and configured to generate a third data signal by combining an output of a first latch series of the fourth group of latches with an output of a second latch series of the fourth group of latches, the electronic device further comprising a compressor receiving the first clock signal and retrieving the third data signal from the scan chain, the compressor configured to retrieve the third data signal from the scan chain at a first data rate according to the first frequency using the first clock signal.

[0209] Example 23 is a method of operating an electronic device, the method including receiving a set of values ​​representing a particular data pattern and generating a first data signal using at least some of the values ​​in the set of values, the first data signal having a first frequency, the method further including extracting alternating values ​​of at least some of the values ​​from the first data signal using a first latch sequence and a second latch sequence, the first latch sequence and the second latch sequence extracting the alternating values ​​at a second frequency that is a fraction of the first frequency, and the method further including combining an output of the first latch sequence with an output of the second latch sequence to generate a second data signal, the second data signal having the first frequency.

[0210] A twenty-fourth embodiment is a system that uses the electronic device according to any one of the first to twenty-second embodiments to provide a test interface configured to receive a test pattern and output a test result.

[0211] A twenty-fifth embodiment is a test system configured to evaluate the performance and functionality of the electronic device according to any one of the first to twenty-second embodiments.

[0212] The above examples have primarily described ambient computing systems implemented as systems-on-chips with integrated processing components. However, the same techniques can also be used to implement ambient computing systems using other arrangements of the underlying computing components. For example, one or more processing components of an ambient computing system, including an ambient ML engine, can be implemented as a co-processor or in a standalone chip.

[0213] The subject matter embodiments and actions and operations described herein may be implemented in digital electronic circuitry, tangibly embodied computer software or firmware, computer hardware, including the structures disclosed herein and their structural equivalents, or one or more combinations thereof. The subject matter embodiments described herein may be implemented as one or more computer programs, i.e., one or more modules of computer program instructions, encoded on a tangible, non-transitory storage medium for execution by or control of the operation of a data processing device. Alternatively, or in addition, the program instructions may be encoded on an artificially generated propagated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, that is generated to encode information for transmission to a suitable receiving device for execution by the data processing device. The computer storage medium may be, or may be a part of, a machine-readable storage device, a machine-readable storage substrate, a random access memory device, or a serial access memory device, or a combination of one or more thereof. The computer storage medium is not a propagating signal.

[0214] A computer program (which may also be called or expressed as a program, software, software application, app, module, software module, engine, script, or code) may be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and a computer program may be deployed in any form, such as as a stand-alone program or as a module, component, engine, subroutine, or other unit suitable for execution in a computing environment, which may include one or more computers interconnected by a data communications network in one or more locations.

[0215] A computer program may, but need not, correspond to a file in a file system: a computer program may be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple associated files (e.g., files that store one or more modules, subprograms, or portions of code).

[0216] To interact with a user, embodiments of the subject matter described herein may be executed on or configured to communicate with a computer having a display device, such as an LCD (liquid crystal display) monitor, for displaying information to the user, and an input device, such as a keyboard, and a pointing device, such as a mouse, trackball, or touchpad, by which the user can provide input to the computer. Other types of devices may also be used to provide interaction with the user. For example, feedback provided to the user may be any form of sensory feedback, such as visual feedback, auditory feedback, or tactile feedback, and input from the user may be received in any form, including acoustic, spoken language, or tactile input. Additionally, the computer may interact with the user by sending documents to and receiving documents from a device used by the user. For example, the computer may interact with the user by sending a web page to a web browser on the user's device in response to a request received from the web browser, or by interacting with an app running on the user's device (e.g., a smartphone or electronic tablet). The computer may also interact with the user by sending text messages or other forms of messages to a personal device (e.g., a smart phone running a messaging application) and receiving reply messages from the user in return.

[0217] An embodiment of the subject matter described herein may be implemented in a computing system including a back-end component, e.g., a data server, or a computing system including a middleware component, e.g., an application server, or a front-end component, e.g., a computing system including a client device having a graphical user interface, web browser, or app by which a user can interact with an embodiment of the subject matter described herein, or any combination of one or more such back-end, middleware, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication, e.g., a communications network. Examples of communications networks include a local area network (LAN), a wide area network (WAN), e.g., the Internet.

[0218] A computing system may include clients and servers. Clients and servers are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and by virtue of having a client-server relationship to each other. In some embodiments, a server sends data, e.g., HTML pages, to a user device for the purpose of displaying the data to and receiving user input from a user interacting with the device functioning as a client. Data generated at the user device, e.g., results of user interaction, may be received from the device at the server.

[0219] Although the present specification contains many specific implementation details, these should not be construed as limitations on the scope of any invention or what is or may be claimed, but rather as descriptions of features that may be specific to certain embodiments of a particular invention. Certain features described in the context of separate embodiments herein may also be implemented in combination in a single embodiment. Conversely, various features of the invention described in the context of a single embodiment may also be provided in multiple embodiments separately or in any suitable subcombination. Furthermore, even if features may be described above as functioning in a particular combination and originally claimed as such, one or more features from the claimed combination may in some cases be deleted from the combination, and the claims may be directed to subcombinations or variations of the subcombinations.

[0220] Similarly, although operations are illustrated in the figures and described in the claims in a particular order, this should not be understood as requiring that such operations be performed in the particular order or sequential order shown, or that all of the operations shown be performed, to achieve desirable results. In certain situations, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the program components and systems described may generally be integrated into a single software product or packaged into multiple software products.

[0221] Specific embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims may be performed in a different order and still achieve desirable results. As an example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some cases, multitasking and parallel processing may be advantageous.

Claims

1. 1. An electronic device comprising: a clock controller for providing a plurality of clock signals including a first clock signal at a first frequency and a second clock signal at a second frequency lower than the first frequency; and a decompressor configured to receive the first clock signal and provide a first data signal having a set of values, the decompressor configured to output the values ​​of the first data signal at a first data rate based on the first frequency of the first clock signal, the electronic device further comprising: a scan chain including two separate sets of latches provided as a first series of latches and a second series of latches; the first series of latches and the second series of latches are both configured to receive the first data signal but to capture different subsets of values ​​from the first data signal; both the first series of latches and the second series of latches receive the second clock signal and capture values ​​from the first data signal at a second data rate based on the second frequency of the second clock signal; The scan chain is configured to provide a second data signal that combines an output of the first latch series with an output of the second latch series, and the electronic device further comprises: an electronic device comprising: a compressor configured to receive the first clock signal and to obtain the second data signal from the scan chain, the compressor configured to obtain the second data signal from the scan chain at the first data rate according to the first frequency using the first clock signal.

2. 13. The electronic device of any preceding claim, wherein extracting the subset of distinct values ​​of the set of values ​​from the first data signal comprises, for each value in the set of values, alternating which of the two series of latches captures the value.

3. Extracting the subset of distinct values ​​of the set of values ​​from the first data signal comprises: capturing every other value of the first data signal with the first series of latches; and capturing, by the second series of latches, other values ​​of the first data signal not captured by the second series of latches.

4. 10. The electronic device of claim 1, wherein the scan chain is configured to generate the second data signal by interleaving the output of the first series of latches with the output of the second series of latches.

5. a multiplexer configured to receive the output of the first latch series, the output of the second latch series, and the first clock signal; 13. The electronic device of any preceding claim, wherein the electronic device is configured to control the multiplexer to alternately sample the outputs of the first and second series of latches at the first frequency of the first clock signal.

6. 11. The electronic device of claim 1, wherein the scan chain includes an element in one of the latch series that introduces a timing difference between when the first latch series can capture a value from the first data signal and when the second latch series can capture a value from the first data signal.

7. The electronic device of claim 6 , wherein the timing difference corresponds to one cycle of the first clock signal.

8. 8. The electronic device of claim 6, wherein the element is a lock-up latch and the other latches of the first and second series of latches are flip-flops.

9. the element is a first latch in the first series of latches, such that any value captured by the first series of latches is loaded into or passes through the element before any other latch in the first series of latches; or 9. The electronic device of claim 6, wherein the element is a first latch of the second series of latches such that any value captured by the second series of latches is loaded into or passes through the element before any other latch of the second series of latches.

10. 10. The electronic device of claim 6, 7, or 9, wherein the element is a first type flip-flop and the other latches of the first series of latches and the second series of latches are second type flip-flops.

11. the flip-flop of the first type is a master-slave flip-flop with a master bypass; 11. The electronic device of claim 10, wherein the flip-flop of the second type is a master-slave flip-flop without a master bypass.

12. the element introduces a timing offset between the first latch series and the second latch series; 12. The electronic device of claim 6, wherein the scan chain includes a second element that removes the timing offset between the first latch series and the second latch series.

13. the element and the second element are both part of the first latch series; or The electronic device of claim 12 , wherein the element and the second element are both part of the second series of latches.

14. the second element is the last latch in the first series of latches, such that any value captured by the first series of latches must pass through each of the other latches in the first series of latches before reaching the second element; or 14. The electronic device of claim 12 or 13, wherein the second element is the last latch in the second series of latches, such that any value captured by the second series of latches must pass through each of the other latches in the second series before reaching the second element.

15. 10. The electronic device of claim 9, wherein the second frequency is a division of the first frequency such that the second frequency is equal to the first frequency divided by an integer power (greater than zero).

16. the integer is 1, 16. The electronic device of claim 15, wherein the second frequency is one-half the first frequency.

17. the integer is 2, 16. The electronic device of claim 15, wherein the second frequency is one-quarter of the first frequency.

18. 10. The electronic device of any preceding claim, wherein the clock controller includes a frequency divider that receives the first clock signal and outputs the second clock signal based on the first clock signal.

19. the frequency divider being a programmable divider configured to output a variable clock signal at a frequency determined by a programmed state of the programmable divider; 20. The electronic device of claim 18, wherein the second clock signal is a variable clock signal having the second frequency based on the programmed state of the programmable divider.

20. 10. An electronic device according to any preceding claim, wherein the decompressor provides the first data signal in response to the electronic device receiving one or more inputs enabling a shift mode of the electronic device.

21. the electronic device receiving one or more second inputs that disable the shift mode of the electronic device; 21. The electronic device of claim 20, wherein the scan chain is configured to generate the second data signal in response to the electronic device receiving one or more third inputs that re-enable the shift mode of the electronic device.

22. 1. An electronic device comprising: a clock controller that provides a plurality of clock signals including a first clock signal at a first frequency, a second clock signal at a second frequency lower than the first frequency, and a third clock signal at a third frequency lower than the first frequency and the second frequency; a decompressor configured to receive the first clock signal and provide a first data signal having a set of values, the decompressor configured to output the values ​​of the first data signal at a first data rate based on the first frequency of the first clock signal, the electronic device further comprising: a scan chain including four separate groups of latches provided as a first group of latches, a second group of latches, a third group of latches, and a fourth group of latches; each of the four separate latch groups having a first series of latches and a second series of latches; Both the first latch series and the second latch series of the first latch group are receiving the first data signal but capturing a subset of distinct values ​​from the first data signal; receiving the second clock signal and capturing values ​​from the first data signal at a second data rate based on the second frequency of the second clock signal; Both the first latch series and the second latch series of the second group of latches are receiving the output of the second series of latches of the first group of latches; receiving the third clock signal and capturing values ​​from the outputs of the second series of latches of the first group of latches at a third data rate based on the third frequency of the third clock signal; Both the first latch series and the second latch series of the third latch group receiving the output of the first series of latches of the first group of latches; receiving the third clock signal and capturing values ​​from the outputs of the first series of latches of the first group of latches at a third data rate based on the third frequency of the third clock signal; Both the first latch series and the second latch series of the fourth latch group receiving a second data signal including the outputs of the second set of latches and the outputs of the third set of latches; receiving the second clock signal and capturing values ​​from the second data signal at a second data rate based on the second frequency of the second clock signal; the scan chain is configured to generate a third data signal by combining an output of the first latch series of the fourth set of latches with an output of the second latch series of the fourth set of latches, and the electronic device further comprises: an electronic device comprising: a compressor that receives the first clock signal and obtains the third data signal from the scan chain, the compressor being configured to use the first clock signal to obtain the third data signal from the scan chain at the first data rate in accordance with the first frequency.

23. 1. A method comprising: Receiving, by an electronic device according to any one of claims 1 to 22, a set of values ​​representing a particular data pattern; generating, by the electronic device, a first data signal using at least some of the values ​​in the set of values, the first data signal having a first frequency, the method further comprising: extracting, by the electronic device, alternating values ​​of at least some of the values ​​from the first data signal using a first latch sequence and a second latch sequence, the first latch sequence and the second latch sequence extracting the alternating values ​​at a second frequency that is a fraction of the first frequency, the method further comprising: combining, by the electronic device, an output of the first latch series with an output of the second latch series to generate a second data signal, the second data signal being provided at the first frequency.

24. A system using an electronic device according to any preceding claim to provide a test interface configured to receive test patterns and output test results.

25. A test system configured to evaluate the performance and functionality of an electronic device according to any of the preceding claims.

Images