Etching profile control method using RF pulse output

Abstract

[Solution] A method for performing a plasma etch process is provided. The method begins with receiving a substrate into a chamber. A high frequency (HF) RF signal is generated, and the HFRF signal is pulsed in at least a three-state cycle including a first state, a second state, and a third state. The first state is configured at a first power level. The second state is configured at a second power level that is lower than the first power level. The third state is configured at a third power level that is lower than the second power level. The second power level of the HFRF signal is in a range of approximately 0 W to 3500 W. The HFRF signal is applied to an electrode of the chamber to perform the plasma etch process.

Description

[Technical field]

[0001] The present embodiment relates to a system and method in which a multi-state pulse output configuration overcomes the trade-off between bow CD and mask clogging typically observed in RF plasma etching of features on semiconductor wafers. [Background technology]

[0002] The plasma tool includes a radio frequency (RF) generator, a matching network, and a plasma reactor. The RF generator is coupled to the plasma reactor through the matching network. A wafer is placed in the plasma chamber and etched.

[0003] An RF generator generates an RF signal, which is fed into a matching network. The matching network reduces reflected power back to the RF generator and provides an output RF signal to a plasma reactor. The output RF signal is used to etch a wafer. However, in some cases, the output RF signal may produce process results that are different than desired.

[0004] A significant challenge for high aspect ratio etch processing is the trade-off between bow critical dimension (CD) control and capping margin. Currently, the primary mechanism used to reduce bow critical dimension (CD) is the use of more polymerizing chemistries. However, deposition from this polymerizing chemistries occurs more in the top region of high aspect ratio (HAR) structures (neck regions) than in the bow regions. This reduces neck CD more than bow CD, causing capping (clogged mask openings) before achieving the desired passivation in the bow region. In addition, deposition from polymerizing chemistries also occurs on the top of the mask, thereby worsening the mask morphology and causing premature capping to occur even with comparable neck CD. Thus, current techniques used for bow control also reduce cap margins during the process and do not meet the target. This trade-off between bow critical dimension (CD) control and cap margins limits the ability of etch processes to achieve the desired HAR feature dimensions.

[0005] The background description provided herein is intended to provide a general overview of the contents of the present disclosure. Work by the currently named inventors within the scope of what is described in this background section, as well as aspects of the description that may not otherwise be regarded as prior art at the time of filing, are not admitted, expressly or impliedly, as prior art against the present disclosure. Summary of the Invention

[0006] The embodiments of the present disclosure provide a system, apparatus, method, and computer program for multi-state pulse power configurations to improve deposition conformality during high aspect ratio etching and overcome the trade-off between bow CD and capping-neck CD. It should be appreciated that the embodiments can be implemented in numerous ways, such as a process, an apparatus, a system, a device, or a method on a computer readable medium. Several embodiments are described below.

[0007] A significant challenge for high aspect ratio etch processes is the trade-off between bow critical dimension (CD) control and capping margin. Lateral etching, which increases the bow CD, is typically prevented by sidewall passivation using chemicals that polymerize. This sidewall passivation also deposits near the top of the mask, causing necking and, in some instances, capping or clogging of the mask. Thus, the amount of sidewall passivation that can be provided is limited by the process margin for capping.

[0008] However, in accordance with embodiments of the present disclosure, the trade-off between bow CD reduction and mask capping can be overcome by the introduction of a multi-state pulse power configuration with intermediate states of high HFRF power. The intermediate pulse power state improves deposition conformality on the mask and on high aspect ratio (HAR) features. This not only reduces deposition in the neck region but also increases deposition in the bottom region, thereby resulting in bow protection with a larger neck CD (and correspondingly smaller bow CD) compared to passivation using conventional process control knobs.

[0009] In addition, the high density of neutrals in the intermediate pulse states reduces the irregularities at the top of the mask, leading to improved mask morphology, which further reduces the likelihood of capping with multi-state pulsing compared to not using multi-state pulsing, even with comparable neck CDs.

[0010] In some embodiments, a method of performing a plasma etch process is provided, comprising receiving a substrate in a chamber and generating a high frequency (HF) RF signal, the HFRF signal being pulsed in a three-state cycle including a first state, a second state, and a third state. The first state is configured at a first power level. The second state is configured at a second power level that is lower than the first power level. The third state is configured at a third power level that is lower than the second power level. The second power level of the HFRF signal is in a range of approximately 0 to 3500 W. The HFRF signal is applied to an electrode of the chamber to perform the plasma etch process.

[0011] In some embodiments, the duty cycle of the second state is in the range of approximately 0% to 90%.

[0012] In some embodiments, the third power level is substantially zero, or approximately zero.

[0013] In some embodiments, the plasma etch process is configured to etch a high aspect ratio (HAR) feature on a substrate, and a second state of the HFRF signal is configured to reduce bowing of a sidewall of the HAR feature and further configured to reduce deposition of passivation in a neck region of the HAR feature.

[0014] In some embodiments, the method further includes generating a low frequency (LF) RF signal, the LF RF signal being pulsed in a multi-state cycle including at least a first state, a second state, and a third state of the LF RF signal.

[0015] In some embodiments, a first state of the LFRF signal is configured at a fourth power level. A second state of the LFRF signal is configured at a fifth power level that is lower than the fourth power level. A third state of the LFRF signal is configured at a sixth power level that is lower than the fifth power level. The fifth power level is in the range of 0-6000 W. The LFRF signal is applied to an electrode of the chamber.

[0016] In some embodiments, the LFRF signal is configured to control the deposition of a passivation on a mask layer of the substrate.

[0017] In some embodiments, a system for performing a plasma etch process is provided, comprising a chamber configured to receive a substrate for processing, and a high frequency generator for generating a high frequency (HF) RF signal, the HFRF signal being pulsed in a three-state cycle including a first state, a second state, and a third state. The first state is configured at a first power level. The second state is configured at a second power level that is lower than the first power level. The third state is configured at a third power level that is lower than the second power level. The second power level is in a range of about 0 to 3500 W. The HFRF signal is applied to an electrode of the chamber to perform the plasma etch process.

[0018] In some embodiments, a non-transitory computer readable medium having program instructions embodied thereon is provided that, when executed by at least one processor, causes the at least one processor to perform a method of performing a plasma etch process. The method includes receiving a substrate into a chamber and generating a high frequency (HF) RF signal, the HFRF signal being pulsed in a three-state cycle including a first state, a second state, and a third state. The first state is configured at a first power level. The second state is configured at a second power level that is lower than the first power level. The third state is configured at a third power level that is lower than the second power level. The second power level of the HFRF signal is in a range of about 0 to 3500 W. The HFRF signal is applied to an electrode of the chamber to perform the plasma etch process.

[0019] Other aspects will become apparent from the following detailed description when taken in conjunction with the accompanying drawings. [Brief description of the drawings]

[0020] The present embodiments may be best understood by reference to the following description taken in conjunction with the accompanying drawings.

[0021] [Figure 1] FIG. 1 is a diagram of an embodiment of a system 100 for performing an etching process in accordance with an embodiment of the present disclosure.

[0022] [Figure 2A] FIG. 2A is a graph conceptually illustrating the phases of a three-state RF pulse output configuration in accordance with an embodiment of the present disclosure.

[0023] [Figure 2B] FIG. 2B is a graph conceptually illustrating the phases of a three-state RF pulse output configuration in accordance with an embodiment of the present disclosure.

[0024] [Figure 3A]FIG. 3A conceptually illustrates cross-sectional views of etched features that have undergone different etching processes according to an embodiment of the present disclosure. [Figure 3B] FIG. 3B conceptually illustrates cross-sectional views of etched features that have undergone different etching processes according to embodiments of the present disclosure. [Figure 3C] FIG. 3C conceptually illustrates cross-sectional views of etched features that have undergone different etching processes according to embodiments of the present disclosure.

[0025] [Figure 4A] FIG. 4A is a graph showing pulse output time of a low frequency (LF) RF signal (eg, 400 kHz) versus low frequency RF power according to an embodiment of the present disclosure.

[0026] [Figure 4B] FIG. 4B is a graph illustrating LFRF power versus pulse output time of an LFRF signal in accordance with an embodiment of the present disclosure.

[0027] [Figure 5A] FIG. 5A is a conceptual top view schematic diagram of a substrate surface illustrating the effect of LFRF power in controlling mask shape, according to an embodiment of the present disclosure. [Figure 5B] FIG. 5B is a conceptual top view schematic diagram of a substrate surface illustrating the effect of LFRF power in controlling mask shape, according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] The following embodiments describe systems and methods for which a multi-state pulse output configuration improves deposition conformality during high aspect ratio etching and overcomes the trade-off between bow CD and capping-neck CD. It will be apparent that the embodiments may be practiced without some or all of these specific details. In other instances, well-known operations have not been described in detail so as not to unnecessarily obscure the embodiments.

[0029] Multi-state pulse power with high HFRF power in the third state addresses the trade-off between bow critical dimension (CD) control and capping margin in two ways. First, it improves the conformality of the deposition in the HAR structure, resulting in less deposition in the neck region and more deposition in the bow region. Not only does it perform faster bow passivation, but it also reduces neck CD loss. Thus, more passivation can be achieved before capping occurs. Second, the neutral species generated during the high HFRF power state cleans the top of the mask, leading to improved mask morphology, thereby further increasing the capping margin. This translates to less / no capping for comparable neck CDs in a process with intermediate states of high HFRF power than would otherwise be achievable, due to better mask morphology.

[0030] The degree of passivation can be controlled by controlling the intermediate state of HFRF power. To further reduce the bow CD, the HFRF power of the intermediate state can be increased. Alternatively, the duration of the intermediate state can also be increased by increasing the pulse width, thereby increasing passivation. By using these two knobs in combination, the desired passivation can be achieved.

[0031] A major advantage of the disclosed multi-state pulsed power configuration is overcoming the trade-off between bow CD and neck CD-capping. Intermediate states of HFRF power lead to more conformal deposition on the HAR structures, which is otherwise very difficult to control in HAR etch processes. This reduces deposition in the neck region but increases deposition in the bow region. As a result, better bow protection is achievable without causing capping, compared to conventional chemistry tuning knobs.

[0032] A second advantage is that while the multi-state pulse output configuration improves bow, it also cleans the top of the mask, thereby improving mask morphology. This improved mask morphology reduces the risk of capping, even for comparable or smaller neck CDs.

[0033] FIG. 1 is a diagram of an embodiment of a system 100 for performing an etching process in accordance with an embodiment of the present disclosure.

[0034] The system 100 includes a high frequency (HF) RF generator, a low frequency (LF) RF generator, a matcher 104, a plasma chamber 106, and a host computer 108. Examples of LFRF generators include RF generators having a low operating frequency of 100 kilohertz (kHz), or 400 kHz, or 1 megahertz (MHz), or 2 MHz. Examples of HFRF generators include RF generators having a high operating frequency of 2 MHz, 13.56 MHz, 27 MHz, 60 MHz, or 120 MHz. Further examples include HFRF generators having a higher operating frequency than the LFRF generator. The LFRF generator is an example of a first generator, and the HFRF generator is an example of a second RF generator.

[0035] In this specification, the matching box 104 may be referred to as an impedance matching circuit or an impedance matching network. As an example, the matching box 104 includes a network of circuit components coupled to each other. Examples of the circuit components include resistors, inductors, or capacitors.

[0036] Examples of the host computer 108 include a desktop computer, a laptop computer, a tablet, a smartphone, and a controller. The host computer 108 includes a processor 112 and a memory device 114. For example, the processor 112 can be a central processing unit (CPU), a combination of a CPU and a graphics processing unit (GPU), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a programmable logic device (PLD), or a microcontroller. Examples of the memory device 114 include a read only memory (ROM) and a random access memory (RAM). The processor 112 is coupled to the memory device 114.

[0037] The plasma chamber 106 includes a substrate support 116, such as an electrostatic chuck (ESC). The plasma chamber 106 further includes an upper electrode 118 located above the substrate support 116, forming a gap 120 between the upper electrode 118 and the substrate support 116. A lower electrode embedded in the substrate support 116 is made of a metal, such as aluminum or an alloy of aluminum. The substrate support 116 is made of a metal and a ceramic, such as aluminum oxide (Al2O3). The upper electrode 118 is made of a metal and is coupled to a reference electric potential, such as a ground potential or a negative potential. An example of the plasma chamber 106 is a capacitively coupled plasma (CCP) chamber.

[0038] As used herein, an example of a substrate S includes a semiconductor wafer having multiple layers. For example, the substrate includes multiple layers forming an integrated circuit, such as an ASIC or PLD. The processor 112 is coupled to the LFRF generator, the HFRF generator, and the electron microscope 110.

[0039] An output O1 of the LFRF generator is coupled to an input I1 of the matching box 104 via an RF cable RFC1. Furthermore, an output OM of the matching box 104 is coupled to a bottom electrode of the substrate support 116 via an RF transmission line RFT. An example of the RF transmission line RFT is an RF cable surrounded by an RF sheath, with an insulator between the RF cable and the RF sheath.

[0040] The plasma chamber 106 includes a sidewall 122, a top wall 124, and a bottom wall 126. The sidewall 122 is located between the top wall 124 and the bottom wall 126. The sidewall 122 is attached to the top wall 124 and the bottom wall 126. A slot 129 extends through the sidewall 122.

[0041] The processor 114 generates a recipe signal 128 and transmits the recipe signal 128 to the LFRF generator. The recipe signal 128 includes LF recipe information such as the number of states of a parameter of the RF signal 130 generated by the LFRF generator, the parameter level for each state of the RF signal 130, the duty cycle of each state, and the frequency of the RF signal 130. Similarly, the processor 114 generates a recipe signal 132 and transmits the recipe signal 132 to the HFRF generator. The recipe signal 132 includes the number of states of a parameter of the RF signal 102 generated by the HFRF generator, the parameter level for each state of the RF signal 102, the duty cycle of each state, and the frequency of the RF signal 102.

[0042] After receiving recipe signal 128, the LFRF generator generates an RF signal 130 based on the parameter levels for the number of states received in recipe signal 128. For example, in some embodiments, RF signal 130 has three states, each of the three states having a corresponding parameter level from the parameter levels received in recipe signal 128. RF signal 130 also has a frequency received in recipe signal 128. Furthermore, after receiving recipe signal 132, the HFRF generator generates an RF signal 134 having a parameter level for the number of states received in recipe signal 132. For example, in some embodiments, RF signal 134 has three states, each of the three states having a corresponding parameter level from the parameter levels received in recipe signal 132. RF signal 134 also has a frequency received in recipe signal 132.

[0043] The RF signal 130 is sent from the output O1 via the RF cable RFC1 and the input I1 to the matching box 104. Additionally, the RF signal 134 is sent from the output O2 to the matching box 104 via the RF cable RFC2 and the input I2.

[0044] The matching network 104 receives the RF signals 130 and 134 and matches the impedance of the load coupled to the output OM with the impedance of the source coupled to the inputs I1 and I2. The impedance matching modifies the impedance of the RF signals 130 and 134, and a modified RF signal 136 is output at the output OM. Examples of loads include the RF transmission line RFT and the plasma chamber 106. Examples of sources coupled to the inputs I1 and I2 include an LFRF generator, an RF cable RFC1, an HFRF generator, and an RF cable RFC2. The modified RF signal 136 is sent from the output OM via the RF transmission line RFT to the bottom electrode of the substrate support 116.

[0045] In addition to the modified RF signal 136, one or more process gases are provided to the gap 120 in the plasma chamber 106 to strike or sustain a plasma in the gap 120 to process the substrate S. Examples of processing the substrate S include depositing material on the substrate S, etching a layer of the substrate S, cleaning the substrate S, and sputtering the substrate S. Examples of the one or more process gases include oxygen-containing gases, fluorine-containing gases, and combinations thereof. Illustratively, the one or more process gases include carbon and hydrogen, such as CHF3. In some implementations, the one or more process gases include H2, CF4, NF3, CH2F2, SF6, and / or CH3F. As another example, if the amount of carbon and hydrogen is reduced, hydrogen gas or nitrogen trifluoride (NF3) gas can be used as the one or more process gases.

[0046] Immediately after processing the substrate for a predetermined period of time, such as 15 or 20 minutes, the substrate S may be removed from the plasma chamber 106 through the slot 129. By way of example, in some implementations, processing of the substrate S may take approximately one hour to complete.

[0047] 2A is a graph conceptually illustrating phases of a three-state RF pulse output configuration in accordance with an embodiment of the present disclosure. In the graph shown, RF power versus time is plotted, and two cycles of a pulsed output high frequency (HF) RF signal are shown. In some embodiments, the pulsed output HFRF signal is a pulsed output HFRF signal of an RF signal generated by a high frequency RF generator at a frequency in the range of approximately 2 to 100 MHz (e.g., 2 MHz, 13.56 MHz, 27.12 MHz, 40.68 MHz, 60 MHz, etc.). In other embodiments, the pulsed output RF signal is a pulsed output RF signal of an RF signal of another frequency used in an etching process.

[0048] 2A, each RF pulse output cycle consists of at least three distinct states. State S1 is a high power state having an RF power level P1 and a duty cycle DC1. State S2 is a medium power state having an RF power level P2 and a duty cycle DC2. State S0 is a low power state having an RF power level P0 and a duty cycle DC0. The illustrated three-state pulse output RF cycle is in contrast to a two-state pulse output RF signal that employs only the high power state S1 and the low power state S0. However, in accordance with an embodiment of the present disclosure, the introduction of the medium power state S2 described herein provides a significant benefit in overcoming the trade-off relationship between bow CD and capping margin.

[0049] The three-state pulsed output RF signal is tuned at least in part by tuning parameters including HFRF power and pulse width of state S2. As an illustrative example only, the S1 power may be 1000W and the S2 power may be 100W.

[0050] As just one example to illustrate the principle, if the S1 duty cycle is 33% of the total pulse width of the RF pulse cycle, then the S2 duty cycle can be 33% of the pulse width, plus the remaining 34% of the pulse width can be in state S0 in the three-state pulse output cycle.

[0051] The specific duty cycles of states S1, S2, and S0 can vary depending on the specific tuning of the pulsed RF signal for a given etch process, but typically S1 is the shortest duty cycle. The duty cycle of S2 can be longer or shorter than the duty cycle of S1 depending on the process and the desired results. The duty cycle of S0 is typically the longest duty cycle, but in some cases may not be the longest duty cycle if the duty cycle of S2 is very long. Generally, in some embodiments, the duty cycle of S2 is tuned for a given process, the duty cycle of S1 is fixed, and the duty cycle of S0 is the remainder after tuning the duty cycle of S2. In other words, in some embodiments, an increase in the duty cycle of S2 results in a corresponding and equivalent decrease in the duty cycle of S0, but does not affect the duty cycle of S1.

[0052] In some embodiments, the high frequency (HF) RF power in state S2 is in the range of about 0 to 3500 W. In some embodiments, the HF RF power in state S2 is in the range of about 1000 W to 3500 W. In some embodiments, the HF RF power in state S2 is in the range of about 1000 W to 2000 W.

[0053] In some embodiments, the pulse width (duty cycle) of state S2 is in the range of about 0 to 90% (of the total duration of one pulse output cycle). In some embodiments, the pulse width of state S2 is in the range of about 20% to 90%. In some embodiments, the pulse width of state S2 is in the range of about 30% to 70%.

[0054] FIG. 2B is a graph conceptually illustrating the phases of a three-state RF pulse output configuration in accordance with an embodiment of the present disclosure. In the graph shown, RF power versus time is plotted, and two cycles of the pulse output RF signal are shown. The RF pulse cycle is similar to that of FIG. 2A, except that in the embodiment of FIG. 2B, state S0 immediately follows state S1, and state S2 immediately follows state S0 in the RF pulse cycle. In contrast, in the embodiment of FIG. 2A, states S2 and S0 are swapped, with S2 immediately following S1 and S0 immediately following S2.

[0055] 3A, 3B, and 3C conceptually illustrate cross-sectional views of etched features that have undergone different etching processes according to embodiments of the present disclosure.

[0056] FIG. 3A conceptually illustrates a cross-sectional view of an etched feature 300 from a conventional high aspect ratio (HAR) etch process. In a typical HAR etch process, a combination of etchants and passivants is utilized. However, as the etch proceeds deeper into the HAR feature, bowing of the sidewalls 302 in the feature 300 tends to develop because ion scattering becomes more pronounced in the deeper feature. This results in some etching of the sidewalls, which adversely affects the directionality (anisotropy) of the etch process, causing a profile that increases the bowing and bow CD. High bow CD can cause device failure due to shorting.

[0057] FIG. 3B illustrates a conceptual cross-sectional view of an etched feature 300 by a HAR etch process with chemistry tuning applied for bow control. To combat the problem of high bow CD as described above, a passivation chemistry is applied, which creates a deposit of passivation 306 (e.g., polymer) along the sidewalls of the feature, thus protecting the feature from bowing. However, such passivation chemistry also deposits on the top of the mask layer 308, which tends to deposit more passivation 304 in the top / neck region of the feature. This reduces the neck CD, creating a risk of capping the feature if the deposition in the neck region clogs or completely closes the hole. Thus, any attempt to reduce bowing of the feature profile is traded off against the possibility of capping the feature. The risk of capping limits the amount of passivation chemistry that can be applied to improve the bow profile.

[0058] 3C illustrates a conceptual cross-sectional view of an etched feature 300 with a HAR etch process using chemistry tuning and the three-state RF pulse power described above applied for bow control in accordance with an embodiment of the present disclosure. As shown, the use of multi-state pulse power including HFRF power and pulse width allows for a more conformal deposition of passivation chemistry. As before, passivation 306 is deposited along the sidewalls to reduce the bow CD, but it also reduces the deposition of passivation 304 in the neck / top of the feature 300, opening up the neck CD and improving the capping margin. Thus, reducing the bow CD while improving the capping margin overcomes the typical trade-off relationship.

[0059] Without being bound to any particular theory of operation, it is believed that the various states S1, S2, and S0 provide different activities that combine to overcome the trade-off between bow control and capping margin in HAR etching. State S1 is a high power state that provides high energy ions, which results in high aspect ratio etching at the etch front. The high energy ions travel vertically and travel very deep due to their high energy. However, these high energy ions also remove passivation from the top of the film. Therefore, S1 is not desirable for the entire RF cycle.

[0060] State S0 is a very low power state (e.g., in some embodiments, 0 or approximately 0 power, in some embodiments, less than a few hundred watts, in some embodiments, less than 500 W, in some embodiments, less than 1000 W, etc.) that allows deposition reactions to occur. While the etch reactions are very fast, the deposition reactions are often slower, and thus S0 provides enough time for deposition species to attach to the sidewalls of the features being etched. However, there is a problem with more deposition at lower aspect ratios (shallower depths), thereby causing capping and reducing the amount of high energy ions that can penetrate and etch in the next step.

[0061] State S2 provides higher power than S0, but not high enough to cause removal of passivation from the mid-stack. S2 provides enough power to remove deposited species from the low AR regions, but not enough power to remove passivation from the mid-hole regions. S2 provides high HFRF power to generate a sufficient amount of neutral species and ions to remove unwanted deposition on top of the mask that causes capping. This therefore improves the capping margin while also providing passivation along the sidewalls of the feature in deeper regions.

[0062] In some etch processes, a pulsed HFRF signal as described above is applied alone. However, in other etch processes, a pulsed low frequency (LF) RF signal is also provided. For example, in some embodiments, an etch process is configured to utilize a pulsed HFRF signal alone, while in other embodiments, such an etch process is configured to utilize both a pulsed HFRF signal as well as a pulsed LFRF signal.

[0063] 4A is a graph showing low frequency RF power versus pulse output time of a low frequency (LF) RF signal (e.g., 400 kHz) according to an embodiment of the present disclosure. In some embodiments, the pulse output LFRF signal is generated by an LFRF generator as described above.

[0064] 4A, each LFRF pulse cycle is composed of three distinct states that are synchronized in time with and have the same duty cycles as the three states of the HFRF signal described above. State S1 of the LFRF signal is a high power state that has the same duty cycle DC1 as S1 of the HFRF signal. State S2 of the LFRF signal is a medium power state that has the same duty cycle DC2 as S2 of the HFRF signal. State S0 of the LFRF signal is a low power state (in some implementations, zero power) that has the same duty cycle DC0 as S0 of the HFRF signal.

[0065] The three-state pulsed output LFRF signal is tuned at least in part by tuning parameters including LFRF power. As an illustrative example only, if the S1 power is 1000W, the S2 power may be 500W.

[0066] In some embodiments, the LFRF power is in the range of about 0 to 20,000 W. In some embodiments, the LFRF power is in the range of about 4,000 W to 16,000 W. In some embodiments, the LFRF power is in the range of about 6,000 W to 12,000 W.

[0067] The addition of low frequency power to a multi-state pulsed output configuration can provide control of mask shape for a particular process. A further extension of this trend is the provision of bow control that helps overcome the trade-off between bow CD and capping / neck CD.

[0068] Some processes do not require LFRF power at S2. In such an embodiment, the LFRF power is set to zero. FIG. 4B is a graph showing the pulse output time of the LFRF signal versus LFRF power, according to an embodiment of the present disclosure. As shown in the graph, the LFRF power is set to zero, resulting in state S0 for the LF being essentially extended to include the duty cycle of state S2 described above. This produces a two-state pulsed output LFRF signal as shown, where S1 of the LFRF signal is synchronized with S1 of the HFRF signal, and S0 of the LFRF signal is synchronized with the combined duty cycle of the S2 and S0 states of the HFRF signal.

[0069] 5A and 5B are conceptual top view schematic diagrams of a substrate surface illustrating the effect of LFRF power in controlling mask shape, according to an embodiment of the present disclosure.

[0070] FIG. 5A shows a top view 500 of a portion of a substrate after an etching process without LFRF power. While the original hole shape is circular, as shown, the shape of the etched holes 502 after the etching process is inconsistent and often non-circular. Some holes are elongated along a given axis and the hole sizes are inconsistent. This can be attributed to uncontrolled deposition on the mask caused by heavily polymerizing chemicals applied for passivation purposes. The uncontrolled deposition causes distortion of the holes and loses their circularity. Non-uniform and non-circular holes cause inconsistent sidewall profiles in the etch features and exacerbate bow CD due to ion deflection effects.

[0071] 5B illustrates a top view 510 of a portion of a substrate after an etching process using LFRF power. As shown, the shape of the hole 512 is improved, both in terms of uniformity and maintaining circular shape. Thus, application of the power of the LFRF signal controls unwanted deposition.

[0072] In some implementations, as previously discussed, LFRF power is not required and is therefore set to zero, resulting in a two-state LFRF signal. However, in other process configurations, LFRF power is applied to control deposition on the mask and improve hole shape and consistency.

[0073] It will be appreciated that during the tuning process, the HFRF power, the S2 duty cycle, and possibly the LFRF power are adjusted and tuned to appropriate values ​​for a given process. The RF power and S2 duty cycle of the HFRF signal, and optionally the LFRF power (for the S2 state of the LFRF signal), provide knobs that can be applied to simultaneously achieve bow reduction and necking reduction, overcoming this typical trade-off relationship. Such multi-state pulse output allows for more conformal deposition along the sidewalls, reducing the bow CD while at the same time providing less deposition on the top of the mask to improve capping margins.

[0074] In some embodiments, the above-mentioned HFRF power, duty cycle, and LFRF power parameters are adjustable through a user interface provided through a computer or controller. The computer or controller may be an example of the host computer 108 of FIG. 1. In some embodiments, such a user interface provides fields for inputting values ​​for these parameters and / or selectable icons that allow incremental adjustment of the values, or other types of interface mechanisms for parameter setting. In some embodiments, predefined values ​​and / or predefined ranges for the HFRF power, duty cycle, and / or LFRF power parameters are provided through the user interface. In some embodiments, such predefined values ​​or ranges are generated automatically in response to the selection or input of other process settings, such as the type of process and whether or not it includes an LFRF signal. In some embodiments, the predefined values ​​are provided as default values ​​that can be tuned or adjusted as desired by the user.

[0075] The embodiments described herein may be practiced with a variety of computer system configurations, including handheld hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, etc. The embodiments may also be practiced in distributed computing environments where tasks are performed by remote processing hardware units that are linked through a network.

[0076] In some embodiments, the controller may be part of a system, which may be part of the examples described above. Such systems include semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems are integrated with electronics to control the operation of the electronics before, during, and after processing of semiconductor wafers or substrates. The electronics are referred to as "controllers" that may control various parts or sub-parts of one or more systems. The controllers may be programmed to control any of the processes disclosed herein depending on the processing requirements and / or type of system. Such processes include delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow settings, fluid delivery settings, position and motion settings, wafer transfer to and from the tool, and other transfer tools and / or load locks connected or coupled to the system.

[0077] In general, in various embodiments, a controller is defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable end-point measurements, etc. Integrated circuits include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as ASICs, PLDs, and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions are instructions communicated to the controller in the form of various individual settings (or program files) that define parameters, factors, variables, etc. for performing a particular process on or for a semiconductor wafer or for a system. In some embodiments, the program instructions may be part of a recipe defined by a process engineer to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon oxides, surfaces, circuits, and / or dies of a wafer.

[0078] In some embodiments, the controller may be part of or coupled to a computer that is integrated into, coupled to, or otherwise networked to the system, or a combination thereof. For example, the controller may be in the "cloud" or may be all or part of a fab host computer system, thereby allowing remote access of wafer processing. The computer allows remote access to the system to monitor the current progress of a fabrication operation, review the history of past fabrication operations, review trends or performance metrics from multiple fabrication operations, modify parameters of a current process, set up processing steps following a current process, or initiate a new process.

[0079] In some embodiments, a remote computer (e.g., a server) provides the process recipe to the system over a network, including a local network or the Internet. The remote computer includes a user interface that allows for input or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data that identify parameters, factors, and / or variables for each processing step performed during one or more operations. It should be understood that the parameters, factors, and / or variables are specific to the type of process being performed and the type of tool the controller is configured to couple to or control. Thus, as described above, a controller is distributed, such as by including one or more separate controllers that are networked together and work toward a common purpose, such as the processes and controls described herein. Examples of controllers distributed for such purposes include one or more integrated circuits on a chamber that are remotely located (e.g., at the platform level or as part of a remote computer) and communicate with one or more integrated circuits that cooperatively control the processes on the chamber.

[0080] In various embodiments, examples of systems to which the methods may be applied include, but are not limited to, a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing system associated with or used in the fabrication and / or manufacturing of semiconductor wafers.

[0081] It is further noted that in some embodiments, the above operations apply to several types of plasma chambers, such as plasma chambers including inductively coupled plasma (ICP) reactors, transformer coupled plasma chambers, conductor tools, dielectric tools, plasma chambers including electron cyclotron resonance (ECR) reactors, etc. For example, one or more RF generators are coupled to an inductor in an ICP reactor. Examples of inductor shapes include a solenoid, a dome coil, a flat coil, etc.

[0082] As described above, depending on the process step or steps being performed by the tool, the host computer communicates with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used for material transport to and from containers of wafers to and from tool locations and / or load ports within the semiconductor manufacturing factory.

[0083] With the above embodiments in mind, it should be understood that some of the embodiments employ various computer-implemented operations involving data stored in computer systems. These operations are operations that physically manipulate physical quantities. Any of the operations that form part of the embodiments described herein are useful machine operations.

[0084] Some of the embodiments also relate to hardware units or apparatus for performing these operations, where the apparatus is specially constructed for a special purpose computer. When defined as a special purpose computer, the computer is operable for its special purpose while performing other processes, program execution or routines that are not part of its special purpose.

[0085] In some embodiments, the operations may be processed by a computer selectively activated or configured by one or more computer programs stored in a computer memory, cache, or obtained over a computer network. If data is obtained over a computer network, the data may be processed by other computers on the computer network, e.g., a cloud of computing resources.

[0086] Also, one or more embodiments may be fabricated as computer readable code on a non-transitory computer readable medium. The non-transitory computer readable medium is any data storage hardware unit, such as a memory device, that stores data, which is then read by a computer system. Examples of non-transitory computer readable media include hard drives, network attached storage (NAS), ROM, RAM, compact disk ROMs (CD-ROMs), CD recordables (CD-Rs), CD rewriteables (CD-RWs), magnetic tapes, and other optical and non-optical data storage hardware units. In some embodiments, the non-transitory computer readable medium includes computer readable tangible media distributed over network-coupled computer systems such that the computer readable code is stored and executed in a distributed manner.

[0087] Although the method operations above have been described in a particular order, it should be understood that in various embodiments, other housekeeping operations are performed between each operation, or each method operation is coordinated to occur at slightly different times, or distributed across a system that allows each method operation to occur at various intervals, or performed in an order different than that described above.

[0088] It should further be noted that in one embodiment, one or more features of any embodiment described above may be combined with one or more features of any other embodiment also described above without departing from the scope as described in the various embodiments described in this disclosure.

[0089] Although the foregoing embodiments have been described in some detail for clarity of understanding, it will be apparent that certain changes and modifications can be practiced within the scope of the appended claims. Thus, the present embodiments should be considered as illustrative rather than restrictive, and the embodiments should not be limited to the details provided herein.

Claims

1. 1. A method of performing a plasma etching process, comprising: Receiving a substrate within a chamber; generating a high frequency (HF) RF signal, the HF RF signal being pulsed in a three-state cycle including a first state, a second state, and a third state; Including, the first state is configured to a first power level; the second state is configured to a second power level that is lower than the first power level; the third state is configured to a third power level that is lower than the second power level; the second power level of the HF RF signal is in a range of approximately 0 to 3500 W; The method wherein the HF RF signal is applied to an electrode of the chamber to perform the plasma etch process.

2. 2. The method of claim 1 , A method wherein a duty cycle of the second state of the HFRF signal is within a range of approximately 0% to 90%.

3. 2. The method of claim 1 , The method, wherein the third power level is substantially zero, or approximately zero.

4. 2. The method of claim 1 , The method, wherein the plasma etch process is configured to etch a high aspect ratio (HAR) feature on a substrate, and the second state of the HFRF signal is configured to reduce bowing of a sidewall of the HAR feature and is further configured to reduce deposition of passivation in a neck region of the HAR feature.

5. 2. The method of claim 1 , 11. The method of claim 10, further comprising generating a low frequency (LF) RF signal, the LF RF signal being pulsed in a multi-state cycle including at least a first state, a second state, and a third state of the LF RF signal.

6. 6. The method of claim 5, the first state of the LFRF signal is configured to a fourth power level; the second state of the LFRF signal is configured to a fifth power level lower than the fourth power level; the third state of the LFRF signal is configured to a sixth power level lower than the fifth power level; the fifth power level is in the range of approximately 0 to 20,000 W; The method wherein the LFRF signal is applied to the electrodes of the chamber.

7. 7. The method of claim 6, The method, wherein the LFRF signal is configured to control deposition of a passivation on a mask layer of a substrate.

8. 1. A system for performing a plasma etch process, comprising: a chamber configured to receive the substrate for processing; a high frequency generator for generating a high frequency (HF) RF signal, the HF RF signal being pulsed in a three-state cycle including a first state, a second state, and a third state; Including, the first state is configured to a first power level; the second state is configured to a second power level that is lower than the first power level; the third state is configured to a third power level that is lower than the second power level; the second power level is within a range of approximately 0 W to 3500 W; The HF RF signal is applied to an electrode of the chamber to perform the plasma etch process.

9. 9. The system of claim 8, The system, wherein the duty cycle of the second state is within a range of approximately 0% to 90%.

10. 9. The system of claim 8, The third power level is substantially zero, or approximately zero.

11. 9. The system of claim 8, The system, wherein the plasma etch process is configured to etch a high aspect ratio (HAR) feature on a substrate, and the second state of the HFRF signal is configured to reduce bowing of a sidewall of the HAR feature and is further configured to reduce deposition of passivation in a neck region of the HAR feature.

12. 9. The system of claim 8, The system further includes a low frequency generator that generates a low frequency (LF) RF signal, the LF RF signal being pulsed in a three-state cycle including a first state, a second state, and a third state of the LF RF signal.

13. 13. The system of claim 12, the first state of the LFRF signal is configured to a fourth power level; the second state of the LFRF signal is configured to a fifth power level lower than the fourth power level; the third state of the LFRF signal is configured to a sixth power level lower than the fifth power level; the fifth power level is in the range of approximately 0 to 20,000 W; The LFRF signal is applied to the electrodes of the chamber.

14. 14. The system of claim 13, The system, wherein the LFRF signal is configured to control deposition of a passivation on a mask layer of a substrate.

15. 1. A non-transitory computer readable medium having program instructions embodied thereon that, when executed by at least one processor, causes the at least one processor to perform a method for performing a plasma etch process, the method comprising: Receiving a substrate within a chamber; generating a high frequency (HF) RF signal, the HF RF signal being pulsed in a three-state cycle including a first state, a second state, and a third state; Including, the first state is configured to a first power level; the second state is configured to a second power level that is lower than the first power level; the third state is configured to a third power level that is lower than the second power level; the second power level of the HF RF signal is in a range of approximately 0 to 3500 W; The HFRF signal is applied to an electrode of the chamber to perform the plasma etch process.

16. 16. The non-transitory computer readable medium of claim 15, A duty cycle of the second state is within a range of approximately 0 to 90%.

17. 16. The non-transitory computer readable medium of claim 15, The third power level is a substantially zero power level.

18. 16. The non-transitory computer readable medium of claim 15, The non-transitory computer-readable medium, wherein the plasma etch process is configured to etch a high aspect ratio (HAR) feature on a substrate, and the second state of the HFRF signal is configured to reduce bowing of a sidewall of the HAR feature and is further configured to reduce deposition of passivation in a neck region of the HAR feature.

19. 16. The non-transitory computer readable medium of claim 15, The method comprises:

11. The non-transitory computer-readable medium, further comprising generating a low frequency (LF) RF signal, the LF RF signal being pulsed in a three-state cycle including a first state, a second state, and a third state of the LF RF signal.

20. 20. The non-transitory computer readable medium of claim 19, the first state of the LFRF signal is configured to a fourth power level; the second state of the LFRF signal is configured to a fifth power level lower than the fourth power level; the third state of the LFRF signal is configured to a sixth power level lower than the fifth power level; the fifth power level of the LFRF signal is in a range of approximately 0 to 20,000 W; The LFRF signal is applied to the electrodes of the chamber.

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