Semiconductor Package

Abstract

A semiconductor package according to an embodiment includes an insulating layer and an electrode portion arranged on the insulating layer, the electrode portion including a plurality of pads and traces connecting the plurality of pads, the plurality of pads including a first pad including a curved portion having a particular radius of curvature around its top surface and a straight portion connected to the curved portion, and a second pad including no straight portion around its top surface opposite the curved portion of the first pad.

Description

[Technical field]

[0001] The embodiment relates to a semiconductor package. [Background technology]

[0002] As the performance of electric / electronic products continues to improve, technologies for attaching more packages to a board with a limited size are being proposed and researched. However, since a typical package is based on mounting one semiconductor chip, there is a limit to achieving the desired performance.

[0003] Recently, semiconductor packages have been provided in which multiple semiconductor elements are arranged on multiple substrates. Such semiconductor packages have a structure in which multiple semiconductor elements are connected to each other horizontally and / or vertically on a substrate. As a result, the semiconductor packages have the advantages of efficiently using the mounting area of ​​the semiconductor elements and transmitting high-speed signals through short signal transmission paths between the semiconductor elements.

[0004] Due to these advantages, the above-mentioned semiconductor packages are widely used in mobile devices and the like.

[0005] In addition, semiconductor packages applied to products providing the Internet of Things (IOT), autonomous vehicles, and high-performance servers are becoming more highly integrated, and the number of semiconductor elements and / or the size of each semiconductor element is increasing, or the functional parts of the semiconductor element are being divided, expanding the concept to semiconductor chiplets.

[0006] This makes intercommunication between semiconductor devices and / or semiconductor chiplets important, and thus there is a trend to place an interposer between a substrate of a semiconductor package and the semiconductor device.

[0007] The interposer functions as a redistribution layer that gradually increases the width or extent of a circuit pattern from the semiconductor device toward the semiconductor package in order to facilitate intercommunication between semiconductor devices and / or semiconductor chiplets or to interconnect the semiconductor device and a semiconductor package substrate, thereby enabling smooth transmission of electrical signals between the semiconductor device and a semiconductor package substrate having a circuit pattern that is relatively larger than the circuit pattern of the semiconductor device.

[0008] The interposer may have an area equal to or larger than the total area of ​​the semiconductor devices and / or semiconductor chiplets in order to mount the semiconductor devices and / or semiconductor chiplets as a whole, or may be disposed only in a portion for interconnecting the semiconductor devices and / or semiconductor chiplets. That is, the area of ​​the interposer may or may not increase as the number of the semiconductor devices and / or semiconductor chiplets increases. However, as the number of the semiconductor devices and / or semiconductor chiplets increases, the area of ​​the substrate of the semiconductor package tends to increase.

[0009] Meanwhile, the number of terminals on semiconductor elements is gradually increasing due to the recent developments in 5G, Internet of Things (IOT), improved image quality, and increased communication speeds, which is leading to an increase in the number of mounting pads on a board.

[0010] However, while the number of terminals of the semiconductor element and the number of mounting pads provided on the substrate are increasing, the surface area of ​​the substrate is limited, which means that it is not possible to arrange all of the mounting pads connected to the terminals of the semiconductor element within the limited space. Therefore, conventional semiconductor packages have the problem that the circuit integration is reduced and the signal transmission characteristics are degraded due to the increase in the length of the traces connecting the multiple mounting pads. Technical Problem

[0011] The embodiments provide a circuit board having a new structure and a semiconductor package including the same.

[0012] The embodiments also provide a circuit board on which a plurality of processor chips can be mounted side-by-side, and a semiconductor package including the circuit board.

[0013] Further, the embodiments provide a circuit board having a modified shape of a pad to be connected to a semiconductor element, and a semiconductor package including the same.

[0014] Furthermore, the embodiments provide a circuit board capable of improving the electrical and / or physical reliability of a die bridge connecting a plurality of semiconductor elements, and a semiconductor package including the same.

[0015] In the proposed embodiments, the technical problems to be solved are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by a person having ordinary skill in the art to which the proposed embodiments pertain from the following description.

[0016] A semiconductor package according to an embodiment includes an insulating layer and an electrode portion arranged on the insulating layer, the electrode portion including a plurality of pads and traces connecting the plurality of pads, the plurality of pads including a first pad including a curved portion having a particular radius of curvature around its top surface and a straight portion connected to the curved portion, and a second pad including no straight portion around its top surface opposite the curved portion of the first pad.

[0017] The first pad also includes a width in a second direction parallel to the linear portion and a width in a first direction perpendicular to the second direction, the width in the first direction being smaller than the width in the second direction.

[0018] Furthermore, the width from the center of the radius of curvature of the first pad in the -first direction is smaller than each of the widths from the center of the radius of curvature of the first pad in the +first direction, the -second direction, and the +second direction.

[0019] Moreover, the widths from the center of the radius of curvature of the first pad in the +first direction, the -second direction, and the +second direction are the same.

[0020] Moreover, the width of the first pad in the first direction satisfies the range of 80% to 95% of the width of the first pad in the second direction.

[0021] Moreover, the width in the first direction is in the range of 16 μm to 76 μm, and the width in the second direction is in the range of 20 μm to 80 μm.

[0022] Moreover, the line width of the trace satisfies the range of 1 μm to 6 μm, and the interval between the pad and the trace or the interval between a plurality of traces satisfies the range of 1 μm to 6 μm.

[0023] Also, the straight portion of the first pad is parallel to the extending direction of the trace connected to the second pad.

[0024] Additionally, the first and second pads are spaced apart from one another in the first direction, and the trace extends in the second direction between the first and second pads.

[0025] At least two traces are disposed between the first pad and the second pad, extending in the second direction and spaced apart from each other in the first direction.

[0026] Furthermore, two traces are disposed between the first pad and the second pad, and the pitch between the first pad and the second pad satisfies the range of 25 μm to 110 μm.

[0027] Furthermore, two traces are disposed between the first pad and the second pad, and the distance between the first pad and the second pad is in the range of 5 μm to 30 μm.

[0028] Moreover, the straight portion of the first pad is disposed adjacent to the trace, and the curved portion of the second pad faces the straight portion of the first pad across the trace.

[0029] The electrode portion further includes a dummy electrode electrically isolated from the pad and the trace.

[0030] The semiconductor package also includes a first connection portion arranged on a first electrode portion of the electrode portion, a second connection portion arranged on a second electrode portion of the electrode portion, a first semiconductor element arranged on the first connection portion, and a second semiconductor element arranged on the second connection portion, and the trace connects between the first electrode portion connected to the first chip and the second electrode portion connected to the second chip.

[0031] Moreover, the first chip is a central processor (CPU), and the second chip is a graphics processor (GPU).

[0032] Moreover, the electrode portion includes a third electrode portion, and the semiconductor package further includes a third connection portion arranged on the third electrode portion and a third semiconductor element arranged on the third connection portion, and the third semiconductor element includes a memory chip.

[0033] The distance between the first and second semiconductor elements is in the range of 60 μm to 150 μm. [Effects of the invention]

[0034] The circuit board of the embodiment includes an electrode portion connected to a semiconductor element. The electrode portion includes a pad and a trace. In this case, the pad has a shape in which a region adjacent to the trace is cut out in a circle having a specific radius of curvature. For example, the periphery of the upper surface of the pad includes a curved portion having a specific radius of curvature and a straight portion connected to the curved portion. The straight portion can be said to be a first portion around the upper surface of the pad, and the curved portion can be said to be a second portion around the pad. The first portion is disposed adjacent to the trace. The extension direction of the straight line of the first portion can be the same direction as or parallel to the extension direction of the trace. Thus, the embodiment can secure a placement space for a plurality of traces between a plurality of pads spaced apart in a first direction D1 through changing the periphery shape of the upper surface of the pad. Thus, the embodiment can form a stable trace between a plurality of pads spaced apart in the first direction D1, thereby improving the physical and electrical reliability of the circuit board.

[0035] Meanwhile, the pads of the embodiment are divided into a plurality of groups. For example, the pads include a first group of pads and a second group of pads. In this case, the first group of pads is provided in a relatively dense area, and thus has a shape in which an area adjacent to the trace is cut off in a circle having the specific radius of curvature. In contrast, the second group of pads is provided in a relatively sparse area, and thus has a circular shape having a planar area larger than that of the first group of pads. This allows the embodiment to stably mount a semiconductor device, and thus allows the semiconductor device to stably operate.

[0036] Also, the circuit board of the embodiment includes a first substrate layer and a second substrate layer. The second substrate layer includes a PID, and can include a fine pattern of line widths and intervals corresponding to a plurality of different semiconductor elements mounted on the circuit board. As a result, the embodiment can mount a plurality of different semiconductor elements on one circuit board, and can easily connect the plurality of semiconductor elements within a limited space. Therefore, the embodiment can separate the plurality of semiconductor elements according to their functions, thereby improving the performance of the application processor. Furthermore, the embodiment can reduce the volume of the semiconductor package by easily connecting the plurality of semiconductor elements within a limited space, thereby slimming down the electronic device.

[0037] In addition, the embodiment may minimize the distance between the first and second semiconductor elements disposed on the circuit board, thereby minimizing loss of signals transmitted between the first and second semiconductor elements and thereby improving product reliability.

[0038] Furthermore, in the embodiment, a plurality of semiconductor elements can be mounted side by side on one substrate, and thus the thickness of the semiconductor package can be significantly reduced compared to the comparative example.

[0039] Furthermore, the embodiment does not require the connection of multiple circuit boards to connect multiple semiconductor elements, which improves process convenience and reliability of electrical connection. [Brief description of the drawings]

[0040] [Figure 1] FIG. 2 is a diagram showing a circuit board according to the first embodiment. [Diagram 2] FIG. 11 is a diagram showing a circuit board according to a second embodiment. [Diagram 3] FIG. 2 is an enlarged view of a first substrate layer of the circuit board according to the embodiment. [Figure 4]FIG. 2 is a diagram specifically illustrating the layer structure of a first circuit pattern layer that constitutes a first substrate layer of the circuit board of the embodiment. [Diagram 5] FIG. 4 is an enlarged view of a second substrate layer of the circuit board according to the embodiment. [Figure 6] FIG. 2 is a diagram specifically illustrating the layer structure of a second circuit pattern layer constituting a second substrate layer in the embodiment. [Figure 7] FIG. 2 is a plan view of an electrode portion according to an embodiment. [Figure 8] FIG. 11 is a diagram for comparing the pad shapes of the electrode portions of the comparative example and the embodiment. [Figure 9] 11A and 11B are diagrams for explaining problems caused by the pad shape of the electrode portion in the comparative example. [Figure 10] FIG. 8 is an enlarged view of an area of ​​FIG. [Figure 11] 2A to 2C are diagrams for explaining the process sequence of the circuit board in FIG. [Figure 12] 2A to 2C are diagrams for explaining the process sequence of the circuit board in FIG. [Figure 13] 2A to 2C are diagrams for explaining the process sequence of the circuit board in FIG. [Figure 14] 2A to 2C are diagrams for explaining the process sequence of the circuit board in FIG. [Figure 15] 2A to 2C are diagrams for explaining the process sequence of the circuit board in FIG. [Figure 16] 2A to 2C are diagrams for explaining the process sequence of the circuit board in FIG. [Figure 17] 2A to 2C are diagrams for explaining the process sequence of the circuit board in FIG. [Figure 18] 2A to 2C are diagrams for explaining the process sequence of the circuit board in FIG. [Figure 19] 2A to 2C are diagrams for explaining the process sequence of the circuit board in FIG. [Figure 20] 2A to 2C are diagrams for explaining the process sequence of the circuit board in FIG. [Figure 21] 2A to 2C are diagrams for explaining the process sequence of the circuit board in FIG. [Figure 22] 2A to 2C are diagrams for explaining the process sequence of the circuit board in FIG. [Figure 23]2A to 2C are diagrams for explaining the process sequence of the circuit board in FIG. [Figure 24] 2A to 2C are diagrams for explaining the process sequence of the circuit board in FIG. [Diagram 25] 2A to 2C are diagrams for explaining the process sequence of the circuit board in FIG. [Figure 26] 2A to 2C are diagrams for explaining the process sequence of the circuit board in FIG. [Figure 27] 2A to 2C are diagrams for explaining the process sequence of the circuit board in FIG. [Figure 28] 2A to 2C are diagrams for explaining the process sequence of the circuit board in FIG. [Figure 29] 2A to 2C are diagrams for explaining the process sequence of the circuit board in FIG. [Diagram 30] 2A to 2C are diagrams for explaining the process sequence of the circuit board in FIG. [Diagram 31] FIG. 1 is a diagram showing a semiconductor package according to a first embodiment. [Diagram 32] FIG. 11 is a diagram showing a circuit board according to a second embodiment. [Diagram 33] FIG. 13 is a diagram showing a semiconductor package according to a second embodiment. BEST MODE FOR CARRYING OUT THE INVENT

[0041] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0042] However, the technical concept of the present invention is not limited to the embodiments described, but may be embodied in various different forms, and one or more of the components of the embodiments may be selectively combined or substituted within the scope of the technical concept of the present invention.

[0043] In addition, the terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as meanings that may be commonly understood by a person having ordinary knowledge in the technical field to which the present invention belongs, unless otherwise clearly defined and described, and commonly used terms such as terms defined in a dictionary may be interpreted in consideration of the contextual meaning of the related art. In addition, the terms used in the embodiments of the present invention are intended to explain the embodiments, and are not intended to limit the present invention.

[0044] In this specification, unless otherwise specified in the phrase, the singular form can include the plural form, and when it is described as "A and (and) at least one (or more) of B and C," it can include one or more of all possible combinations of A, B, and C. In addition, terms such as first, second, A, B, (a), (b), etc. can be used to describe components of the embodiments of the present invention.

[0045] Such terms are used merely to distinguish a component from other components, and do not limit the nature, order, or sequence of the components. Furthermore, when a component is described as being "coupled," "coupled," or "connected" to another component, it includes not only the case where the component is directly coupled, coupled, or connected to the other component, but also the case where the component is "coupled," "coupled," or "connected" by another component between the other component and the component.

[0046] In addition, when described as being formed or located "above or below" each component, "above" or "below" includes not only the case where two components are in direct contact with each other, but also the case where one or more other components are formed or located between the two components. In addition, when described as "above or below," it can include not only the upper direction based on one component, but also the lower direction.

[0047] -Electronic Devices-

[0048] Prior to describing the embodiment, an electronic device including a semiconductor package of the embodiment will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiment. Various chips may be mounted in the semiconductor package. Mainly, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory, application processor chips such as a central processor (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller, and logic chips such as an analog-to-digital converter and an application-specific IC (ASIC), etc. may be mounted in the semiconductor package.

[0049] Furthermore, the embodiment makes it possible to mount at least two semiconductor elements of different types on one substrate while reducing the thickness of a semiconductor package connected to a main board of an electronic device.

[0050] In this case, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, etc. However, the electronic device is not limited to these, and may be any other electronic device that processes data.

[0051] Working Example

[0052] Hereinafter, a circuit board and a package substrate including the circuit board according to the embodiment will be specifically described.

[0053] FIG. 1 is a diagram showing a circuit board according to a first embodiment, FIG. 2 is a diagram showing a circuit board according to a second embodiment, FIG. 3 is an enlarged view of a first substrate layer of the circuit board of the embodiment, FIG. 4 is a diagram specifically showing the layer structure of a first circuit pattern layer constituting the first substrate layer of the circuit board of the embodiment, FIG. 5 is an enlarged view of a second substrate layer of the circuit board of the embodiment, and FIG. 6 is a diagram specifically showing the layer structure of a second circuit pattern layer constituting the second substrate layer of the embodiment.

[0054] In the following, general features of a circuit board 300 according to an embodiment will be described with reference to FIGS.

[0055] 1 to 6, a circuit board 300 includes multiple substrate layers.

[0056] The circuit board 300 is adapted to mount at least two different semiconductor elements.

[0057] The circuit board 300 includes electrodes electrically connected to at least two semiconductor elements.

[0058] The electrode unit includes a plurality of pads respectively connected to at least two semiconductor elements and a trace electrically connecting the plurality of pads. The electrode unit including the plurality of pads and the trace may be referred to as a die bridge.

[0059] The circuit board 300 includes a first substrate layer 100 and a second substrate layer 200 .

[0060] The first substrate layer 100 may have a multi-layer structure. For example, the first substrate layer 100 may have at least a two-layer structure. For example, the first substrate layer 100 includes at least two insulating layers. The first substrate layer 100 may be one side of a circuit board that is connected to a main board of an electronic device.

[0061] The second substrate layer 200 is disposed on the first substrate layer 100 .

[0062] For example, the second substrate layer 200 may be the other side of the circuit board that is connected to the semiconductor device.

[0063] The second substrate layer 200 may have a multi-layer structure, but is not limited thereto. Exemplarily, the second substrate layer 200 may include at least two insulating layers. The second substrate layer 200 provides an area on which at least two semiconductor elements are mounted.

[0064] The first substrate layer 100 includes a number of insulating layers.

[0065] By way of example, the first substrate layer 100 may include, but is not limited to, a 1-1 insulating layer 111, a 1-2 insulating layer 112, and a 1-3 insulating layer 113.

[0066] The 1-1 insulating layer 111, the 1-2 insulating layer 112, and the 1-3 insulating layer 113 may each include the same insulating material, but are not limited to this.

[0067] Exemplarily, the 1-1 insulating layer 111, the 1-2 insulating layer 112, and the 1-3 insulating layer 113 may each include the same first insulating material as each other. For example, the 1-1 insulating layer 111, the 1-2 insulating layer 112, and the 1-3 insulating layer 113 may be made of a prepreg.

[0068] Each of the 1-1 insulating layer 111, the 1-2 insulating layer 112, and the 1-3 insulating layer 113 may have a thickness in the range of 10 μm to 30 μm. For example, each of the 1-1 insulating layer 111, the 1-2 insulating layer 112, and the 1-3 insulating layer 113 may have a thickness in the range of 15 μm to 25 μm. For example, each of the 1-1 insulating layer 111, the 1-2 insulating layer 112, and the 1-3 insulating layer 113 may have a thickness in the range of 18 μm to 23 μm. Here, the thickness of the insulating layer may refer to the vertical distance between circuit pattern layers arranged on different layers.

[0069] The first substrate layer 100 includes a first circuit pattern layer 120 .

[0070] At this time, the circuit pattern layer 120 of the first substrate layer 100 may have an ETS (Embedded Trace Substrate) structure. For example, the circuit pattern layer disposed on the uppermost side of the first substrate layer 100 may have a structure embedded in the insulating layer of the first substrate layer 100.

[0071] Exemplarily, the first substrate layer 100 includes a 1-1 circuit pattern layer 121 embedded in an upper surface of a 1-1 insulating layer 111. The 1-1 circuit pattern layer 121 may have an ETS structure. For example, the upper surface of the 1-1 circuit pattern layer 121 may be flush with the upper surface of the 1-1 insulating layer 111. The side and lower surfaces of the 1-1 circuit pattern layer 121 may be covered with the 1-1 insulating layer 111.

[0072] That is, the 1-1 circuit pattern layer 121 is the circuit pattern layer that is disposed vertically most adjacent to the second substrate layer 200 among the first circuit pattern layers 120 disposed on the first substrate layer 100. The 1-1 circuit pattern layer 121 has an ETS structure. That is, the 1-1 circuit pattern layer 121 is manufactured through the ETS method, and thus can be embedded in the 1-1 insulating layer 111.

[0073] Such an ETS structure allows the circuit pattern layer to be finer than a circuit pattern layer having a structure in which the circuit pattern layer protrudes onto the insulating layer.

[0074] As a result, the embodiment can minimize the line width or spacing difference between the second circuit pattern layer 220 disposed on the second substrate layer 200 and the first circuit pattern layer 120. That is, the second circuit pattern layer 220 of the second substrate layer 200 has a width and spacing corresponding to the width and spacing of terminals of a semiconductor element, as described below.

[0075] At this time, if the difference in line width between the second circuit pattern layer 220 and the 1-1 circuit pattern layer 121 (specifically, the line width of the trace of the second circuit pattern layer and the line width of the trace of the 1-1 circuit pattern layer) is large, the signal transmission loss due to the difference in width increases, and thus the signal transmission characteristics may be deteriorated. Therefore, in the embodiment, the 1-1 circuit pattern layer 121 has an ETS structure, thereby minimizing the difference in line width and / or space between the 1-1 circuit pattern layer 121 and the second circuit pattern layer 220. As a result, the embodiment can minimize the signal transmission loss that may occur due to the difference in line width and / or space between the second circuit pattern layer and the 1-1 circuit pattern layer 121. Furthermore, the embodiment further minimizes the difference in line width and / or space between the first circuit pattern layer and the second circuit pattern layer through the change in the layer-by-layer line width and / or space of the second circuit pattern layer 220 described later.

[0076] The first substrate layer 100 includes a 1-2 circuit pattern layer 122 disposed on the lower surface of the 1-1 insulating layer 111. The 1-2 circuit pattern layer 122 protrudes downward from the lower surface of the 1-1 insulating layer 111. The side surfaces and lower surface of the 1-2 circuit pattern layer 122 are covered with the 1-2 insulating layer 112.

[0077] The first substrate layer 100 includes a 1-3 circuit pattern layer 123 disposed on the lower surface of the 1-2 insulating layer 112. The 1-3 circuit pattern layer 123 protrudes downward from the lower surface of the 1-2 insulating layer 112. The side surfaces and lower surface of the 1-3 circuit pattern layer 123 are covered with the 1-3 insulating layer 113.

[0078] The first substrate layer 100 includes a 1-4 circuit pattern layer 124 disposed on the lower surface of the 1-3 insulating layer 113. The 1-4 circuit pattern layer 124 protrudes downward from the lower surface of the 1-3 insulating layer 113.

[0079] The first circuit pattern layer 120 including the 1-1 circuit pattern layer 121, the 1-2 circuit pattern layer 122, the 1-3 circuit pattern layer 123, and the 1-4 circuit pattern layer 124 may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Also, the first circuit pattern layer 120 may be formed of a paste or solder paste containing at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) having excellent bonding strength. Preferably, the first circuit pattern layer 120 may be formed of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

[0080] The first circuit pattern layer 120, including the 1-1 circuit pattern layer 121, the 1-2 circuit pattern layer 122, the 1-3 circuit pattern layer 123, and the 1-4 circuit pattern layer 124, includes pads and traces. The pads may include through electrode pads connected to the through electrodes, and core pads or BGA pads on which a connection part (described later) connected to a main board of an electronic device is disposed. The traces may refer to wiring in the form of a long line that is connected to the pads and transmits an electric signal. The pads (e.g., through electrode pads) of the first circuit pattern layer 120 may have a width in the range of 20 μm to 90 μm. The pads of the first circuit pattern layer 120 may have a width in the range of 22 μm to 85 μm. The pads of the first circuit pattern layer 120 may have a width in the range of 25 μm to 80 μm. For example, the first substrate layer 100 includes first through electrodes disposed in each insulating layer. At this time, the first insulating layer 110 is formed of a prepreg including reinforcing fibers. Thus, the first through electrode in the first insulating layer 110 has a size of at least 15 μm or more. Therefore, the pad of the first circuit pattern layer 120 can have a width larger than the width of the first through electrode in order to connect to the first through electrode.

[0081] The line width of the traces of the first circuit pattern layer 120 can be in the range of 6 μm to 20 μm. For example, the line width of the traces of the first circuit pattern layer 120 can be in the range of 7 μm to 15 μm. For example, the line width of the traces of the first circuit pattern layer 120 can be in the range of 8 μm to 12 μm. In addition, the spacing between the traces of the first circuit pattern layer 120 can be in the range of 6 μm to 20 μm. For example, the spacing between the traces of the first circuit pattern layer 120 can be in the range of 7 μm to 15 μm. For example, the spacing between the traces of the first circuit pattern layer 120 can be in the range of 8 μm to 12 μm.

[0082] The first substrate layer 100 also includes a first through electrode 130 disposed in the first insulating layer 110. The first through electrode 130 may be formed to penetrate one first insulating layer, or alternatively, may be formed to commonly penetrate at least two first insulating layers.

[0083] The first through electrode 130 includes a 1-1 through electrode 131 that penetrates the 1-1 insulating layer 111. The first through electrode 130 includes a 1-2 through electrode 132 that penetrates the 1-2 insulating layer 112. The first through electrode 130 includes a 1-3 through electrode 133 that penetrates the 1-3 insulating layer 113.

[0084] The 1-1 through electrode 131, the 1-2 through electrode 132, and the 1-3 through electrode 133 may have the same shape. For example, the 1-1 through electrode 131, the 1-2 through electrode 132, and the 1-3 through electrode 133 may have a trapezoidal shape with a different width at the top and a different width at the bottom. Preferably, the 1-1 through electrode 131, the 1-2 through electrode 132, and the 1-3 through electrode 133 may each have a smaller width at the top than at the bottom.

[0085] The width of each of the 1-1 through electrode 131, the 1-2 through electrode 132, and the 1-3 through electrode 133 may be in the range of 15 μm to 70 μm. The width of each of the 1-1 through electrode 131, the 1-2 through electrode 132, and the 1-3 through electrode 133 may be in the range of 18 μm to 65 μm. The width of each of the 1-1 through electrode 131, the 1-2 through electrode 132, and the 1-3 through electrode 133 may be in the range of 20 μm to 60 μm. The width of each of the 1-1 through electrode 131, the 1-2 through electrode 132, and the 1-3 through electrode 133 may refer to the width of a portion having a relatively large width among the upper surface and the lower surface of each of the 1-1 through electrode 131, the 1-2 through electrode 131 electrode 132, and the 1-3 through electrode 133.

[0086] The first circuit pattern layer 120 and the first through electrode 130 have a plurality of layer structures. However, in the embodiment, one of the first circuit pattern layers 120 has an ETS structure, and thus the circuit pattern layer of the ETS structure can have a layer structure different from the other circuit pattern layers.

[0087] For example, the 1-1 circuit pattern layer 121 can have a layer structure different from that of the 1-2 circuit pattern layer 122 and the 1-3 circuit pattern layer 123. For example, the number of layers of the 1-1 circuit pattern layer 121 can be different from the number of layers of each of the 1-2 circuit pattern layer 122 and the 1-3 circuit pattern layer 123. For example, the number of layers of the 1-1 circuit pattern layer 121 may be less than the number of layers of each of the 1-2 circuit pattern layer 122 and the 1-3 circuit pattern layer 123.

[0088] As an example, the 1-1 circuit pattern layer 121 may include only the second metal layer (e.g., electrolytic plating layer). In contrast, the 1-2 circuit pattern layer 122 may include a first metal layer 122-1 (e.g., seed layer) and a second metal layer 122-2 (e.g., electrolytic plating layer). Also, the 1-3 circuit pattern layer 123 may include a first metal layer 123-1 and a second metal layer 123-2. This is because the seed layer of the 1-1 circuit pattern layer 121 is finally removed in the manufacturing process of the circuit board.

[0089] The 1-1 through electrode 131 includes a first metal layer 131-1 and a second metal layer 131-2 corresponding to the 1-2 circuit pattern layer 122. In addition, the 1-2 through electrode 132 includes a first metal layer 132-1 and a second metal layer 132-2 corresponding to the 1-3 circuit pattern layer 123.

[0090] The first substrate layer 100 includes a protective layer 140. The protective layer 140 can protect the insulating layer and the circuit pattern layer disposed on the outermost side of the first substrate layer 100. For example, the protective layer 140 can be disposed on the lower surface of the 1-3 insulating layer 113. The protective layer 140 can include an opening (not shown) that exposes at least a portion of the lower surface of the 1-4 circuit pattern layer 124 disposed on the lower surface of the 1-3 insulating layer 113.

[0091] As a result, the lower part of the first substrate layer 100 includes a protective area PP covered by the protective layer 140 and an open area OP exposed through the opening of the protective layer 140. At least a portion of the lower surface of the 1-4th circuit pattern layer 124 may be exposed to the outside of the substrate through the open area OP.

[0092] In addition, the upper portion of the first substrate layer 100 may include a first bonding region or a first lamination region AR1. That is, a second insulating layer constituting the second substrate layer 200 may be laminated or bonded to the upper portion of the first substrate layer 100.

[0093] At this time, the first substrate layer 100 includes an insulating layer including a reinforcing member (e.g., glass fiber) so as to impart rigidity to the circuit board 300. The first substrate layer 100 can transmit signals transmitted from the second substrate layer 200 to the main board of the electronic device. As a result, the first substrate layer 100 can have a standard corresponding to the specifications (e.g., the number of pads, the spacing between pads, etc.) of the main board of the electronic device.

[0094] Meanwhile, the second substrate layer 200 is disposed on the first substrate layer 100. The multiple insulating layers of the second substrate layer 200 may be stacked on the 1-1 insulating layer 111 of the first substrate layer 100 in sequence.

[0095] In one embodiment, the second substrate layer 200 may be, but is not limited to, a re-distribution layer (RDL). The second substrate layer 200 provides a device mounting area on which a plurality of semiconductor devices are mounted.

[0096] The second substrate layer 200 transmits signals transmitted from the first substrate layer 100 to at least two semiconductor devices. In addition, the second substrate layer 200 may transmit signals acquired or processed in the at least two semiconductor devices to the first substrate layer 100.

[0097] The second substrate layer 200 is provided in a plurality of layers, and each of the plurality of layers of the second substrate layer 200 may have a different wiring structure. Here, the wiring structure may include the line width of the circuit pattern layer, the interval between the circuit patterns, the width of the through electrodes, etc.

[0098] The lower part of the second substrate layer 200 includes a second stacked region AR2 stacked on the first stacked region AR1. The upper part of the second substrate layer 200 includes an element mounting region where a plurality of semiconductor elements are mounted. For example, the upper part of the second substrate layer 200 includes an element mounting region R1 where the semiconductor elements are mounted, and an area R2 other than the element mounting region R1.

[0099] The element mounting region R1 includes a first mounting region MR1 in which a first semiconductor element is mounted. The element mounting region R1 also includes a second mounting region MR2 in which a second semiconductor element is mounted. The element mounting region R1 also includes a connection region CR that connects the first mounting region MR1 and the second mounting region MR2 (specifically, electrically connects the first semiconductor element and the second semiconductor element).

[0100] Exemplarily, the first mounting area MR1 may be an area in which a first processor chip is mounted, and the second mounting area MR2 may be an area in which a second processor chip of a different type from the first processor chip is mounted. For example, the first processor chip may be any one of application processor (AP) chips such as a central processor (e.g., CPU), a graphic processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller. The second processor chip may be a processor chip of a different type from the first processor chip, among application processor (AP) chips such as a central processor (e.g., CPU), a graphic processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller. For example, the first processor chip may be a central processor chip, and the second processor chip may be a graphic processor chip. That is, the circuit board of the embodiment may be a circuit board for die splitting in which a plurality of processor chips in which application processors are separated by function are mounted on one board.

[0101] The second substrate layer 200 includes a fine pattern. For example, the circuit pattern layer included in the second substrate layer 200 is required to have a line width of 6 μm or less, 5 μm or less, or 4 μm or less.

[0102] Additionally, the circuit pattern layer included in the second substrate layer 200 is required to have an interval of 6 μm or less, 5 μm or less, or 4 μm or less.

[0103] For example, the circuit pattern layer provided in the element mounting region R1 of the second substrate layer 200 is required to have a line width of 1 μm to 6 μm, preferably 1.2 μm to 5 μm, and more preferably 1.5 μm to 4 μm. Also, the circuit pattern layer provided in the element mounting region R1 of the second substrate layer 200 of the embodiment is required to have an interval of 1 μm to 6 μm, preferably 1.2 μm to 5 μm, and more preferably 1.5 μm to 4 μm.

[0104] That is, the number of functions required for application processors is increasing, and there is a demand to mount multiple semiconductor elements separated by function on a single board. Also, the number of terminals provided on each of the multiple separated semiconductor elements is increasing.

[0105] In this case, if the spacing between the semiconductor elements is large, the communication speed for signal exchange between them may decrease. Also, if the spacing between the semiconductor elements is large, the power consumption required for communication increases. Also, if the spacing between the semiconductor elements is large, the length of the traces connecting the semiconductor elements increases, which makes the semiconductor elements vulnerable to noise and increases signal transmission loss.

[0106] That is, the interval between the plurality of semiconductor elements must be 150 μm or less. For example, the interval between the plurality of semiconductor elements must be 120 μm or less. For example, the interval between the plurality of semiconductor elements must be 100 μm or less.

[0107] Therefore, the circuit pattern layer of the second substrate layer 200 is required to have fine line widths and fine intervals in order to arrange all the wiring connecting a plurality of semiconductor elements within a limited space.

[0108] The second substrate layer 200 may have a multi-layer structure. The second substrate layer 200 may have at least two layers based on the number of insulating layers. The second substrate layer 200 includes a second insulating layer 210.

[0109] The second insulating layer 210 may include a 2-1 insulating layer 211, a 2-2 insulating layer 212, and a 2-3 insulating layer 213, but the number of layers of the second insulating layer is not limited. However, in the embodiment, the second insulating layer 210 may be configured with at least two layers, thereby facilitating wiring connection between a plurality of semiconductor elements mounted in the element mounting region R1.

[0110] The 2-1 insulating layer 211 is disposed on the first substrate layer 100. The 2-1 insulating layer 211 is disposed on the 1-1 insulating layer 111 of the first substrate layer 100. The 2-2 insulating layer 212 is disposed on the 2-1 insulating layer 211. In addition, the 2-3 insulating layer 213 is disposed on the 2-2 insulating layer 212.

[0111] In one embodiment, the second insulating layer 210, including the 2-1 insulating layer 211, the 2-2 insulating layer 212, and the 2-3 insulating layer 213, can include a second insulating material. For example, the second insulating layer 210 can include a second insulating material that is different from the first insulating material that constitutes the first insulating layer 110.

[0112] Exemplarily, the second insulating layer 210 may not include reinforcing fibers so that a fine pattern can be realized. Preferably, the second insulating layer 210 may include a photocurable resin or a photosensitive resin. For example, the second insulating layer 210 may include a photoimageable dielectics (PID).

[0113] The second insulating layer 210 of the second substrate layer 200 may include a photocurable resin such as PID, thereby enabling miniaturization of the circuit pattern layer and the through electrodes of the second substrate layer 200. However, the embodiment is not limited thereto, and the second insulating layer 210 of the second substrate layer 200 may include a thermosetting resin without reinforcing fibers, instead of a photocurable resin.

[0114] The thickness of each layer of the second insulating layer 210 may be smaller than the thickness of each layer of the first insulating layer 110. For example, each of the 2-1 insulating layer 211, the 2-2 insulating layer 212, and the 2-3 insulating layer 213 may have a thickness in the range of 3 μm to 20 μm. For example, each of the 2-1 insulating layer 211, the 2-2 insulating layer 212, and the 2-3 insulating layer 213 may have a thickness in the range of 4 μm to 18 μm. For example, each of the 2-1 insulating layer 211, the 2-2 insulating layer 212, and the 2-3 insulating layer 213 may have a thickness in the range of 6 μm to 15 μm. If each of the 2-1 insulating layer 211, the 2-2 insulating layer 212, and the 2-3 insulating layer 213 has a thickness less than 3 μm, the second circuit pattern layer 220 formed on the second insulating layer 210 may not be stably protected. If the thickness of each of the 2-1 insulating layer 211, the 2-2 insulating layer 212, and the 2-3 insulating layer 213 exceeds 20 μm, it may be difficult to make the second circuit pattern layer 220 finer.

[0115] The second substrate layer 200 may include a second circuit pattern layer 220. The second circuit pattern layer 220 is disposed on the second insulating layer 210.

[0116] The second circuit pattern layer 220 includes a 2-1 circuit pattern layer 221 disposed on a 2-1 insulating layer 211. The second circuit pattern layer 220 includes a 2-2 circuit pattern layer 222 disposed on a 2-2 insulating layer 212. The second circuit pattern layer 220 includes a 2-3 circuit pattern layer 223 disposed on a 2-3 insulating layer 213.

[0117] At this time, the 2-3 circuit pattern layer 223 may be a circuit pattern disposed on the top side of the circuit board, and may be embedded in the insulating layer of the second substrate layer 200 .

[0118] For example, the 2-3 circuit pattern layer 223 may be provided by filling the grooves provided on the upper surface of the 2-3 insulating layer 213. Therefore, the embodiment can stably protect the 2-3 circuit pattern layer 223 arranged on the uppermost side of the second substrate layer 200. That is, the 2-3 circuit pattern layer 223 includes an electrode portion connected to a plurality of semiconductor elements. The electrode portion includes a trace having a relatively fine line width. If the trace of the 2-3 circuit pattern layer 223 has a structure protruding above the 2-3 insulating layer 213, cracks and / or peeling may occur due to various external factors. Therefore, the embodiment has a structure in which the 2-3 circuit pattern layer 223 is embedded in the 2-3 insulating layer 213. Thus, the embodiment can improve physical reliability and / or mechanical reliability.

[0119] However, the embodiment is not limited thereto. As an example, the 2-3 circuit pattern layer 223a may protrude above the upper surface of the 2-3 insulating layer 213 as shown in FIG. 2. As another example, the 2-3 circuit pattern layer 223a may be partially embedded in the 2-3 insulating layer 213 and protrude above the 2-3 insulating layer 213.

[0120] The second circuit pattern layer 220 can have a layer structure different from that of the first circuit pattern layer 120. For example, the second circuit pattern layer 220 can have a greater number of layers than the first circuit pattern layer 120. However, the second circuit pattern layer 220 can have a thickness smaller than that of the first circuit pattern layer 120 while having a greater number of layers than the first circuit pattern layer 120.

[0121] Each of the 2-1 circuit pattern layer 221, the 2-2 circuit pattern layer 222, and the 2-3 circuit pattern layer 223 of the second circuit pattern layer 220 can have a three-layer structure. For example, each of the 2-1 circuit pattern layer 221, the 2-2 circuit pattern layer 222, and the 2-3 circuit pattern layer 223 can include a first metal layer 220-1, a second metal layer 220-2, and a third metal layer 220-3. The first metal layer 220-1 and the second metal layer 220-2 can be seed layers.

[0122] The first metal layer 220-1 may be a titanium (Ti) layer formed through a sputtering process. The first metal layer 220-1 may have a thickness of 0.01 μm to 0.15 μm. For example, the first metal layer 220-1 may have a thickness of 0.03 μm to 0.12 μm. For example, the first metal layer 220-1 may have a thickness of 0.05 μm to 0.10 μm. The first metal layer 220-1 may be a first seed layer formed to enhance the adhesive strength between the second metal layer 220-2 and the third metal layer 220-3 and the second insulating layer 220.

[0123] The second metal layer 220-2 may be a copper (Cu) layer formed through a sputtering process. The second metal layer 220-2 may have a thickness of 0.01 μm to 0.35 μm. For example, the second metal layer 220-2 may have a thickness of 0.05 μm to 0.32 μm. For example, the second metal layer 220-2 may have a thickness of 0.1 μm to 0.3 μm. The second metal layer 220-2 may be a second seed layer formed for electrolytic plating of the third metal layer 220-3. In an embodiment, the total thickness of the first metal layer 220-1 and the second metal layer 220-2 may be 0.5 μm or less. Preferably, the total thickness of the first metal layer 220-1 and the second metal layer 220-2 may be 0.4 μm or less. More preferably, the total thickness of the first metal layer 220-1 and the second metal layer 220-2 may be 0.3 μm or less. If the total thickness of the first metal layer 220-1 and the second metal layer 220-2 exceeds 0.5 μm, it may be difficult to miniaturize the second circuit pattern layer 220. Specifically, the manufacturing process of the second circuit pattern layer 220 includes a process of etching the first metal layer 220-1 and the second metal layer 220-2. At this time, if the thicknesses of the first metal layer 220-1 and the second metal layer 220-2 increase, the amount of etching in the etching process increases, which makes it difficult to miniaturize the second circuit pattern layer 220.

[0124] The seed layer of the second circuit pattern layer 220 includes a first metal layer 220-1 and a second metal layer 220-2. At this time, the first metal layer 220-1 and the second metal layer 220-2 are formed by a sputtering process, and thus have a smaller thickness than the seed layer of the first circuit pattern layer 120. This allows the second circuit pattern layer 220 to be miniaturized.

[0125] The third metal layer 220-3 may be an electrolytic plating layer formed by electrolytic plating using the second metal layer 220-2 as a seed layer. The third metal layer 220-3 may have a thickness in the range of 2 μm to 12 μm. The third metal layer 220-3 may have a thickness in the range of 3 μm to 11 μm. The third metal layer 220-3 may have a thickness in the range of 4 μm to 10 μm.

[0126] If the thickness of the third metal layer 220-3 is less than 2 μm, the third metal layer 220-3 may be etched together in the process of etching the seed layer, which may make it difficult to properly implement the second circuit pattern layer 220. If the thickness of the third metal layer 220-3 is more than 12 μm, it may be difficult to miniaturize the second circuit pattern layer 220.

[0127] The second circuit pattern layers 220 may each have a thickness in the range of 3 μm to 13 μm. The second circuit pattern layers 220 may each have a thickness in the range of 4 μm to 12 μm. The second circuit pattern layers 220 may each have a thickness in the range of 5 μm to 11 μm. If the thickness of the second circuit pattern layers 220 is less than 5 μm, the resistance of the second circuit pattern layer may increase, and the reliability of electrical connections between a plurality of semiconductor elements may decrease. If the thickness of each of the first circuit pattern layers 220 exceeds 11 μm, it may be difficult to realize a fine pattern.

[0128] The second circuit pattern layer 220 can be a very fine pattern. For example, the second circuit pattern layer 220 can have a line width of 6 μm or less, or 5 μm or less, or 4 μm or less. The second circuit pattern layer 220 can have a spacing of 6 μm or less, or 5 μm or less, or 4 μm or less.

[0129] The second circuit pattern layer 220 may have a line width of 1 μm to 6 μm. The line width may refer to the line width of the traces constituting the second circuit pattern layer 220. The second circuit pattern layer 220 may have a line width in the range of 1.2 μm to 5 μm. The second circuit pattern layer 220 may have a line width in the range of 1.5 μm to 4 μm. If the line width of the second circuit pattern layer 220 is smaller than 1 μm, the resistance of the second circuit pattern layer 220 increases, which may make it difficult to normally communicate with multiple semiconductor elements. Also, if the line width of the second circuit pattern layer 220 is smaller than 1 μm, the rigidity of the second circuit pattern layer 220 decreases, which may cause mechanical reliability problems such as cracks. If the line width of the second circuit pattern layer 220 is larger than 6 μm, it may be difficult to connect multiple semiconductor elements within a limited space. For example, if the line width of the second circuit pattern layer 220 is greater than 6 μm, it may be difficult to arrange all of the electrodes for connecting multiple semiconductor elements within a limited space. For example, if the line width of the second circuit pattern layer 220 is greater than 6 μm, the arrangement space for arranging traces for connecting multiple semiconductor elements increases, which may increase the size of the semiconductor package.

[0130] The second circuit pattern layer 220 may have a spacing in the range of 1 μm to 6 μm. The spacing may refer to the spacing between the traces of the second circuit pattern layer 220. The second circuit pattern layer 220 may have a spacing in the range of 1.2 μm to 5 μm. The second circuit pattern layer 220 may have a spacing in the range of 1.5 μm to 4 μm. If the spacing of the second circuit pattern layer 220 is smaller than 1 μm, there is a problem that adjacent traces are connected to each other and an electrical short occurs. For example, if the spacing of the second circuit pattern layer 220 is larger than 6 μm, it may be difficult to arrange all traces connected to multiple semiconductor elements within a limited space. For example, if the spacing of the second circuit pattern layer 220 is larger than 6 μm, the arrangement space of the traces for connecting between multiple semiconductor elements increases, which may increase the size of the semiconductor package.

[0131] The line width and interval of the second circuit pattern layer 220 described above may refer to the line width and interval of the 2-3 circuit pattern layer 223 disposed on the top side of the second substrate layer 200. The 2-1 circuit pattern layer 221 and the 2-2 circuit pattern layer 222 may have the same line width and interval as the 2-3 circuit pattern layer 223. However, the embodiment is not limited thereto, and the 2-1 circuit pattern layer 221 and the 2-2 circuit pattern layer 222 may have a line width and interval different from the 2-3 circuit pattern layer 223. For example, the 2-1 circuit pattern layer 221 and the 2-2 circuit pattern layer 222 may have a line width and interval larger than the 2-3 circuit pattern layer 223.

[0132] As one example, the traces of the 2-1 circuit pattern layer 221 and the traces of the 2-2 circuit pattern layer 222 can have the same line width and spacing as the traces of the 2-3 circuit pattern layer 223. As another example, the traces of the 2-1 circuit pattern layer 221 and the traces of the 2-2 circuit pattern layer 222 can have different line widths and spacing than the traces of the 2-3 circuit pattern layer 223. For example, the traces of the 2-1 circuit pattern layer 221 and the traces of the 2-2 circuit pattern layer 222 can have line widths and spacings that are larger than the line widths and spacings of the traces of the 2-3 circuit pattern layer 223.

[0133] Also, the pads of the 2-1 circuit pattern layer 221 and the pads of the 2-2 circuit pattern layer 222 can have a different width than the pads of the 2-3 circuit pattern layer 223. For example, the pads of the 2-1 circuit pattern layer 221 and the pads of the 2-2 circuit pattern layer 222 can have a width larger than the width of the pads of the 2-3 circuit pattern layer 223.

[0134] The second substrate layer 200 includes a second through electrode 230. The second through electrode 230 includes a 2-1 through electrode 231 that penetrates the 2-1 insulating layer 211. The second through electrode 230 includes a 2-2 through electrode 232 that penetrates the 2-2 insulating layer 212. The second through electrode 230 includes a 2-3 through electrode 233 that penetrates the 2-3 insulating layer 213.

[0135] The 2-1 through electrode 231, the 2-2 through electrode 232, and the 2-3 through electrode 233 may have different widths. For example, among the 2-1 through electrode 231, the 2-2 through electrode 232, and the 2-3 through electrode 233, the through electrode located closest to the first substrate layer 100 may have the largest width. For example, among the 2-1 through electrode 231, the 2-2 through electrode 232, and the 2-3 through electrode 233, the through electrode located farthest from the first substrate layer 100 (for example, the through electrode located closest to the multiple semiconductor elements) may have the smallest width.

[0136] However, each of the 2-1 through electrode 231, the 2-2 through electrode 232, and the 2-3 through electrode 233 may have a width smaller than that of the first through electrode 130. In this case, the width of the through electrode described below may refer to the width of the surface having a relatively larger width among the upper surface and the lower surface. For example, each of the widths of the 2-1 through electrode 231, the 2-2 through electrode 232, and the 2-3 through electrode 233 may refer to the width of the upper surface of each of the 2-1 through electrode 231, the 2-2 through electrode 232, and the 2-3 through electrode 233.

[0137] The 2-1 through electrode 231, the 2-2 through electrode 232, and the 2-3 through electrode 233 of the embodiment are formed in the 2-1 insulating layer 211, the 2-2 insulating layer 212, and the 2-3 insulating layer 213 of the second insulating layer 210, respectively. At this time, as described above, the 2-1 insulating layer 211, the 2-2 insulating layer 212, and the 2-3 insulating layer 213 are configured with PID. As a result, the widths of the 2-1 through electrode 231, the 2-2 through electrode 232, and the 2-3 through electrode 233 may be smaller than the width of the first through electrode 130 formed in the first insulating layer 110.

[0138] For example, the widths of the 2-1 through electrode 231, the 2-2 through electrode 232, and the 2-3 through electrode 233 may be ½ or less of the width of the first through electrode 130. For example, the widths of the 2-1 through electrode 231, the 2-2 through electrode 232, and the 2-3 through electrode 233 may be ⅕ or less of the width of the first through electrode 130. For example, the widths of the 2-1 through electrode 231, the 2-2 through electrode 232, and the 2-3 through electrode 233 may be 1 / 10 or less of the width of the first through electrode 130.

[0139] Specifically, since the first through electrode 130 is formed in the first insulating layer 110 made of prepreg, it can have a width of at least 15 μm or more.

[0140] In contrast to this, the 2-1 through electrode 231, the 2-2 through electrode 232, and the 2-3 through electrode 233 are formed in the second insulating layer 210 made of PID, and this allows them to be formed at the level of 1 μm.

[0141] As described above, the widths of the 2-1 through electrode 231, the 2-2 through electrode 232, and the 2-3 through electrode 233 may be 1 / 10 of the width of the first through electrode 130. In this case, if the 2-1 through electrode 231, the 2-2 through electrode 232, and the 2-3 through electrode 233 each have 1 / 10 of the width of the first through electrode 130, the reliability of signal transmission may be reduced. For example, the 1-1 through electrode 131 and the 2-1 through electrode 231 are connected to each other with the 1-1 circuit pattern layer 121 sandwiched therebetween. In this case, if the 2-1 through electrode 231 has 1 / 10 of the width of the 1-1 through electrode 131, the resistance due to the difference in width between the 2-1 through electrode 231 and the 1-1 through electrode 131 may increase, which may cause a reliability problem. For example, signal transmission loss due to noise may increase during the process of transmitting a signal from the 2-1 through electrode 231 to the 1-1 through electrode 131. Furthermore, when the transmitted signal is a high-frequency signal in the high-frequency (mmWave) band (e.g., 6 GHz, 28 GHz, 35 GHz) or higher of 5G or higher (6G, 7G-etc.), the signal transmission loss may cause an even greater problem in communication performance.

[0142] For example, the width of the second through electrode 230 in the region where the semiconductor element of the embodiment is mounted may have a fine width according to the width of a terminal included in the semiconductor element. Also, the width of the second through electrode 230 may gradually increase as it approaches the first substrate layer 100. And, the 2-1 through electrode 231 of the second through electrode 230 disposed closest to the first substrate layer 100 may have a width corresponding to the first through electrode (e.g., the 1-1 through electrode 131) formed in the first substrate layer 100.

[0143] For example, as described, the 1-1 through electrode 131 can have a width in the range of 15 μm to 70 μm.

[0144] The width of the 2-1 through electrode 231 disposed most adjacent to the 1-1 through electrode 131 in the vertical direction may correspond to the width of the 1-1 through electrode 131 .

[0145] In addition, the second through-electrodes 230 may have a gradually decreasing width as they move vertically away from the 1-1 through-electrode 131. The 2-3 through-electrode 233, which is the furthest away from the 1-1 through-electrode 131, may have the smallest width among the second through-electrodes 230.

[0146] The 2-2 through electrode 232 disposed between the 2-1 through electrode 231 and the 2-3 through electrode 233 may be smaller in width than the 2-1 through electrode 231 and larger in width than the 3 through electrode 233. For example, the width of the 2-2 through electrode 232 may be a value between the width of the 2-1 through electrode 231 and the width of the 2-3 through electrode 233.

[0147] In the embodiment, the width of the second through electrodes 230 included in the second substrate layer 200 increases toward the first substrate layer 100 and decreases away from the first substrate layer 100. As a result, the embodiment can minimize signal transmission loss caused by the difference in width of the through electrodes provided in different layers, thereby improving communication performance.

[0148] On the other hand, the thickness T1 of the circuit board 300 of the embodiment may be smaller than the thickness of a conventional circuit board.

[0149] For example, if the first substrate layer 100 has a five-layer structure based on the number of first insulating layers, and the second substrate layer 200 has a three-layer structure based on the number of second insulating layers, the thickness T1 of the circuit substrate 300 may be 400 μm or less, 380 μm or less, or 360 μm or less.

[0150] Meanwhile, in the embodiment, the first insulating layer 110 included in the first substrate layer 100 of the circuit board 300 may be made of the same photocurable resin PID as the second insulating layer 220 included in the second substrate layer 200 .

[0151] However, if all the insulating layers of the circuit board 300 are made of PID, which is a photocurable resin, the product price may increase. That is, PID, which is a photocurable resin, is more expensive than prepreg, and therefore, if the circuit board 300 is entirely made of PID, the product price of the circuit board 300 and the semiconductor package including the same may increase. Also, if the first insulating layer 110 of the first substrate layer 100 is also made of PID, problems may occur in the rigidity of the circuit board 300, and thus the warpage characteristics may decrease. Therefore, in the embodiment, the first substrate layer 100 includes the first insulating layer 110 made of prepreg.

[0152] The second circuit pattern layer 220 disposed on the second substrate layer 200 will be described in more detail below. That is, the 2-3 circuit pattern layer 223 of the second circuit pattern layer 220 on which the semiconductor elements are mounted will be described in detail below. The 2-3 circuit pattern layer 223 can be considered as an electrode part electrically connected to the semiconductor elements. Therefore, for convenience of explanation, the 2-3 circuit pattern layer 223 will be described as an "electrode part" below.

[0153] FIG. 7 is a plan view of the electrode portion of the embodiment, FIG. 8a is a diagram for comparing the pad shapes of the electrode portion of the comparative example and the embodiment, FIG. 8b is a diagram for explaining problems that arise due to the pad shape of the electrode portion of the comparative example, and FIG. 9 is an enlarged view of one area of ​​FIG. 7.

[0154] The electrode portion of the embodiment will be specifically described below with reference to FIGS.

[0155] The second substrate layer 200 includes a device mounting region R1. The device mounting region R1 includes a first mounting region MR1 that vertically overlaps with a first semiconductor device. The device mounting region R1 also includes a second mounting region MR2 that vertically overlaps with a second semiconductor device. The device mounting region R1 also includes a connection region CR between the first mounting region M1 and the second mounting region MR2. The connection region CR may vertically overlap with a separation region between the first and second semiconductor devices.

[0156] The electrode portion 223 may be disposed in the element mounting region R1. The electrode portion 223 refers to the circuit pattern layer that is disposed on the uppermost side of the second circuit pattern layer 220 of the second substrate layer 200.

[0157] The electrode unit 223 may include a pad 223P and a trace 223T1. For example, the electrode unit 223 may include a pad 223P on which a connection portion (e.g., a solder ball) is disposed for mounting a semiconductor element, and a trace 223T1 that electrically connects between the pad 223P and a plurality of pads.

[0158] Pads 223P and traces 223T1 are divided by function.

[0159] Exemplarily, the pad 223P allows a semiconductor element to be mounted or attached. The pad 223P refers to an electrode on which a connection part such as a solder ball for mounting a semiconductor element is disposed. The trace 223T1 refers to a signal transmission line. For example, the trace 223T1 may be a connection electrode that electrically connects a plurality of pads.

[0160] Additionally, the pads 223P and traces 223T1 are classified according to shape and size.

[0161] Illustratively, the shape of the pad 223P is different from the shape of the trace 223T1, and the horizontal width of the pad 223P is different from the horizontal width of the trace 223T1.

[0162] Additionally, pad 223P has a curved portion at least partially around its top surface, while trace 223T1 does not have a curved portion around its top surface.

[0163] The pad 223P has a width equal to or greater than a certain level for mounting a semiconductor element. The trace 223T1 has a width smaller than that of the pad 223P, which allows as many signal transmission lines as possible to be arranged in a limited area.

[0164] For example, the electrode portion 223 may include a first pad portion 223P1 arranged in the first mounting area MR1, a second pad portion 223P2 arranged in the second mounting area MR2, and a trace 223T1 that connects between the pad portion 223P1 and the second pad portion 223P2 and is arranged in the connection area CR.

[0165] The first pad portion 223P1 vertically overlaps the first semiconductor element disposed in the first mounting region MR1, and is electrically connected to a terminal of the first semiconductor element.

[0166] The second pad portion 223P2 vertically overlaps the second semiconductor element disposed in the second mounting region MR2 and is electrically connected to a terminal of the second semiconductor element.

[0167] The trace 223T1 electrically connects the first pad portion 223P1 and the second pad portion 223P2.

[0168] Specifically, the first semiconductor device and the second semiconductor device are electrically connected to each other to transmit and receive electrical signals to each other, for example, at least one of a plurality of terminals of the first semiconductor device is electrically connected to at least one of a plurality of terminals of the second semiconductor device to enable communication between the first semiconductor device and the second semiconductor device.

[0169] For example, the first semiconductor device includes a plurality of terminals, the plurality of terminals of the first semiconductor device includes at least one first terminal electrically connected to the second semiconductor device and a second terminal excluding the first terminal, and the plurality of terminals of the second semiconductor device includes a third terminal electrically connected to the first terminal of the first semiconductor device and a fourth terminal excluding the third terminal.

[0170] The first pad portion 223P1 includes a first group of pads 223P11 that vertically overlap with a first terminal of the first semiconductor element, and a second group of pads 223P12 that vertically overlap with a second terminal of the first semiconductor element.

[0171] At this time, the pads 223P11 of the first group in the first pad portion 223P1 have a shape, width, and planar area that are different from at least one of the shape, width, and planar area of ​​the pads 223P12 of the second group in the first pad portion 223P1.

[0172] That is, the first group of pads 223P11 of the first pad unit 223P1 are connected to the plurality of traces 223T1 and therefore should have a relatively small width. Exemplarily, the first group of pads 223P11 of the first pad unit 223P1 are provided in an area with a relatively high degree of circuit integration (circuit-dense area) and therefore should have a relatively small width and / or planar area. In contrast, the second group of pads 223P12 of the first pad unit 223P1 are provided in an area with a lower degree of circuit integration compared to the first group of pads 223P11 and therefore may have a larger width and / or area than the first group of pads 223P11.

[0173] Therefore, in this embodiment, the first group of pads 223P11 and the second group of pads 223P11 of the first pad portion 223P1 have different shapes, widths, or planar areas.

[0174] The second pad portion 223P2 also includes a first group of pads 223P21 that vertically overlap with a third terminal of the second semiconductor element, and a second group of pads 223P22 that vertically overlap with a fourth terminal of the second semiconductor element.

[0175] At this time, the pads 223P21 of the first group of the second pad portion 223P2 have a shape, width, and planar area that are different from at least one of the shape, width, and planar area of ​​the pads 223P22 of the second pad portion 223P2.

[0176] That is, the first group of pads 223P21 of the second pad unit 223P2 are connected to the plurality of traces 223T1 and therefore should have a relatively small width. For example, the first group of pads 223P21 of the second pad unit 223P2 are provided in an area with a relatively high degree of circuit integration (a circuit-dense area) and therefore should have a relatively small width and / or planar area. In contrast, the second group of pads 223P22 of the second pad unit 223P2 are provided in an area with a lower degree of circuit integration compared to the first group of pads 223P21 and therefore may have a larger width and / or area than the first group of pads 223P21.

[0177] Therefore, in this embodiment, the first group of pads 223P21 and the second group of pads 223P21 of the second pad portion 223P2 have different shapes, widths, or planar areas.

[0178] As an example, the planar shape of the first group of pads 223P11, 223P21 of each of the first and second pad portions 223P1, 223P2 may have a semicircular shape, and the planar shape of the second group of pads 223P12, 223P22 of each of the first and second pad portions 223P1, 223P2 may have a circular shape.

[0179] The pads 223P11 and 223P21 of the first group of each of the first and second pad portions 223P1 and 223P2 will be specifically described below. The pads 223P11 and 223P21 of the first group of each of the first and second pad portions 223P1 and 223P2 will be referred to as "pads 223P" in the following description.

[0180] The pad 223P may have a width W1 in the first direction D1 and a width W2 in the second direction D2 that are different from each other. For example, the pad 223P may have a width W1 in the first direction D1 that is smaller than a width W2 in the second direction D2. In this case, the first direction D1 may refer to the x-axis direction or the longitudinal direction. The second direction D2 may be a direction perpendicular to the first direction D1. For example, the second direction D2 may refer to the y-axis direction or the width direction. The first direction D1 may refer to a direction in which the trace 223T1 adjacent to the pad 223P is located.

[0181] For example, the first direction D1 may refer to a direction in which the trace 223T1 adjacent to the pad 223P is arranged with the pad 223P at the center, and the second direction D2 may refer to a direction perpendicular to the first direction D1.

[0182] The width W2 of the pad 223P in the second direction D2 can be in the range of 20 μm to 80 μm. For example, the width W2 of the pad 223P in the second direction D2 can be in the range of 25 μm to 75 μm. For example, the width W2 of the pad 223P in the second direction D2 can be in the range of 30 μm to 70 μm. If the width W2 of the pad 223P in the second direction D2 is less than 20 μm, it may be difficult to stably arrange a connection portion for mounting a semiconductor element on the pad 223P. If the width W2 of the pad 223P in the second direction D2 exceeds 80 μm, it may be difficult to arrange all the pads connected to the terminals of the first and second semiconductor elements in a limited space. For example, if the width W2 of the pad 223P in the second direction D2 exceeds 80 μm, the horizontal size of the circuit board may be large.

[0183] The width W1 of the pad 223P in the first direction D1 may be smaller than the width W2 in the second direction D2. For example, the width W1 of the pad 223P in the first direction D1 may be in the range of 80% to 95% of the width W2 in the second direction D2. For example, the width W1 of the pad 223P in the first direction D1 may be in the range of 82% to 93% of the width W2 in the second direction D2. For example, the width W1 of the pad 223P in the first direction D1 may be in the range of 83% to 92% of the width W2 in the second direction D2.

[0184] Specifically, the width W1 of the pad 223P in the first direction D1 can be in the range of 16 μm to 76 μm. For example, the width W1 of the pad 223P in the first direction D1 can be in the range of 20.5 μm to 70 μm. For example, the width W1 of the pad 223P in the first direction D1 can be in the range of 25 μm to 58 μm. If the width W1 of the pad 223P in the first direction D1 is less than 16 μm, it may be difficult to stably arrange a connection part for mounting a semiconductor element on the pad 223P. If the width W1 of the pad 223P in the first direction D1 exceeds 76 μm, the physical and / or electrical reliability of the trace arranged between the multiple pads spaced apart in the first direction D1 may be reduced. For example, if the width W1 of the pad 223P in the first direction D1 exceeds 76 μm, it may be impossible to ensure a space for arranging multiple traces between the multiple pads spaced apart in the first direction D1. In addition, if the arrangement space of the multiple traces is not secured, pattern formation defects may occur in the process of forming the traces. For example, if the arrangement space of the multiple traces is not secured, defects such as trace distortion may occur. In addition, if the arrangement space of the multiple traces is not secured, an electrical short problem may occur in which adjacent traces and pads or multiple traces are connected to each other.

[0185] As described above, the pad 223P of the embodiment may have a shape in which the portion where the adjacent trace is arranged is cut out in a circular shape having a specific radius of curvature. For example, the pad 223P of the embodiment may have a shape in which 5% to 20% of the entire area of ​​a circle having a specific radius of curvature is removed or cut out. And, the removed or cut out area of ​​the entire area of ​​the pad 223P may be an area adjacent to the area where the trace is arranged.

[0186] At this time, as shown in FIG. 8(a), the pad 223P' of the circuit board of the comparative example has a circular shape with a specific radius of curvature. FIG. 8(a) is a diagram showing the pads of the first group in the pad section provided in the comparative example. For example, the pad 223P' of the comparative example has the same width w1 in the first direction D1 and the same width w2 in the second direction D2. That is, the pads of the first group of the comparative example have the same circular shape as the pads of the second group.

[0187] For example, the pad 223P' of the comparative example has widths w1 and w2 in the first direction D1 and the second direction D2 that are the same within a range of 20 μm to 80 μm. For example, the pad 223P' of the comparative example has width b1 in the -1 direction, width b2 in the +1 direction, width a1 in the -2 direction, and width a2 in the +2 direction that are all the same from the center c of a circle having a specific radius of curvature.

[0188] 9, in the comparative example, exposure defects, development defects, or pattern groove defects of the dry film (not shown) may occur in an area A between multiple pads spaced apart in the first direction D1. As a result, in the circuit board of the comparative example, it is difficult to arrange multiple traces with high electrical and physical reliability between multiple pads spaced apart in the first direction D1.

[0189] Unlike this, as shown in FIG. 8(b), the pad 223P of the circuit board of the embodiment has a shape in which a portion adjacent to the trace is removed or cut in a circle having a specific radius of curvature. For example, the pad 223P of the circuit board of the embodiment has a width W1 in the first direction D1 and a width W2 in the second direction D2 that are different from each other. For example, the pad 223P of the circuit board of the embodiment has a width W1 in the first direction D1 that is smaller than the width W2 in the second direction D2. For example, the pad 223P of the embodiment has a width B2 in the +1 direction, a width A1 in the -2 direction, and a width A2 in the +2 direction from the center C of a circle having a specific radius of curvature that are the same as the radius of the circle, and the width B1 in the -1 direction is smaller than the radius of the circle. As a result, the embodiment allows a stable arrangement of multiple traces between multiple pads spaced apart in the first direction D1 while maximally maintaining the physical and electrical reliability of the pad 223P through the shape change of the pad 223P as described above.

[0190] Meanwhile, unlike the embodiment, the shape of the first group of pads may be changed to an elliptical shape. However, when the pad has an elliptical shape, various physical and electrical reliability problems may occur. For example, the entire area of ​​the pad should vertically overlap with the through electrode arranged thereunder. However, when the pad has an elliptical shape, at least a part of the pad may not vertically overlap with the through electrode due to tolerance in the process of forming the pad, which may cause problems in electrical and physical reliability. In addition, when the pad has an elliptical shape, stress applied to the pad due to thermal stress may be biased to one side, which may reduce physical reliability at high temperatures.

[0191] Therefore, the pad 223P of the embodiment has a shape in which only the area adjacent to the trace is cut out in a circle having a specific radius of curvature, which can improve physical and electrical reliability.

[0192] The above-mentioned pads 223P refer to the first group pads 223P11 and 223P21 of the first and second pad portions 223P1 and 223P2, respectively.

[0193] In contrast, the pads 223P12, 223P22 of the second group of each of the first and second pad portions 223P1, 223P2 have a circular shape different from the pads 223P11, 223P21 of the first group. This makes it possible in the embodiment to improve the bonding strength between the pads 223P12, 223P22 of the second group of each of the first and second pad portions 223P1, 223P2 and the first and second semiconductor elements, thereby enabling the first and second semiconductor elements to operate stably.

[0194] In the following, the pads 223P corresponding to the pads 223P12, 223P22 of the second group of each of the first and second pad portions 223P1, 223P2 will be specifically described.

[0195] The periphery of the upper surface 223PU of the pad 223P includes a curved portion having a specific radius of curvature and a straight portion connected to the curved portion. In this case, the straight portion around the upper surface 223PU can be referred to as a first portion 223PU1, and the curved portion can be referred to as a second portion 223PU2.

[0196] One end of the second portion 223PU2 may be connected to one end of the straight line of the first portion 223PU1, and the other end of the second portion 223PU2 may be connected to the other end of the straight line of the first portion 223PU1. For example, the second portion 223PU2 of the pad 223P may connect between one end and the other end of the first portion 223PU1 while having a specific radius of curvature.

[0197] The first portion 223PU1 of the upper surface 223PU of the pad 223P may mean a region adjacent to the trace 223T1 among the entire region of the upper surface 223PU of the pad 223P. In this case, the first portion 223PU1 of the upper surface 223PU of the pad 223P may be parallel to the trace 223T1. For example, the extension direction of the straight line of the first portion 223PU1 of the upper surface 223PU of the pad 223P may be parallel to the extension direction of the trace 223T1 adjacent to the pad 223P. Here, the parallel direction may mean that the difference between the angle at which the first portion 223PU1 extends and the angle at which the trace 223T1 extends is 10 degrees or less, 8 degrees or less, 5 degrees or less, or 2 degrees or less.

[0198] That is, the pad 223P may include a first pad 223Pa and a second pad 223Pb spaced apart in the first direction D1. The first pad 223Pa and the second pad 223Pb may refer to a first group of pads 223P11 of the first pad portion 223P1 or a first group of pads 223P21 of the second pad portion 223P2.

[0199] The first portion 223PU1 of the first pad 223Pa may be a region adjacent to the trace 223T1 disposed adjacent to the first direction D1. The first portion of the first pad 223Pa may face the second portion of the second pad 223Pb. For example, the second pad 223Pb may have a second portion located in a region adjacent to the trace 223T1. That is, the second pad 223Pb may not include a straight portion around the upper surface facing the first portion, which is the straight portion, of the first pad 223Pa. In addition, if there is no additional third pad spaced apart from the second pad 223Pb in the first direction, the periphery of the upper surface of the second pad 223Pb may not include a straight portion. However, in the following description, it is assumed that there is an additional third pad spaced apart from the second pad 223Pb in the first direction (e.g., downward direction in the drawing), and therefore at least a portion of the periphery of the upper surface of the second pad 223Pb includes a straight portion. However, the embodiment is not limited to this, and the periphery of the upper surface of the second pad 223Pb may include only curved portions and may not include straight portions.

[0200] On the other hand, when the first pad 223Pa and the first portion of the second pad 223Pb are arranged to face each other while including a first portion that is a straight line portion around the upper surface of the second pad 223Pb, a sufficient space for arranging the trace can be secured in the area where the first portions face each other. However, in such a case, the space between the second pad 223Pb and a third pad spaced apart from the second pad 223Pb in the first direction may not be sufficient to arrange the trace, which may cause problems with physical or electrical reliability.

[0201] That is, a plurality of traces may be arranged between the first pad 223Pa and the second pad 223Pb, extending in the second direction D2.

[0202] At this time, the pitch W3 between the first pad 223Pa and the second pad 223Pb may mean the linear distance in the first direction between the center of the first pad and the center of the second pad. The pitch W3 may be in the range of 25 μm to 110 μm. For example, the pitch W3 may be in the range of 31 μm to 100 μm. For example, the pitch W3 may be in the range of 37 μm to 90 μm. If the pitch W3 is less than 25 μm, it may be difficult to stably arrange the multiple traces 223T1 between the first pad 223Pa and the second pad 223Pb that are spaced apart in the first direction D1. If the pitch W3 exceeds 110 μm, the space between the first pad 223Pa and the second pad 223Pb may become too large, which may increase the horizontal size of the circuit board.

[0203] The trace 223T1 is disposed in the first mounting region MR1 and includes a first portion 223T1a coupled to the first pad portion 223P1. The trace 223T1 is also disposed in the second mounting region MR2 and includes a second portion 223T1b coupled to the second pad portion 223P2. The trace 223T1 is also disposed in the coupling region CR and includes a third portion 223T1c coupling between the first portion 223T1a and the second portion 223T1b.

[0204] At this time, as described above, in order to mount the first semiconductor element, mount the second semiconductor element, and connect the first and second semiconductor elements within a limited space, the trace 223T1 needs to be ultra-fine. For this reason, in the embodiment, the second insulating layer 210 is formed by PID, so that the trace 223T1 can be ultra-fine.

[0205] Preferably, the line width W4 of the trace 223T1 may be in the range of 1 μm to 6 μm. For example, the line width W4 of the trace 223T1 may be in the range of 1.2 μm to 5 μm. For example, the line width W4 of the trace 223T1 may be in the range of 1.5 μm to 4 μm. If the line width W4 of the trace 223T1 is smaller than 1 μm, the resistance of the trace 223T1 increases, which may make it difficult to properly electrically connect the trace 223T1 to a semiconductor element. Also, if the line width W4 of the trace 223T1 is smaller than 1 μm, not only is it difficult to realize the trace 223T1, but there may also be a reliability problem in that the trace 223T1 is easily broken due to various factors. If the line width W4 of the trace 223T1 is larger than 6 μm, it may be difficult to connect multiple semiconductor elements in a limited space. For example, if the line width W4 of the trace 223T1 is larger than 6 μm, it may be difficult to arrange all the traces for connecting multiple semiconductor elements in a limited space. For example, if the line width W4 of the trace 223T1 is greater than 6 μm, the arrangement space for arranging the traces for connecting multiple semiconductor elements within the connection region CR increases, which may increase the size of the circuit board and semiconductor package.

[0206] On the other hand, the interval W6 between the plurality of traces 223T1 or the interval W5 between the pad 223P and the trace 223T1 may range from 1 μm to 6 μm. The interval W6 between the plurality of traces 223T1 or the interval W5 between the pad 223P and the trace 223T1 may range from 1.2 μm to 5 μm. The interval W6 between the plurality of traces 223T1 or the interval W5 between the pad 223P and the trace 223T1 may range from 1.5 μm to 4 μm. If the interval W6 between the plurality of traces 223T1 or the interval W5 between the pad 223P and the trace 223T1 is smaller than 1 μm, there is a problem that adjacent traces or a trace and a pad are connected to each other, causing an electrical short. For example, if the interval W6 between the plurality of traces 223T1 or the interval W5 between the pad 223P and the trace 223T1 is larger than 6 μm, it may be difficult to arrange all the traces for connecting between the plurality of semiconductor elements within a limited space.

[0207] As a result, when two traces 223T1 are arranged in the second direction D2 between the first pad 223Pa and the second pad 223P, the width W7 of the trace arrangement space can be in the range of 3 μm to 18 μm. For example, the width W7 of the trace arrangement space can be in the range of 3.6 μm to 15 μm. For example, the width W7 of the trace arrangement space can be in the range of 4.5 μm to 12 μm.

[0208] The width W8 in the first direction D1 between the first pad 223Pa and the second pad 223Pb or the interval W8 between the first pad 223Pa and the second pad 223Pb spaced apart in the first direction D1 may be in the range of 5 μm to 30 μm. For example, the interval W8 between the first pad 223Pa and the second pad 223Pb spaced apart in the first direction D1 may be in the range of 6 μm to 25 μm. For example, the interval W8 between the first pad 223Pa and the second pad 223Pb spaced apart in the first direction D1 may be in the range of 7.5 μm to 20 μm.

[0209] Meanwhile, the electrode unit 223 may include a dummy electrode 223D. The dummy electrode 223D is not electrically connected to the pad 223P and the trace 223T1 of the electrode unit 223. For example, the dummy electrode 223D may not be electrically connected to the pad 223P and the trace 223T1, and thus may not be an electrode that performs a function of transmitting an electrical signal. The dummy electrode 223D may be disposed in the first connection region CR1. For example, the dummy electrode 223D may be disposed in an area in the first connection region CR1 that is not disposed in the trace 223T1. The line width of the dummy electrode 223D may be larger than the line width of the trace 223T1. The dummy electrode 223D may be formed for the flatness of the circuit board. For example, an additional insulating layer (e.g., a protective layer such as a solder resist) may be disposed on the electrode unit 223. Furthermore, in a state where the dummy electrode 223D is not included, the additional insulating layer may have a height difference between a region that vertically overlaps with the electrode portion 223 and a region that does not vertically overlap with the electrode portion 223. The height difference may reduce the flatness of the circuit board. Thus, the embodiment uses the dummy electrode 223D to minimize the height difference of the additional insulating layer, thereby improving the flatness of the circuit board.

[0210] As described above, the first group of pads 223P11, 223P21 of the first and second pad parts 223P1, 223P2 of the embodiment may have a shape in which the area adjacent to the adjacent trace is cut off in a circle having a specific radius of curvature. For example, the upper surface 223PU of the first group of pads 223P11, 223P21 of the first and second pad parts 223P1, 223P2 includes a first portion 223PU1 that is a straight line adjacent to the trace. Also, the upper surface 223PU of the first group of pads 223P11, 223P21 of the first and second pad parts 223P1, 223P2 includes a second portion 223PU2 that is connected to the first portion 223PU1 and is a curved line having a specific radius of curvature. The extension direction of the straight line of the first portion 223PU1 may be the same direction as or parallel to the extension direction of the trace 223T1. As a result, in the embodiment, by changing the shapes of the first group pads 223P11 and 223P21 of the first and second pad units 223P1 and 223P2, respectively, it is possible to secure a space for arranging a plurality of traces between a plurality of pads spaced apart in the first direction D1. As a result, in the embodiment, it is possible to form stable traces between a plurality of pads spaced apart in the first direction D1, thereby improving the physical and electrical reliability of the circuit board.

[0211] Furthermore, the pads 223P12, 223P22 of the second group of each of the first and second pad portions 223P1, 223P2 of the embodiment may not include straight portions, but may include only curved portions. Alternatively, the pads 223P12, 223P22 of the second group of each of the first and second pad portions 223P1, 223P2 of the embodiment may have a planar area larger than the planar area of ​​the pads of the first group. This allows the embodiment to stably mount a semiconductor element.

[0212] A method for manufacturing a circuit board according to an embodiment will be described below.

[0213] 11 to 30 are diagrams for explaining the process of manufacturing the circuit board of FIG. 1 in sequence.

[0214] The method for manufacturing a circuit board according to the embodiment can be divided into a first step of manufacturing a first substrate layer 100 and a second step of manufacturing a second substrate layer 200 on the manufactured first substrate layer 100.

[0215] Referring to FIG. 11, the embodiment may perform a process of preparing a basic material for manufacturing a first substrate layer 100 using the ETS method. For this purpose, the embodiment may prepare a carrier board CB. The carrier substrate CB may include a carrier insulating layer CB1 and a carrier metal layer CB2 disposed on at least one surface of the carrier insulating layer CB1. At this time, the drawing shows that the carrier metal layer CB2 is disposed only on the first surface of the carrier insulating layer CB1, but is not limited thereto. For example, the carrier substrate CB of the embodiment may have a carrier metal layer CB2g formed on the first surface of the carrier insulating layer CB1 and the second surface opposite to the first surface. When the carrier metal layer is formed on both surfaces of the carrier insulating layer CB1, the manufacturing process of the first substrate layer 100 described below may be performed on both surfaces of the carrier substrate CB. For example, the embodiment may perform the following processes on the upper and lower sides of the carrier substrate CB at the center to form a plurality of first substrate layers at once. In the following, the manufacturing process of the first substrate layer is performed only on one side of the carrier substrate CB.

[0216] The carrier metal layer CB2 can be formed by electroless plating on the carrier insulating layer CB1. In addition, in the embodiment, a CCL (Copper Clad Laminate) can be used as the carrier board CB.

[0217] Next, the embodiment may perform a process of forming a first metal layer 610 on the carrier metal layer CB2. The first metal layer 610 may be formed to a certain thickness on the carrier metal layer CB2 by performing a chemical copper plating process.

[0218] 12, a process of forming a first mask 620 on the first metal layer 610 may be performed. At this time, the first mask 620 may be formed to cover the entire first surface of the first metal layer 610, and may include an opening (not shown) that exposes a portion of the surface of the first metal layer 610 through a process of subsequently opening the first mask 620. That is, the first mask 620 may include an opening (not shown) that opens an area of ​​the first surface of the first metal layer 610 where the 1-1 circuit pattern layer 121 is to be formed.

[0219] Next, in an embodiment, as shown in FIG. 13, a process can be performed in which electrolytic plating is performed using the first metal layer 610 as a seed layer to form a 1-1 circuit pattern layer 121 that fills the openings of the first mask 620.

[0220] 14, the embodiment may perform a process of removing the first mask 620 disposed on the first metal layer 610. Also, the embodiment may perform a process of forming a 1-1 insulating layer 111 covering the 1-1 circuit pattern layer 121 on the first metal layer 610. The 1-1 insulating layer 111 may include a prepreg.

[0221] 15, the embodiment may perform a process of forming a 1-1 through hole VH1 in the 1-1 insulation layer 111. The 1-1 through hole VH1 may be formed through a laser process to open the resin and reinforcing fibers that constitute the 1-1 insulation layer 111.

[0222] Next, in the embodiment, a process of forming first metal layers 131-1, 122-1 on the surface of the 1-1 insulating layer 111 and the inner wall of the 1-1 through hole VH1 can be performed as shown in Fig. 16. The first metal layers 131-1, 122-1 can be formed by a chemical copper plating process, but are not limited thereto.

[0223] 17, the embodiment may perform a process of forming a second mask 630 on the first metal layer 122-1 formed on the surface of the 1-1 insulating layer 111. At this time, the second mask 630 may include at least one opening (not shown). For example, the second mask 630 may include an opening exposing an area where the 1-1 through electrode 131 is to be formed and an opening exposing an area where the 1-2 circuit pattern layer 122 is to be formed.

[0224] 18, in the embodiment, electrolytic plating is performed using the first metal layers 131-1 and 122-1 to form second metal layers 131-2 and 122-2 that fill the openings of the second mask 630. At this time, the first metal layer 131-1 and the second metal layer 131-2 can form the 1-1 through electrode 131. In addition, the first metal layer 121-1 and the second metal layer 121-2 can form the 1-2 circuit pattern layer 122.

[0225] Next, an embodiment may perform a step of removing the second mask 630 and etching the first metal layer 122-1, as shown in Figure 19. For example, an embodiment may perform a seed layer etch step that removes portions of the first metal layer 122-1 that do not vertically overlap the second metal layer 122-2.

[0226] Next, in the embodiment, as shown in FIG. 20, the steps of FIGS. 12 to 19 are repeated to perform a step of forming a multi-layer first substrate layer 100.

[0227] For example, the embodiment may perform a step of forming a 1-2 insulating layer 112 on the 1-1 insulating layer 111. Also, the embodiment may perform a step of forming a 1-2 through electrode 132 and a 1-3 circuit pattern layer 123 on the 1-2 insulating layer 112. For example, the embodiment may perform a step of forming a 1-3 insulating layer 113 on the 1-2 insulating layer 112. Also, the embodiment may perform a step of forming a 1-3 through electrode 133 and a 1-4 circuit pattern layer 124 on the 1-3 insulating layer 113.

[0228] Next, as shown in Fig. 21, when the manufacture of the first substrate layer 100 is completed, a process of removing the carrier board CB can be performed. In addition, when the carrier substrate CB is removed, a process of etching and removing the first metal layer 610, which is a seed layer of the 1-1 circuit pattern layer 121 formed on the 1-1 insulating layer 111, can be performed. As described above, in the embodiment, the first substrate layer 100 can be manufactured by proceeding with the processes of Figs. 11 to 21.

[0229] Next, as shown in FIG. 22, the embodiment may perform a process of laminating a 2-1 insulating layer 211 on the 1-1 insulating layer 111 of the first substrate layer 100. At this time, the 2-1 insulating layer 211 may include an insulating material different from that of the 1-1 insulating layer 111. For example, the 2-1 insulating layer 211 may include a PID. The 2-1 insulating layer 211 may be disposed over the ETS pattern of the first substrate layer 100. Specifically, the 2-1 insulating layer 211 may be disposed over the first surface of the 1-1 insulating layer 111 and the first surface of the 1-1 circuit pattern layer 121.

[0230] Meanwhile, in the embodiment, a process of forming a carrier film CF may be performed on a surface opposite to a surface on which the 2-1 insulating layer 211 is disposed. For example, in the embodiment, the carrier film CF may be formed on a second surface of the 1-3 insulating layer 113 of the first substrate layer 100. The carrier film CF may protect the 1-3 insulating layer 113 and the 1-3 circuit pattern layer 123 during a manufacturing process of the second substrate layer 200 performed below.

[0231] 23, the embodiment may perform a process of exposing the 2-1 insulating layer 211. To this end, the embodiment may form a third mask 650 on the 2-1 insulating layer 211. At this time, the third mask 650 may include an opening (not shown) corresponding to an area where the 2-1 through electrode 231 is to be formed. Then, the embodiment may perform a process of exposing a partial area A of the 2-1 insulating layer 211 exposed through the opening of the third mask 650.

[0232] 24 , in the embodiment, a step of developing the region A can be performed, and a step of removing the partial region A can be performed. Then, in the embodiment, by removing the partial region A, the 2-1 through hole VH2 can be formed in the 2-1 insulating layer 211.

[0233] 25, in the embodiment, a third mask 650 may be formed on the 1-1 insulating layer 211, a plating process may be performed to fill the openings of the third mask 650, and a process may be performed to form the 2-1 through electrode 231 and the 2-1 circuit pattern layer 221. At this time, the manufacturing process of the 2-1 through electrode 231 and the 2-1 circuit pattern layer 221 may include the steps of sequentially forming the first metal layer 220-1 containing titanium, the second metal layer 220-2 containing copper, and the third metal layer 220-3 containing copper, as described above.

[0234] Next, the embodiment may perform a step of removing the third mask 650, as shown in FIG. 26. Next, the embodiment may perform a step of forming a 2-2 insulating layer 212 on the 2-1 insulating layer 211. Subsequently, the embodiment may perform a step of forming a 2-2 through electrode 232 and a 2-2 circuit pattern layer 222 on the 2-2 insulating layer 212. Next, the embodiment may perform a step of forming a 2-3 insulating layer 213 on the 2-2 insulating layer 212.

[0235] Next, in the embodiment, as shown in FIG. 27, a primary exposure and development process can be performed, and a process of forming a 2-3 through hole VH3 in the 2-3 insulating layer 213 can be performed.

[0236] Next, as shown in FIG. 28, the embodiment may perform a process of performing a secondary exposure and development process to form a pattern groove PG on the surface of the 2-3 insulating layer 213. At this time, the conditions of the primary exposure and development may be different from the conditions of the secondary exposure and development. For example, the primary exposure and development may be performed under conditions for forming a 2-3 through hole VH3 penetrating the 2-3 insulating layer 213. For example, the secondary exposure and development may be performed under conditions for forming a pattern groove PG having a certain depth on the surface of the 2-3 insulating layer 213. Meanwhile, the embodiment may simultaneously perform a process of forming the 2-3 through hole VH3 and the pattern groove PG using a mask (not shown) having a different transmittance for each region. And the pattern groove PG includes a portion corresponding to the pad 223P and a portion corresponding to the trace 223T1. And the pattern groove PG corresponding to the pad 223P may have a shape as described.

[0237] 29, a plating process is performed to fill the 2-3 through holes VH3 and the pattern grooves PG, thereby forming the outermost 2-3 through electrodes 233 and the 2-3 circuit pattern layer 223 of the second substrate layer 200. The 2-3 circuit pattern layer 223 may be an electrode portion including the pads 223P and the traces 223T1.

[0238] Next, the embodiment may perform a process of removing the carrier film CF formed on the underside of the first substrate layer 100, thereby forming a protective layer 140 including an opening on the second surface of the 1-3 insulating layer 113, as shown in FIG.

[0239] FIG. 31 is a diagram showing a semiconductor package according to the first embodiment.

[0240] Referring to FIG. 31, an embodiment may have a structure in which a plurality of semiconductor elements are mounted on the circuit board 300 of FIG.

[0241] For example, the semiconductor package 500 may include a first connection portion 410 disposed on a first pad portion 223P1 of a 2-3 circuit pattern layer 223 (e.g., an electrode portion) disposed on the outermost side of the second substrate layer 200. The semiconductor package 500 may also include a second connection portion 440 disposed on a second pad portion 223P2 of the 2-3 circuit pattern layer 223 disposed on the outermost side of the second substrate layer 200.

[0242] The first connecting portion 410 and the second connecting portion 440 may have the same shape as each other, or alternatively, may have different shapes from each other.

[0243] For example, the first connecting portion 410 and the second connecting portion 440 may have a hexahedral shape. For example, the cross section of the first connecting portion 410 and the second connecting portion 440 may include a quadrilateral shape. The cross section of the first connecting portion 410 and the second connecting portion 440 may include a rectangular shape or a square shape. For example, the first connecting portion 410 and the second connecting portion 440 may include a spherical shape. For example, the cross section of the first connecting portion 410 and the second connecting portion 440 may include a circular shape or a semicircular shape. For example, the cross section of the first connecting portion 410 and the second connecting portion 440 may include a partially or entirely rounded shape. The cross-sectional shape of the first connecting portion 410 and the second connecting portion 440 may be flat on one side and curved on the other side. The first connecting portion 410 and the second connecting portion 440 may be, but is not limited to, a solder ball.

[0244] The embodiment may include a first semiconductor element 420 disposed on the first connection portion 410. The first semiconductor element 420 may be a first processor chip. For example, the first semiconductor element 420 may be an application processor (AP) chip of a central processor (e.g., CPU), a graphic processor (e.g., GPU), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller. A terminal 425 of the first semiconductor element 420 may be electrically coupled to the first pad portion 223P1 via the first connection portion 410.

[0245] The embodiment may also include a second semiconductor element 450 disposed on the second connection unit 440. The second semiconductor element 450 may be a second processor chip. For example, the second semiconductor element 450 may be an application processor (AP) chip of a type different from that of the first semiconductor element 420, such as a central processor (e.g., CPU), a graphic processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, or a microcontroller. A terminal 455 of the second semiconductor element 450 may be electrically coupled to the second pad portion 223P2 via the second connection unit 440.

[0246] As an example, but not limited to, the first semiconductor device 420 may be a central processor chip and the second semiconductor device 450 may be a graphic processor chip.

[0247] Meanwhile, the first semiconductor element 420 and the second semiconductor element 450 may be disposed on the circuit board 300 with a first separation width D1. The first separation width D1 may be 150 μm or less. For example, the first separation width D1 may be 120 μm or less. For example, the first separation width D1 may be 100 μm or less.

[0248] Preferably, the first separation width D1 may be in the range of 60 μm to 150 μm. Preferably, the first separation width D1 may be in the range of 70 μm to 120 μm. Preferably, the first separation width D1 may be in the range of 80 μm to 110 μm. If the first separation width D1 is smaller than 60 μm, a problem may occur in the operational reliability of the first semiconductor element 420 or the second semiconductor element 420 due to mutual interference between the first semiconductor element 420 and the second semiconductor element 420. If the first separation width D1 is smaller than 60 μm, it may not be possible to arrange all of the wiring for connecting the first semiconductor element 420 and the second semiconductor element 420 in the space corresponding to the first separation width D1. If the first separation width D1 is larger than 150 μm, the distance between the first semiconductor element 420 and the second semiconductor element 420 increases, and signal transmission loss may increase. If the first gap width D1 is greater than 150 μm, the volume of the semiconductor package 500 may become large.

[0249] The semiconductor package 500 may include a first fillet layer 430 and a second fillet layer 460. The first fillet layer 430 may be disposed surrounding the first substrate layer 100 and the terminal 425 of the first semiconductor element 420. The first fillet layer 430 may prevent foreign matter (e.g., moisture) from penetrating into the space between the circuit board and the first semiconductor element 420. The second fillet layer 460 may be disposed surrounding the first substrate layer 100 and the terminal 455 of the second semiconductor element 420. The second fillet layer 460 may prevent foreign matter (e.g., moisture) from penetrating into the space between the circuit board and the second semiconductor element 420.

[0250] The semiconductor package 500 may include a molding layer 470. The molding layer 470 may be disposed to cover the first semiconductor element 420 and the second semiconductor element 420. For example, the molding layer 470 may be, but is not limited to, an epoxy mold compound (EMC) formed to protect the mounted first semiconductor element 420 and the second semiconductor element 420.

[0251] The molding layer 470 may be in direct contact with the first surface of the 2-3 insulating layer 213 disposed on the uppermost side of the circuit board. Here, the solder resist is not disposed on the first surface of the 2-3 insulating layer 213, so that the first surface of the 2-3 insulating layer 213 may be in direct contact with the molding layer 470. At this time, the molding layer 470 may have a low dielectric constant in order to enhance heat dissipation characteristics. For example, the dielectric constant Dk of the molding layer 470 may be 0.2 to 10. For example, the dielectric constant Dk of the molding layer 470 may be 0.5 to 8. For example, the dielectric constant Dk of the molding layer 470 may be 0.8 to 5. As a result, in the embodiment, the molding layer 470 has a low dielectric constant, so that the heat dissipation characteristics for the heat generated in the first semiconductor element 420 and / or the second semiconductor element 420 can be enhanced. Furthermore, in the embodiment, the electrode portion includes the dummy electrode 223D, so that the flatness of the molding layer 470 can be ensured, and further the flatness of the semiconductor package can be ensured.

[0252] Meanwhile, the semiconductor package 500 may include a third connection portion 480 disposed on the bottom side of the circuit board 300. The third connection portion 480 may be disposed on the second surface or the lower surface of the first to fourth circuit pattern layers 124 exposed through the protective layer 140.

[0253] FIG. 32 is a diagram showing a circuit board according to the second embodiment.

[0254] 32, in the circuit board 300a according to the second embodiment, the element mounting region R1 may further include a third mounting region MR3, as compared to the circuit board 300 according to the first embodiment.

[0255] For example, the circuit board 300 according to the first and second embodiments provides two mounting areas on which a plurality of semiconductor elements of different types are mounted.

[0256] Differently, the circuit board 300a according to the second embodiment can provide at least three mounting areas on which at least three semiconductor elements are mounted.

[0257] The circuit board 300a can include a first substrate layer 100a and a second substrate layer 200a.

[0258] The basic features of the first substrate layer 100a and the second substrate layer 200a are substantially the same as those of the first substrate layer 100 and the second substrate layer 200 in FIG. 1 or FIG. 2, and therefore a detailed description thereof will be omitted.

[0259] The element mounting region R1 of the second substrate layer 200a may include a first mounting region MR1 in which a first semiconductor element is mounted, a second mounting region MR2 in which a second semiconductor element of a type different from the first processor chip is mounted, a third mounting region MR3 in which a third semiconductor element is mounted, a first connecting region CR1 connecting the first mounting region MR1 and the second mounting region MR2, and a second connecting region CR2 connecting the first mounting region MR1 and the third mounting region MR3.

[0260] That is, the embodiment provides a circuit board 300a capable of mounting at least three semiconductor elements (e.g., multiple processor chips and at least one memory chip). This can be achieved by including a PID in the insulating layer constituting the second substrate layer 200a, thereby allowing the circuit pattern of the second substrate layer 200a to be ultra-fine.

[0261] The 2-3 circuit pattern layer 223 (eg, an electrode portion) included in the second substrate layer 200a of the embodiment includes a third pad portion 223P3 arranged in the third mounting region MR3.

[0262] In addition, the 2-3 circuit pattern layer 223 included in the second substrate layer 200a of the embodiment may include a trace 223T2 in the second connection region CR2 connecting the first pad portion 223P1 and the third pad portion 223P3.

[0263] In this case, in one embodiment, the trace 223T1 in the first connection region CR1 may have the same line width or spacing as the trace 223T2 in the second connection region CR2.

[0264] Also, in other embodiments, the traces 223T1 in the first connection region CR1 may have a different line width or spacing than the traces 223T2 in the second connection region CR2. That is, the traces 223T1 in the first connection region CR1 must be ultra-fine as described above to connect the first and second semiconductor elements. In contrast, the second connection region CR2 connects the first and third semiconductor elements. In this case, the number of connection wires in the second connection region CR2 is less than the number of connection wires in the first connection region CR1. As a result, the traces 223T2 in the second connection region CR2 may not require as ultra-fine line width or spacing as the traces 223T1 in the first connection region CR1.

[0265] This allows the traces 223T2 in the second coupling region CR2 to have a line width and spacing greater than the line width and spacing of the traces 223T1 in the first coupling region CR1.

[0266] FIG. 33 is a diagram showing a semiconductor package according to the second embodiment.

[0267] 33, a semiconductor package 500a further includes a third semiconductor device compared to the semiconductor package 500 according to the first embodiment.

[0268] Specifically, the semiconductor package 500a includes a third semiconductor device 490 disposed side by side with the first semiconductor device 420 at a certain distance from the first semiconductor device 420. In this case, the third semiconductor device may have a multi-layer structure with an adhesive layer 492 sandwiched therebetween. In addition, the semiconductor package 500a may include a connecting member 494 connected to the third semiconductor device 490. The connecting member 494 may be, but is not limited to, a wire.

[0269] The thickness T2 of the semiconductor package 500a of the embodiment may be smaller than the thickness of the semiconductor package of the comparative example. The thickness T2 of the semiconductor package 500a may be 95% of the thickness of the semiconductor package of the comparative example. The thickness T2 of the semiconductor package 500a may be 90% of the thickness of the semiconductor package of the comparative example. The thickness T2 of the semiconductor package 500a may be 85% of the thickness of the semiconductor package of the comparative example.

[0270] For example, the thickness T2 of the semiconductor package 500a may be less than 1000 μm. For example, the thickness T2 of the semiconductor package 500a may be less than 900 μm. For example, the thickness T2 of the semiconductor package 500a may be less than 850 μm.

[0271] The circuit board of the embodiment includes an electrode portion connected to a semiconductor element. The electrode portion includes a pad and a trace. In this case, the pad has a shape in which a region adjacent to the trace is cut out in a circle having a specific radius of curvature. For example, the periphery of the upper surface of the pad includes a curved portion having a specific radius of curvature and a straight portion connected to the curved portion. The straight portion can be said to be a first portion around the upper surface of the pad, and the curved portion can be said to be a second portion around the pad. The first portion is disposed adjacent to the trace. The extension direction of the straight line of the first portion can be the same direction as or parallel to the extension direction of the trace. Thus, the embodiment can secure a placement space for a plurality of traces between a plurality of pads spaced apart in a first direction D1 through changing the periphery shape of the upper surface of the pad. Thus, the embodiment can form a stable trace between a plurality of pads spaced apart in the first direction D1, thereby improving the physical and electrical reliability of the circuit board.

[0272] Meanwhile, the pads of the embodiment are divided into a plurality of groups. For example, the pads include a first group of pads and a second group of pads. In this case, the first group of pads is provided in a relatively dense area, and thus has a shape in which an area adjacent to the trace is cut off in a circle having the specific radius of curvature. In contrast, the second group of pads is provided in a relatively sparse area, and thus has a circular shape having a planar area larger than that of the first group of pads. This allows the embodiment to stably mount a semiconductor device, and thus allows the semiconductor device to stably operate.

[0273] Also, the circuit board of the embodiment includes a first substrate layer and a second substrate layer. The second substrate layer includes a PID, and can include a fine pattern of line widths and intervals corresponding to a plurality of different semiconductor elements mounted on the circuit board. As a result, the embodiment can mount a plurality of different semiconductor elements on one circuit board, and can easily connect the plurality of semiconductor elements within a limited space. Therefore, the embodiment can separate the plurality of semiconductor elements according to their functions, thereby improving the performance of the application processor. Furthermore, the embodiment can reduce the volume of the semiconductor package by easily connecting the plurality of semiconductor elements within a limited space, thereby slimming down the electronic device.

[0274] In addition, the embodiment may minimize the distance between the first and second semiconductor elements disposed on the circuit board, thereby minimizing loss of signals transmitted between the first and second semiconductor elements and thereby improving product reliability.

[0275] Furthermore, in the embodiment, a plurality of semiconductor elements can be mounted side by side on one substrate, and thus the thickness of the semiconductor package can be significantly reduced compared to the comparative example.

[0276] Furthermore, the embodiment does not require the connection of multiple circuit boards to connect multiple semiconductor elements, which improves process convenience and reliability of electrical connection.

[0277] Meanwhile, when the circuit board having the above-mentioned inventive features is used in IT devices and home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when the circuit board having the features of the present invention functions as a semiconductor package, it can safely protect the semiconductor chip from external moisture and contaminants, and can solve the problems of leakage current or electrical short circuit between terminals, or electrical open of terminals supplying power to the semiconductor chip. In addition, when it functions as a signal transmission, it can solve the noise problem. As a result, the circuit board having the above-mentioned inventive features can maintain stable functions of IT devices and home appliances, and the entire product and the circuit board to which the present invention is applied can form functional unity or technical interrelationship with each other.

[0278] When the circuit board having the above-mentioned features of the present invention is used in a transportation device such as a vehicle, it can solve the problem of distortion of signals transmitted to the transportation device, safely protect the semiconductor chip that controls the transportation device from the outside, and solve the problems of leakage current or electrical short circuit between terminals, or electrical open of terminals supplying power to the semiconductor chip, thereby further improving the stability of the transportation device. Therefore, the transportation device and the circuit board to which the present invention is applied can be functionally integrated or technically linked with each other.

[0279] The features, structures, effects, etc. described in the above embodiments are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person having ordinary skill in the art to which the embodiment belongs. Therefore, the contents related to such combinations and modifications should be interpreted as being included in the scope of the embodiment.

[0280] The above description focuses on the embodiments, but these are merely illustrative and do not limit the embodiments. Those skilled in the art will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For example, each component specifically illustrated in the embodiments can be modified and implemented. Differences related to such modifications and applications should be interpreted as being included in the scope of the embodiments defined in the appended claims.

Claims

1. An insulating layer; an electrode portion disposed on the insulating layer; the electrode portion includes a plurality of pads and traces connecting the plurality of pads; The plurality of pads include: A first pad including a curved portion having a specific radius of curvature around an upper surface thereof and a straight portion connected to the curved portion; a second pad, the periphery of which does not include a straight line portion on an upper surface opposite the curved portion of the first pad.

2. the first pad has a width in a second direction parallel to the linear portion and a width in a first direction perpendicular to the second direction, The semiconductor package according to claim 1 , wherein the width in the first direction is smaller than the width in the second direction.

3. The width of the first pad in the negative first direction from the center of the radius of curvature is The semiconductor package according to claim 1 , wherein the radius of curvature is smaller than each of widths of the first pad in the +first direction, the -second direction, and the +second direction from the center of the radius of curvature.

4. 4. The semiconductor package of claim 3, wherein widths of the first pad from the center of the radius of curvature in a +first direction, a -second direction, and a +second direction are the same as each other.

5. The width of the first pad in the first direction is The semiconductor package according to claim 1 , wherein the width of the first pad in the second direction is in the range of 80% to 95%.

6. The width in the first direction is in the range of 16 μm to 76 μm, The semiconductor package according to claim 5 , wherein the width in the second direction is in the range of 20 μm to 80 μm.

7. The line width of the trace is in the range of 1 μm to 6 μm; 3. The semiconductor package according to claim 1, wherein the spacing between the pad and the trace or the spacing between multiple traces is in the range of 1 μm to 6 μm.

8. The semiconductor package of claim 1 , wherein the straight portion of the first pad is parallel to an extension direction of a trace connected to the second pad.

9. the first and second pads are spaced apart from each other in the first direction; The trace may be The semiconductor package of claim 7 , extending in the second direction between the first and second pads.

10. Between the first pad and the second pad, The semiconductor package of claim 9 , wherein at least two traces are disposed extending in the second direction and spaced apart from each other in the first direction.

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