N-polar device including a depletion layer with improved conductivity - Patents.com

Abstract

Described herein is a lateral III-N (e.g., GaN) device having a III-N depletion layer. The circuit includes a depletion mode transistor with a source connected to a drain of an enhancement mode transistor. The gate of the depletion mode transistor and the gate of the enhancement mode transistor are biased at zero volts, and the drain of the depletion mode transistor is biased at a positive voltage to block current flow in the forward direction. The bias of the gate of the enhancement mode transistor is then changed to a first voltage greater than the threshold voltage of the enhancement mode transistor, allowing a first current to flow through the channel in the forward direction. The bias of the gate of the depletion mode transistor is then changed to a second voltage, allowing a second current to flow through the channel in the forward direction, the second current being greater than the first current.

Description

[Technical field]

[0001] The disclosed technology relates to semiconductor devices, and in particular to III-nitride transistors and switches. [Background technology]

[0002] Currently, typical power semiconductor devices, including devices such as transistors, diodes, power MOSFETs, and insulated gate bipolar transistors (IGBTs), are fabricated using silicon (Si) semiconductor materials. More recently, wide bandgap materials (SiC, III-N, III-O, diamond) have been considered for power devices due to their superior properties. III-Nitride or III-N semiconductor devices, such as gallium nitride (GaN) devices or AlGaN / GaN HEMT transistors, are now emerging as attractive candidates for carrying large currents, supporting high voltages, and offering very low on-resistance and fast switching times.

[0003] FIG. 1 shows a cross-sectional view of a group III-polar (i.e., Ga-polar) lateral III-N device 100. The device 100 includes a source contact 21, a drain contact 22, a gate contact 23, and access regions 82 and 83. As used herein, the "access region" of the device refers to the two regions between the source and gate contacts of the device, and between the gate and drain contacts, i.e., regions 82 and 83 in FIG. 1. The access region 82 on the source side of the gate is typically referred to as the source-side access region, and the access region 83 on the drain side of the gate is typically referred to as the drain-side access region. As used herein, the "gate region" 81 of the device refers to the portion of the transistor between the two access regions 82 and 83 in FIG. 1. The gate module of the device refers to the portion of the layers and materials of the device in or adjacent to the gate region 81 of the device, in which the electric field is modulated by application of a gate voltage to modulate the channel conductivity in the gate region of the device. The device channel refers to the conductive region that serves as the current path of the device between the source and drain contacts when the device is biased in the on-state. The source contact 21 and the drain contact 22 are electrically connected to a lateral two-dimensional electron gas (2DEG) channel 19 (shown by dashed lines in FIG. 1 ) induced in the III-N channel layer 12 adjacent the interface between the III-N barrier layer 13 and the III-N channel layer 12, which serves as the device channel. The III-N material structure of the device 100 includes a III-N buffer layer 11 formed on a suitable substrate 10. The III-N channel layer 12 is formed on the III-N buffer layer, and the III-N barrier layer 13 is formed on the III-N channel layer 12. The band gap of the III-N barrier layer 13 is larger than the band gap of the III-N channel layer 12. The source contact 21, the drain contact 22, and the gate contact 23 are all formed on the side of the III-N material structure opposite the substrate, which characterizes the device as a lateral device. An insulating layer 18 is formed on the surface of the III-N material structure between the source 21 and the drain 22.If the device 100 is a depletion mode device, a portion of the insulator layer 18 may be formed between the gate contact 23 and the top of the III-N material structure, as shown in FIG. 1. The device 100 includes a field plate 26 that extends onto the insulator layer 18 in the drain side access region 83 toward the drain 22 and is connected to the gate 23. The field plate 26 may help manage the profile of the electric field in the drain side access region during operation of the device. However, when the field plate 26 is the primary method used to control the electric field, high electric field peaks may occur at the corners of the field plate, resulting in poor electric field uniformity across the drain side access region. As a result, a large gate-drain spacing is required to fabricate a reliable III-N transistor such as the device 100.

[0004] High-voltage Ga-polar III-N transistors, such as device 100 of Figure 1, are beginning to be commercialized, but so far, designing and manufacturing III-N transistors with high performance has proven difficult. Design improvements are needed to improve device size, efficiency, and power characteristics to accelerate market adoption. Summary of the Invention

[0005] Described herein is a lateral III-N (e.g., GaN) device having an improved conductivity III-N depletion layer (also called a charge compensation layer), where the III-N material is formed in an N-polar orientation. The device structure can be configured to have stable threshold voltages, low leakage currents, and high breakdown voltages, while maintaining a small separation between the gate and drain, ensuring low device on-resistance. Details of one or more embodiments of the subject matter described herein are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages of the subject matter will become apparent from the specification, drawings, and claims.

[0006] In a first aspect, a method of operating a circuit is described, the method comprising a depletion mode transistor having a channel and an enhancement mode transistor, the source of the depletion mode transistor being connected to the drain of the enhancement mode transistor. The method includes biasing the gate of the depletion mode transistor and the gate of the enhancement mode transistor at zero volts and biasing a positive voltage to the drain of the depletion mode transistor to block voltages in a forward direction. The bias of the gate of the enhancement mode transistor is then changed to a first voltage greater than a threshold voltage of the enhancement mode transistor, allowing a first current to flow through the channel in a forward direction. The bias of the gate of the depletion mode transistor is then changed to a second voltage, allowing a second current greater than the first current to flow through the channel in a forward direction.

[0007] In a second embodiment, a III-N device is described. The III-N device includes a III-N layer structure including a III-N channel layer and a III-N barrier layer, where a compositional difference between the III-N channel layer and the III-N barrier layer induces a 2DEG channel therein. The device further includes a source contact, a gate contact, and a drain contact. The III-N device is characterized as a depletion mode device. The 2DEGB channel has a first on-resistance between the source and drain contacts when the gate contact is biased at zero voltage, and the 2DEG channel has a second on-resistance between the source and drain contacts when the gate contact is biased at a positive voltage, where the second on-resistance is less than the first on-resistance.

[0008] In a third embodiment, a III-N device is described. The III-N device includes a substrate and a III-N layer structure. The III-N layer structure includes a buffer layer, a first channel layer between a first III-N barrier layer and a first p-type III-N depletion layer, the first III-N channel layer includes a first 2DEG channel formed therein. The device further includes a second III-N barrier layer between a second III-N channel layer and a second p-type III-N depletion layer, the second III-N channel layer includes a second 2DEG channel formed therein. The second 2DEG channel is between the first 2DEG channel and the substrate. The device includes source and drain electrodes electrically connected to the first and second 2DEG channels, respectively, and a gate electrode between the source and drain, the gate being on the III-N layer structure. The second p-type depletion layer is formed between the buffer layer and the second III-N barrier layer, and the first p-type III-N depletion layer and the second p-type depletion layer are electrically connected to the gate electrode.

[0009] Each of the electronic devices, transistors, and methods described herein may include one or more of the following features. The method may include removing a bias from a gate of the depletion mode transistor, removing a bias from a gate of the enhancement mode transistor, and blocking current flow in the forward direction. The second current may be substantially greater than the first current, for example, the second current may be at least 25% greater than the first current. The second voltage may be less than or equal to the first voltage. A time between changing the gate of the enhancement mode transistor to the first voltage and changing the gate of the depletion mode transistor to the second voltage is less than 100 ns. The channel has an on-resistance, and when the drain of the depletion mode transistor is biased with the second voltage, the on-resistance of the channel may be at least 25% lower than when the gate of the depletion mode transistor is biased with zero volts. The depletion mode transistor may be an N-polarity III-N HEMT transistor. The depletion mode transistor may include a p-type depletion layer formed between the gate and the channel. When the gate of the depletion-mode transistor is biased with a second voltage, the capacitive conduction modulation between the p-type depletion layer and the channel is at least 1e 13 cm -2The first voltage can be greater than +5V and the second voltage can be less than +5V and greater than 0V. The first on-resistance can be greater than 300 Ω / sq and the second on-resistance can be less than 150 Ω / sq. The first p-type III-N depletion layer and the second p-type III-N depletion layer are physically separated from the source and drain electrodes. The dopant concentration in the first p-type III-N depletion layer is such that the p-type doping areal density in the first p-type III-N layer is in the range of 10-150% of the surface sheet charge density of the mobile charge in the first 2DEG channel. The dopant concentration in the second p-type III-N depletion layer is such that the p-type doping areal density in the second p-type III-N layer is in the range of 10-150% of the surface sheet charge density of the mobile charge in the second 2DEG channel. The mobile charge in the first 2DEG channel is greater than the mobile charge in the second 2DEG channel. The device can include more than two 2DEG channels, each 2DEG channel having an associated p-type III-N layer, and each associated p-type depletion layer having a p-type doping areal density in the range of 10-150% of the areal sheet charge density of the mobile charge in the associated 2DEG channel.

[0010] As used herein, the term Group III nitride or III-N materials, layers, devices, etc., refers to materials having a stoichiometric formula B w Al x In y Ga z III-N refers to a material or device composed of III-N compound semiconductor materials, where w+x+y+z is approximately 1 and 0≦w≦1, 0≦x≦1, 0≦y≦1, 0≦z≦1. III-N materials, layers, or devices can be formed or prepared either by growing them directly on a suitable substrate (e.g., by metalorganic chemical vapor deposition), or by growing them on a suitable substrate, peeling them off from the original substrate, and bonding them to another substrate.

[0011] As used herein, two or more contacts or other items, e.g., conductive channels or components, are said to be "electrically connected" when they are connected by a material that is sufficiently conductive to ensure that the electrical potential at each of the contacts or other items is the same, e.g., is intended to always be approximately the same under any bias conditions.

[0012] As used herein, "blocking voltage" refers to the ability of a transistor, device, or component to prevent significant current, such as current exceeding 0.001 times the operating current during normal conduction. The operating current is what flows through the transistor, device, or component when a voltage is applied across the transistor, device, or component. In other words, when the transistor, device, or component is blocking an applied voltage, the total current passing through the transistor, device, or component does not exceed 0.001 times the operating current during normal conduction. Devices with off currents greater than this value exhibit high losses and low efficiency and are typically not suitable for many applications, especially power switching applications.

[0013] As used herein, a "depletion mode device" refers to a transistor that has a negative threshold voltage and is considered to be in the "on" state when the gate of the depletion mode transistor is biased greater than the negative threshold voltage, thereby causing the device to be on when the gate is biased at zero volts. An "enhancement mode device" refers to a transistor that has a positive threshold voltage and is considered to be in the "off" state when the gate of an enhancement mode transistor is biased at zero volts. The "on-resistance" of a transistor is the resistance at which a transistor is in the on-state (i.e., R DS(ON) ) the resistance between the source and drain contacts of a transistor when it is biased at

[0014] As used herein, a "high voltage device", e.g., a high voltage switching transistor, HEMT, bidirectional switch, or four quadrant switch (FQS), is an electronic device that is optimized for high voltage applications. That is, when the device is off, it is capable of blocking high voltages, such as about 300 V or more, about 600 V or more, or about 1200 V or more, and when the device is on, it has an on-resistance (R) that is low enough for the application in which the device is used. ON ), e.g., undergoes sufficiently low conduction losses when substantial current passes through the device. A high voltage device is capable of blocking at least a voltage equal to the high voltage source or maximum voltage in the circuit in which it is used. A high voltage device is capable of blocking 300V, 600V, 1200V, 1700V, 2500V, 3300V, or other suitable blocking voltages required by the application. In other words, a high voltage device is capable of blocking between 0V and at least V max where V max is the highest voltage that can be supplied by the circuit or power supply, and V max is, for example, 300V, 600V, 1200V, 1700V, 2500V, 3300V, or other suitable blocking voltage required by the application. For a bidirectional or four-quadrant switch, the blocked voltage is the voltage when the switch is off (V max ), which is less than a certain polarity, and current can be in either direction when the switch is on.

[0015] As used herein, a "III-N device" is a device based on or essentially comprising III-N materials, including III-N heterostructures. III-N devices can be designed to operate as transistors or switches, where the state of the device is controlled by a gate terminal, or as two terminal devices that block current in one direction and conduct in the other direction without a gate terminal. III-N devices can be high-voltage devices suitable for high-voltage applications. In such high-voltage devices, when the device is biased off (e.g., when the voltage on the gate relative to the source is less than the device threshold voltage), the device is at least capable of supporting all source-drain voltages up to the high voltage in the application in which the device is used, e.g., 100V, 300V, 600V, 1200V, 1700V, 2500V, or more. When a high-voltage device is biased (e.g., when the voltage on the gate relative to the source or associated power terminal is greater than the device threshold voltage), the device can conduct substantial current at low on-voltages (i.e., low voltages between the source and drain terminals or between the opposite power terminals). The maximum allowable on-voltage is the maximum on-state voltage that can be sustained in the application in which the device is used.

[0016] As used herein, a "III-polar" or "group III-polar" III-N material is a III-N material whose group III face (i.e., the [0 0 0 1] face) is opposite the substrate on which the material is grown. In a "III-polar" or "group III-polar" lateral III-N device, at least some of the device contacts (e.g., source and / or drain contacts) are typically formed on the [0 0 0 1] face (e.g., opposite the [0 0 0 -1] face) of the III-N material.

[0017] As used herein, an "N-polar" III-N material is a III-N material whose nitrogen face (i.e., the [0 0 0 -1] face) is opposite the substrate on which the material is grown. In an "N-polar" lateral III-N device, at least some of the device contacts (e.g., source and / or drain contacts) are typically formed on the [0 0 0 -1] face (e.g., opposite the [0 0 0 1] face) of the III-N material.

[0018] As used herein, a "regrowth" III-N layer structure or III-N material structure refers to an additional material deposition process performed after a previous material deposition process. Between the subsequent growth and regrowth processes, the device can be removed from the deposition tool and the vacuum environment can be interrupted. Thus, the regrown III-N material structure may require a separate insertion into the III-N material structure deposition device from the initial insertion of the III-N material structure. For example, the regrown III-N layer may be deposited after removal of at least a portion of the initial III-N material structure. The removal of the portion of the initial III-N material structure is typically performed in an environment external to the primary III-N material structure deposition device.

[0019] The terms "above," "below," "between," and "on" as used herein refer to the relative position of one layer with respect to another layer. Thus, for example, a layer disposed above or below another layer may be in direct contact with the other layer or may have one or more intervening layers. Additionally, a layer disposed between two layers may be in direct contact with the two layers or may have one or more intervening layers. In contrast, a first layer that is "on" a second layer is in contact with that second layer. Additionally, the relative positions of one layer with respect to another layer are provided assuming that operations are performed with respect to the substrate without consideration of the absolute orientation of the substrate.

[0020] The details of one or more disclosed implementations of the subject matter described herein are set forth in the accompanying drawings and the following description. Additional features and variations may also be included in the implementations. Other features, aspects, and advantages will become apparent from the description, drawings, and claims. [Brief description of the drawings]

[0021] [Figure 1] FIG. 1 is a cross-sectional view of a prior art Ga-polar III-N device.

[0022] [Diagram 2] FIG. 1C is a cross-sectional view of a depletion-mode N-polarity III-N device with a III-N depletion layer.

[0023] [Figure 3A] FIG. 1C is a cross-sectional view of a depletion-mode N-polar III-N device having multiple III-N depletion layers. [Figure 3B] FIG. 1C is a cross-sectional view of a depletion-mode N-polar III-N device having multiple III-N depletion layers. [Figure 3C] FIG. 1C is a cross-sectional view of a depletion-mode N-polar III-N device having multiple III-N depletion layers. [Figure 3D] FIG. 1C is a cross-sectional view of a depletion-mode N-polar III-N device having multiple III-N depletion layers.

[0024] [Figure 4A] 1 is an alternative embodiment of a III-N device having multiple depletion layers. [Figure 4B] 1 is an alternative embodiment of a III-N device having multiple depletion layers. [Figure 4C] 1 is an alternative embodiment of a III-N device having multiple depletion layers.

[0025] [Figure 5A] FIG. 1 is a schematic circuit diagram of a hybrid III-N device.

[0026] [Figure 5B] FIG. 1 is a logic block diagram showing a gate driving method.

[0027] [Figure 5C] FIG. 5B is a waveform diagram used to switch the hybrid device of FIG. 5A.

[0028] [Figure 5D] FIG. 1 is a schematic circuit diagram of a hybrid III-N device.

[0029] [Figure 6A] FIG. 1C is a cross-sectional view of an enhancement mode N-polarity III-N device with III-N depletion layer. [Figure 6B] FIG. 1C is a cross-sectional view of an enhancement mode N-polarity III-N device with III-N depletion layer.

[0030] [Figure 7] FIG. 1C is a cross-sectional view of a bidirectional III-N device with III-N depletion layers.

[0031] [Figure 8A] FIG. 1 is a schematic diagram of a two-way hybrid III-N device.

[0032] [Figure 8B] FIG. 8B is a waveform diagram used to switch the bidirectional hybrid device of FIG. 8A. [Figure 8C] FIG. 8B is a waveform diagram used to switch the bidirectional hybrid device of FIG. 8A.

[0033] [Figure 9] FIG. 1 is a cross-sectional view of an N-polarity III-N diode with a III-N depletion layer.

[0034] [Figure 10] FIG. 1C is a cross-sectional view of a depletion-mode Ga-polar III-N JFET device without a gate dielectric layer. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0035] Described herein are lateral III-N devices such as AlGaN / GaN HEMTs. These devices have a III-N layer used as a channel charge depletion layer (also called a charge compensation layer), and the III-N material structure of the device is grown with an N-polar (i.e., N-face or nitrogen-polar) orientation, such as the [0 0 0 -1] orientation, where the bracket notation indicates the Miller index orientation of the material lattice structure. Specifically, the III-N depletion layer can partially or completely deplete some (or all) of the 2DEG channel charge in the access region of the transistor when the transistor's gate is biased with respect to the source at a voltage below a certain value (e.g., -5V, -10V, or -20V), but not partially or completely deplete while the transistor is biased on (e.g., when the transistor's gate is biased with respect to the source at a similar voltage above 0V). Such a structure can realize compact transistors with very high breakdown voltage while maintaining a low on-resistance.

[0036] A typical III-N high electron mobility transistor (HEMT) and related devices, such as device 100 of FIG. 1, is formed on III-nitride material grown in a group III polar (e.g., Ga polar) orientation, such as the [0 0 0 1] (C-face) orientation, as shown in FIG. 1. That is, the source, gate, and drain contacts of the HEMT are formed on the group III face (e.g., [0 0 0 1] face) of the III-N material layer, which is typically on the opposite side of the III-N material layer from the substrate on which the III-N layer is formed. Alternatively, III-N HEMTs can be formed on III-nitride material grown in an N-polar (i.e., N-face or N-polar) orientation, such as the [0 0 0 -1] orientation. In this case, the source, gate, and drain contacts of the HEMT are formed on the N face (e.g., [0 0 0 -1] face) of the III-N material layer. N-polar III-N materials have an opposite polarization field than group-III-polar III-N materials and therefore can enable the implementation of III-N devices that cannot be fabricated using group-III-polar structures. In addition, N-polar III-N devices have demonstrated superior electrical properties compared to similarly sized group-III-polar devices, including lower static and dynamic on-resistance, higher current density, and higher power density.

[0037] III-N devices with charge depletion layers may be advantageous using N-polar III-N materials over Ga-polar III-N materials for at least the following reasons. First, when used in N-polar III-N devices, the channel depletion layer does not have a significant effect on the mobility and charge density of the 2DEG channel between the source and drain electrodes compared to Ga-polar III-N devices. Thus, the 2DEG sheet resistance of N-polar III-N devices can be reduced even with the channel depletion layer formed above the 2DEG channel (e.g., less than 450 Ω / sq, or less than 300 Ω / sq) required for improved device on-resistance. Second, N-polar III-N materials have high dopant ionization efficiency (e.g., the ratio between the hole concentration and the acceptor concentration in the p-type layer is 10% or more or 50% or more), high hole mobility (e.g., 10 cm), which are essential for fast transient times (turn on and off) and small switching losses, as described in the following figures. 2 / Vs) and low contact resistance (e.g., 1 Ω cm 2 Less than or equal to 10 -3 Ωcm 2 In addition, the N-polarity material structure offers the possibility to integrate a high voltage charge depletion module with a normally-off enhancement mode gate module and a p-type body (as further described in FIG. 6A).

[0038]

[0039] Referring to FIG. 2, an N-polarity depletion mode III-N device 200 is shown. The III-N device 200 includes a III-N buffer layer 11 (e.g., GaN or AlGaN) grown on a suitable substrate 10, which can be, for example, silicon (Si), silicon carbide (SiC), sapphire, AlN, or GaN. The substrate can be electrically conductive (e.g., p-type Si), electrically semi-insulating (e.g., SiC), or electrically insulating (e.g., sapphire). The substrate can be thinned, for example, to a thickness of less than 200 μm, to improve heat dissipation. The substrate can have a lattice constant and / or thermal expansion coefficient similar (e.g., within 10%) or different from that of any material layer of the III-N structure. If the lattice constants and / or thermal expansion coefficients between the substrate and the III-N layer are different, a nucleation and / or stress relaxation management layer can be introduced between the substrate 10 and the buffer layer 11 (not shown). The substrate 10 can be either floating (i.e., no fixed potential) or grounded (i.e., the substrate potential is fixed to the same voltage as the source). In some implementations, the substrate 10 can be omitted.

[0040] The buffer layer 11 can be made insulating or substantially free of unintended n-type mobile carriers by including dislocations or point defects in the layer or by doping the layer with compensating elements such as Fe, C, and / or Mg. The buffer layer can have a substantially uniform composition throughout, or the composition can vary. For example, in some implementations, the buffer layer is compositionally graded, such as by grading the aluminum composition along a vertical axis within the buffer layer. The buffer layer 11 can be substantially thicker than any of the other III-nitride layers in the structure. For example, the buffer layer 11 can have a thickness that is at least 5 times, but typically at least 10 times, the combined thickness of the III-N layers between the buffer layer 11 and the gate 23. N-polar III-N devices may allow for a thinner buffer layer 11 than Ga-polar III-N devices due to growth conditions that may result in a higher quality nucleation layer and better dislocation management in the buffer layer 11 on a foreign substrate.

[0041] The III-N device 200 further includes a III-N back barrier layer 14, e.g., AlxGa1-xN, above the III-N buffer layer 11, and a III-N channel layer 15, e.g., unintentionally doped (UID) GaN, above the III-N back barrier layer 14. The band gap of the III-N back barrier layer 14 is larger than the band gap of the III-N channel layer 15. The III-N channel layer 15 has a different composition than the III-N back barrier layer 14, and the respective thicknesses and compositions of the III-N back barrier layer 14 and the III-N channel layer 15 are selected such that a conductive layer of electrons is induced in the III-N channel layer 15. The interface between the III-N back barrier layer 14 and the III-N channel layer 15 may be abrupt. In this case, a conductive two-dimensional electron gas (2DEG) channel 19 (shown by the dashed line in FIG. 2) is induced in the III-N channel layer 15 adjacent to the interface between layers 14 and 15. The composition of the III-N back barrier layer 14 and the III-N channel layer 15 may be constant or may vary throughout. For example, layer 14 may have a first portion that is a graded AlGaN portion with increasing Al concentration (e.g., having the lowest Al concentration on the side closest to the substrate) and a second AlGaN portion that has a constant Al concentration.

[0042] In another example, the III-N back barrier layer has a first portion that is n-type GaN or AlGaN and a second portion that is undoped AlGaN. The III-N back barrier layer 14 can include a first portion (near the substrate) that is an n-type III-N portion, a second portion above the first portion that is a graded III-N portion (e.g., graded in aluminum composition), and a third portion above the second portion that has a constant composition. Additionally, the graded or n-type portion of the III-N back barrier layer 14 can be doped with Si or any other dopant that prevents the formation of holes. The doping concentration per unit area can range from 1e11 donor / cm2 to 1e14 donor / cm2. Preferably, the doping concentration is selected such that the equivalent areal density (expressed in cm-2) is similar (e.g., within ±50%) to the surface charge density in the 2DEG channel.

[0043] Different portions of the III-N back barrier layer 14 can act to prevent the formation of a parasitic two-dimensional hole gas near the bottom of the back barrier layer. For example, if holes accumulate near the bottom of the back barrier, the device may suffer from parasitic leakage current and threshold voltage instability due to hole trapping. If the doping of the layer is too low, parasitic hole accumulation can occur, but if the doping is too high, parasitic electron accumulation can occur near the bottom of the back barrier layer 14. Mobile carriers (either holes and / or electrons) can be reduced in the back barrier layer 14 and / or buffer layer 11 by adding impurities (such as carbon, other amphoteric dopants or deep level traps) that can capture excess mobile carriers and pin (stabilize) the Fermi level in the band gap (e.g., EV+0.5 eV, EV+0.9 eV, EC-0.6 eV, etc.) far enough away from both the valence and conduction bands.

[0044] The back barrier layer 14 may have a thickness of 5 nm to 50 nm. The back barrier layer 14 may have a thickness greater than 15 nm. The channel layer 15 may have a thickness of 2 nm to 300 nm. The channel layer 15 may have a thickness greater than 15 nm. The thickness of the channel layer 15 may determine the threshold voltage (VTH) of the device. For example, a channel layer 15 thickness less than 30 nm may result in a threshold voltage greater than -10 V. Minimizing the negative threshold voltage of a depletion mode device is useful when used in a cascode configuration with low voltage enhancement mode FETs to prevent the enhancement mode FETs from entering avalanche mode during the off state or being biased outside the safe operating area and suffering thermal runaway during a short circuit event. Also, a 0.5 to 5 nm AlXGa1-xN intermediate layer (x>50%, not shown) may be disposed between the barrier layer 14 and the channel layer 15. This AlXGa1-xN intermediate layer can help increase the polarization charge and reduce electron scattering at the interface between the III-N back barrier layer 14 and the III-N channel layer 15, improving the 2DEG channel sheet resistance. For example, the 2DEG channel sheet resistance can be between 500 Ω / sq and 150 Ω / sq. Preferably, the 2DEG channel sheet resistance is less than 400 Ω / sq.

[0045] In another example, a portion of the III-N channel layer 15 can have bulk n-type conductivity produced by either impurity doping (e.g., silicon incorporation) and / or polarization doping. To achieve polarization doped n-type conductivity, the composition of the III-N channel layer 15 is graded so that the gradient of the polarization field is negative in the [000-1] direction. For example, the III-N channel layer 15 in the III-N device 200 can be formed of AlyGa1-yN (0≦y≦1), where on the side adjacent to the III-N back barrier layer 14, y is equal to the y in the III-N back barrier layer 14, and y decreases (e.g., continuously decreases) from the side adjacent to the III-N back barrier layer 14 to the opposite side of the III-N back barrier layer 14. Alternatively, the III-N channel layer 15 can be formed of InyGa1-yN (0≦y≦1), where y increases (e.g., increases continuously) from the side adjacent to the III-N back barrier layer 14 to the opposite side of the III-N back barrier layer 14.

[0046] The III-N depletion layer 16 is formed above at least a portion of the III-N channel layer 15 and is used as a channel charge depletion layer (also called a charge compensation layer). Specifically, the III-N depletion layer can partially or completely deplete some (or all) of the 2DEG channel charge in the access region of the transistor when the gate of the transistor is biased with respect to the source at a voltage lower than some negative value (e.g., VGS=-5V, -10V, or -20V), but not partially or completely deplete while the transistor is biased higher than some value (e.g., VGS=-1V, 0V, or higher than 0V). The III-N depletion layer can act as a charge compensation layer that compensates some or all of the ionized positive charge in the channel layer 15 and the AlGaN back barrier layer 14 with ionized negatively charged acceptors when the device is biased off, and does not affect the 2DEG charge when the device is biased on.

[0047] As shown in FIG. 2, the III-N depletion layer 16 is above the channel layer in the gate region 81 and can extend laterally into the drain-side access region 83 between the gate contact 23 and the drain contact 22. The III-N depletion layer includes a first end and a second end, the first end adjacent to the source contact 21 and the second end adjacent to the drain contact 22. The III-N depletion layer 16 is electrically isolated from the drain contact 22 via a lateral isolation 25. The spacing from the second end of the depletion layer 16 to the drain contact 22 can be between 0.5 μm and 10 μm, preferably less than 5 μm. Optionally, a portion of the III-N depletion layer 16 can also extend into the source-side access region 82.

[0048] The III-N depletion layer 16 is electrically isolated from the source contact 21 via the lateral isolation 27. The spacing from the first end of the depletion layer 16 to the source contact 21 can be 0.5 μm to 10 μm, preferably less than 5 μm. The lateral isolation 25 can be the same as or different from the lateral isolation 27. For example, the lateral isolation 25 can be larger than the lateral isolation 27 to support a higher drain-to-gate voltage (VDG), which may require a larger isolation than is required to support the gate-to-source voltage (VGS). The III-N depletion layer 16 can be formed throughout the III-N channel layer and then removed (e.g., by dry etching and / or wet etching) in a portion of the source side access region 82 adjacent to the source contact 21 and in a portion of the drain side access region 83 adjacent to the drain contact 22.

[0049] The III-N depletion layer 16 can be realized by a single III-N layer or by multiple III-N layers with various Al compositions. The III-N depletion layer 16 can be p-type. The p-type doping can be provided by impurity incorporation (e.g., magnesium) or by polarization engineering (e.g., a positive polarization field gradient in the [000-1] direction). The p-type doping distribution across the depletion layer 16 can have a uniform or graded profile. The depletion layer 16 can have a box profile or a delta function profile. The depletion layer 16 can have multiple repetitions of any of the above profiles.

[0050] The p-type doped III-N depletion layer 16 can be doped with an active acceptor concentration greater than 1×1016 cm-3 and less than 2×1020 cm-3, for example, greater than 1×1018 / cm-3. The acceptor concentration can be less than 3×1019 cm-3 to avoid excessive incorporation of impurities (such as carbon and hydrogen) that can be detrimental to the ionization rate and hole mobility. If the III-N depletion layer 16 is p-type doped with Mg, the device can be treated with a high temperature anneal to make the Mg dopants electrically active. The III-N depletion layer 16 can have a thickness of 1 nm to 1 μm. For example, the III-N depletion layer 16 can have a thickness greater than 4 nm and less than 80 nm.

[0051] When the depletion layer 16 operates in the off state, the area density of the ionized negative charges in the depletion layer 16 can be designed to be in the range of 10% to 150% of the area density of the ionized positive charges in the channel layer 15 and the AlGaN back barrier layer 14 (the ionized negative and positive charges can constitute ionized acceptors, ionized donors, spontaneous and piezoelectric polarization charges, ionized deep levels, ionized interface states). In some embodiments, the ratio between the ionized negative charges and the ionized positive charges can be 90% to 110%. However, due to process variations and difficulties in controlling the doping density of the charge depletion layer 16, it is possible that the ionized negative charges in the depletion layer 16 can be significantly smaller (e.g., less than 70% or less than 40%) or larger (e.g., more than 120%) than the ionized positive charges in the channel layer 15 and the AlGaN back barrier layer 14. The mismatch between the ionized positive and negative charges can be taken into account in the device design. An embodiment of the device for improving the electric field uniformity in the case of a mismatch between the ionized positive charge and the ionized negative charge is described below. The depletion layer 16 can be designed to be substantially fully ionized (fully depleted) when the gate voltage relative to the source (VGS) is sufficiently negative than a minimum value (e.g., −5V, −10V, or −20V) that may be less than, similar to, or greater than the threshold voltage of the device. Furthermore, the depletion layer 16 can be partially or substantially fully ionized (depleted) in the drain-side access region 83 when the gate is biased ON (e.g., above the threshold voltage of the device) and the drain voltage exceeds a second minimum voltage (e.g., 10V, 20V, 30V, 100V, etc.). The depletion layer 16 can be partially or substantially fully ionized (depleted) in the drain-side access region 83 when the device operates in the ON-state saturation regime (linear mode).

[0052] When the depletion layer 16 is fully ionized (i.e., depleted), it can block high voltages while improving the electric field uniformity in the device. The depletion layer 16 can be designed such that when operating in the on-state, the ionized acceptors in the depletion layer 16 are neutralized by positive carriers (i.e., positive holes) and drain-source current flows. The depletion layer 16 can be designed such that the neutralization and ionization of the depletion layer 16 is sufficiently rapid during turn-on and turn-off transitions to ensure sufficiently fast device switching times (e.g., less than 20 ns) and sufficiently low switching losses. The ionization and neutralization of the depletion layer 16 can be improved by reducing the resistivity of the depletion layer 16 and / or by reducing the contact resistance between the depletion layer 16 and the gate contact 23.

[0053] A low resistivity of the depletion layer 16 can be achieved by improving the hole mobility and by increasing the acceptor ionization efficiency (e.g., more holes for the same number of acceptors). For example, the ionization efficiency can be greater than 1%, or greater than 10%, or greater than 50%, and the hole mobility can be greater than 5 cm2 / Vs, or greater than 10 cm2 / Vs. High hole mobility and / or high acceptor ionization efficiency can be achieved with p-type modulation doped III-N heterostructures, e.g., the depletion layer 16 can be formed of an AlxGa1-xN layer (x can be made high enough so that the valence band discontinuity between the III-N depletion layer 16 and the channel layer 15 is greater than the ionization energy of the p-type acceptors). In another example, the depletion layer 16 can be formed with a thin GaN layer (0.5-5 nm) deposited on a thin AlxGa1-xN layer (0.5-5 nm, where x may be higher than 50%, where x may be high enough so that the valence band discontinuity between the thin GaN layer 16 and the thin AlxGa1-xN layer is greater than the ionization energy of the p-type acceptor). In another example, the depletion layer 16 can be formed with a periodic repeat (superlattice) of a thin GaN layer deposited on a thin AlxGa1-xN layer (where x may be higher than 50%). The p-type doping distribution in the III-N heterostructure can have a uniform profile, or can have a box profile, or can have a delta function profile. Each III-N layer comprising the p-type modulation doping superlattice can have a thickness of 0.1 nm to 10 nm. Preferably, the AlxGa1-xN layer in the p-type modulation doping superlattice can have a thickness of less than 3 nm or less than 2 nm. For example, a p-type modulation doping III-N heterostructure can be composed of a thin AlxGa1-xN layer, a thin p-type GaN layer, and a thin AlxGa1-xN layer deposited on the III-N channel layer 15, where a two-dimensional hole gas (2DHG) is formed at the interface between the III-N channel 15 and the first thin AlGaN layer, and the p-type GaN has a high ionization efficiency (higher than 90%).

[0054] Also, a 0.5-5 nm AlGaN or AlN intermediate layer can be disposed between the III-N depletion layer 16 and the channel layer 15. This AlGaN or AlN intermediate layer can help prevent unwanted Mg diffusion from Mg doping of the p-type III-N depletion layer into the III-N channel layer 15. This AlGaN or AlN intermediate layer can also act as a selective etch stop layer to improve the control and precision of the etching process used to remove the III-N depletion layer 16 in the drain-side and source-side access regions.

[0055] Alternatively, the p-type of the III-N depletion layer 16 can be achieved by polarization-induced doping (e.g., by grading the band gap of the layer without introducing dopant impurities). In this case, the aluminum or indium composition of the III-N depletion layer 16 is graded to induce a bulk negative polarization charge that can attract holes, making the III-N depletion layer 16 p-type. The graded III-N depletion layer 16 has a composition that grades (e.g., continuously grades) from the side adjacent to the III-N channel layer 15 to the opposite side of the III-N channel layer 15. The composition of the graded p-type III-N depletion layer 16 is selected such that the gradient of the polarization field is positive in the [000-1] direction. For example, the III-N depletion layer 16 in the III-N device 200 can be formed of AlyGa1-yN (0≦y≦1), where on the side adjacent to the III-N channel layer 15, y is equal to the y of the III-N channel layer 15, and y increases (e.g., continuously increases) from the side adjacent to the III-N channel layer 15 toward the opposite side of the III-N channel layer 15. Alternatively, the III-N depletion layer 16 can be formed of InyGa1-yN (0≦y≦1), where y decreases (e.g., continuously decreases) from the side adjacent to the III-N channel layer 15 toward the opposite side of the III-N channel layer 15.

[0056] The gate contact 23 may be in direct contact with the III-N depletion layer 16. Alternatively, an optional III-N contact layer 17 may be used, e.g., an n-type GaN layer formed at least above the III-N depletion layer 16 in the gate region 81 of the device 200 between the gate 23 and the III-N depletion layer 16, to improve the electrical connection between the gate contact 23 and the III-N depletion layer 16. The thickness of the III-N contact layer 17 may be between 10 nm and 1 μm. The III-N contact layer 17 may be doped with a donor, e.g., silicon. The doping concentration of the III-N contact layer may be high enough to result in an electron concentration density of more than 1×1016 cm-3. The thickness and net n-type doping of the III-N contact layer 17 may be high enough so that the layer 17 is not completely depleted of free electrons by the III-N depletion layer 16, e.g., the thickness may be greater than 50 nm and the average n-type doping may be greater than 1×1018 cm-3. The n-type doping can be greater than 1×10 19 cm −3 .

[0057] Alternatively, for ease of manufacturability, the III-N contact layer 17 can be, for example, a p-type GaN layer. The thickness of the p-type III-N contact layer 17 can be 10 nm to 1 μm. The III-N contact layer 17 can be doped with a donor, for example magnesium. The doping concentration of the III-N contact layer can be high enough to result in a hole concentration greater than 1×10 16 cm −3 . The thickness and net p-type doping of the III-N contact layer 17 can be high enough such that the layer 17 has a p-type doping density greater than the p-type doping density of the III-N depletion layer 16. For example, the thickness of the layer 17 can be greater than 50 nm and the average p-type doping greater than 1×10 18 cm −3 . The p-type doping can be greater than 1×10 19 cm −3 .

[0058] The III-N contact layer 17 is removed in a portion of the source-side and drain-side access regions. The III-N contact layer may be left in place in the gate region 81. The length of the gate region 81 may be between 10 nm and 10 μm, for example between 0.5 μm and 3 μm. The gate aspect ratio may be defined as the ratio of the length of the gate region 81 to the thickness of the III-N channel 15. The gate aspect ratio may be sufficiently large, for example greater than 5, to prevent the drain-induced barrier reduction (DIBL) parasitic effect under high drain bias conditions. The method of removing the III-N contact layer 17 may be selected to substantially minimize damage to the exposed surfaces of the III-N depletion layer 16 in the source-side and drain-side access regions 82 and 83. The removal step may be performed by means of dry etching techniques, wet etching techniques, or may be performed by a combination of dry etching and wet etching techniques. The removal process may be non-selective or selective. A thin AlxGa1-xN layer can be inserted as an etch stop layer between the III-N contact layer 17 and the III-N depletion layer 16. After removing the III-N contact layer 17, chemical and thermal surface treatments can be carried out to restore the surface of the III-N depletion layer 16.

[0059] The III-N depletion layer 16 is removed in portions of the source and drain side access regions. The method of removing the III-N depletion layer 16 can be selected to substantially minimize damage to the surface of the exposed III-N material in the source and drain side access regions 82 and 83. The removal step can be performed by means of dry etching techniques, wet etching techniques, or a combination of dry and wet etching techniques. For example, a low power dry etch can be used to remove the bulk of the III-N contact layer 17 and the III-N depletion layer 16, followed by an acid wet etch treatment to remove the remaining portion of the III-N depletion layer 16. The removal process can be non-selective or selective. A thin AlxGa1-xN layer can be inserted between the III-N depletion layer 16 and the III-N channel layer 15 as an etch stop layer.

[0060] Alternatively, the process of removing the III-N depletion layer 16 may include partial removal of the III-N channel layer 15. The partial removal of the III-N channel layer 15 may be performed by over-etching the III-N depletion layer 16 in successive dry etching steps or by a combination of multiple dry and wet etching steps. The etching rate of the III-N depletion layer 16 may be less than the etching rate of the III-N channel layer 15, and the process of removing the III-N depletion layer 16 may result in substantial removal of the III-N channel layer in parts of the source-side and drain-side access regions due to insufficient over-etching control. For example, before the etching process, the III-N channel layer 15 may have a thickness of 50 nm, and in the area where the III-N depletion layer 16 has been removed, the over-etching of the III-N channel layer 15 may be 10-30 nm. In the area where the III-N depletion layer has been removed, the thickness of the remaining III-N channel layer 15 may be greater than 20 nm. More than 50% of the thickness of the III-N channel layer can be removed during the overetch process of the III-N depletion layer 16.

[0061] Alternatively, the III-N depletion layer 16 and the III-N contact layer 17 can be selectively regrown by means of selective area regrowth, which can avoid the need for a removal process.

[0062] In the gate region 81, a gate contact 23 (gate electrode) is formed on the III-N contact layer 17. The gate contact 23 can be formed from a suitable conductive material, such as a metal stack (Al, Ti / Al, Ti / Al / Ni / Au, Ni / Au, etc.), and can be deposited by metal evaporation or sputtering or chemical vapor deposition or various atomic layer deposition (ALD) to achieve ohmic contact with the III-N contact layer 17. After the deposition of the gate contact 23, a gate post-deposition anneal process can be optionally performed. The post-gate deposition anneal can be performed in an oxygen-containing ambient gas or forming gas (H2 + N2). The post-gate deposition anneal temperature can be higher than 300°C or even higher than 400°C. Finally, the gate contact 23 can be used as an etching mask to etch the III-N contact layer 17, so that the III-N contact layer 17 remains directly under the gate contact 23 but is etched away.

[0063] Source and drain contacts 21 and 22 (i.e., source and drain electrodes), respectively, are on either side of the gate contact 23. The source 21 and drain 22 form ohmic contacts with the device 2DEG channel 19 formed in layer 15. The source and drain contacts 21 and 22 can be formed by metal stacks (Al, Ti / Al, Ti / Al / Ni / Au, Ni / Au, etc.) and / or n-type semiconductor regrowth. The source and drain contact the channel layer 15. Recesses can be formed at least partially in the III-N channel layer 15 to improve contact of the source and drain electrodes to the 2DEG channel 19.

[0064] Referring to FIG. 3A , a portion of the channel layer 15 beneath the source and / or drain contacts may be doped n-type, or an additional n-type layer 29 may be inserted between the source and / or drain contacts and the channel layer 15 to improve the electrical contact of the source and drain metals to the 2DEG.

[0065] The n-type semiconductor layer below the source and / or drain contacts can be selectively regrown. The regrown n-type semiconductor can have a doping greater than 1×10 17 cm −3 , preferably greater than 1×10 19 cm −3 . The metal stack can be Al, Ti / Al, Ti / Al / Ni / Au, etc. A portion of unintentionally doped (UID) GaN 28 (portion 28 can be AlGaN or low n-type doped GaN) can be formed between the III-N depletion layer 16 and the regrown n-type semiconductor 29 formed below the drain contact 22. The drain contact 22 can include an extension portion 22a that extends over the III-N material structure toward the gate contact 25. The extension portion can be long enough to overhang a portion of the III-N depletion layer 16. The extension portion 22a can allow the depletion region to reach the drain contact with the challenge of charge injection into the dielectric layer. The portion 22a can also help reduce buffer dispersion. The contacts can be formed by metal deposition and post deposition annealing methods. Other ohmic contact processes can also be used, including sputtering and dry etching processes.

[0066] Referring again to FIG. 2, an insulator layer 18 (e.g., a SiN layer) can be grown or deposited conformally above the top surfaces of the III-N contact layer 17 and the III-N depletion layer 16 at least in the source-side access region 82 and the drain-side access region 83. The insulator 18 can be formed of or include, for example, aluminum oxide (Al2O3), silicon dioxide (SiO2), silicon nitride (SixNy), Al1-xSixN, Al1-xSixO, Al1-xSixON, or any other wide band gap insulator. The insulator 16 can be deposited either ex-situ (e.g., with a tool different from that used for the growth of the underlying III-N material) or in-situ (i.e., with the same tool and during the same growth session as that used for the growth of the underlying III-N material). In the case of in-situ deposition, the device surface is not exposed to air and therefore is not exposed to oxidizing elements (e.g., oxygen) and undesired impurities / contaminants. For this reason, in-situ deposition can provide superior interface quality (e.g., lower interface states, lower fixed charges and / or lower trapped charges) compared to ex-situ deposition, resulting in superior electrical performance and better electric field profile. For ex-situ deposition, the III-N material structure surface can be treated with chemical and thermal processes to improve the surface quality (e.g., lower interface states, lower fixed charges and / or lower trapped charges) prior to deposition of the insulator layer 18. The insulator layer 18 can perform the functions of passivation, neutralization of active trap states or fixed charges, and / or prevention of charge trapping and / or current leakage in surface states, and / or increase lateral breakdown between the gate and drain contacts.

[0067] 2 operates as follows: when the gate 23 is biased with respect to the source 21 at a voltage greater than the threshold voltage of the device (e.g., 0V), there is 2DEG charge under the gate 23 in the gate region, and thus there is a continuous 2DEG from the source 21 to the drain 22. When a positive voltage is applied to the drain 22, electrons flow from the source 21 through the continuous 2DEG channel 19 to the drain 22. Conventional current flows from the drain to the source and the device is considered to be on.

[0068] When the gate 23 is biased with respect to the source 21 at a voltage higher than the threshold voltage of the device, the III-N depletion layer remains at substantially the same potential as the gate contact 23. As the voltage on the gate-source voltage is gradually decreased to a negative voltage, a positive electric field is generated from the portion of the 2DEG directly below the III-N depletion layer 16. Holes are gradually drawn out of the depletion layer 16, and the ionized negative charges in the III-N depletion layer 16 gradually deplete electrons from the 2DEG. When the gate 23 is biased with respect to the source 21 at a voltage lower than a certain value (e.g., −5V, −10V, −20V), the depletion layer 16 is fully ionized (fully depleted). When the gate 23 is biased with respect to the source 21 at a voltage lower than the threshold voltage of the device, there is no 2DEG below the charge depletion layer 16 (including the region 81 under the gate), and therefore the 2DEG is discontinuous between the source 21 and the drain 22. As discussed above, the doping levels, Al composition, and layer thicknesses are selected to achieve the desired full p-type ionization voltage and the desired threshold voltage of the device.

[0069] When the device is used in a cascode configuration, the threshold voltage of the device can be designed to be lower, in absolute value, than the breakdown voltage of a low-voltage normally-off common-source device. For example, the threshold voltage can be higher than -30V (i.e., close to 0V), higher than -20V, and higher than -10V. When the gate voltage relative to the source is lower than the full ionization voltage for layer 16 and lower than the threshold voltage of the device, a subsequent increase in the drain voltage causes charge imaging from the region in or near drain 22 to gate 23. The III-N depletion layer 16, being fully depleted, no longer stays at the gate potential and can withstand the voltage gradient. Thus, there is a smooth change in potential from drain 22 to gate 23. This results in a larger, more uniform electric field before breakdown occurs, and therefore a larger breakdown voltage than a conventional HEMT without a charge depletion layer.

[0070] In addition to improving the electric field management and increasing the breakdown voltage, an N-polarity III-N device with a junction-based channel depletion layer such as device 200 can have further advantages over conventional III-N devices such as device 100 fabricated with an industry-standard dielectric-based field plate (e.g., field plate 26). For example, III-N device 200 with a channel depletion layer 16 can have a more stable threshold voltage than III-N device 100 with a dielectric-based field plate. Device 200 does not include dielectric bulk and interface traps formed during the field plate process, and in device 200, holes generated in depletion layer 16 by impact ionization can be efficiently removed by the junction gate terminal. Also, when device 200 is switched in a cascode configuration and exposed to high dv / dt and / or di / dt transients, the junction gate terminal formed with the junction-based III-N channel depletion layer 16 can be turned on (i.e., forward biased), clamping the gate voltage to a relatively low value (e.g., less than 4 V), thus preventing gate failure during high transients. On the other hand, in III-N device 100 with dielectric-based field plate, when switched in cascode configuration and exposed to high dv / dt and / or di / dt transients, the gate voltage increases uncontrollably and reaches relatively high values ​​(e.g., greater than 15 V), causing gate dielectric degradation such as charge trapping, leakage, and premature failure. III-N device 200 with channel depletion layer 16 may also enable substantial improvement in electrostatic discharge (ESD) protection, which cannot be easily designed into dielectric-based field plate devices such as device 100. Furthermore, III-N devices with junction-based channel depletion layers such as device 200 may enable the design of lateral devices with very high breakdown voltages (e.g., greater than 1.2 kV, greater than 1.7 kV, greater than 3.3 kV, greater than 6.6 kV).This is very difficult to implement in practice using lateral III-N devices with dielectric-based field plates because the field plate structures to accommodate such high breakdown voltages would become very long with many field plate steps.

[0071] The electric field profile in the device 200 may need to be further refined. One reason for miniaturization is that electric field peaks may exist at abrupt discontinuities in the device structure. For example, the electric field may need to be optimized at the drain side of the gate region 81. Also, the electric field may need to be optimized at the side of the depletion layer 16 in the region 83 adjacent to the drain 22, where the electric field tends to be higher due to abrupt discontinuities in the device structure. Another reason for optimization is when the areal density of ionized negative charges in the p-type III-N depletion layer 16 is different (e.g., lower or higher) than the areal density of ionized positive charges in the channel layer 15 and the back barrier layer 14. Some solutions for improving the electric field profile of the device 200 are described below.

[0072] FIG. 3A is a cross-sectional view of a device 300 including similar features to the device 200 of FIG. 2. However, the device 300 of FIG. 3A incorporates a buried p-type III-N depletion layer 316 formed between the III-N buffer layer 11 and the III-N back barrier layer 14. The III-N depletion layer 316 contacts and is electrically connected to the metal of the gate contact 23 via the connection metal 323 and in a manner similar to the connection of layer 16 to the gate 23 as described above with respect to FIG. 2 (e.g., using a contact layer). As shown in FIG. 3A, the region 26 where the buried depletion layer 316 is connected to the metal 323 can be formed in a region outside the source and drain access regions so as not to affect the 2DEG channel 19. The buried III-N depletion layer 316 can further improve the uniformity of the electric field profile. In this case, the 2DEG channel charge can be partially or fully depleted across the entire device length between the source and drain contacts when the gate-source voltage is below a minimum value (e.g., −5V, −10V, −20V) or below the device threshold voltage.

[0073] Optionally, when forming the device 300 with the buried III-N depletion layer 316, the III-N depletion layer 16 can be omitted. However, when both the III-N depletion layer 16 and the buried III-N depletion layer 316 are present, the electron density in the 2DEG charge can be increased (e.g., 1.3×10 cm−2, 1.5×10 cm−2, 2×10 cm−2) to achieve a lower specific on-state resistance compared to the device 200 of FIG. 2. The thickness and doping of the III-N depletion layer 16 and the buried III-N depletion layer 316 are designed to fully deplete when the gate-source voltage is lower than the threshold voltage. The gate voltage relative to the source at which the buried III-N depletion layer 316 is fully depleted can be less negative or more negative than the gate voltage relative to the source at which the III-N depletion layer 16 is fully depleted.

[0074] FIG. 3B is a cross-sectional view of a device 310 that includes similar features to the device 300 of FIG. 3A. However, the device 310 of FIG. 3B has a III-N depletion layer 16 partitioned into multiple vertically stacked layers 16a and 16b. In the device 310, the depletion layers 16a and 16b can have different compositions and thicknesses. For example, the surface doping density of layer 16a can be higher than the surface doping density of layer 16b. Since the surface doping density is the product of the volume doping density and the thickness, any combination of a suitable volume doping density and a suitable thickness can be used to achieve a given surface doping density of layer 16a or 16b.

[0075] FIG. 3C is a cross-sectional view of a device 320 including similar features to the device 300 of FIG. 3A. However, the device 320 of FIG. 3C has a buried p-type III-N depletion layer 316 partitioned into multiple vertically stacked layers 316a and 316b. In the device 320, the buried depletion layers 316a and 316b can have different compositions and thicknesses. For example, the surface doping density of the layer 316a can be higher than the surface doping density of the layer 316b. Since the surface doping density is the product of the volume doping density and the thickness, any combination of suitable volume doping density and suitable thickness can be used to achieve a given surface doping density of the layer 316a or 316b.

[0076] FIG. 3D is a cross-sectional view of a device 3300 including similar features to the device 300 of FIG. 3A. However, the device 330 of FIG. 3D is formed with multiple vertically stacked 2DEG channels. Multiple 2DEG channels can be formed by repeating III-N channel layers, such as alternating GaN / AlGaN layers, and III-N back barrier layers. FIG. 3D shows an example where two channels are formed, including a top 2DEG channel 19a formed near the interface between the III-N channel layer 15a and the III-N back barrier layer 14a. A bottom 2DEG channel 19b is formed near the interface between the III-N channel layer 15b and the III-N back barrier layer 14b. The positive charge of the first p-type III-N layer 16 can be matched to the negative charge of the first III-N channel layer 15a. The dopant concentration in the first p-type III-N depletion layer 16 is such that the p-type doping areal density in the first p-type III-N depletion layer 16 is in the range of 10-150% of the surface sheet charge density of the mobile charges in the first 2DEG channel 19a. The positive charge in the second p-type III-N layer 316 can be matched to the negative charge in the second III-N channel layer 15b. The dopant concentration in the second p-type III-N depletion layer 316 is such that the surface p-type doping density in the second p-type III-N layer 316 is in the range of 10-150% of the surface sheet charge density of the mobile charges in the second 2DEG channel 19b. Although two 2DEG channels are shown in FIG. 3D, the number of channels formed in the device is not constrained and can be more if desired. Forming multiple channels allows for an increase in the total charge while maintaining high mobility. For devices containing more than two 2DEG channels, each 2DEG channel has an associated p-type III-N layer, and each associated p-type III-N depletion layer can have an areal p-type doping density in the range of 10 to 150% of the areal sheet charge density of the mobile charges in the associated 2DEG channel.

[0077] 4A-4C show some examples of how the device 200 of FIG. 2 can be modified to form devices with multiple channels. Briefly, the device includes at least a p-channel and an n-channel that form a "period" of a periodic layer structure. The period is repeated multiple times in the device structure, with each period being charge balanced. For example, in FIG. 4A, a p-channel (such as III-N depletion layer 16) is formed and an n-channel is formed from a suitable AlGaN / GaN structure (such as III-N channel layer 15 and III-N back barrier layer 14) to form a periodic structure. The 2DEG is indicated by the dashed line in the n-channel. Alternatively, the periodic structure can be structured with 2x p-channels and 1x n-channels as shown in FIG. 4B, or 1x p-channels and 2x n-channels as shown in FIG. 4C. Each period is charge balanced and consists of a suitable AlGaN / GaN structure and modulation doping required to achieve an electron or hole gas. Each period can be formed with multiple p-channels and / or multiple n-channels. Creating multiple channels allows for an increase in the charge in each period while maintaining high mobility. For example, if the desired charge is 2e13 cm-2 of charge in each period, the charge can be split into 2x n-channels with 1e13 cm-2 of charge in each n-channel to maintain high electron mobility.

[0078] FIG. 5A shows a schematic circuit diagram of a hybrid device 500. Because the high-voltage device 200 of FIG. 2 is a depletion mode device (i.e., the device is "on" when the gate is biased at zero volts), it can be combined in series with a low-voltage enhancement mode MOSFET device to form a hybrid device that can act and function like a single normally-off electronic device. As seen in FIG. 5A, the source of device 510 (which can be a high-voltage depletion mode device such as device 200 of FIG. 2 or the devices of FIGS. 3A, 3B, or 4A-4C) is connected to the drain of device 520 (which can be a low-voltage enhancement mode MOSFET device) to form hybrid device 500. Device 510 and device 520 can optionally be placed in a single package 51. Package 51 can have four terminals. A drain terminal 52 of the hybrid device can be connected to the drain of device 510. A source terminal 53 can be connected to the source of device 520. The G1 terminal 54 (i.e., the first gate) of the device 500 may be the enhancement mode gate of the device 520. The G2 terminal 55 (i.e., the second gate) of the device 500 may be connected to the depletion mode gate of the device 510.

[0079] The device 500 can be operated as follows: in a first mode of operation, the G1 terminal 54 and the G2 terminal 55 are biased at zero volts. A voltage is applied to the drain terminal 52, blocking current flow in the forward direction between the drain terminal 52 and the source terminal 53. In a second mode of operation, the G1 terminal 54 is biased at a positive voltage. A voltage is applied to the drain terminal 52, blocking current flow in the forward direction between the drain terminal 52 and the source terminal 53. The source terminal 53 remains at zero volts. In a third mode of operation, both the G1 terminal 54 and the G2 terminal 55 are biased at a positive voltage. A voltage is applied to the drain terminal 52, blocking current flow in the forward direction between the drain terminal 52 and the source terminal 53, the second current being greater than the first current. For example, when the gate terminals 54 and 55 are biased at zero volts, the device 500 is considered "off." Device 500 can be turned "on" by applying a forward bias voltage to G1 terminal 54 that is greater than the threshold voltage of MOSFET device 520 (e.g., greater than +7V). Because device 510 is a depletion mode device, current is allowed to flow in the forward direction.

[0080] Next, the G2 terminal 55 is forward biased (e.g., +2.5V) and the specific channel on-resistance of the III-N device 520 is reduced by the conductivity modulation achieved by capacitive coupling. As a result, the total on-resistance of the device 500 is reduced in the third mode of operation compared to the second mode of operation, increasing the saturation current (i.e., IDS(SAT)) carried through the device for a fixed voltage. The capacitive conductivity modulation of the device 520 can reduce the on-resistance in the device channel by more than 25%, or more than 50%, or even more, compared to when the depletion mode gate of the device 510 is biased at zero volts. This can therefore result in lower conduction losses. When the gate of the III-N device is biased to +2.5V, an additional 1e13 cm-2 of 2DEG charge can be added to the channel. For example, when the gate of a depletion mode device is biased at zero volts, the channel on-resistance may be greater than 300 or 400 Ω / sq, and when the gate of a depletion mode device is forward biased with a positive voltage, the channel on-resistance may be less than 150 or 200 Ω / sq. Conductivity modulation is achieved by using a device such as device 200 of FIG. 2 or the devices of FIGS. 3A, 3B, or 4A-4C, in which the gate is connected to III-N depletion layer 16. A capacitance exists between III-N doping layer 16 and III-N channel layer 15. When the gate of depletion mode device 510 is forward biased, the capacitance can induce additional charge in 2DEG channel 19, thereby reducing the channel on-resistance. Device 500 can be operated by forward biasing G1 terminal 54 and G2 terminal 55 simultaneously, or device 500 can be operated by forward biasing G1 terminal 54 before forward biasing G2 terminal 55.

[0081] A logic block diagram is shown in Figure 5B, where the gate drives can be implemented using digital logic or microcode. A single gate driver can be implemented, where a first delay τ1 is used to switch the first gate G1 and a second delay τ2 is used to switch the second gate G2, where τ2 is longer than τ1. The logic blocks can be specified appropriately for MOSFET and HEMT gate requirements, including both current drive requirements and voltage levels.

[0082] Typically, a depletion mode III-N device, such as device 100 of Figure 1, is connected to an enhancement mode MOSFET device in a cascode configuration to operate as a single normally-off hybrid device. In such a cascode configuration, the gate of the depletion mode device is connected to the source of the enhancement mode device and is typically maintained at ground potential (i.e., zero volts). This prohibits the gate of the depletion mode device from being biased to a positive voltage.

[0083] A method of operating a circuit including a depletion mode transistor and an enhancement mode transistor, where the source of the depletion mode transistor is connected to the drain of an enhancement mode transistor similar to hybrid device 500, is shown in the switching diagram of FIG. 5C. The method includes: biasing a first gate of the enhancement mode device and a second gate of the depletion mode device at zero volts (S0), biasing the drain of the depletion mode device to a positive voltage, and blocking current flow in a forward direction. The bias of the first gate of the enhancement mode device is then changed to a first voltage that is greater than the threshold voltage of the enhancement mode device (S1), allowing a first current to flow in a forward direction through the channel of the depletion mode device. The bias of the second gate of the depletion mode device is then changed to a second voltage (S2), allowing a second current to flow in a forward direction through the channel of the depletion mode device, where the first current is less than the second current and the second voltage is less than or equal to the first voltage.

[0084] The method further includes removing the bias from the depletion mode device (S3) and then removing the bias from the enhancement mode device (S4) and blocking the current in the forward direction. The time delay between S1 and S2 can be, for example, between 10 ns and 100 ns. The second current can be substantially greater than the first current, for example, the second current can be at least 25% to 50% greater than the first current. An on-resistance of the depletion mode device channel can be at least 25% lower when the gate of the depletion mode device is biased with the second voltage compared to a channel where the gate of the depletion mode device is biased with zero volts. The first voltage can be a positive voltage greater than +5V and the second voltage can be a positive voltage less than +5V and greater than 0V.

[0085] Alternatively, device 500 can be simplified by connecting the gates of depletion mode III-N device 510 to the same gate terminal 54, as shown in device 530 in FIG. 5D. By using a common gate terminal 54, the complexity of the gate drive can be significantly reduced, simplifying the implementation of the device. However, a limitation of this configuration is that both devices 510 and 520 are subject to the same voltage bias. This can result in selecting a MOSFET for device 520 that has a lower threshold voltage than would be considered to prevent over-biasing the gate of depletion mode device 520. When the gate of depletion mode device 520 is forward biased beyond a certain voltage, the p-n junction formed between the p region of III-N depletion layer 16 and the n region of III-N channel layer 15 turns on. When the p-n junction turns on, holes are injected from the p region into the n region, and the device moves from a capacitive conduction modulation to a minority carrier conduction modulation. As a result, additional holes need to be removed during device turn-off, increasing the reverse recovery charge and limiting the switching frequency. This limitation can be reduced by optionally including a resistor 56 (or other type of resistive / capacitive device, such as a ferrite bead) connected between the gate terminal 54 of hybrid device 530 and the gate of depletion mode device 520. Resistor 56 can reduce the bias voltage applied to the gate of device 510 and can also add a small delay to the gate timing so that the gate of device 520 turns on first.

[0086] Although the hybrid device 500 of FIG. 5A is formed using two separate semiconductor devices assembled into a single package, similarly functioning integrated devices can be used. FIG. 6A is an embodiment of enhancement mode and depletion mode devices integrated into a single enhancement mode JFET device 600. The integrated JFET device 600 includes an enhancement mode portion 610 adjacent to a depletion mode portion 620. The depletion mode portion 620 can be formed in a manner similar to the device 200 of FIG. 2 or the devices of FIGS. 3A, 3B, or 4A-4C.

[0087] The enhancement mode section 610 includes a p-type GaN layer 625 formed between an e-mode gate contact 623 and a III-N channel layer 15. The p-type GaN layer 625 and the e-mode gate contact 623 are formed between a source contact 21 and a depletion mode gate contact 23. The source contact 21 is electrically connected to the 2DEG channel. The p-type GaN layer 625 is formed in a recess 626 in the top surface of the III-N channel layer 15. The recess 626 is deep enough so that the p-type GaN layer 625 formed inside the recess fully depletes the 2DEG charge 19 in the region directly under the e-mode gate contact when biased at zero volts. The p-type GaN layer 625 is physically separated from the III-N depletion layer 16, and the two layers are not directly electrically connected (i.e., layer 625 and layer 16 may be at different potentials). Layer 625 and layer 16 may be formed with similar thicknesses and compositions, or they may be different. For example, p-type GaN layer 625 may be doped to have a hole concentration greater than 1e19 cm-2 and III-N depletion layer 16 may be doped to have a hole concentration less than 2e13 cm-2. The doping of p-type layer 625 may be independent of the n-type doping used to form the 2DEG, while the doping of III-N depletion layer 16 is doped to match the face sheet charge density of III-N channel layer 15.

[0088] Device 600 can be operated in a manner similar to hybrid device 500 of Figure 5A. For example, e-mode gate 623 can be biased "on", as can G1 terminal 54, depletion mode gate 23 can be biased "on", as can G2 terminal 55, and source contact 21 can be held at 0V.

[0089] Alternatively, the device 601 shown in FIG. 6B can be used as an integrated enhancement mode device that can operate in a manner similar to the hybrid device 500 of FIGS. 5A-5D. As seen in FIG. 6B, the device 601 also includes an enhancement mode portion 610 and a depletion mode portion 620. The depletion mode portion 620 can be similar to the device 200 of FIG. 2, or the devices of FIGS. 3A, 3B, or 4A-4C. The enhancement mode portion 610 of the device 601 includes an e-mode gate contact 627 and a dielectric channel layer 628. The device 601 includes a source region 640 having a hole channel layer 616 formed of a p-type III-N material, a source contact layer 617, and a source contact 621. The hole channel layer 616 is formed on the III-N channel layer 15, and the source contact layer 617 is formed between the hole channel layer 616 and the source contact 621. The hole channel layer 616 may be of the same composition and thickness as the III-N depletion layer 16, or may be different. The source contact layer 617 may be of the same composition and thickness as the III-N contact layer 17, or may be different. Layer 616 and layer 16 may be formed from a single continuous layer and layer 617, layer 17 may be formed from a single continuous layer that is later etched to form a physical separation between the source region 640 and the depletion mode region 620.

[0090] As seen in FIG. 6B, the source contact 621 is formed between the e-mode gate contact 627 and the depletion mode gate contact 23. The source contact layer 617, the hole channel layer 616, and the III-N channel layer 15 are etched away in portions of the e-mode gate region 610 (e.g., the III-N channel layer 15 can be completely removed or partially removed) to form sloped or vertical "sidewalls". The e-mode gate contact 627 and the dielectric channel layer 628 are conformally formed on the sidewalls. The dielectric channel layer 627 can be a true dielectric material such as an oxide or nitride layer (e.g., SiO2, SiN, SiON, AlN, AlSiON, AlSiO, etc.) or can be a combination of a dielectric material and a regrown thin n-channel layer such as a thin GaN layer or a thin AlGaN / GaN layer.

[0091] The device 601 operates as follows: when the e-mode gate 627 is biased at zero volts, the hole channel layer 616 against the sidewalls in the e-mode region 610 blocks current flow between the gate 627 and the hole channel 616. When the e-mode gate 627 is biased at a positive voltage, an inversion channel is formed near the dielectric channel layer 628, and current can flow from the source contact 621 between the gate contact 627 and the hole channel layer 616 along the arrows in FIG. 6B, connecting to the 2DEG channel 19 formed in the III-N channel layer 15, and continuously between the source contact 621 and the drain contact 22. Also, the depletion mode gate contact 23 can be forward biased, reducing the on-resistance of the channel. The device 601 can be operated in a manner similar to the hybrid device 500 of FIG. 5A. For example, the e-mode gate 627 can be biased "on" similar to the G1 terminal 54, the depletion mode gate 23 can be biased similar to the G2 terminal 55, and the source contact 621 can be held at 0V.

[0092] Another implementation of a III-N device 700 is shown in FIG. 7. The device 700 is configured to operate as a bidirectional switch, sometimes referred to as a four-quadrant switch (i.e., FQS). The bidirectional switch 700 can be a depletion mode device. As with other devices described herein, the device 700 includes a substrate 10 (although the substrate is optional), a III-N material structure including III-N layers 11 and 14 on the substrate 10, a 2DEG channel 19 in the III-N material structure, and an insulator layer 18 on the III-nitride material structure. The device 700 also includes a first source contact 21, a second source contact 721, a first gate electrode 23 formed on the first p-type III-N depletion layer 16, and a second gate electrode 723 formed on the second p-type III-N depletion layer 716. The first source contact 21 and the second source contact 721 are each in electrical contact with the 2DEG channel 19. As with the previous embodiment, device 700 may also include gate-connected and / or source-connected field plates (not shown) to further assist in electric field management.

[0093] The first III-N depletion layer 16 can be designed such that when a gate bias lower than the device threshold voltage is applied to the first gate electrode 23 relative to the first source contact 21 and the second source contact 721 is biased at a voltage higher than the first source contact 124, the device channel in the gate region corresponding to the gate 23 is depleted of charge and the bidirectional switch is in the off state, but when 0V is applied to the first gate electrode 23 relative to the first source contact 21 and the second source contact 721 is still biased at a voltage higher than the first source contact 21, the device channel in the gate region corresponding to the gate 23 is readily conductive.

[0094] The III-N depletion layer 716 can be designed such that when the gate bias applied to the second source contact 721 and the second gate electrode 723 relative to the second source contact 721 is biased at a lower voltage than the first source contact 21, the device channel in the gate region corresponding to the gate 723 is depleted of charge and the bidirectional switch is in an off state, but when 0V is applied to the second gate electrode 38 relative to the second source contact 721, the device channel in the gate region corresponding to the gate 723 readily conducts while the second source contact 721 is still biased at a lower voltage than the first source contact 21.

[0095] When gate 23 is biased off (i.e., below its threshold voltage relative to contact 21) and gate 723 is biased off (i.e., below its threshold voltage relative to contact 721), device 700 blocks voltages between contacts 21 and 721 of either polarity (i.e., both when the voltage at contact 21 is greater than the voltage at contact 721 and when the voltage at contact 721 is greater than the voltage at contact 21). When gate 35 is biased on (i.e., above its threshold voltage relative to contact 21) and gate 738 is biased on (i.e., above its threshold voltage relative to contact 721), device 700 can conduct current in either direction.

[0096] FIG. 8A shows a schematic circuit diagram of a hybrid switching device 800. Because the III-N bidirectional switching device 700 is a depletion mode device (i.e., the device is normally "on" when the first gate electrode 23 and the second gate electrode 723 are biased to 0V), it can be combined in series with two low-voltage enhancement mode devices (e.g., silicon MOSFET devices) to form a hybrid device that can act and function like a single normally "off" bidirectional switch. The switching device 800 can optionally be housed in a single electronic package 81. A schematic diagram of the bidirectional switch 700 of FIG. 7 is shown in the dashed area 700 of FIG. 8A. The switch 700 includes a first source contact 21 electrically connected to the drain of the first enhancement mode device 82. The switch 700 includes a second source contact 721 electrically connected to the drain of the second enhancement mode device 83. The electronic package 81 can include four gate terminals. A first gate terminal 84 is connected to the gate of the first enhancement mode device 82 and a second gate terminal 85 is connected to the gate of the second enhancement mode device 83. A third gate terminal 86 is connected to the first gate electrode 23 of the device 700 and a third gate terminal 87 is connected to the second gate electrode 726 of the device 700. The electronic package 81 may include two power supply terminals, a first power supply terminal 88 is connected to the drain of the first enhancement mode device 82 and a second power supply terminal 89 is connected to the drain of the second enhancement mode device 83.

[0097] The device 800 of FIGS. 8A-8C can be operated as follows: in a first mode of operation, the first gate terminal 84 is biased at a voltage above the threshold voltage of the first enhancement mode device 82, and the third gate terminal 86 is biased at a positive voltage. The second gate terminal 85 and the fourth gate terminal 87 are biased at zero volts. A voltage is applied to the first power supply terminal 88, and a current is blocked in the forward direction between the first power supply terminal 88 and the second power supply terminal 89. In a second mode of operation, the second gate terminal 85 is biased above the threshold voltage of the second enhancement mode device 83, and a first current flows in the forward direction between the first power supply terminal 88 and the second power supply terminal 89. In a third mode of operation, the fourth gate terminal 87 is biased at a positive voltage, and a second current flows in the forward direction, the first current being smaller than the second current. In a fourth mode of operation, the first gate terminal 84 and the third gate terminal 86 are biased at zero volts. The second gate terminal 85 is biased above the threshold voltage of the first enhancement mode device 82 and the fourth gate terminal 87 is biased at a positive voltage. A voltage is applied to the second power supply terminal 89, blocking current in the reverse direction between the first power supply terminal 88 and the second power supply terminal 89. In a fifth mode of operation, the first gate terminal 84 is biased above the threshold voltage of the first enhancement mode device 82 and a third current flows in the reverse direction between the first power supply terminal 88 and the second power supply terminal 89. In a sixth mode of operation, the third gate terminal 86 is biased at a positive voltage and a fourth current flows in the reverse direction, the third current being less than the fourth current. In a seventh mode of operation, all four gate terminals are biased at zero volts and the device 800 blocks current in both the forward and reverse directions.

[0098] Because the bidirectional switching device 700 used in the hybrid device 800 is a depletion mode device, the switching device 700 has a specific on-resistance when the first and second gate electrodes are biased at zero volts. However, in the third and sixth modes of operation, both the first and second gate electrodes of the bidirectional switch 700 are forward biased with a positive voltage, reducing the specific channel on-resistance of the device 700. The specific channel on-resistance is reduced by the conductivity modulation achieved by capacitive coupling compared to when either the first or second gate electrodes are biased at zero volts, or compared to when both the first and second electrodes are biased at zero volts. This reduction in channel on-resistance in the third and sixth modes increases the current carried through the device for a fixed voltage. This may therefore result in faster switching speeds and lower switching losses.

[0099] A method of operating the hybrid bidirectional device 800 is shown in the switching diagrams of Figures 8B and 8C. The first method shown in Figure 8B includes: biasing a first gate of a first enhancement mode device with a voltage higher than the threshold voltage of the device, biasing a first gate electrode of a depletion mode bidirectional device with a positive voltage, biasing a second gate of a second enhancement mode device with zero volts, and biasing a second gate electrode of a depletion mode bidirectional device with zero volts (S0). A positive voltage is applied to the first power terminal to block current flow in a first direction. Next, the second gate of the second enhancement mode device is biased with a first voltage higher than the threshold voltage of the device (S1) such that a first current flows in a first direction between the first and second power terminals. Next, the second gate of the depletion mode bidirectional device is biased with a second voltage such that a second current flows in a first direction, the first current being less than the second current and the second voltage being less than or equal to the first voltage (S2). The method further includes removing the bias from a second gate of the depletion mode bidirectional device (S3) and then removing the bias from a second gate of the second enhancement mode device (S4) and blocking current flow in the first direction.

[0100] The second method shown in FIG. 8C includes: biasing a first gate of the first enhancement mode device with zero volts, biasing a first gate electrode of the depletion mode bidirectional device with zero volts, biasing a second gate of the second enhancement mode device with a voltage greater than the threshold voltage of the second enhancement mode device, and biasing a second gate electrode of the depletion mode bidirectional device with a positive voltage (S5). A positive voltage is applied to the second power terminal to block current flow in a second direction. Then, biasing a first of the first enhancement mode devices with a first voltage greater than the threshold voltage (S6), thereby causing a third current to flow in a second direction between the first power terminal and the second power terminal, the first direction being opposite to the second direction. And biasing a first gate of the depletion mode bidirectional element with a second voltage to cause a fourth current to flow in the second direction, the third current being less than the fourth current and the second voltage being less than or equal to the first voltage (S7). The method further includes removing the bias from the first gate of the depletion mode bidirectional device (S8) and then removing the bias from the first gate of the first enhancement mode device (S9) and blocking current flow in the second direction.

[0101] FIG. 9 illustrates a device 900 that is a diode formed with a III-N channel depletion layer that can operate in a manner similar to the III-N channel depletion layer 16 described in connection with the device 200 of FIG. 2. The device 900 includes an anode 91 and a cathode 92. The device further includes an electron channel 93 that can be an AlGaN / GaN material structure similar to the III-N back barrier layer 14 and the III-N channel layer 15. The anode 91 and the cathode 92 can be electrically connected to the electron channel 93, or the anode 91 can be separated from the electron channel 93 by a Schottky barrier (not shown). The device 900 further includes a hole channel layer 94 partially formed on the top surface of the electron channel layer 93. The hole channel layer 94 can be p-type doped and have similar properties to the III-N depletion layer 16. The hole channel layer 94 is connected to the cathode 91 and separated from the cathode 92. The device 900 may further include a hole contact layer 95, which may help improve the electrical contact of the anode 91 to the hole channel layer 94. The hole contact layer 95 may be doped p-type or n-type. Layer 95 may have similar properties as the III-N contact layer 17 and may be connected to the hole channel layer 94 in a similar manner.

[0102] The device 900 of FIG. 9 operates as follows: when a positive voltage exceeding the first threshold voltage of the device 900 relative to the cathode 92 is applied to the anode 91, current flows in the forward direction from the anode to the cathode through the electron channel 93. In addition, capacitive coupling between the hole channel 94 and the electron channel 93 induces additional charge in the electron channel layer 93, reducing the device on-resistance. When a positive voltage exceeding a minimum voltage (e.g., +1V, +2V, +5V) is applied to the cathode relative to the anode, the hole channel 94 is completely depleted of positive charge from the electron channel 93, and the current is blocked in the reverse direction. If the positive voltage applied to the cathode is less than the minimum voltage, the current can be blocked by a Schottky barrier between the anode 91 and the electron channel 93. Furthermore, when a positive voltage is applied to the anode 91 that exceeds the second threshold voltage of the device 900 relative to the cathode 92 (e.g., a surge voltage), the entire p-n junction formed between the hole channel layer 94 and the electron channel 93 turns "on," thereby being able to supply a large amount of current to support the surge.

[0103] While the devices discussed above have referred to N-polarity depletion mode devices, device 1000 of FIG. 10 is a Ga-polarity depletion mode junction FET device. Device 1000 includes source contact 101 and drain contact 102 electrically connected to electron channel layer 105. Electron channel layer 105 can be an n-type layer formed from an AlGaN / GaN material structure, and a 2DEG can be present in channel layer 105. Gate contact 103 is formed on electron channel layer 105 between source contact 101 and drain contact 102. Gate contact 103 can include a field plate 104 that extends on electron channel layer 105 in a drain side access region. Field plate 104 can be a stepped field plate. Device 1000 includes a p-type III-N layer 106 formed between gate contact 103 and electron channel 105 in a region directly below the gate contact forming a p-n junction. The p-type III-N layer 106 does not necessarily extend toward the drain in a region below field plate 104. Additionally, a passivation layer 107 is formed between the source, gate, and drain contact layers. The passivation layer 107 can be a PECVD dielectric layer (e.g., a SiN layer) formed directly on the surface of the electron channel layer 105 without the use of an intermediate in-situ dielectric layer (e.g., an in-situ MOCVD SiN layer) between the electron channel 105 and the passivation layer 107.

[0104] The depletion mode III-N JFET device 1000 may have several advantages over the device 100 of FIG. 1. Typically, Ga polarity depletion mode devices, such as the device 100 of FIG. 1, include a pure high quality insulating layer formed between the gate contact and the electron channel layer, ensuring a reliable and robust negative turn-off voltage. If the insulating layer is not pristine and defects are formed, device leakage and failure may occur. However, methods of forming a pure high quality insulator layer under the gate, such as an “in-situ” MOCVD SiN layer, are time consuming and expensive methods that severely impact the throughput of MOCVD reactor tools. The device 1000 of FIG. 10 may eliminate the insulating layer by forming a p-n junction under the gate instead. Additionally, device stability may be improved under reverse bias conditions. Holes generated during reverse bias high voltage stress may be drained through the reverse biased p-n junction gate, proving reliability and reducing switching losses. The depletion mode device 1000 may be used in a cascode circuit with an enhancement mode device to operate as a normally-off hybrid device.

[0105] Having described several implementations, it will nevertheless be understood that various modifications may be made without departing from the spirit and scope of the techniques and devices described herein.

Claims

1. 1. A method of operating a circuit comprising a depletion mode transistor having a channel and an enhancement mode transistor, the source of the depletion mode transistor being connected to a drain of the enhancement mode transistor, the method comprising: biasing a gate of the depletion mode transistor and a gate of the enhancement mode transistor at zero volts and biasing a positive voltage to the drain of the depletion mode transistor to block current flow in a forward direction; changing the bias of the gate of the enhancement mode transistor to a first voltage greater than a threshold voltage of the enhancement mode transistor while leaving the gate of the depletion mode transistor biased at zero volts, thereby causing a first current to flow through the channel in a forward direction; changing the bias of the gate of the depletion mode transistor to a second voltage while leaving the gate of the enhancement mode transistor biased at the first voltage, thereby causing a second current to flow through the channel in a forward direction, the second current being greater than the first current; The method according to claim 1,

2. 2. The method of claim 1, further comprising removing the bias from the gate of the depletion mode transistor and then removing the bias from the gate of the enhancement mode transistor to block current flow in a forward direction.

3. The method of claim 1 , wherein the second voltage is less than or equal to the first voltage.

4. 2. The method of claim 1, wherein the time between changing the gate of the enhancement mode transistor to the first voltage and changing the gate of the depletion mode transistor to the second voltage is less than 100 ns.

5. 2. The method of claim 1 , wherein the channel has an on-resistance, the on-resistance of the channel being at least 25% lower when the drain of the depletion mode transistor is biased at the second voltage than when the gate of the depletion mode transistor is biased at zero volts.

6. The method of claim 5 , wherein the depletion mode transistor is a III-N HEMT transistor.

7. The method of claim 6 , wherein said depletion mode transistors are N-polarity transistors.

8. The method of claim 7 , wherein the depletion mode transistor comprises a p-type depletion layer formed between the gate and the channel.

9. 9. The method of claim 8, wherein when the gate of the depletion mode transistor is biased at the second voltage, capacitive conduction modulation between the p-type depletion layer and the channel induces an additional net negative charge in the channel.

10. The additional negative charge is at least 1 e １３ cm －２ The device of claim 9 which is an electric charge.

11. 2. The method of claim 1, wherein said first voltage is greater than +5V and said second voltage is less than +5V.

12. A III-N device, a III-N layer structure comprising a III-N channel layer and a III-N barrier layer, wherein a compositional difference between the III-N channel layer and the III-N barrier layer induces a 2DEG channel therein; source contact, gate contact, and drain contact; Equipped with the III-N device is characterized as a depletion mode device, the 2DEG channel having a first on-resistance between the source and drain contacts when the gate contact is biased at zero voltage, and the 2DEG channel having a second on-resistance between the source and drain contacts when the gate contact is biased at a positive voltage, the second on-resistance being less than the first on-resistance; III-N device.

13. The III-N device of claim 12 , wherein the second on-resistance is less than 25% of the first on-resistance when the gate contact is biased at +2.5V or greater.

14. The III-N device of claim 13 , wherein the first on-resistance is greater than 300 Ω / sq and the second on-resistance is less than 150 Ω / sq.

15. The III-N device of claim 12 , wherein the III-N layer structure is formed in an N-polarity direction.

16. The III-N device of claim 15 , wherein the device comprises a p-type layer formed between the gate contact and the III-N channel layer.

17. A III-N device, substrate; a III-N layer structure on the substrate, the III-N layer structure comprising: Buffer layer, a first III-N channel layer between a first III-N barrier layer and a first p-type III-N depletion layer, the first III-N channel layer having a first 2DEG channel formed in the first III-N channel layer; a second III-N barrier layer between a second III-N channel layer and a second p-type III-N depletion layer, the second III-N channel layer having a second 2DEG channel formed between the first 2DEG channel and the substrate, and a second p-type depletion layer formed between the buffer layer and the second III-N barrier layer; A III-N layer structure having a source electrode and a drain electrode electrically connected to the first 2DEG channel and the second 2DEG channel, respectively; a gate electrode between the source and the drain, the gate being above the III-N layer structure, the first p-type III-N depletion layer and the second p-type depletion layer being electrically connected to the gate electrode; A III-N device comprising:

18. The III-N device of claim 17 , wherein the III-N layer structure is grown with an N-polar orientation.

19. 20. The III-N device of claim 18, wherein the first p-type III-N depletion layer and the second p-type depletion layer are physically separated from the source electrode and the drain electrode.

20. 18. The III-N device of claim 17, wherein a dopant concentration in the first p-type III-N depletion layer is such that a p-type doping areal density in the first p-type III-N layer is in the range of 10% to 150% of a surface sheet charge density of mobile charges in the first 2DEG channel.

21. 21. The III-N device of claim 20, wherein a dopant concentration in the second p-type III-N depletion layer is such that a p-type doping areal density in the second p-type III-N layer is in the range of 10 to 150% of a surface sheet charge density of mobile charges in the second 2DEG channel.

22. The III-N device of claim 21 , wherein the mobile charge in the first 2DEG channel is greater than the mobile charge in the second 2DEG channel.

23. 22. The device of claim 21, further comprising more than two 2DEG channels, each of the 2DEG channels having an associated p-type III-N layer, and each associated p-type depletion layer having a surface p-type doping density in the range of 10 to 150% of a surface sheet charge density of mobile charges in the associated 2DEG channel.

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