Josephson parametric converter with impedance matching network

Abstract

One or more systems, devices, or methods of use, or combinations thereof, provided herein relate to a device that can provide bandwidth or saturation power or both for amplifying multiple readout frequencies or converting one or more frequencies. In quantum technology, one or more systems, devices, or methods of use, or combinations thereof, provided herein can be used to simultaneously read out multiple qubit resonators. The device can include a Josephson ring modulator including a pair of nodes and a Josephson parametric converter device including an impedance matching circuit network operatively connected via the pair of nodes. The device can be separately operable in an amplification mode or in a conversion mode.

Description

[Technical field]

[0001] The present disclosure relates to signal amplification and signal movement in frequency space, and more particularly to performing one or more of these operations with Josephson parametric converters that include impedance matching networks. [Background technology]

[0002] Quantum computing generally utilizes quantum mechanical phenomena to perform computational and information processing functions. Quantum computing can be viewed in contrast to classical computing, which generally uses transistors to operate on binary values. That is, while classical computers can operate on bit values ​​that are either 0 or 1, quantum computers operate on quantum bits (qubits), which contain superpositions of both 0 and 1. Quantum computing has the potential to solve problems that are impossible or time-consuming to solve on classical computers due to their computational complexity.

[0003] At scale, a quantum computing cloud service provider may run millions of quantum jobs for users over the course of a year. Each quantum job may include the execution of one or more quantum programs. If a qubit state can only exist (or be coherent) for a limited amount of time, the purpose of the operation of a quantum logic circuit (e.g., involving one or more qubits) may be to reduce the time of the operation or to increase the speed of the operation, or both. The time spent operating a quantum logic circuit may unnecessarily reduce the available time for operations on one or more qubits. This may be due to the coherence time of one or more qubits that can be used before decoherence of one or more qubits. For example, in some cases, a qubit state may be lost in less than 100-200 microseconds. Furthermore, operations on qubits typically introduce some error, such as some degree of decoherence and / or some degree of quantum noise, further impacting the availability of the qubits. Quantum noise refers to noise due to the discrete and / or stochastic nature of quantum interactions. It may be desirable to design devices that extend the lifetime of quantum states and increase coherence times.

[0004] Also, at large scale, the large number of quantum jobs may pressure each quantum program to execute quickly. That is, increased execution speed may correlate, directly or indirectly, or both, with maximizing system usage, minimizing users having to wait for measurement results, or minimizing unwanted consumption of classical computational resources. There may also be pressure to execute these quantum jobs properly so that maximum performance can be extracted from an error-prone system in the short term, and / or the quality of measurements on one or more qubits of each quantum system that are compiled into physical-level pulses (e.g., related to accuracy, precision, or measurement efficiency, or a combination thereof) is improved.

[0005] A physical real-world quantum logic circuit controlled by a quantum system can contain multiple qubits. One type of qubit, the superconducting qubit, can contain Josephson junctions and typically operates exclusively in a cryogenic chamber such as a dilution refrigerator. One or more such superconducting qubits can be multiplexed per measurement circuit contained within the cryogenic chamber.

[0006] Josephson parametric converters (JPCs) are non-degenerate three-wave mixing devices operating near the quantum noise limit. They can act as preamplifiers in high-fidelity qubit readout setups and enable lossless quantum conversion in the microwave regime. Josephson parametric converters constitute the fundamental building blocks in frequency-preserving non-reciprocal devices operated using a single pump tone, such as Josephson directional amplifiers and Josephson isolators. Summary of the Invention

[0007] The following presents a summary intended to provide a basic understanding of one or more embodiments described herein. This summary is not intended to identify key or critical elements or to delineate the scope of particular embodiments or the claims. The sole purpose of this summary is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. In one or more embodiments described herein, a system, computer-implemented method, apparatus, or computer program product, or combination thereof, facilitates a process for increasing the bandwidth or saturation power or both of a Josephson device, such as a Josephson parametric converter. Such an achievement in the quantum field may enable the simultaneous readout of multiple qubit resonators facilitated by a common Josephson parametric converter device.

[0008] According to an embodiment, a device can include a Josephson ring modulator (JRM) including a pair of nodes and a Josephson parametric converter (JPC) including an impedance matching circuit network operatively connected via the pair of nodes.

[0009] According to another embodiment, a method may include, by a system operably coupled to a processor, increasing a bandwidth of a Josephson Parametric Converter (JPC) device including a Josephson Ring Modulator (JRM) having a pair of nodes by operably coupling an impedance matching circuit network via the pair of nodes by the system.

[0010] According to yet another embodiment, a system may include a processor, a chip controlled by the processor, and a Josephson Parametric Converter (JPC) device including a Josephson Ring Modulator (JRM) including a pair of nodes and an impedance matching circuit network operatively connected via the pair of nodes.

[0011] An advantage of the above described devices, systems and / or methods is that the bandwidth and / or saturation power of the device may be increased.

[0012] In one or more embodiments of the aforementioned devices, systems, and / or methods, the device may include another impedance matching circuit network operatively connected via the JRM and another pair of nodes, the JRM including the other pair of nodes. An advantage is that an increased bandwidth amplification mode may be facilitated for simultaneously reading out states from multiple qubits.

[0013] In one or more embodiments of the aforementioned devices, systems, or methods, or combinations thereof, the devices may be capable of operating separately in an amplification mode or a conversion mode. Advantages may be availability and resilience compared to existing technologies.

[0014] In one or more embodiments of the aforementioned devices, systems, and / or methods, the JRM may include a matrix of Josephson junctions connected in series between adjacent nodes along an outer ring of the JRM, the benefits of which may be both increased saturation power and increased bandwidth of the device.

[0015] According to yet another embodiment, a device can include a Josephson ring modulator (JRM) including a plurality of nodes, one or more impedance matching circuit networks operably connected to the JRM, and a pump circuit operably connected to the plurality of nodes of the JRM.

[0016] The advantage of this device can be an increase in the bandwidth and / or saturation power of the device.

[0017] According to yet another embodiment, a device can include a plurality of stacked layers and a Josephson ring modulator (JRM) disposed in one or more of the stacked layers, with nodes of the JRM oriented toward corners of a footprint of the JRM in one of the stacked layers.

[0018] The advantage of this method is that it limits the amount of node crossover to the signal and idler ports of JPC devices that employ JRM. [Brief description of the drawings]

[0019] [Figure 1]FIG. 1 illustrates a block diagram of an example, non-limiting system that can facilitate readout of measurements from one or more quantum bits and / or convert frequency in accordance with one or more embodiments described herein. [Diagram 2] FIG. 2 illustrates a schematic diagram of a Josephson parametric converter device in accordance with one or more embodiments described herein. [Diagram 3] FIG. 1 illustrates a schematic diagram of another Josephson parametric converter device in accordance with one or more embodiments described herein. [Figure 4] FIG. 3 provides a pair of graphs illustrating functional results of operation of the Josephson parametric converter device of FIG. 2 in an amplification mode and a conversion mode in accordance with one or more embodiments described herein. [Diagram 5] FIG. 2 illustrates a schematic diagram of a portion of a Josephson parametric converter device in accordance with one or more embodiments described herein. [Figure 6] FIG. 13 illustrates a schematic diagram of yet another Josephson parametric converter device in accordance with one or more embodiments described herein. [Figure 7] FIG. 2 illustrates a flow diagram of an example method for forming a tile arrangement in accordance with one or more embodiments described herein. [Figure 8] FIG. 1 illustrates a block diagram of an example non-limiting operating environment that can facilitate one or more embodiments described herein. [Figure 9] FIG. 1 illustrates a block diagram of an exemplary non-limiting cloud computing environment in accordance with one or more embodiments described herein. [Figure 10] FIG. 2 illustrates a block diagram of an example non-limiting abstract model layer in accordance with one or more embodiments described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] The following detailed description is merely an example and is not intended to limit the embodiments, or the application and / or utilization of the embodiments. Furthermore, there is no intention to be bound by any express or implied information presented in the above "Summary of the Invention" section or "Description of the Preferred Embodiments" section. One or more embodiments are now described with reference to the drawings, in which like reference numerals are utilized to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more embodiments. However, in various instances, one or more embodiments may be practiced without these specific details.

[0021] Quantum computing uses quantum bits as its fundamental units, instead of classical computational bits. A quantum bit (e.g., a quantum binary digit) is the quantum mechanical analogue of a classical bit. While a classical bit uses only one of two basis states (e.g., 0 or 1), a quantum bit can exist in any superposition of these basis states (e.g., α|0>+β|1>, where α and β are |α| 2 +|β| 2A quantum computer (e.g., a computer that employs qubits rather than just classical bits) can theoretically use a quantum number of qubits, which can hold exponentially more information than the same number of classical bits. Thus, a quantum computer (e.g., a computer that employs qubits rather than just classical bits) can theoretically quickly solve problems that are extremely difficult for classical computers. A classical computer's bit is simply a binary digit that has a value of either 0 or 1. Almost any device that has two distinct states, such as a switch, a valve, a magnet, a coin, or a similar binary form of measure of states, can serve to represent a classical bit. A qubit, with its quantum mystique, can have a superposition of 0 and 1 states. This does not mean that a qubit can have an intermediate value, such as 0.63, but rather that if the state of a qubit is measured, the result will be either 0 or 1. However, in the course of a computation, a qubit can behave as if it were a mixture of states, such as 63 percent 0 and 37 percent 1.

[0022] In fact, a general quantum program may employ a coordination of quantum mechanical and classical parts of the computation. One way to think about a general quantum program is to identify the processes and abstractions involved in specifying a quantum algorithm, translating that algorithm into an executable form, running experiments or simulations, and analyzing the results. A concept that runs through these processes is the use of intermediate representations. An intermediate representation (IR) of a computation is neither a source language description nor a target machine instruction, but something in between. A compiler may utilize multiple IRs during the process of translating and optimizing a program. The input is source code describing the quantum algorithm and compile-time parameters. The output is a combined quantum / classical program represented using high-level IR. The difference between quantum and classical computers is that quantum computers are probabilistic, and therefore measurements of the output of an algorithm provide a good solution within a confidence interval specific to the algorithm. The computation is repeated until a satisfactory degree of certainty of a likely solution can be reached.

[0023] By utilizing quantum mechanics to process information, quantum computers can provide new ways to perform computational tasks such as molecular computing, optical photons, optimization, and many more. Many algorithms and system components can be implemented to efficiently perform such computational tasks.

[0024] With current technology, quantum mechanical or otherwise, efficient and / or fast electronic readout and / or frequency conversion may be limited, for example, by bandwidth, amplification power, and / or saturation power.

[0025] One or more devices, systems, or methods, or combinations thereof, described herein can take into account one or more of these deficiencies, thereby enabling more efficient readout and / or frequency conversion. In the quantum field, such one or more devices, systems, or methods, or combinations thereof, enable simultaneous readout of multiple qubit resonators over a range of frequencies, and thus over a large bandwidth not possible with existing technology. In one or more cases, such a capability allows for an increase in the number of qubits in a chain, layout, or other grouping, relative to existing technology. Furthermore, saturation power can be increased along with bandwidth.

[0026] To achieve one or more of these features, Josephson Parametric Converter (JPC) devices may be employed. JPCs are the components most commonly used as amplifiers in readout chains to increase the readout signal power read by classical electronics. In general, JPCs may be considered as broadband JPCs that include an impedance matching network. JPCs may be non-degenerate three-wave mixing devices with two resonant modes that may be accessed through separate pairs of nodes. These resonant modes may be referred to as the signal resonant mode (X mode) and the idler resonant mode (Y mode).

[0027] Two alternative working mode embodiments can be the wideband JPC in amplification mode and the wideband JPC in conversion mode, which are different from the resonant mode mentioned above. The JPC in amplification mode can be used to amplify the read signal. The JPC in conversion mode can help to prevent frequency congestion by moving the signal in frequency space as needed. Both the wideband JPC in amplification mode and the JPC in conversion mode can be components of more complex non-reciprocal circuits, such as the Josephson directional amplifier (JDA) and the Josephson isolator (JIS).

[0028] One or more JPC devices according to one or more embodiments described herein can include a Josephson ring modulator (JRM), a nonlinear dispersive element based on Josephson junctions that can perform three-wave mixing of microwave signals at the quantum limit. The JRM can include multiple Josephson Junctions (JJs). The JRM can be operatively coupled to one or more impedance matching network circuits (IMNCs) to construct a non-degenerate parametric device that is a Josephson parametric converter (JPC), which can perform amplification and / or mixing of microwave signals at the quantum limit.

[0029] A pump may be employed to drive the JRM, and thus the JJ. The signal and idler ports may be fed to the JPC by separate ports, and may also be fed to a coupling capacitor of the JPC operably coupled to the JRM, such as connected to the JRM.

[0030] By employing one or more suitable IMNCs, the resulting broadband JPC including the IMNC can operate in an amplification mode or a conversion mode. In the amplification mode, the parametric converter device can function as a quantum-limited amplifier that amplifies a readout signal carrying information about the qubit state. In the conversion mode, the parametric converter device can function as a Josephson mixer that performs frequency conversion, i.e., converts the readout signal from one frequency to another. By construction and / or use of one or more parametric converter devices described herein, resiliency can be built into the quantum operation, such as at the end of the readout of the quantum operation. This resiliency can include the ability to simultaneously read out over a wide bandwidth, to simultaneously amplify one or more readout signals, or to simultaneously convert one or more frequencies over a wide frequency range, or a combination thereof.

[0031] That is, generally, a JPC device according to one or more embodiments described herein may include one or more of the following: a circulating pump circuit capable of optimally pumping the JPC device at all four nodes of the JRM, which when shorted to ground may allow a flux bias to be provided to the pump circuit from a DC current, thus allowing an external coil to be omitted; a high saturation power (HSP) JRM that may use an array of Josephson junctions instead of a single JJ; a square JRM that includes corner junctions to prevent undesirable asymmetries in passing through crossovers to join pairs of nodes of an impedance matching network; or an implementation of single-ended idler or signal ports or both, or a combination thereof.

[0032] One or more embodiments are now described with reference to the drawings, in which like reference numerals are used to refer to like elements throughout. As used herein, the terms "entity," "requesting entity," and "user entity" can refer to a machine, device, component, hardware, software, smart device, or human, or a combination thereof. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more embodiments. However, in various instances, one or more embodiments may be practiced without these specific details.

[0033] Generally, the subject computer processing systems, methods, apparatus, devices, or computer program products, or combinations thereof, may be employed to solve new problems that may arise due to advances in technology, computer networks, the Internet, or the like.

[0034] Additionally, the embodiments shown in one or more figures described herein are merely illustrative, and as such, the architecture of the embodiments is not limited to the systems, devices, and / or components shown herein, nor to any particular order, connection, or coupling of any of the systems, devices, and / or components shown herein. For example, in one or more embodiments, a non-limiting system described herein, such as the non-limiting system 100 as shown in FIG. 1 and / or the system, can further comprise, be associated with, be coupled to, or be a combination of one or more computer and / or computation-based elements described herein with reference to an operating environment, such as the operating environment 800 shown in FIG. 8. In one or more described embodiments, the computer and / or computation-based elements can be used in connection with implementing one or more of the systems, devices, components, and / or computer-implemented operations shown and / or described in connection with FIG. 1 and / or the other figures described herein.

[0035]

[0023] Referring initially generally to Figure 1, one or more embodiments described herein may include one or more devices, systems, or apparatus, or combinations thereof, that may facilitate performing one or more quantum operations to facilitate outputting one or more quantum results. For example, Figure 1 illustrates a block diagram of an exemplary, non-limiting system 100 that may improve quantum readout.

[0036] A quantum system 101 (e.g., a quantum computer system, a superconducting quantum computer system, or the like, or a combination thereof) may employ quantum algorithms and / or quantum circuits and may include computing components and / or computing devices for performing quantum operations and / or quantum functions on input data and generating results that may be output to an entity. A quantum circuit may comprise quantum bits (qubits), such as multi-bit quantum bits, physical circuit level components, higher level components, or functions, or a combination thereof. A quantum circuit may comprise physical pulses that may be structured (e.g., arranged and / or designed) to perform a desired quantum function and / or quantum computation on data (e.g., input data and / or intermediate data derived from the input data) and generate one or more quantum results as output. A quantum result, e.g., a quantum measurement result 120, may be responsive to a quantum job request 104 and associated with the input data and may be based at least in part on the input data, the quantum function, and / or the quantum computation.

[0037] In one or more embodiments, quantum system 101 may include one or more quantum components, such as a quantum computing component 103, a quantum processor 106, quantum readout / control electronics including a Josephson Parametric Converter (JPC) device 112, a waveform generator 110, or a quantum logic circuit 108 including a plurality of qubits 107 (e.g., qubits 107A, 107B, or 107C, or any combination thereof), also referred to herein as qubit devices 107A, 107B, and 107C.

[0038] The quantum processor 106 can be any suitable processor. The quantum processor 106 can generate one or more instructions for controlling one or more processes of the quantum computing component 103, or for controlling the quantum logic circuit 108 and / or the waveform generator 110.

[0039] Quantum computing component 103 may obtain (e.g., download, receive, retrieve, or the like, or a combination thereof) a quantum job request 104 requesting execution of one or more quantum programs. Quantum computing component 103 may determine one or more quantum logic circuits, such as quantum logic circuit 108, to execute the quantum programs. Request 104 may be provided in any suitable format, such as text format, binary format, or another suitable format, or a combination thereof. In one or more embodiments, request 104 may be received by a component other than a component of quantum system 101, such as by a component of a classical system that is coupled to and / or in communication with quantum system 101.

[0040] The waveform generator 110 can perform one or more quantum processes, quantum computations, and / or quantum measurements to operate one or more quantum circuits on one or more qubits 107A, 107B, or 107C, or combinations thereof. For example, the waveform generator 110 can operate one or more qubit effectors, such as qubit oscillators, harmonic oscillators, pulse generators, or the like, or combinations thereof, to cause one or more pulses to stimulate and / or manipulate the state of one or more qubits 107A, 107B, or 107C, or combinations thereof, included in the quantum system 101. That is, the waveform generator 110, in combination with a quantum processor 106 or the like, can perform quantum logic circuit operations on multiple qubits 107 (e.g., qubits 107A, 107B, or 107C, or combinations thereof) of the quantum logic circuit 108. In response, the quantum computation component 103 may output one or more quantum job results, such as one or more quantum measurement result readouts 120, in response to the quantum job request 104.

[0041] In one or more embodiments, the quantum processor 106 may comprise a quantum logic circuit 108 .

[0042] The quantum logic circuit 108, and some or all of the waveform generator 110, may be contained in a cryogenic environment, such as that generated by a cryogenic chamber 116, such as a dilution refrigerator. Indeed, signals may be generated by the waveform generator 110 in the cryogenic chamber 116 to affect one or more of the qubits 107. If the qubits 107 are superconducting qubits, cryogenic temperatures, such as about 4K or less, may be used to facilitate the functioning of these physical qubits. Thus, elements of the quantum logic circuit 108 are also constructed to perform at such cryogenic temperatures.

[0043] JPC device 112 can function separately in multiple modes, such as an amplification mode and a conversion mode. In the amplification mode, JPC device 112 can function as a quantum-limited amplifier that amplifies a readout signal that carries information about the qubit state. In the conversion mode, JPC device 112 can function as a Josephson mixer that performs frequency conversion, i.e., converts the readout signal from one frequency to another.

[0044] The JPC device 112 may include a Josephson Ring Modulator (JRM), two or more capacitances, one or more IMNCs, and one or more signal and / or idler ports.

[0045] In view of such a structure, the use of increased saturation power compared to existing JPCs can facilitate readout over a wide bandwidth, such as simultaneously, of multiple qubit states of multiple qubits, such as about 1 to about 10 qubits, or about 5 to about 10 qubits, for non-limiting examples. In one example, for a gain of about 20 decibels (dB) or a reflection of about -20 dB in the conversion mode, the wide band can be considered to be about 300 MHz to about 1 GHz. Alternatively, for a gain of about 20 dB, the narrow band can be about 5 MHz. For a reflection of about -20 dB in the conversion mode, the narrow band can be about 5 MHz to about 10 MHz. In view of such a structure, the use of increased saturation power compared to existing JPCs can also facilitate readout of one or more frequencies, such as simultaneously.

[0046] That is, in one embodiment, the JPC device 112 can be a cryogenic electronic device, for example, located in the same dilution stage as the quantum logic circuit 108. In one or more embodiments, there is some isolation between the quantum logic circuit 108 and the JPC device 112 to protect the quantum logic circuit 108 and / or the quantum processor 106 connected thereto from noise or amplified signals generated by the JPC device 112. The isolation can be provided by at least one stage of isolation. Microwave isolators and / or microwave circulators can be employed to route the readout signal from the quantum logic circuit 108 to the broadband JPC device 112. The output amplified signal from the JPC device 112 can be routed from the cryogenic environment to an output line rather than back to the quantum processor 106.

[0047] The following / above description refers to the operation of a single quantum program from a single quantum job request on the quantum logic circuitry. This operation may include one or more reads, such as occurring simultaneously from the perspective of the JPC device 112, from the cryogenic environment electronics in the cryogenic chamber 116. The employment of the JPC device 112 may be scalable, such as where two or more such JPC devices 112 may be included in the quantum system 101, in one or more embodiments. Furthermore, one or more of the processes described herein may additionally and / or alternatively be scalable, such as to include the execution of one or more quantum programs and / or quantum job requests in parallel with one another.

[0048] In one or more embodiments, non-limiting system 100 can be a hybrid system and thus can include both one or more classical systems, such as a quantum programmable system, and one or more quantum systems, such as quantum system 101. In one or more other embodiments, quantum system 101 can be separate from the classical systems, but can function in combination with the classical systems.

[0049] In such cases, one or more communications between one or more components of the non-limiting system 100 and the classical system may be facilitated by wired and / or wireless means, including, but not limited to, employing a cellular network, a wide area network (WAN) (e.g., the Internet), or a local area network (LAN), or combinations thereof.Suitable wired or wireless technologies to facilitate communications include, but are not limited to, wireless fidelity (Wi-Fi), global system for mobile communications (GSM), universal mobile telecommunications system (UMTS), worldwide interoperability for microwave access (WiMAX), general packet radio service (GPRS), third generation partnership project (3GPP) long term evolution (LTE), third generation partnership project 2 (3GPP2) ultra mobile broadband (UMB), high speed packet access (HSPA), Zigbee and other 802.XX wireless technologies and / or legacy communication technologies, BLUETOOTH®, Session Initiation Protocol (SIP), and / or other 802.XX wireless technologies. Protocol), ZIGBEE®, RF4CE protocol, WirelessHART protocol, 6LoWPAN (IPv6 over Low power Wireless Area Networks), Z-Wave, ANT, ultra-wideband (UWB) standard protocols, or other proprietary and / or non-proprietary communications protocols.

[0050] Referring now to FIG. 2, a schematic diagram of a JPC device 200 is shown that can function as a parametric converter with an amplification mode to generate gain over a bandwidth of interest, or can operate in a conversion mode where frequencies can be converted to idler frequencies. In general, the JPC device 200 can be used for readout multiplexing. In quantum systems where multiple readout resonators are to be readout, one readout line can be used for multiple readout resonators. That is, a wider bandwidth can facilitate readout multiplexing, typically when there is minimal frequency difference between the resonators. Additionally, the high saturation power provided by the broadband JPC device 200 embodiment can also be used to multiplex and amplify more signals.

[0051] It should further be noted that the JPC device 200 may also be used as a component of additional electronic devices, such as a Josephson directional amplifier or a Josephson isolator.

[0052] As shown in the figure, the JPC device 200 includes two pairs of physical ports with two different frequencies that are non-degenerate and refer to different microwave modes. Ports 202 and 204 can be for routing the idler frequencies, while ports 206 and 208 can be for routing the signal frequencies.

[0053] Additionally, the JPC 200 may include a JRM 210 , capacitance pairs 224 , 228 , and one or more impedance matching networks or IMNCs 230 .

[0054] The JRM 210, as shown, can include an outer ring 212 and an inner section 214. The outer ring 212 can include four or more JJs separated / spaced apart from one another along the outer ring 212 by nodes 220.

[0055] The inner section 214 may include two or more JJs, such as operably coupled in series between two of the nodes 220. Another two JJs may be included in the inner section 214, coupled in series between two additional nodes 220. The nodes 220 may be referenced as pairs 1,2 and 3,4, where one pair of nodes is connected to one ladder 222 and / or one capacitance 224, and the other pair of nodes is connected to another ladder 226 and / or another capacitance 228, etc. As shown in the figure, capacitance 224 may be connected to nodes 220 1,2, and capacitance 228 may be connected to nodes 220 3,4. The capacitances 224, 228 may be shunted through the JRM 210 as shown, however, in one or more other embodiments, one or more of the capacitances 224, 228 may be split into two capacitances, one for each node 1,3 and 2,4, in which case the capacitors become shunt capacitors to ground.

[0056] In one or more embodiments, any one or more of the JJs of the JRM 210 may be replaced with two or more JJs, such as a matrix of JJs as also shown in the JRM 250 of Figure 2. This concept is also applicable to any of the JPC devices 112, 300, or 600, or combinations thereof, or the JRM 500, or both.

[0057] Two different modes of the JPC device 200, namely, a signal resonant mode (X mode) and an idler resonant mode (Y mode), can be realized because the capacitances 224, 228 are placed across two different sets of nodes 220 of the JRM 210. For example, calculations using the center frequencies, matching sections, and single-ended or differential excitation of the X (signal) and Y (idler) modes can be used to shape the device response, as calculated in the simulation.

[0058] As further shown, one or more IMNCs 230 may be operatively coupled to node 220 of JRM 210, such as to increase the bandwidth of JPC 200. The IMNCs 230 may be connected between a basic JPC unit cell (e.g., JRM 210 and capacitances 224, 228) and an external port 202-208 or feed line. At least one IMNC 230 may be included to function in a translation mode. At least one IMNC 230 may be included to function in an amplification mode.

[0059] In one or more embodiments, the JPC 200 can function separately in any of these modes. In one or more other embodiments, such as based on the particular structure of the IMNC 230, the JPC 200 can be specialized for one mode or the other based on various design requirements of the IMNC 230.

[0060] Each IMNC 230 can be a lumped-element IMNC, or a non-lumped-element IMNC using distributed elements, etc. In the case of a non-lumped-element IMNC, a transmission line resonator (e.g., parallel or series) may be used via the ladders 222 and 226.

[0061] To aid in the determination of the particular IMNC 230 to employ, the JPC central unit (e.g., JRM 210 and capacitances 224, 228) may be probed in a simulation. For example, the JPC central unit may be probed in a simulation to determine the components to use for the IMNC 230. In one embodiment, the elements of the system coupled to the JPC central unit may be calculated based on probing the JPC central unit in an amplification mode. Harmonic balance simulations may allow the dynamics of the Josephson junctions to be captured to any accuracy dictated by the limitations of computational resources. Based on these simulations, S-parameters may be extracted and then used to calculate an approximate equivalent circuit of the JPC central unit. The equivalent circuit of the JPC central unit in an amplification mode typically behaves approximately like a parallel resonator and negative resistance for a defined alternating current (AC) pump and direct current (DC) flux bias. These values ​​may be input into well-established microwave design methods and techniques to generate an impedance matching network for the wideband JPC. In another embodiment, the elements of the system coupled to the JPC central unit can be calculated based on probing in a simulation in the conversion mode of the JPC central unit, which typically behaves approximately like a parallel resonator, a series resonator, and a positive resistor for a defined alternating current (AC) pump or direct current (DC) flux bias. In the conversion mode, the X / Y mode couples to the frequency conversion resonance of the other mode, generating this additional series resonator section of the equivalent circuit. The total number of resonator sections in the equivalent circuit can be equal to two plus the total number of matching sections added on either the signal side or the idler side. If properly compensated, this feature can increase the bandwidth of the device even more than a design in the amplification mode using the same number of matching IMNC sections.

[0062] In one or more embodiments, additional IMNC sections may be added to one or more of ladders 222 and 226.

[0063] 3, another JPC device 300 is shown including a JRM 310, capacitances 322 and 326, and an IMNC 330. Repetitive descriptions of similar elements and / or processes employed in each embodiment have been omitted for the sake of brevity.

[0064] Shown is an example of one type of circuitry that may be included in the IMNC 330. As shown, these lumped-element IMNCs 330 may each include one section, although additional sections may be used, such as to further increase bandwidth.

[0065] 3, a pump circuit 350 is shown coupled to the JRM 310 (e.g., to a pair of nodes 320 of the JRM 310, such as to one node 320 connected to each of the different capacitance sections / ladders 322, 326 of the JPC device 300). The pump circuit 350 may be actuated, such as via a system coupled to the JPC device 300, to drive the JRM 310, and thus the JPC device 300 to provide, e.g., the non-linear characteristics of the JPC device 300.

[0066] 4, a pair of graphs 400 and 450 are shown. Graph 400 shows the performance in amplification mode of a JPC device according to an embodiment described herein. Graph 400 is a plot of the reflection gain S11 in decibels (dB) of a wideband JPC versus frequency in gigahertz (GHz) for a device including a single additional impedance matching network at both the signal and idler ports. The signal frequency of the device is centered at about 7.25 GHz and the idler frequency is centered at about 10 GHz. Graph 450 shows the performance in translation mode of a JPC device according to an embodiment described herein. Graph 450 shows the reflection coefficient S11 in dB versus frequency in gigahertz (GHz) for a device including a single additional impedance matching network at both the signal and idler ports. 11 (solid line). The conversion efficiency (dashed line) is shown in dB, with approximately 0 dB corresponding to 100% of the signal converted to the idler frequency. For this device, the signal frequency is centered at approximately 7.25 GHz, and the idler frequency is centered at approximately 10 GHz.

[0067] That is, for the JPC devices 200 or 300 described thus far, the IMNC parameters may depend on the termination impedance, such as the termination impedance at the port at either the idler frequency or the signal frequency, or may depend on these signal and / or idler frequencies, etc. Thus, equations may be utilized by designers and the like to determine the optimum impedance and frequency for each JPC device.

[0068] In general, if impedance matching X and Y modes are selected to have the same fractional bandwidth (FBW), f X ≠f Yand the device response can be more difficult to predict because the reflected response can be a combination of the X and Y bandwidths in Hertz (Hz) rather than a fractional bandwidth. Here, f X is the center frequency of the X mode, and f Y is the center frequency of the Y mode.

[0069] One way to handle this case is to set the port impedance according to the following relationship:

[0070]

number

[0071] In addition, the signal port impedance Z s = 50 ohms and effective idler port impedance Z i = 100 ohms and

number

[0072] A single-ended design replaces one of the signal and / or idler ports with a shunt capacitance to ground. The impedance matching network section corresponding to that port is folded onto the remaining port to properly impedance match the device. This is done by the equivalence between the differentially excited JPC and the single-ended excited JPC. For example, the component values ​​(C 12,X , C 23,X , C 2,X , and C 1,X )teeth,

number

number

[0073] That is, in one or more embodiments, the signal port or the idler port or both may be excited single-ended by replacing one termination with a shunt capacitor to ground. Single-ended designs can also reduce complexity when used as building blocks in Josephson Isolator (JIS) and Josephson Directional Amplifier (JDA) designs.

[0074] 5, a layout diagram of a JRM 500 is shown, such as for use with any of the JPC devices 112, 200, 300, or 600, or combinations thereof. As shown in the figure, the layout of the JRM 500 may include a square JRM configuration. The JRM 500 may include a stack of multiple layers, such as metallization layers, such as two or more layers. In one embodiment, three layers may be included.

[0075] As shown in FIG. 5, nodes 511-514 (e.g., nodes) of the JRM 500 are disposed on sides of a stack footprint. A first node 511, a second node 512, a third node 513, and a fourth node 514 are disposed on different sides. The first node 511 and the second node 512 can be part of a signal capacitor. The fourth node 514 and the third node 513 can be part of an idler capacitor.

[0076] Node 1 (511) and Node 2 (512) may be on a first (e.g., top) metallization layer. Node 3 (513) may be on a bottom metallization layer different from the layers of Nodes 1 and 2, such as inside the JRM 500, and may be connected to the top layer through a via 520, such as outer via 520. Node 4 (514) may be on a bottom metallization layer inside the JRM 500, and may be connected to the top layer through a via 520, such as outer via 520.

[0077] The inner ring of Josephson junctions 528 can include at least four JJs. The outer ring of Josephson junctions 524 can include at least four JJs. One or more of these JJs can be replaced with a JJ matrix such as that shown in JRM 250 of Figure 2. For example, each of the outer ring JJs 524 can be replaced with a JJ matrix of multiple JJs.

[0078] As shown in the figure, the JJ524 are placed at the corners of the footprint of the JRM500, which can help minimize parasitic or crossover capacitance between at least two metallization layers of the JRM500.

[0079] One advantage of this layout of the JRM500 is that it can create an electrically symmetric environment for each node exiting the JRM with the other node in the pair (e.g., from the node directly through the center of the JRM, such as when nodes 1 and 2 are paired, and when nodes 3 and 4 are paired), and therefore have lower bandwidth and minimize parasitic inductance or capacitance that increases design difficulties.

[0080] 6, another embodiment of a JPC device is shown at 600. Repetitive descriptions of similar elements and / or processes employed in each embodiment have been omitted for the sake of brevity.

[0081] The JPC device 600 includes a JRM 610, capacitances 622 and 626, an IMNC 630, and a pump circuit 650. The pump circuit 650 drives the JRM 610 and therefore the JPC device 600.

[0082] Both the pump tone and flux bias from direct current (DC) can be sent along a pump circuit wrapped around the JRM 610 to drive the JRM 610, thereby allowing for the omission of an external flux bias coil. The pump circuit 650 can be shorted to ground at one of its two ends to allow a DC current input to flux bias the JRM 610.

[0083] In general, each of the amplification or conversion mode embodiments of the JPC device 600 can include a pump circuit capable of injecting a pump tone at a specified frequency. For an amplification mode JPC, the pump tone is at a sum frequency fp =f s +f i For conversion mode JPC, the pump tone is at the difference frequency f p =f i -f s (f i >f s (where: .times. ...

[0084] As shown, the pump circuit 650 can set the signal frequency and the idler frequency to form the capacitive connection of the pump circuit 650. Connections for flux bias are not shown. The pump circuit 650 is connected to each of the nodes 620 of the JRM 610 and wraps around the JPC device 600, thereby flux biasing through the JPC device 600 to optimally pump all four nodes 620 with the appropriate pump power.

[0085] As shown, a series of transmission lines capacitively couple to each node 620 of the JRM 610. Different lengths of transmission lines may be used for different primary modes of the JPC device 600 (e.g., amplifying primary mode or converting primary mode). When the pump circuit 650 is shorted to ground, DC current can be sent down these transmission lines, thereby flux biasing the JPC device 600. This can be in contrast to existing technology where an external coil is used to supply magnetic flux to each JRM.

[0086] An advantage of the pump circuit 650 is that power can be coupled to all nodes 620 of the JRM, thus reducing non-ideal imbalances between the pump currents at each of the nodes 620, whereas the pump current 350 connects to only two nodes, as shown in FIG. 3. That is, use of the pump circuit 350 may limit the performance of the JPC device 300 compared to use of the pump circuit 650, such as by limiting the usable bandwidth of the JPC device 300.

[0087] 7 illustrates a flow diagram of an exemplary non-limiting method 700 that can facilitate a process for increasing the bandwidth and / or saturation power of a parametric converter device or in conjunction with a Josephson Ring Modulator (JRM). Although the non-limiting method 700 is described in conjunction with the JPC device 112 of FIG. 1, the non-limiting method 700 is also applicable to other systems and / or devices described herein, such as the JPC devices 200, 300, and 600 shown in FIGS. 2, 3, 6, and 5, respectively, and the JPM 500. Repetition of descriptions of similar elements and / or processes employed in each embodiment has been omitted for the sake of brevity.

[0088] At 704, the non-limiting method 700 can include, by a system (e.g., quantum system 101) operably coupled to the processor, increasing the bandwidth of a device (e.g., JPC device 112) including a Josephson Ring Modulator (JRM) that includes the pair of nodes by operably coupling an impedance matching circuit network through the pair of nodes by the system.

[0089] At 706, the non-limiting method 700 may include operably coupling, by a system (e.g., quantum system 101), the capacitor to the JRM.

[0090] At 708, the non-limiting method 700 may include shunting a capacitor to ground or via the pair of nodes by a system (eg, quantum system 101).

[0091] At 710, the non-limiting method 700 can include calculating, by a system (e.g., quantum system 101), an equivalent circuit of the device based on probing the JRM in an amplification mode of the device, the equivalent circuit including a parallel resonator and negative resistance for a defined alternating current (AC) pump or direct current (DC) flux bias.

[0092] At 712, the non-limiting method 700 can include calculating, by a system (e.g., quantum system 101), an equivalent circuit of the device based on probing the device in a transformation mode, the equivalent circuit including a parallel resonator, a series resonator, and a positive resistor for a given alternating current (AC) pump or direct current (DC) flux bias.

[0093] At 714, the non-limiting method 700 may include converting, by the system (e.g., quantum system 101), the plurality of signals from a first frequency to a second frequency by operating the device in a conversion mode.

[0094] At 716, the non-limiting method 700 may include, by the system (e.g., quantum system 101), simultaneously amplifying multiple signals from multiple resonators by operating the device in an amplification mode.

[0095] At 718, the non-limiting method 700 can include driving the JRM with a pump circuit by transmitting a pump tone by a system (e.g., quantum system 101) along a circuit line operably connected to two or more nodes of the JRM that includes a node pair.

[0096] At 720, the non-limiting method 700 can include transmitting, by a system (e.g., quantum system 101), a pump tone and a flux bias from a direct current (DC) along a pump circuit wrapped around the JRM to drive the JRM.

[0097] For ease of explanation, the computer-implemented methods and non-computer-implemented methods provided herein are depicted and / or described as a series of operations. The subject innovation is not limited by the operations depicted and / or by the order of operations, e.g., operations can occur in one or more orders, or simultaneously, or both, with other operations not presented and described herein. Moreover, not all depicted operations may be utilized to practice the computer-implemented methods and non-computer-implemented methods in accordance with the described subject matter. In addition, the computer-implemented methods and non-computer-implemented methods may alternatively be represented as a series of interrelated states or events via a state diagram. Furthermore, to facilitate transporting and transferring the computer-implemented methods to a computer, the computer-implemented methods described below and throughout this specification may be stored in an article of manufacture. The term article of manufacture, as used herein, is intended to encompass a computer program accessible from any computer-readable device or computer-readable storage medium.

[0098] In summary, one or more systems, devices, or methods of use, or combinations thereof, provided herein relate to a device that can provide bandwidth or saturation power or both for reading out and amplifying multiple readout electronics, or for converting one or more frequencies, or both. In quantum technology, one or more systems, devices, or methods of use, or combinations thereof, provided herein can be used to simultaneously read out multiple qubit resonators. The device can include a Josephson Ring Modulator (JRM) including a pair of nodes and an impedance matching circuit network operatively connected via the pair of nodes. The device can be separately operable in an amplification mode and a conversion mode.

[0099] 2-6 in addition to FIG. 1, a Josephson parametric converter (JPC) device may be employed. The JPC device may include a Josephson ring modulator (JRM), a nonlinear dispersive element based on Josephson junctions, capable of performing three-wave mixing of microwave signals at the quantum limit. The JRM may include multiple Josephson junctions (JJs). The JRM may be operatively coupled to one or more impedance matching network circuits (IMNCs) to construct a non-degenerate parametric device that is a Josephson parametric converter (JPC), capable of performing amplification and / or mixing of microwave signals at the quantum limit.

[0100] A pump may be employed to drive the JRM, and thus the JJ. The signal and idler ports may be fed by separate ports to the JPC, and may also be fed to a coupling capacitor of the JPC that is operably coupled to the JRM, such as being connected to the JRM.

[0101] By employing one or more suitable IMNCs, the resulting JPC containing the IMNC can operate in an amplification mode and in a conversion mode. In the amplification mode, the parametric converter device can function as a quantum-limited amplifier that amplifies a readout signal carrying information about the qubit state. In the conversion mode, the parametric converter device can function as a Josephson mixer that performs frequency conversion, i.e., converts the readout signal from one frequency to another. By construction and / or use of one or more parametric converter devices described herein, resiliency can be built into the quantum operation, such as at the end of the readout of the quantum operation. This resiliency can include the ability to simultaneously read out over a wide bandwidth, the ability to simultaneously amplify one or more readout signals, or the ability to simultaneously convert one or more frequencies over a wide frequency range, or a combination thereof.

[0102] Indeed, in view of one or more embodiments described herein, a practical application of the parametric converter devices described herein can be the ability to simultaneously amplify multiple readout signals, such as to read out the quantum states of multiple qubits. This is a useful and practical application of a computer to provide efficient quick readout in quantum processes that may be time-limited due to degeneracy, noise, or coherence, or a combination thereof, thus facilitating improved (e.g., improved and / or optimized) operation of each quantum system. Similar advantages can be realized in non-quantum systems to read out multiple electronic devices in a quick and efficient manner. Overall, such computerized tools can constitute a concrete, tangible technological improvement in the field of quantum computing and readout electronics.

[0103] Furthermore, when scaling up quantum systems, larger quantum systems may include increased multiplexing of readouts, and frequency congestion may occur. In such cases, frequency conversion and multiplexed readout may be beneficial, and both may be provided, such as by one or more JPC devices, as described herein.

[0104] Furthermore, one or more embodiments described herein may be employed in real-world systems based on the disclosed subject matter. For example, one or more embodiments described herein may function within a quantum system, e.g., to facilitate improved quantum state readout, where the quantum system may receive a quantum job request as an input and may measure real-world qubit states of one or more qubits, such as superconducting qubits, of the quantum system.

[0105] Additionally, the devices and / or methods described herein may be implemented in one or more domains, such as the quantum domain, to enable scaled quantum program execution. Indeed, use of devices as described herein may be scalable, such as where the devices described herein may be employed in large numbers with a single quantum system or in multiple quantum systems.

[0106] Systems and / or devices have been described (and / or further described) herein with respect to interactions between one or more components. Such systems and components may include those components or subcomponents designated therein, one or more of the designated components and / or subcomponents, or additional components, or combinations thereof. Subcomponents may be implemented as components that are communicatively coupled to other components rather than being included within a parent component. One or more components and / or subcomponents may be combined into a single component that provides a collective functionality. Components may interact with one or more other components not specifically described herein for brevity but known by those skilled in the art.

[0107] One or more embodiments described herein may, in one or more embodiments, essentially or intimately relate to computer technology and may not be implemented outside of a computing environment. For example, one or more processes performed by one or more embodiments described herein may facilitate the execution of programs and / or program instructions in a more efficient and even more feasible manner, such as in connection with qubit state readout, as compared to existing systems and / or techniques. Systems, computer-implemented methods, and / or computer program products that facilitate the execution of these processes are highly useful in the fields of quantum computing and superconducting quantum systems and may not be equally feasibly implemented in a sensible manner outside of a computing environment.

[0108] One or more embodiments described herein may employ hardware and / or software to solve highly technical problems that cannot be performed as a series of mental activities by a human being that are not abstract. For example, a single human being, or even thousands of humans, cannot efficiently, accurately, or effectively, or a combination thereof, simultaneously read out multiple qubit states over a wide bandwidth as one or more embodiments described herein can facilitate this process. Moreover, neither the human mind nor a human with pen and paper can electronically read out multiple qubit states simultaneously over a wide bandwidth as performed by one or more embodiments described herein.

[0109] In one or more embodiments, one or more of the processes described herein may be executed by one or more specialized computers (e.g., specialized processing units, specialized classical computers, specialized quantum computers, specialized hybrid classical / quantum systems, or another type of specialized computer, or a combination thereof) to perform defined tasks associated with one or more of the techniques described above. One or more embodiments and / or components of the embodiments described herein may be employed to solve new problems that arise due to advances in the aforementioned technologies, quantum computing systems, cloud computing systems, computer architectures, or another technique, or a combination thereof.

[0110] One or more embodiments described herein may be fully operable to perform one or more other functions (e.g., fully powered on, fully running, or another function, or a combination thereof) while also performing one or more operations described herein.

[0111] 8-10, additional background details are provided regarding one or more embodiments described herein in FIGS. 1-7.

[0112] FIG. 8 and the following discussion are intended to provide a brief general description of a suitable operating environment 800 in which one or more embodiments described herein in FIGS. 1-7 may be implemented. For example, one or more components or other aspects of the embodiments described herein may be associated with, such as implemented within, or accessible via, the operating environment 800. Additionally, while one or more embodiments are described above in the general context of computer-executable instructions that may be executed on one or more computers, those skilled in the art will recognize that one or more embodiments may also be implemented in combination with other program modules, or as a combination of hardware and software, or both.

[0113] Typically, program modules include routines, programs, components, data structures, or the like, or combinations thereof, that perform particular tasks and / or implement particular abstract data types. Additionally, the methods of the present invention can be practiced using other computer system configurations, including single or multi-processor computer systems, minicomputers, mainframe computers, Internet of Things (IoT) devices, distributed computing systems, as well as personal computers, handheld computing devices, microprocessor-based or programmable consumer electronics, or the like, or combinations thereof, each of which may be operatively coupled to one or more associated devices.

[0114] A computing device typically includes a variety of media, which may include computer-readable storage media, machine-readable storage media, or communication media, or a combination thereof, and in this specification, the two terms are used differently from each other as follows. A computer-readable storage medium or machine-readable storage medium can be any available storage medium that can be accessed by a computer, and includes both volatile and non-volatile media, removable and non-removable media. By way of example, a computer-readable storage medium or machine-readable storage medium or both may be implemented in association with any method or technology for storage of information, such as, but not limited to, computer-readable and / or machine-readable instructions, program modules, structured and / or unstructured data.

[0115] A computer readable storage medium may include, but is not limited to, random access memory (RAM), read only memory (ROM), electrically erasable programmable read only memory (EEPROM), flash memory or other memory technology, compact disk read only memory (CD-ROM), digital versatile disk (DVD), Blu-ray disc (BD), or other optical disk storage, or combinations thereof, magnetic cassettes, magnetic tapes, magnetic disk storage, or other magnetic storage devices, or combinations thereof, solid state drives or other solid state storage devices, or other tangible and / or non-transitory media that may be used to store the specified information. In this regard, the terms "tangible" or "non-transient" in this specification, when applied to storage, memory, or computer-readable medium, or a combination thereof, should be understood to exclude as modifiers only transient signals that themselves propagate, and not to disclaim any claim to all standard storage, memory, or computer-readable medium that is not itself merely a transient signal that propagates.

[0116] The computer-readable storage medium may be accessed by one or more local or remote computing devices for various operations on the information stored by the medium, for example, via access requests, queries, or other data retrieval protocols, or a combination thereof.

[0117] Communication media typically embodies computer-readable instructions, data structures, program modules, or other structured or unstructured data in a data signal, such as a modulated data signal (e.g., carrier wave or other transport mechanism), and includes any information delivery or transport media. The term "modulated data signal" refers to a signal that has one or more of its characteristics set and / or changed in such a manner as to encode information in the signal or signals. By way of example, and not limitation, communication media may include wired media, such as a wired network or direct-wired connection, or wireless media, such as acoustic, RF, infrared, or other wireless media, or combinations thereof.

[0118] 8, an exemplary operating environment 800 for implementing one or more embodiments of the aspects described herein can include a computer 802 including a processing unit 806, a system memory 804, and / or a system bus 808. One or more aspects of the processing unit 806 can be applied to a processor, such as 106 of the non-limiting system 100. The processing unit 806 can be implemented in combination with a processor, such as 106, or in place of a processor, or both.

[0119] Memory 804 may store components and / or instructions that are readable, writable, or executable, or a combination thereof, by one or more computers and / or machines, which, when executed by processing unit 806 (e.g., a classical processor, a quantum processor, or the like, or a combination thereof), can facilitate performance of operations defined by the executable components and / or instructions. For example, memory 804 may store components and / or instructions that are readable, writable, or executable, or a combination thereof, by a computer or machine, which, when executed by processing unit 806, can facilitate performance of one or more functions described herein in connection with non-limiting system 100, as described herein with or without reference to one or more figures of one or more embodiments.

[0120] The memory 804 may include volatile memory (e.g., random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), or the like, or a combination thereof) and / or non-volatile memory (e.g., read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or the like, or a combination thereof), which may employ one or more memory architectures.

[0121] The processing unit 806 may include one or more types of processors and / or electronic circuitry (e.g., classical, quantum, or similar processors, or a combination thereof) that may implement components and / or instructions that may be stored in the memory 804 that may be readable, written, and / or executed by one or more computers and / or machines. For example, the processing unit 806 may perform one or more operations, including but not limited to, logic, control, input / output (I / O), arithmetic, and / or the like, that may be specified by components and / or instructions that may be readable, written, and / or executed by a computer and / or machine. In one or more embodiments, the processing unit 806 may be any of one or more commercially available processors. In one or more embodiments, the processing unit 806 may include one or more central processing units, multi-core processors, microprocessors, dual microprocessors, microcontrollers, system on a chip (SOC), array processors, vector processors, quantum processors, or other types of processors, or combinations thereof. Examples of the processing unit 806 may be employed to implement one or more embodiments described herein.

[0122] The system bus 808 can couple system components, including but not limited to the system memory 804, to the processing unit 806. The system bus 808 can include one or more types of bus structures that can be further interconnected to a memory bus (with or without a memory controller), a peripheral bus, or a local bus, or combinations thereof, using any of a variety of commercially available bus architectures. The system memory 804 can include a ROM 810 and / or a RAM 812. A basic input / output system (BIOS) can be stored in a non-volatile memory, such as a ROM, an erasable programmable read-only memory (EPROM), or an EEPROM, or combinations thereof, and the BIOS contains basic routines that help transfer information between elements in the computer 802, such as during start-up. The RAM 812 can include a high-speed RAM, such as a static RAM, for caching data.

[0123] The computer 802 may include an internal hard disk drive (HDD) 814 (e.g., EIDE, SATA), one or more external storage devices 816 (e.g., a magnetic floppy disk drive (FDD), a memory stick or flash drive reader, a memory card reader, or the like, or a combination thereof), and / or a drive 820 (e.g., a solid-state drive or optical disk drive that can read from or write to a disk 822, such as a CD-ROM disk, a DVD, a BD, or the like, or a combination thereof). Additionally and / or alternatively, if a solid-state drive is included, the disk 822 may not be included unless it is separate. Although the internal HDD 814 is shown as being within the computer 802, the internal HDD 814 may also be configured for use within an external suitable enclosure (not shown). Additionally, although not shown in operating environment 800, a solid state drive (SSD) may be used in addition to or in place of HDD 814. HDD 814, external storage device 816, and drive 820 may be connected to system bus 808 by HDD interface 824, external storage interface 826, and drive interface 828, respectively. HDD interface 824 for external drive implementations may include at least one or both of Universal Serial Bus (USB) interface technology and Institute of Electrical and Electronics Engineers (IEEE) 1394 interface technology. Other external drive connection technologies are within the contemplation of the embodiments described herein.

[0124] The drives and their associated computer-readable storage media provide non-volatile storage of data, data structures, computer-executable instructions, and the like. The drives and storage media of computer 802 accommodate the storage of any data in a suitable digital format. Although the above description of computer-readable storage media refers to various storage devices, other types of storage media that can be read by a computer, whether currently existing or developed in the future, may also be used within the exemplary operating environment, and / or any such storage media may contain computer-executable instructions for performing the methods described herein.

[0125] A number of program modules, including an operating system 830, one or more applications 832, other program modules 834, and / or program data 836, may be stored in the drives and RAM 812. All or portions of the operating system, applications, modules, and / or data may be cached in RAM 812. The systems and / or methods described herein may be implemented using one or more commercially available operating systems and / or combinations of operating systems.

[0126] Computer 802 may optionally include emulation technology. For example, a hypervisor (not shown) or other intermediary may emulate the hardware environment of operating system 830, and the emulated hardware may optionally be different than the hardware shown in FIG. 8. In a related embodiment, operating system 830 may include one of a number of virtual machines (VMs) hosted on computer 802. Additionally, operating system 830 may provide a runtime environment, such as the JAVA® runtime environment or the .NET framework, to application 832. The runtime environment is a consistent execution environment that may enable application 832 to run on any operating system that includes the runtime environment. Similarly, operating system 830 may support containers, and application 832 may be in the form of a container, which is a lightweight, standalone, executable software package that includes, for example, code, runtime, system tools, system libraries, and / or settings for the application.

[0127] Additionally, computer 802 may be enabled with a security module, such as a trusted processing module (TPM). For example, with a TPM, a boot component may hash the next boot component in time and wait for a match of the hash result with a protected value before loading the next boot component. This process may occur at any layer within the code execution stack of computer 802, for example, applied at the application execution level or at the operating system (OS) kernel level, or both, thereby enabling security at any level of code execution.

[0128] An entity may input and / or send commands and / or information to the computer 802 via one or more wired / wireless input devices (e.g., a keyboard 838, a touch screen 840, and / or a pointing device such as a mouse 842). Other input devices (not shown) may include a microphone, an infrared (IR) remote control, a radio frequency (RF) remote control, or other remote control, or a combination thereof, a joystick, a virtual reality controller or / and a virtual reality headset, a game pad, a stylus, an image input device (e.g., a camera), a gesture sensor input device, a visual movement sensor input device, an emotion or face detection device, a biometric input device (e.g., a fingerprint or iris scanner or / and), or the like, or a combination thereof. These and other input devices may often be connected to the processing unit 806 via an input device interface 844 which may be coupled to the system bus 808, but may also be connected by other interfaces, such as a parallel port, an IEEE 1394 serial port, a game port, a USB port, an IR interface, a BLUETOOTH® interface, or the like, or combinations thereof.

[0129] Alternatively and / or additionally, a monitor 846 or other type of display device may be connected to the system bus 808 via an interface, such as a video adapter 848. In addition to the monitor 846, a computer typically includes other peripheral output devices (not shown), such as speakers, printers, or the like, or a combination thereof.

[0130] The computer 802 can operate in a networked environment using logical connections via wired and / or wireless communications to one or more remote computers, such as a remote computer 850. The remote computer 850 can be a workstation, a server computer, a router, a personal computer, a portable computer, a microprocessor-based entertainment device, a peer device, or other common network node, or a combination thereof, and typically includes many or all of the elements described relative to the computer 802, although for simplicity only a memory / storage device 852 is shown. Additionally and / or alternatively, computer 802 may be communicatively coupled (e.g., communicatively, electrically, operatively, optically, or the like, or a combination thereof) to one or more external systems, sources, or devices (e.g., classical and / or quantum computing devices, communication devices, or the like, or a combination thereof) via a data cable (e.g., a High-Definition Multimedia Interface (HDMI), recommended standard (RS) 232, Ethernet cable, or the like, or a combination thereof).

[0131] In one or more embodiments, the network may include one or more wired and / or wireless networks, including, but not limited to, a cellular network, a wide area network (WAN) (e.g., the Internet), or a local area network (LAN). For example, one or more embodiments described herein may be used in conjunction with wireless fidelity (Wi-Fi), global system for mobile communications (GSM), universal mobile telecommunications system (UMTS), worldwide interoperability for microwave access (WiMAX), enhanced general packet radio service (enhanced GPRS), third generation partnership project (3GPP) long term evolution (LET), third generation partnership project 2 (3GPP2) ultra mobile broadband (UMB), high speed packet access (HSPA), Zigbee, and other 802.11b standards.XX The device may communicate with (and vice versa) one or more external systems, sources, or devices (e.g., computing devices) or any combination thereof using virtually any specified wired or wireless technology, including, but not limited to, wireless and / or legacy communications technologies, BLUETOOTH®, Session Initiation Protocol (SIP), ZIGBEE®, RF4CE protocol, WirelessHART protocol, IPv6 over Low power Wireless Area Networks (6LoWPAN), Z-Wave, ANT, ultra-wideband (UWB) standard protocols, and / or other proprietary and / or non-proprietary communications protocols. In a related example, one or more embodiments described herein may include hardware (e.g., a central processing unit (CPU), a transceiver, a decoder, quantum hardware, a quantum processor, or the like, or a combination thereof), software (e.g., a set of threads, a set of processes, running software, a quantum pulse schedule, a quantum circuit, a quantum gate, or the like, or a combination thereof), or a combination of hardware or software or both, that facilitates the transfer of information between one or more embodiments described herein and an external system, source, or device (e.g., a computing device, a communication device, or the like, or a combination thereof).

[0132] The logical connections depicted in the diagram include wired / wireless connections to a local area network (LAN) 854 or larger networks, such as a wide area network (WAN) 856. LAN and WAN networking environments may be commonplace in offices and companies, facilitating enterprise-wide computer networks, such as intranets, all of which may connect to a global communications network, such as the Internet.

[0133] When used in a LAN networking environment, the computer 802 may be connected to the local network 854 via a wired and / or wireless communication network interface or adapter 858. The adapter 858 may facilitate wired and / or wireless communication with the LAN 854, which may also include a wireless access point (AP) disposed for communicating with the adapter 858 in a wireless mode.

[0134] When used in a WAN network environment, the computer 802 may include a modem 860 or may be connected to a communications server on the WAN 856 by other means for establishing communications over the WAN 856, such as via the Internet, or both. The modem 860, which may be a wired and / or wireless device that is internal and / or external, may be connected to the system bus 808 via the input device interface 844. In a network environment, program modules depicted relative to the computer 802 or portions thereof may be stored in a remote memory / storage device 852. The network connections shown are merely examples and one or more other means of establishing a communications link between the computers may be used.

[0135] When used in either a LAN or WAN network environment, the computer 802 may access a cloud storage system or other network-based storage system, such as, but not limited to, a networked virtual machine, that provides one or more aspects of information storage and / or processing in addition to or in place of the external storage device 816 as previously described, when used in either a LAN or WAN network environment. In general, a connection between the computer 802 and the cloud storage system may be established via the LAN 854 or the WAN 856, for example, by an adapter 858 or a modem 860, respectively. Upon connecting the computer 802 to an associated cloud storage system, the external storage interface 826 may manage the storage provided by the cloud storage system as well as other types of external storage, such as by using the adapter 858 or the modem 860, or both. For example, the external storage interface 826 may be configured to provide access to the cloud storage sources as if the cloud storage sources were physically connected to the computer 802.

[0136] The computer 802 may be operable to communicate with any wireless device or entity operatively disposed in wireless communication (e.g., a printer, a scanner, a desktop computer or portable computer or both, a portable data assistant, a communications satellite, a telephone, or any piece or location of equipment associated with a wirelessly detectable tag (e.g., a kiosk, a newsstand, a store shelf, or the like, or any combination thereof). This communication may include Wireless Fidelity (Wi-Fi) and BLUETOOTH® wireless technologies. Thus, this communication may be of a predefined structure, similar to a conventional network, or may simply be an ad-hoc communication between at least two devices.

[0137] Example embodiments described herein may be employed in distributed computing environments (e.g., cloud computing environments) where certain tasks are performed by remote processing devices that are linked through a communications network, such as the distributed computing environment described below with respect to Figure 9. In a distributed computing environment, program modules may be located in local and / or remote memory storage devices.

[0138] For example, one or more embodiments or one or more components of embodiments described herein may employ one or more computational resources of cloud computing environment 950 described below with reference to FIG. 9 or with reference to one or more functional abstraction layers (e.g., quantum software, and / or the like) described below with reference to FIG. 10 to perform one or more operations in accordance with one or more embodiments described herein. For example, cloud computing environment 950, or one or more of functional abstraction layers 1060, 1070, 1080, or 1090, or combinations thereof, may include one or more classical computing devices (e.g., classical computers, classical processors, virtual machines, servers, or the like, or combinations thereof), quantum hardware, and / or quantum software (e.g., quantum computing devices, quantum computers, quantum processors, quantum circuit simulation software, superconducting circuits, and / or the like), that may be employed by one or more embodiments or components of embodiments described herein to perform one or more operations in accordance with one or more embodiments described herein. For example, one or more embodiments and / or components of embodiments described herein may use one or more such classical and / or quantum computing resources to execute one or more classical and / or quantum mathematical functions, calculations, or equations, or combinations thereof, computational and / or processing scripts, algorithms, models (e.g., artificial intelligence (AI) models, machine learning (ML) models, or similar models, or combinations thereof), or other operations in accordance with one or more embodiments described herein, or combinations thereof.

[0139] Although one or more embodiments described herein include detailed descriptions of cloud computing, it should be understood that implementation of the subject matter presented herein is not limited to a cloud computing environment. Rather, one or more embodiments described herein may be implemented in conjunction with any other type of computing environment now known or later developed.

[0140] Cloud computing is a service delivery model for enabling convenient, on-demand network access to a shared pool of configurable computational resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and / or services) and for rapidly provisioning and releasing these resources with minimal administrative effort or interaction with the service provider. This cloud model can include at least five characteristics, at least three service models, and at least four deployment models.

[0141] The features are as follows:

[0142] On-Demand Self-Service: Cloud customers can automatically provision server time and computing power, such as network storage, as needed, without the need for unilateral, human interaction with the service provider.

[0143] Broad network access: Cloud capabilities are available over the network and can be accessed using standard mechanisms, facilitating usage by heterogeneous thin- or thick-client platforms (e.g., mobile phones, laptops, and PDAs).

[0144] Resource Pool: The provider's computing resources are pooled and offered to multiple consumers using a multi-tenant model. Different physical and virtual resources are dynamically allocated and reallocated according to demand. There is a sense of location independence, consumers typically have no control or knowledge regarding the exact location of the resources offered, although at a higher level of abstraction they can specify the location (e.g. country, state, and / or data center).

[0145] Rapid Elasticity: Cloud capacity can be rapidly and elastically provisioned automatically in one or more cases, quickly scaled out, and quickly released to quickly scale in. Capacity available for provisioning can appear to consumers as unlimited and available for purchase in any quantity at any time.

[0146] Metered Services: Cloud systems leverage metering to automatically control and optimize resource usage at one or more levels of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, and / or active user accounts). Resource usage can be monitored, controlled, and reported, providing transparency to both providers and consumers of the services utilized.

[0147] The service model is as follows:

[0148] SaaS (Software as a Service): The capability provided to the consumer is the use of the provider's applications running on a cloud infrastructure. Those applications can be accessed from a variety of client devices through thin-client interfaces such as web browsers (e.g., web-based email). The consumer does not manage or control the underlying cloud infrastructure, including networks, servers, operating systems, storage, or individual application functionality, or any combination thereof, except for the possibility of limited user-specific application configuration settings.

[0149] PaaS (Platform as a Service): The capability provided to a customer is to deploy applications that the customer creates or acquires, written using programming languages ​​and tools supported by the provider, onto a cloud infrastructure. The customer does not manage or control the underlying cloud infrastructure, including networks, servers, operating systems, and / or storage, but does have control over the deployed applications and, in some cases, the configuration of the application hosting environment.

[0150] Infrastructure as a Service (IaaS): The capability provided to a customer is the provisioning of processing, storage, network, or other basic computing resources, or a combination thereof, onto which the customer can deploy and run any software, which may include operating systems and applications. The customer does not manage or control the underlying cloud infrastructure, but has control over the operating systems, storage, deployed applications, and in some cases, limited control over selected network components (e.g., host firewalls).

[0151] The deployment model is as follows:

[0152] Private Cloud: This cloud infrastructure is operated solely for the organization. It can be managed by the organization or a third party and can exist on-premise or off-premise.

[0153] Community Cloud: This cloud infrastructure is shared by multiple organizations to support a specific community that has a shared concern (e.g., mission, security requirements, policy and / or compliance considerations). It can be managed by the organization or a third party and can exist on-premise or off-premise.

[0154] Public Cloud: This cloud infrastructure is available for use by general users or large industry organizations and is owned by an organization that sells cloud services.

[0155] Hybrid Cloud: This cloud infrastructure is a combination of two or more clouds (private, community, or public) that remain unique entities but are joined together by standardized or proprietary technologies that allow for the portability of data and applications (e.g., cloud bursting to balance the load between clouds).

[0156] A cloud computing environment is a service-oriented environment with an emphasis on statelessness, loose coupling, modularity, and / or semantic interoperability. At the heart of cloud computing is an infrastructure that contains a network of interconnected nodes.

[0157] Additionally, the non-limiting system 100 and / or the exemplary operating environment 800 may be associated with and / or included in a data analysis system, a data processing system, a graph analysis system, a graph processing system, a big data system, a social network system, a voice recognition system, an image recognition system, a graphical modeling system, a bioinformatics system, a data compression system, an artificial intelligence system, an authentication system, a syntactic pattern recognition system, a medical system, a health monitoring system, a network system, a computer network system, a communication system, a router system, a server system, a high availability server system (e.g., a telecommunications server system), a web server system, a file server system, a data server system, a disk array system, a powered insertion board system, a cloud-based system, or the like, or any combination thereof. Accordingly, the non-limiting system 100, and / or the exemplary operating environment 800, may be employed using hardware and / or software to solve problems that are highly technical in nature that are not abstract and / or cannot be implemented as a series of mental activities by a human being.

[0158] Referring now to details of one or more aspects depicted in FIG. 9, an exemplary cloud computing environment 950 is illustrated. As depicted, the cloud computing environment 950 includes one or more cloud computing nodes 910 with which local computing devices used by the cloud consumers (e.g., a personal digital assistant (PDA) or cell phone 954A, a desktop computer 954B, a laptop computer 954C, or an automobile computer system 954N, or combinations thereof) can communicate. Although not depicted in FIG. 9, the cloud computing nodes 910 may further comprise a quantum platform (e.g., a quantum computer, quantum hardware, quantum software, or the like, or combinations thereof) with which the local computing devices used by the cloud consumers can communicate. The cloud computing nodes 910 may communicate with each other. The nodes 910 may be physically or virtually grouped together in one or more networks (not depicted), such as in a private cloud, a community cloud, or a hybrid cloud, or combinations thereof, as previously described herein. This allows the cloud computing environment 950 to provide an infrastructure, platform, and / or SaaS that does not require cloud consumers to maintain resources on local computing devices. It is understood that the types of computing devices 954A-N illustrated in Figure 9 are intended to be exemplary only, and that the cloud computing node 910 and cloud computing environment 950 can communicate with any type of computer-controlled device via any type of network and / or network-addressable connection (e.g., a connection using a web browser).

[0159] Referring now to details of one or more aspects depicted in FIG. 10, a set of functional abstraction layers 1000 is shown, such as a set of functional abstraction layers provided by cloud computing environment 950 (FIG. 9). One or more embodiments described herein may be associated with one or more functional abstraction layers, such as accessible through one or more functional abstraction layers (e.g., hardware and software layer 1060, virtualization layer 1070, management layer 1080, and / or workload layer 1090) described below with reference to FIG. 10. It should be understood in advance that the components, layers, and / or combinations thereof depicted in FIG. 10 are intended to be illustrative only and that the embodiments described herein are not limited thereto. As depicted in the figure, the following layers and / or corresponding functions are provided:

[0160] The hardware and software layer 1060 may include hardware and software components. Examples of hardware components include mainframes 1061, Reduced Instruction Set Computer (RISC) architecture based servers 1062, servers 1063, blade servers 1064, storage devices 1065, and / or networks and / or network components 1066. In one or more embodiments, the software components may include network application server software 1067, quantum platform routing software 1068, and / or quantum software (not shown in FIG. 10).

[0161] The virtualization layer 1070 may comprise an abstraction layer that can provide virtual entities such as virtual servers 1071, virtual storage 1072, virtual networks including virtual private networks 1073, virtual applications and / or operating systems 1074, and / or virtual clients 1075.

[0162] In one example, the management layer 1080 can provide the functionality described below. Resource provisioning 1081 can provide dynamic procurement of computational and other resources that can be utilized to execute tasks within the cloud computing environment. Metering and pricing 1082 can provide cost tracking and / or billing and / or invoicing for the utilization of resources within the cloud computing environment. In one example, the resources can include one or more application software licenses. Security can provide identity verification of cloud consumers and / or tasks, as well as protection of data and / or other resources. User (or entity) portal 1083 can provide consumers and system administrators with access to the cloud computing environment. Service level management 1084 can provide allocation and / or management of cloud computational resources to meet required service levels. Service level agreement (SLA) planning and execution 1085 can provide advance provisioning and procurement of cloud computational resources in anticipation of upcoming demands and in accordance with SLAs.

[0163] The Workload Layer 1090 may represent examples of functionality available in a cloud computing environment. Non-limiting examples of workloads and functionality that may be provided from this layer include mapping and navigation 1091, software development and lifecycle management 1092, virtual classroom instructional delivery 1093, data analytics processing 1094, transaction processing 1095, or application transformation software 1096, or any combination thereof.

[0164] The embodiments described herein may be directed to one or more of a system, method, apparatus, or computer program product, or combinations thereof, at any possible level of technical detail of integration. The computer program product may include a computer readable storage medium that includes computer readable program instructions for causing a processor to execute aspects of one or more of the embodiments described herein. The computer readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, or a superconducting storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer readable storage media may include portable floppy disks, hard disks, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, or mechanically encoded devices such as punch cards or raised structures in grooves on which instructions are recorded, or any suitable combination of these. As used herein, computer readable storage media should not be construed as being signals that are themselves ephemeral, such as radio waves or other freely propagating electromagnetic waves or both, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses passing through a fiber optic cable) or both, or electrical signals transmitted over wires, or combinations thereof.

[0165] The computer readable program instructions described herein may be downloaded from a computer readable storage medium to each computing device / processing device, or to an external computer or external storage device, or both, over a network (e.g., the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof). This network may comprise copper transmission cables, optical transmission fiber, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface within each computing device / processing device receives the computer readable program instructions from the network and forwards those computer readable program instructions for storage on a computer readable storage medium within each computing device / processing device. The computer readable program instructions for carrying out the operations of one or more embodiments described herein can be source and / or object code written in any combination of one or more programming languages, including assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for an integrated circuit, and / or object-oriented programming languages ​​such as Smalltalk®, C++, and / or procedural programming languages ​​such as the “C” programming language and / or similar programming languages. The computer readable program instructions can be executed entirely on the computer, partially on the computer as a stand-alone software package, partially on the computer or partially on a remote computer, or both, or entirely on a remote computer or a server, or both, or combinations thereof.In the latter scenario, the remote computer may be connected to the computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or both, and / or the connection may be to an external computer (e.g., via the Internet using an Internet Service Provider). In one or more embodiments, to perform aspects of one or more embodiments described herein, electronic circuitry, including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), or combinations thereof, may execute computer-readable program instructions to customize the electronic circuitry by utilizing state information of the computer-readable program instructions.

[0166] Aspects of one or more embodiments described herein are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to one or more embodiments described herein. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks included in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions. These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, or a combination thereof, to create a machine, such that the instructions, executed via a processor of the computer or other programmable data processing device, can create means for performing the functions / operations specified in one or more blocks of the flowcharts and / or block diagrams. These computer-readable program instructions can also be stored in a computer-readable storage medium and can instruct a computer, programmable data processing device, or other device, or a combination thereof, to function in a particular manner, such that the computer-readable storage medium on which the instructions are stored can include a product including instructions that can perform aspects of the functions / operations specified in one or more blocks of the flowcharts and / or block diagrams. Computer readable program instructions may also be loaded into a computer, other programmable data processing apparatus, or other device, or combination thereof, such that the instructions, executed on the computer, other programmable apparatus, or other device, or combination thereof, perform the functions / operations specified in one or more blocks of the flowcharts and / or block diagrams, thereby causing a series of operable operations to be performed on the computer, other programmable apparatus, or other device, or combination thereof, to generate a computer-implemented process.

[0167] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and / or operation of possible implementations of a system, computer-implementable method, or computer program product, or combination thereof, according to one or more embodiments described herein. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, or a combination thereof, including one or more executable instructions for implementing the specified logical function. In one or more alternative implementations, the functions shown in the blocks may occur in a different order than the order shown in the figures. For example, two blocks shown in succession may be executed substantially simultaneously or may be executed in reverse order, or both, depending on the functionality involved. It is also noted that each block of the block diagrams and / or flowchart illustrations, or combinations of blocks included in the block diagrams and / or flowchart illustrations, may be implemented by a dedicated hardware-based system capable of performing the specified functions and / or operations, or one or more combinations of dedicated hardware and / or computer instructions and / or both.

[0168] Although the subject matter has been described above in the general context of computer-executable instructions for a computer program product executed on one or more computers, or both, those skilled in the art will recognize that one or more embodiments herein may also be implemented in combination with one or more other program modules. Typically, a program module includes routines, programs, components, data structures, or the like, or a combination thereof, that perform particular tasks and / or implement particular abstract data types. Furthermore, the computer-implemented methods of the present invention may be practiced using other computer system configurations, including single-processor or multi-processor computer systems or both, minicomputing devices, mainframe computers, as well as computers, handheld computing devices (e.g., PDAs, phones), microprocessor-based or programmable consumer and / or industrial electronics, or the like, or a combination thereof. The illustrated aspects may also be practiced in distributed computing environments, where tasks are performed by remote processing devices linked through a communications network. However, one or more aspects, if not all aspects, of one or more embodiments described herein may be practiced on a stand-alone computer. In a distributed computing environment, program modules may be located in both local and remote memory storage devices.

[0169] As used in this application, the terms "component", "system", "platform", "interface", or the like, or combinations thereof, can refer to or include a computer-related entity or an operable machine-related entity that includes one or more specific functions. The entities described herein can be either hardware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, or a computer, or combinations thereof. As an example, both an application running on a server and the server can be a component. One or more components can reside within a process and / or a thread of execution, and a component can be localized on one computer or distributed between two or more computers, or both. In another example, each component can execute from various computer readable media having various data structures stored thereon. A component may communicate via local and / or remote processes, such as according to signals containing one or more data packets (e.g., data from one component communicating with another component in a local or distributed system, or communicating with other systems via signals over a network such as the Internet, or both). As another example, a component may be a device having a specific function provided by mechanical parts operated by electrical or electronic circuits, and operated by software and / or firmware applications executed by a processor.In such cases, the processor may be internal and / or external to the device and may execute at least a portion of the software and / or firmware applications. As yet another example, the components may be devices that provide certain functionality through electronic components that do not include mechanical parts, and those electronic components may include a processor and / or other means for executing software and / or firmware that provides at least a portion of the functionality of the electronic components. In one aspect, the components may emulate the electronic components via a virtual machine, for example, in a cloud computing system.

[0170] In addition, the term "or" is intended to mean an inclusive or rather than an exclusive or. That is, unless otherwise specified or clear from the context, "X employs A or B" is intended to mean any of the natural inclusive permutations. That is, if X employs A, or X employs B, or X employs both A and B, then "X employs A or B" is satisfied in any of the foregoing cases. Furthermore, the articles "a" and "an" used in this specification and the accompanying drawings should generally be construed to mean "one or more" unless otherwise specified or clear from the context to cover the singular form. As used herein, the terms "example" and / or "exemplary" are used to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter described herein is not limited by such examples. Additionally, any aspect or design described herein as "example" and / or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs, and is not intended to exclude equivalent exemplary structures and techniques known to those skilled in the art.

[0171] As used herein, the term "processor" may refer to substantially any computational processing unit and / or device, including, but not limited to, a single-core processor, a single processor with software multithreaded execution capabilities, a multi-core processor, a multi-core processor with software multithreaded execution capabilities, a multi-core processor with hardware multithreading techniques, a parallel platform, or a parallel platform with distributed shared memory, or combinations thereof. Additionally, a processor may refer to an integrated circuit, an application specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), discrete gate or transistor logic, or discrete hardware components, or any combination thereof, designed to perform the functions described herein. Additionally, a processor may utilize nanoscale architectures, such as, but not limited to, molecular and quantum dot-based transistors, switches, or gates, or combinations thereof, to optimize space utilization and / or improve the performance of associated equipment. A processor may be implemented as a combination of computing processing units.

[0172] As used herein, terms such as "store," "storage," "data store," "data storage," "database," and substantially any other information storage component relating to the operation and functionality of a component are used to refer to a "memory component," an entity embodied in a "memory," or a component that comprises a memory. The memory and / or memory components described herein can be either volatile or nonvolatile memory, or can include both volatile and nonvolatile memory. Examples of nonvolatile memory include, but are not limited to, read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or nonvolatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory can include RAM, which can act as an external cache memory, for example. For example, RAM can be available in many forms, such as, but not limited to, synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), or Rambus dynamic RAM (RDRAM), or combinations thereof. Additionally, memory components described in systems and / or computer-implemented methods herein are intended to include memory including, but not limited to, these or any other suitable types of memory or both.

[0173] The foregoing includes merely examples of systems and computer-implemented methods. Of course, for purposes of describing one or more embodiments, it is not possible to describe every conceivable combination of components and / or computer-implemented methods, but one of ordinary skill in the art will recognize that many further combinations and / or permutations of one or more embodiments are possible. Furthermore, to the extent that terms such as "includes," "has," "possesses," and the like are used in the detailed description, claims, appendices, and / or drawings, such terms are intended to be inclusive, similar to the term "comprising" as "comprising" is interpreted when used as a transitional term in a claim.

[0174] The description of one or more embodiments is presented for illustrative purposes, but is not intended to be exhaustive and is not limited to the embodiments described herein. Many changes and modifications that do not depart from the scope and spirit of the described embodiments will be apparent to those skilled in the art. The terms used in this specification are selected to best explain the principles of the embodiments, practical applications, or technical improvements beyond the technology found in the market, or combinations thereof, or to allow other skilled in the art to understand the embodiments described herein, or both.

Claims

1. a Josephson ring modulator (JRM) including a pair of nodes; an impedance matching network operatively connected via said pair of nodes; A device comprising a Josephson parametric converter (JPC) including:

2. The JPC:

10. The device of claim 1, further comprising a capacitor connected to said JRM, said capacitor being a shunt capacitor to ground or shunted across said pair of nodes.

3. The JPC: the JRM including another pair of nodes; another impedance matching network operatively connected via said another pair of nodes; The device of claim 1 or 2, further comprising:

4. 4. A device according to claim 1, wherein the device is separately operable in an amplification mode or in a conversion mode.

5. 5. The device of claim 4, wherein the JRM can be probed in the amplification mode or in the translation mode to determine the slope of an equivalent resistance and an equivalent impedance to determine one or more components to be used as the impedance matching circuit network.

6. the JRM includes another pair of nodes; 6. The device of claim 1, wherein the JPC further comprises a pump circuit capacitively connected to the node for exciting a common mode of the JRM.

7. The device of claim 6 , wherein the pump circuit wraps around the entire circumference of the JRM.

8. 7. The device of claim 6, wherein the JRM further comprises another pair of nodes, and the pump circuit comprises a section of transmission line that wraps around the JRM and capacitively couples to each of the nodes of the JRM at predetermined intervals along the transmission line.

9. 9. A device as claimed in any preceding claim, wherein the JRM includes a further pair of nodes, the pair of nodes and each of the nodes of the further pair of nodes being positioned at a corner of the JRM having a rectangular two-dimensional footprint.

10. The JRM:

10. The device of claim 1, further comprising a matrix of Josephson junctions connected in series between adjacent nodes along an outer ring of the JRM.

11. A method comprising: increasing a bandwidth of a Josephson Parametric Converter (JPC) device having a Josephson Ring Modulator (JRM) including a pair of nodes by a system operably coupled to a processor, the system increasing the bandwidth of the device by operably coupling an impedance matching circuit network via the pair of nodes.

12. By the system, operably coupling a capacitor to the JRM; shunting said capacitor to ground or via said pair of nodes; The method of claim 11 further comprising:

13. 13. The method of claim 11 or 12, further comprising: calculating, by the system, an equivalent circuit of the device based on the probing of the JRM, the equivalent circuit including a parallel resonator and resistor for a defined alternating current (AC) pump or direct current (DC) flux bias.

14. 14. The method of claim 11, further comprising amplifying, by the system, multiple signals from multiple resonators simultaneously by operating the device in an amplification mode.

15. 15. The method of any of claims 11 to 14, further comprising converting, by the system, a plurality of signals from a first frequency to a second frequency by operating the device in a conversion mode.

16. 16. The method of claim 11, further comprising driving the JPC with a pump circuit by transmitting, by the system, a pump tone along a circuit line operably connected to two or more nodes of the JRM, including the pair of nodes.

17. 17. The method of claim 11, further comprising transmitting, by the system, a pump tone and a flux bias from a direct current (DC) along a pump circuit wrapped around the JRM to drive the JRM.

18. A processor; a chip controlled by said processor; a Josephson ring modulator (JRM) including a pair of nodes, and a Josephson parametric converter (JPC) device including an impedance matching network operatively connected via the pair of nodes; Including, the system.

19. The device, the JRM including another pair of nodes; another impedance matching network operatively connected via said another pair of nodes; 20. The system of claim 18, further comprising:

20. 20. The system of claim 19, wherein the pair of nodes and the other pair of nodes are connected to the outer circuit ring of the JRM in alternating fashion around the ring between the node of the pair of nodes and the node of the other pair of nodes.

21. a Josephson Ring Modulator (JRM) including a plurality of nodes; one or more impedance matching networks operably connected to the JRM; a pump circuit operatively connected to the plurality of nodes of the JRM; Including, the device.

22. 22. The device of claim 21, wherein the pump circuit is operably coupled to the complex node of the JRM by a transmission line section that wraps around the JRM.

23. 23. The device of claim 21 or 22, further comprising a signal frequency port and an idler frequency port operably connected to the plurality of nodes of the JRM, wherein one of the signal frequency port or the idler frequency port is single-ended excited.

24. A plurality of stacked layers; a Josephson ring modulator (JRM) disposed in one or more of the stacked layers; A device comprising: A device wherein the nodes of the JRM are located at corners of the footprint of the JRM in one of the stacked layers.

25. 25. The device of claim 24, wherein the nodes of the JRM are connected in series in an outer ring with a matrix of Josephson junctions further connected in series between adjacent nodes along the outer ring.

Images