Damage reduction during spacer deposition

Abstract

The semiconductor structure includes a semiconductor channel structure having a body and a tip, and a dielectric spacer adjacent the tip, the tip having a thickness that is at least 70% of the thickness of the body.

Description

[Technical field]

[0001] The present invention relates to the electrical, electronic and computer technologies, and more particularly to semiconductor manufacturing. [Background technology]

[0002] In the fabrication of modern field effect transistors (FETs), a semiconductor channel structure (e.g., one or more fins or nanosheets) is typically formed, followed by the formation of a spacer around the channel structure. During the deposition of the spacer material, e.g., silicon nitride or other dielectric, damage typically occurs at the tip of the channel structure due to either physical effects (e.g., plasma interactions during plasma-enhanced atomic layer deposition of the spacer) or chemical effects (e.g., oxidation of the surface of the channel structure due to residual oxygen during the deposition process) or both. The damage causes the tip of the channel structure to thin, which results in an increase in the on-resistance of the channel structure. Summary of the Invention

[0003] Principles of the present invention provide techniques for mitigating damage to the tip of a channel structure during spacer deposition. In accordance with one aspect of the present invention, an exemplary semiconductor structure includes a semiconductor channel structure having a body and a tip, and a dielectric spacer adjacent a portion of the channel structure near the tip. The tip is substantially the same thickness as the body.

[0004] In accordance with another aspect of the invention, a semiconductor structure includes a semiconductor channel structure having a body and a tip, a dielectric spacer adjacent a portion of the channel structure near the tip, and a liner between and in direct contact with the spacer and the body of the channel structure, the liner being thicker away from the tip than it is near the tip.

[0005] In accordance with another aspect of the invention, a method of fabricating a semiconductor structure includes obtaining a precursor structure including a semiconductor channel structure having a body and a tip, depositing a liner around at least the tip of the semiconductor channel structure, and depositing a spacer on the liner.

[0006] In view of the above, the techniques of the present invention may provide significant beneficial technical advantages. For example, one or more embodiments may achieve one or more of the following:

[0007] To form a dielectric spacer around a semiconductor channel structure without reducing the thickness of the tip of the channel structure, or at least with a reduced reduction compared to the prior art.

[0008] Improved electrical performance of field effect transistors incorporating aspects of the present invention in the manufacturing process.

[0009] Some embodiments may not have these possible advantages, and these possible advantages are not necessarily required for all embodiments. These and other features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings. [Brief description of the drawings]

[0010] [Figure 1] 1A-1C are side-by-side photographs of channel and spacer structures formed by conventional means and novel channel and spacer structures formed in accordance with an exemplary embodiment; [Diagram 2] 2 is a flow chart illustrating process steps for forming a vertical transport field effect transistor (VTFET) with the novel channel and spacer structure shown in FIG. 1 according to an exemplary embodiment. [Diagram 3] FIG. 2 is a schematic diagram showing the precursor structure of the novel channel and spacer structure shown in FIG. 1. [Figure 4]FIG. 2 is a schematic diagram showing the precursor structure of the novel channel and spacer structure shown in FIG. 1. [Diagram 5] FIG. 2 is a schematic diagram showing the novel channel and spacer structures shown in FIG. 1. [Figure 6] 6 is a schematic diagram showing a VTFET with the novel channel and spacer structure shown in FIG. 1 and FIG. 5 according to the process shown in FIG. 2. [Figure 7] 1 is a flowchart showing process steps for forming a nanosheet FET with a novel channel and spacer structure according to an illustrative embodiment. [Figure 8] FIG. 8 is a schematic diagram showing a precursor structure of a nanosheet FET formed according to the process shown in FIG. 7. [Figure 9] FIG. 8 is a schematic diagram showing a precursor structure of a nanosheet FET formed according to the process shown in FIG. 7. [Figure 10] FIG. 8 is a schematic diagram showing a precursor structure of a nanosheet FET formed according to the process shown in FIG. 7. [Figure 11] FIG. 8 is a schematic diagram showing a precursor structure of a nanosheet FET formed according to the process shown in FIG. 7. [Figure 12] FIG. 8 is a schematic diagram showing a precursor structure of a nanosheet FET formed according to the process shown in FIG. 7. [Figure 13] FIG. 8 is a schematic diagram showing a precursor structure of a nanosheet FET formed according to the process shown in FIG. 7. [Figure 14] FIG. 8 is a schematic diagram showing a nanosheet FET with a novel channel and spacer structure formed according to the process shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] One problem addressed by one or more embodiments is that during transistor fabrication, deposition of silicon nitride spacers around the tips of silicon or silicon-germanium alloy fins or nanosheets ("channel structures" as defined herein) tends to erode the tips, resulting in the tips becoming thinner than the body of the fin or nanosheet. This thinning of the tips adversely affects electrical performance. In one or more embodiments of the invention, a thin layer of amorphous silicon covers the tips of the channel structures, thereby reducing or eliminating tip erosion during spacer deposition. This advantageously improves the electrical performance of the final transistor.

[0012] FIG. 1 shows side-by-side photographs of a channel and spacer structure 100 formed by conventional means and a novel channel and spacer structure 150 formed in accordance with an exemplary embodiment.

[0013] In FIG. 1, structure 100 includes a semiconductor (e.g., silicon) fin 102 protruding from a substrate 103. In one or more embodiments, the substrate is of the same composition as the fin. Fin 102 has a tip 104. Due to the depletion process inherent in the deposition of spacers 106 (in one or more embodiments, spacers including silicon nitride), tip 104 tends to be thinner than fin 102. This thinning of the tip during spacer deposition increases the resistance of the fin, thereby impairing the performance of structure 100. Other components of structure 100 that together form a precursor structure in the fabrication of a vertical transport field effect transistor (VTFET) include a work function material (WFM) 108 (as discussed further below), an interlayer dielectric (ILD) 110, a high-k dielectric liner 112 (e.g., hafnium oxide, other suitable materials are discussed below), a bottom spacer 114 (in one or more embodiments, a low-k dielectric), and a bottom source / drain 116.

[0014] Components of structure 150 that are similar to components of structure 100 are numbered in increments of 50 from the numbering of structure 100. In this case, structure 150 includes a fin 152 having a tip 154, where the fin 152 protrudes from a substrate 304. Structure 150 also includes a spacer 156, a WFM 158, an ILD 160, a liner 162, a bottom spacer 164, and a bottom source / drain 302. Structure 150 differs from structure 100 in two important respects: fin tip 154 ​​is thicker than fin tip 104 when viewed along the thickness of fins 102 and 152, and fin tip 154 ​​is thicker because an amorphous silicon (a-Si) liner 166 is deposited on the fin tip prior to deposition of spacer 156, thereby mitigating the depletion process described above.

[0015] Thus, in one aspect of the invention, the deposition of a-Si liner 166 protects fin tip 154 ​​from depletion due to the subsequent deposition of spacer 156. This advantageously results in improved electrical performance of a VTFET subsequently formed from structure 150 compared to a VTFET formed from structure 100.

[0016] Figure 2 is a flow chart showing steps of a process 200 for forming a vertical transport field effect transistor (VTFET) with the novel channel and spacer structure 150 shown in Figure 1 according to an exemplary embodiment. Figures 3 and 4 show schematic diagrams of precursor structures of the novel channel and spacer structure shown in Figure 1. Figure 5 is a schematic diagram showing the novel channel and spacer structure shown in Figure 1.

[0017] 2, starting at 202 with a precursor structure 300 shown in FIG 3. The precursor structure 300 includes a fin 152, a high-k dielectric liner 162, a work function material 158, an interlayer (low-k) dielectric 160, a bottom spacer 164, a bottom source / drain semiconductor 302, a semiconductor substrate 304, and a shallow trench isolation 306. The interlayer dielectric 160 defines a trench 308.

[0018] At 204, a thin (in one or more embodiments, approximately 1 nm thick) liner 166 of amorphous silicon (a-Si) is deposited. FIG.

[0019] At 206, spacers 156, e.g., silicon nitride (SiN) spacers, are deposited. Figure 5 shows an intermediate structure 500 formed in step 206, including the novel channel and spacer structure shown in Figure 1. Note how the liner 166 thins around the tips of the fins 152 due to depletion of the liner by the spacers. It should be noted that while plasma enhanced atomic layer deposition (PEALD) can deposit conformal SiN for gap filling at low temperatures, it can result in plasma damage to the fin tips unless a sacrificial layer of a-Si is employed as described herein.

[0020] At 208, and also referring to Figure 6, a VTFET 600 is completed, including a top contact 602, a top source / drain semiconductor 604, and an additional dielectric layer 606. Figure 6 is a schematic diagram showing a VTFET with the novel channel and spacer structure shown in Figures 1 and 5 according to the process shown in Figure 2.

[0021] 7 is a flow chart showing steps of a process 700 for forming a nanosheet FET with a novel channel and spacer structure according to an exemplary embodiment. FIGs. 8 to 13 show schematic diagrams of precursor structures of a nanosheet FET formed according to the process shown in FIG.

[0022] 8, starting with a precursor structure 800 in which a layer of semiconductor nanosheets 806 (e.g., silicon) and a sacrificial material 808 (e.g., silicon-germanium alloy) are formed on a substrate 802, supporting a dummy gate stack 810. A bottom dielectric isolator 804 separates the layer of nanosheets from the substrate. A hard mask 812 covers the top of the dummy gate stack, and spacers 814 cover the sides of the dummy gate stack.

[0023] At 704, the nanosheet 806 is retracted and the sacrificial material 808 is indented to form the intermediate structure 900 as shown in Figure 9. The indentation of the sacrificial material defines the tip 906 of the nanosheet.

[0024] In 705, a thin layer of amorphous silicon (a-Si) 1016 is deposited to form an intermediate structure 1000 as shown in FIG.

[0025] At 706, spacers 1118 (e.g., silicon nitride spacers) are deposited and isotropically etched to form individual spacers between the nanosheet tips 906, and the exposed a-Si is removed by slightly trimming the Si to form the intermediate structure 1100 as shown in Figure 11. After spacer deposition, remnants of the liner may be detectable at the tips by energy dispersive x-ray spectroscopy (EDX).

[0026] In 708, an epitaxial semiconductor structure 1220 (source / drain regions) is grown, an interlayer dielectric 1222 is deposited, and planarized (e.g., by chemical-mechanical polishing) to remove the hard mask 812, thereby forming intermediate structure 1200 as shown in FIG. 12.

[0027] At 710, the dummy gate 810 and sacrificial material 808 are removed to form an intermediate structure 1300 having a void 1324 (as shown in FIG. 13), which is then filled at 712 with a high-k / metal gate stack 1426 (as shown in FIG. 14).

[0028] FIG. 14 is a schematic diagram illustrating a nanosheet FET 1400 with novel channel and spacer structures 906, 1016, 1118 formed according to the process 700 shown in FIG.

[0029] The fabrication of semiconductor devices involves various steps in the device patterning process. For example, the fabrication of a semiconductor chip may begin with multiple device patterns, e.g., generated by CAD (Computer Aided Design), followed by efforts to replicate these device patterns onto a substrate. The replication process may include various exposure techniques and various subtractive (etching) and / or additive (deposition) material processing steps.

[0030] A number of different precursors may be used for epitaxial deposition of in situ doped semiconductor material. In some embodiments, the gas source for depositing the epitaxially formed in situ doped semiconductor material may include silicon (Si) deposited from silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, disilane, and combinations thereof. In another example, if the in situ doped semiconductor material includes germanium, the germanium gas source may be selected from the group consisting of germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. Examples of other epitaxial growth processes that can be employed to grow the semiconductor layers described herein include rapid thermal chemical vapor deposition (RTCVD), low energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE).

[0031] "In situ" means that the dopant that determines the conductivity type of the doped layer is introduced during the process step that forms the doped layer, e.g., epitaxial growth. The terms "epitaxial growth" or "epitaxial deposition" or "epitaxial growth and deposition" and "epitaxially formed" or "epitaxially deposited" or "epitaxially formed and deposited" refer to the growth of a semiconductor material (a crystalline material) on a deposition surface of another semiconductor material (a crystalline material) where the semiconductor material being grown (the crystalline overlayer) has substantially the same crystalline properties as the semiconductor material on the deposition surface (the seed material). In an epitaxial deposition process, chemical reactants provided by source gases are controlled and system parameters are set such that the depositing atoms arrive at the deposition surface with sufficient energy to move around the deposition surface of the semiconductor substrate and thereby orient themselves to the crystalline arrangement of the atoms on the deposition surface. Thus, epitaxially grown semiconductor material has substantially the same crystalline properties as the deposition surface upon which it is formed.

[0032] As used herein, the term "conductivity type" refers to a dopant region being p-type or n-type. As further used herein, "p-type" refers to the addition of an impurity to an intrinsic semiconductor that creates a valence electron deficiency. In silicon-containing substrates, examples of p-type dopants, or impurities, include, but are not limited to, boron, aluminum, gallium, and indium. As used herein, "n-type" refers to the addition of an impurity to an intrinsic semiconductor that provides free electrons. Examples of n-type dopants, or impurities, in silicon-containing substrates include, but are not limited to, antimony, arsenic, phosphorus, and the like.

[0033] As an exemplary subtractive process, in a photolithography process, a layer of photoresist material is first applied onto a substrate, which is then selectively exposed according to one or more predetermined device patterns. The portions of the photoresist exposed to light or other ionizing radiation (e.g., ultraviolet light, electron beam, x-rays, etc.) may undergo some change in their solubility in a particular solution. The photoresist can then be developed in a developer, which removes either the non-irradiated portions (negative resist) or the irradiated portions (positive resist) of the resist layer, forming a photoresist pattern or photomask. The photoresist pattern or photomask is then replicated or transferred to the substrate underlying the photoresist pattern.

[0034] There are many techniques used by those skilled in the art to remove material at various stages in creating semiconductor structures. As used herein, these processes are collectively referred to as "etching." For example, etching techniques include wet etching, dry etching, chemical oxide removal (COR) etching, and reactive ion etching (RIE), all of which are known techniques for removing selected materials in forming semiconductor structures. Standard Clean 1 (SC1) contains a strong base, typically ammonium hydroxide, and hydrogen peroxide. SC2 contains a strong acid, such as hydrochloric acid, and hydrogen peroxide. The techniques and applications of etching are well understood by those skilled in the art, and therefore, a more detailed description of such processes is not presented herein.

[0035] While the overall fabrication method and structures formed thereby are novel, each particular processing step required to carry out the method may utilize conventional semiconductor manufacturing techniques and conventional semiconductor manufacturing tooling. These techniques and tooling will already be familiar to those skilled in the relevant art given the teachings herein. Furthermore, one or more of the processing steps and tooling used to fabricate semiconductor devices are also described in a number of readily available publications, such as, for example, James D. Plummer et al., Silicon VLSI Technology: Fundamentals, Practice, and Modeling 1st Edition, Prentice Hall, 2001, and PH Holloway et al., Handbook of Compound Semiconductors: Growth, Processing, Characterization, and Devices, Cambridge University Press, 2008, all of which are incorporated herein by reference. It is emphasized that while several individual processing steps are described herein, they are merely for illustrative purposes, and that one of ordinary skill in the art may be familiar with several equally suitable alternatives that may be applicable.

[0036] It should be appreciated that the various layers or regions, or combinations thereof, illustrated in the accompanying figures may not be drawn to scale. Furthermore, for ease of illustration, one or more semiconductor layers of a type commonly used in such integrated circuit devices may not be explicitly shown in a given figure. This is not intended to imply that the semiconductor layers not explicitly shown are omitted in the actual integrated circuit device.

[0037] Various materials are referred to herein as being epitaxially grown. As used herein, "epitaxy" or "epitaxial growth" refers to a process of forming a layer of single crystal or large grain polycrystalline material on an existing material with similar crystallographic properties. One feature of epitaxy is that the process reproduces the crystallographic structure of the existing substrate or seed layer, including any defects therein, in the epitaxially grown material. Epitaxial growth can include heteroepitaxy (i.e., growing a material with a different composition than the underlying layer) or homoepitaxy (i.e., growing a material with the same composition as the underlying layer). Heteroepitaxy can result in strain in the epitaxially grown material because the crystal structure of the epitaxially grown material may be distorted to match the crystal structure of the underlying layer. In some applications, such strain may be desirable. In an epitaxial deposition process, chemical reactants provided by source gases are controlled and system parameters are set such that the depositing atoms arrive at the deposition surface with sufficient energy to move around the deposition surface of the semiconductor substrate and orient themselves to the crystalline arrangement of the atoms of the deposition surface. Thus, the epitaxial semiconductor material may have the same crystalline characteristics as the deposition surface on which it is formed. For example, epitaxial semiconductor material deposited on a {100} crystal plane may be oriented {100}. In some embodiments, the epitaxial growth and / or deposition process may be selective in formation on semiconductor surfaces and may not deposit material on dielectric surfaces, such as silicon dioxide or silicon nitride surfaces.

[0038] The gate stacks of both nFET and pFET structures (in embodiments having both types of regions) include a work function material (WFM) layer. Non-limiting examples of suitable work function (gate) metals include p-type work function materials and n-type work function materials. P-type work function materials include compositions such as ruthenium, palladium, platinum, cobalt, nickel, and conductive metal nitrides such as TiN, WN, or any combination thereof. N-type metal materials include compositions such as hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), aluminides, or any combination thereof.

[0039] The work function material may be deposited by any suitable deposition process, such as ALD, CVD, PECVD, PVD, plating, and thermal or e-beam evaporation. During deposition, pinch-off of the work function material between the semiconductor fins is essentially avoided. The WFM layer is removed from one of the regions in structures including both nFET and pFET regions, while the other region is protected. An SC1 etch, SC2 etch, or other suitable etching process may be employed to remove selected portions of the initially deposited WFM layer. A new WFM layer appropriate for that region is then deposited. Devices formed in the nFET region will accordingly include a WFM layer (gate electrode) having a first composition, while devices in the pFET region will have a WFM layer having a second composition. For example, the WFM employed in the nFET region may be a Ti, Al, TiAl, TiAlC, or TiAlC layer, or a metal stack, such as TiN / TiAl / TiN, TiN / TiAlC / TiN, TiN / TaAlC / TiN, or any combination of aluminum alloy and TiN layers. The WFM layer employed in the pFET region can be, for example, a TiN, TiC, TaN, or tungsten (W) layer. The threshold voltage (Vt) of nFET devices is highly sensitive to the thickness of the work function material, such as titanium nitride (TiN).

[0040] In light of the foregoing discussion, it will be appreciated that, in general terms, an exemplary semiconductor structure 150 according to an aspect of the present invention includes a semiconductor channel structure having a body 152 and a tip 154, and a dielectric spacer 156 adjacent a portion of the channel structure proximate the tip. The tip is substantially the same thickness as the body. In one or more embodiments, the tip of the channel structure is 70% or more thick than the body. In one or more embodiments, the body of the channel structure is 8 nm or less thick and the tip of the channel structure is 6 nm or more thick. In one or more embodiments, the channel structure includes an alloy of silicon and germanium. In one or more embodiments, the spacer includes silicon nitride and the liner includes amorphous silicon.

[0041] As used herein, "channel structure" refers to the physical region of a device in which a channel is formed when a gate is energized to turn on the device, e.g., the fin in a FINFET, or the nanosheet in a nanosheet FET.

[0042] According to another aspect, a semiconductor structure 1400 includes a semiconductor channel structure 906 having a body and a tip, a dielectric spacer 1118 adjacent a portion of the channel structure proximate the tip, and a liner 1016 between the spacer and the body of the channel structure in direct contact therewith. The liner is thicker away from the tip than it is near the tip. In one or more embodiments, the channel structure includes an alloy of silicon and germanium. In one or more embodiments, the spacer includes silicon nitride. In one or more embodiments, the liner includes amorphous silicon. In one or more embodiments, the liner is 1 nm or less thick at its thickest portion. In one or more embodiments, the tip is 70% or more thick than the body. In one or more embodiments, the body of the channel structure is 8 nm or less thick and the tip of the channel structure is 6 nm or more thick.

[0043] According to another aspect, a method 200 of fabricating a semiconductor structure includes obtaining a precursor structure 300 including a semiconductor channel structure 152 having a body and a tip, depositing a liner 166 around at least the tip of the semiconductor channel structure, at 204, and depositing a spacer 156 on the liner, at 206. In one or more embodiments, the spacer absorbs at least a portion of the liner near the end of the tip, thereby absorbing the tip less than would be absorbed in the absence of the liner. In one or more embodiments, the channel structure includes an alloy of silicon and germanium. In one or more embodiments, the spacer includes silicon nitride. In one or more embodiments, the liner includes amorphous silicon. In one or more embodiments, before the deposition of the spacer, the tip has a thickness equal to the body. In one or more embodiments, after the deposition of the spacer, the tip has a thickness equal to or greater than 70% of the body. In one or more embodiments, before the deposition of the spacer, the body of the channel structure has a thickness equal to or less than 8 nm, and after the deposition of the spacer, the tip of the channel structure has a thickness equal to or greater than 6 nm. In one or more embodiments, prior to spacer deposition, the liner is 1 nm thick or less, and after spacer deposition, remnants of the liner are detectable at the tip by energy dispersive x-ray spectroscopy (EDX).

[0044] Although the description of various embodiments of the present invention has been presented for illustrative purposes, they are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been selected to best explain the principles of the embodiments, practical applications, or technical improvements to the technology found in the market, or to allow other skilled in the art to understand the embodiments disclosed herein. It should be understood that "adjacent" does not mean "in direct contact" and that there may be intervening layers or features between "adjacent" structures, features, or layers.

Claims

1. 1. A semiconductor structure comprising: a semiconductor channel structure having a body and a tip; a dielectric spacer adjacent to the tip portion, A semiconductor structure, wherein the tip has a thickness that is 70% or greater than the thickness of the body.

2. The structure of claim 1 , wherein the body of the channel structure has a thickness of 8 nm or less and the tip of the channel structure has a thickness of 6 nm or more.

3. The structure of claim 1 , wherein the channel structure comprises silicon.

4. The structure of claim 3 , wherein the channel structure comprises an alloy of silicon and germanium.

5. The structure of claim 1 , wherein the spacers comprise silicon nitride and the liner comprises amorphous silicon.

6. 1. A semiconductor structure comprising: a semiconductor channel structure having a body and a tip; a dielectric spacer adjacent to the tip; a liner between and in direct contact with the spacer and the body of the channel structure, the liner being thicker away from the tip than it is near the tip.

7. The structure of claim 6 , wherein the channel structure comprises an alloy of silicon and germanium.

8. The structure of claim 7 , wherein the spacers comprise silicon nitride.

9. The structure of claim 8 , wherein the liner comprises amorphous silicon.

10. 7. The structure of claim 6, wherein said liner is less than 1 nm thick at its thickest point.

11. The structure of claim 10 , wherein remnants of the liner are detectable at the tip by Energy Dispersive X-ray Spectroscopy (EDX).

12. 7. The structure of claim 6, wherein the thickness of said tip is 70% or greater than the thickness of said body.

13. The structure of claim 6 , wherein the body of the channel structure has a thickness of 8 nm or less and the tip of the channel structure has a thickness of 6 nm or more.

14. 1. A method of fabricating a semiconductor structure, comprising: obtaining a precursor structure comprising a semiconducting channel structure having a body and a tip; protecting said tip by depositing an amorphous silicon liner at least around said tip; and absorbing at least a portion of the liner around the tip by depositing a silicon nitride spacer on the liner, the spacer absorbing the tip to a lesser extent than would be the case if the liner were not present.

15. The method of claim 14 , wherein in the step of obtaining the precursor structure, the channel structure comprises silicon.

16. The method of claim 15 , wherein in the step of obtaining the precursor structure, the channel structure comprises an alloy of silicon and germanium.

17. The method of claim 14 further comprising forming the tip and the body to the same thickness.

18. 20. The method of claim 17, further comprising reducing a thickness of the tip to a minimum of 70% of the body during deposition of the spacer.

19. forming the body and the tip of the channel structure to a thickness of 8 nm or less; reducing a thickness of the tip of the channel structure to a minimum of 6 nm during deposition of the spacer; 20. The method of claim 17, further comprising:

20. The method of claim 17 , further comprising depositing the liner to a thickness of 1 nm or less.

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