A low transistor count binary adder.

Abstract

A method for implementing a logic circuit employing a combination of binary adders of different lengths with sum and carry outputs and AND gates, comprising replacing a CMOS implemented binary adder with an improved binary adder consisting of a logic block for performing a sum between the binary inputs of the logic block and a restore block connected between the output of the logic block and an output of the binary adder circuit to compensate for voltage level loss when the output is at a high or low logic state. A CMOS AND gate with a high fan-in AND gate above a predefined threshold is replaced with an AND gate consisting of a logic block for performing an AND operation between the binary inputs of the logic block and a restore block connected between the output of the logic block and an output of the AND gate to compensate for voltage level loss when the output is at a high or low logic state.

Description

[Technical field]

[0001] The present invention relates to the field of static logic digital circuits, and more particularly to an efficient design of binary adders that allows reducing the number of transistors required, the semiconductor area, and the power consumption. [Background technology]

[0002] Binary adders are key building blocks used in VLSI circuits for arithmetic operations, multiplexing, and digital filters. The circuit performance of a multi-bit adder depends on the design of the elementary adder and the topology of multiple elementary adders forming the multi-bit adder, i.e., cascaded stages, tree structures, etc.

[0003] CMOS gates are superior to single-type MOSFETs in terms of power dissipation, but inferior in packing density and speed. CMOS gates are also limited to a relatively small fan-in (the number of inputs a gate can handle - up to four inputs in most cases), so functions higher than simple logic (e.g., arithmetic operations) require cascading multiple stages of CMOS gates, which increases semiconductor area, as well as power dissipation and latency. Furthermore, advanced CMOS technology nodes (i.e., from 65 nm down to 3 nm) suffer from high static power dissipation (due to subthreshold and junction leakage). Because CMOS adders are complex and use a relatively large semiconductor area, other alternatives are sought, either through alternative topologies or other types of logic.

[0004] A comprehensive study of 1-bit full adder cells has been conducted by Mehedi et al. (Comprehensive study of 1-Bit full adder cells: review, performance comparison, and scalability analysis, Mehedi Hasan, Abdul Hasib Siddique, Abdal Hoque Mondol, Mainul Hossain, Hasan U. Zaman & Sharnali Islam. SN Applied Sciences volume 3, Article number: 644, 2021), who discussed the advantages and disadvantages of single-transistor logic adders such as complementary pass logic (CPL), where voltage swing degradation is the main concern, or transmission-gate (TG)-based adders, where the voltage swing degradation issue is solved but poor drive power is the main challenge. US Patent No. 4,559,609 describes such a TG adder. Hybrid logic-based full adder circuits that attempt to solve the voltage swing degradation suffer from either increased area, higher transistor count, or both. Recent Gate Diffusion Input (GDI) adders such as those described by Arkadiy Morgenshtein et al. (Arkadiy Morgenshtein et al., Full-Swing Gate Diffusion Input logic-Case-study of low-power CLA adder design, Integration-the VLSI journal Vol47, pp.62-70, 2014) also suffer from voltage degradation and reduced drive capability. Mehedi et al. analyzed other implementations of adders that all suffer from one or more of the above-mentioned drawbacks. In general, pass-transistor-based adders such as those described in U.S. Pat. No. 4,905,180 are at a disadvantage over CMOS adders because NMOS transistors are weak conductors for logic "1" and PMOS transistors are weak conductors for logic "0".Propagating a logic "1" through an NMOS transistor results in impaired signal integrity due to a voltage drop at the output (Vdd-Vtn instead of Vdd). Similarly, propagating a logic "0" through a PMOS transistor results in |Vtp| at the output instead of zero voltage (i.e., ground).

[0005] Most basic CMOS 1-bit half adders (1bHA) consist of a 2-input XOR gate to compute the sum and a 2-input AND gate to compute the carry of the addition operation of two 1-bit numbers. U.S. Pat. No. 4,054,788, for example, describes one of many implementations of a 1bHA that improves latency at the expense of increased transistor count (for CMOS) and increased complexity (i.e., resistors). It is difficult to devise a 1bHA circuit that outperforms CMOS on all performance criteria (i.e., area, power, and latency).

[0006] The smallest CMOS 1-bit full adder (1bFA) contains 28 transistors. As discussed by Mehedi et al., alternatives containing fewer transistors are inferior in either signal integrity, drive power, semiconductor area, or a combination thereof.

[0007] Apart from 1-bit adders, 4-bit adders are most commonly used in designing multi-bit adders (i.e., 8-bit, 16-bit, 32-bit, and 64-bit). 4-bit adder circuits either exhibit a regular repetitive structure by chaining or cascading 1-bit adders, or trade off increased area and complexity (irregular structure) for improved speed. The literature is rich in 4-bit adders with different architectures. The Carry Ripple Adder (CRA) is described in U.S. Pat. No. 4,439,835 and U.S. Pat. No. 6,978,290 by concatenating four 1bFAs in series. It is the most basic of 4-bit adders and has a simple and regular structure. However, the CRA is slow for multi-bit addition of binary numbers (e.g., 16-bit). It is characterized by O(n) area and latency, where n is the number of additional bits. US Patent No. 3,100,835, US Patent No. 5,027,312, and US Patent No. 5,396,445 described a carry-select-adder (CSelA) that improves on the latency of the CRA. It consists of two parallel carry-propagate adders and a multiple conversion unit. CSelA has an O(n) area and

number

[0008] It is therefore an object of the present invention to provide 1-bit and 4-bit adder circuit implementations that reduce the number of transistors required compared to similar implementations using known CMOS technology.

[0009] It is another object of the present invention to provide 1-bit and 4-bit adder circuit implementations that reduce power dissipation.

[0010] Another object of the present invention is to provide an arbitrary multi-bit adder implementation that saves semiconductor area and reduces latency and power dissipation.

[0011] Other objects and advantages of the present invention will become apparent as the description proceeds. Summary of the Invention

[0012] 1. A 1-bit binary adder with a reduced number of transistors and semiconductor area having sum and carry outputs, comprising: a) a logic block for performing summation between binary inputs of the logic block; b) a restoration block connected between the output of the logic block and the output of the binary adder circuit for compensating for voltage level loss when the output is in a high logic state or a low logic state.

[0013] A multi-bit adder implemented by a combination of the 1-bit binary adders described above.

[0014] The voltages at the sum and carry outputs can conform to a "1" logic level or a "0" logic level.

[0015] In one embodiment, the number of transistors required to implement a binary adder is less than 28.

[0016] The binary adder according to claim 1 may be implemented as a full adder (FA) or as a half adder (HA) or as a combination thereof.

[0017] The recovery block is -Standard CMOS inverter, -Standard CMOS buffer, - Schmitt trigger, -Any combination of them It may consist of:

[0018] 1. A method for implementing a logic circuit employing a combination of binary adders of different lengths with sum and carry outputs and AND gates, comprising: a) replacing at least one known CMOS implemented binary adder with an improved binary adder, the improved binary adder comprising: a.1) a logic block for performing summation between binary inputs of the logic block; a.2) a restore block connected between the output of the logic block and the output of the binary adder circuit for compensating for voltage level loss when the output is in a high or low logic state; b) replacing at least one CMOS AND gate having a high fan-in AND gate above a predefined threshold with an improved AND gate, the improved AND gate comprising: b.1) a logic block for performing an AND operation between binary inputs of the logic block; and b.2) a restore block connected between the output of the logic block and the output of the AND gate to compensate for voltage level loss when the output is in a high or low logic state.

[0019] 1. A method for implementing a logic circuit employing a combination of binary adders of different lengths with sum and carry outputs and AND gates, comprising: a) replacing at least one known CMOS implemented binary adder with an improved binary adder, the improved binary adder comprising: a.1) a logic block for performing summation between binary inputs of the logic block; a.2) a restore block connected between the output of the logic block and the output of the binary adder circuit for compensating for voltage level loss when the output is in a high or low logic state; a.3) replacing at least one CMOS AND gate having a high fan-in AND gate above a predefined threshold with an improved AND gate, the improved AND gate comprising: b.1) a logic block for performing an AND operation between binary inputs of the logic block; and b.2) a restore block connected between the output of the logic block and the output of the AND gate to compensate for voltage level loss when the output is in a high or low logic state.

[0020] The high fan-in AND gate further includes a pull-down block connected between the logic block and the output of the AND gate for further discharging the voltage corresponding to a high logic state to ground following a logic operation involving a low logic state, in addition to discharging via an inherent leakage path.

[0021] The pull-down block is -diode, a transistor configured to operate as a diode; a plurality of transistors configured to operate as diodes; - A combination of PMOS and NMOS transistors acting as a diode may be selected from the group:

[0022] A logic block of a high fan-in AND gate can be a stack of connected transistors implementing an AND gate, or a parallel connection of transistors implementing an AND gate, or a combination thereof.

[0023] The default fan-in threshold may be three.

[0024] A multi-bit adder implemented by a combination of the 1-bit binary adders described above and at least one high fan-in AND gate.

[0025] A multi-bit binary adder with reduced number of transistors and semiconductor area having sum and carry outputs, comprising a combination of two or more parallel or series connected 1-bit and / or 4-bit binary adders, each 1-bit and / or 4-bit adder having: a) a logic block for performing summation between binary inputs of the logic block; b) a restoration block connected between the output of said logic block and the output of said binary adder circuit for compensating for voltage level loss when the output is in a high logic state or a low logic state.

[0026] The addends may contain any number of bits and may be connected in a hierarchical architecture.

[0027] A binary adder may be used to perform the subtraction operation, for example, using two's complement.

[0028] Unless otherwise defined, all technical and / or scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Methods and materials similar or equivalent to those described herein may be used in the practice or testing of embodiments of the present invention, and exemplary methods and / or materials are described below. In case of conflict, the patent specification, including definitions, shall control. In addition, the materials, methods, and examples are illustrative only and are not intended to be necessarily limiting.

[0029] The above and other features and advantages of the present invention will be better understood through the following illustrative and non-limiting detailed description of preferred embodiments of the invention, with reference to the accompanying drawings. [Brief description of the drawings]

[0030] [Figure 1] FIG. 1 is a circuit diagram of a 1-bit half adder of the present invention using a single transistor as a logic element, according to an embodiment of the present invention, which is made of 12 transistors. [Diagram 2] FIG. 2 shows another embodiment of a 1-bit half adder consisting of 12 transistors, combining single transistor logic and known CMOS logic. [Diagram 3] FIG. 3 is a circuit diagram of the smallest known CMOS low-voltage 1-bit full adder, which contains 14 CMOS pairs, i.e., 28 transistors. [Figure 4] FIG. 4 is a circuit diagram of a hybrid 1-bit full adder of the present invention, which includes 18 transistors in combination with CMOS logic. [Diagram 5] FIG. 5 is a circuit diagram of a 1-bit full adder of the present invention, which includes 22 transistors. [Figure 6] FIG. 6 shows another circuit diagram implementation of a 1-bit full adder of the present invention, which includes 16 transistors. [Figure 7] FIG. 7 is a block diagram of a three-input AND gate as described in PCT / IL2022 / 050981. [Figure 8] FIG. 8 is a block diagram of a 4-bit carry propagate adder (CRA) architecture that includes four 1-bit full adders connected in series (prior art). [Figure 9] FIG. 9 is a block diagram of a 4-bit carry-save adder (CSA) architecture (prior art). [Figure 10]FIG. 10 is a circuit diagram of a parallel prefix adder basic architecture known as a carry lookahead adder (CLA) (prior art). [Figure 11] FIG. 11 is a block diagram illustrating an implementation of a CLA with half and full adders of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031] The present invention describes low transistor count static 1-bit and 4-bit base adders that can be used to design any multi-bit adder to achieve area savings, reduced power dissipation, and lower latency. The 1-bit and 4-bit adder circuits provided by the present invention use fewer transistors than the same circuits that can be implemented using existing CMOS technology.

[0032] The present invention relates to digital circuits, in particular binary adders, which employ single-transistor based logic, i.e., circuits in which the addition function is accomplished by non-CMOS logic. The method of the present invention can be implemented in any adder architecture, including, but not limited to, parallel prefix adders (PPA - adders that use prefix arithmetic to perform efficient addition), such as the Kogge-Stone adder, the Brent-Kung adder (which is a parallel prefix of the CSA adder form), tree adders, such as the Wallace tree adder, and others.

[0033] Multiple adders can be further combined in series or parallel to form addition, subtraction, multiplication, and division circuits. The preferred embodiments of the present invention and their advantages can be better understood by referring to Figures 1-11, in which like numerals are utilized for like and corresponding parts.

[0034] A half adder with binary inputs A and B computes the sum output as follows:

number

[0035] The bar in equation (1) indicates the complement of the value, and the plus sign represents a logical OR.

number

[0036] The carry of the half adder is C out =AB (Formula 2) It is.

[0037] Equation (2) is equivalent to a logical AND operation on the binary numbers A and B.

[0038] Referring now to the drawings, and specifically to FIG. 1, the 1-bit half adder of FIG. 1 uses single transistor logic.

[0039] The 1-bit half adder combines two 1-bit binary numbers to form their sum and carry, and any carry from a previous operation is ignored. Two 1-bit inputs 1 and 2 are connected to multiple gates of single-type transistors that calculate the binary sum. A drive voltage 3 provides a supply voltage to the adder. According to the present invention, a 1-bit half adder novel implementation is provided that includes a first and a second block. The first block consists of a number of single-type transistors 4-11 to perform the addition of two 1-bit binary numbers (inputs 1, 2). The second block includes transistors 12-15 and is adapted to restore the signals generated by the first block and output the sum (Sum) and the carry (Cout) to an acceptable voltage level. In one embodiment of the half adder, the threshold voltage and channel width of the transistors 4-5 may be different from that of the transistors 6-7 or 8-9 and the transistors 10-11. In another embodiment, the threshold voltage and channel width of the transistors 12, 13, or 14, 15 may be different from that of the transistors 4-11. In another embodiment of the adder depicted in FIG. 1, transistors 4, 5 have a higher threshold voltage that is different from the threshold voltage of transistors 6, 7. In another embodiment, transistors 8 and 9 have a different threshold voltage and channel width than transistors 10-11, as well as transistors 4, 5 versus transistors 6, 7. The use of multiple threshold voltages as well as multiple channel widths allows for tuning of the half adder to output an acceptable voltage and reduce power loss.

[0040] In one embodiment, a 1-bit half adder is implemented by connecting two 1-bit inputs to multiple gates of single type transistors that compute the binary addition. The sum is then generated by a first block of 1-bit half adders made of a first group of transistors. The carry is generated by a second block of 1-bit half adders made of a second group of transistors.

[0041] Figure 2 presents another implementation of a half adder according to the invention. Two 1-bit inputs 18 and 19 are connected to a number of single-type transistors that calculate the binary addition. A drive voltage Vdd provides the supply voltage to the adder. According to the invention, a 1-bit half adder novel implementation is provided that includes a first block of transistors 20-25 for generating the sum 32 and a second block of transistors 26-31 for generating the carry 33.

[0042] Figure 3 presents the smallest known CMOS low voltage 1-bit full adder implementation, containing 28 transistors. The number of transistors required to implement a binary adder may be less than 28. Two 1-bit numbers 34, 36 and a carry 35 are fed into the circuit to obtain a sum 37 and an additional carry 38 (A+B|Carry=Sum|Carry). In Figure 3, the 1-bit full adder is formed by cascading two 1-bit half adders. A drive voltage Vdd provides the supply voltage to the adder.

[0043] The 1-bit binary numbers (A,B) 34 and 36 and the carry (Cin) 35 from the previous stage are added to form a sum 37 and a carry 38, as given by:

[0044]

number

[0045]

number

[0046] A different Boolean representation of equations (3)-(4) can be obtained as follows:

[0047]

number

[0048]

number

[0049] In the formula, the symbol

number

[0050] 4 illustrates a 1-bit full adder implementation including 18 transistors and using single-transistor logic according to one embodiment of the present invention based on equations (5)-(6). Two 1-bit binary numbers 39 and 40 are added including a carry 41 from the previous stage. The first block consists of multiple single-type transistors 42-51 to compute the carry-out addition of the two 1-bit binary numbers. Transistors 42-45 perform an XNOR operation on the inputs 39 and 40 (i.e.,

number

[0051] The transistors 50-51 act as selectors and output a carry based on the inputs 39-41 (A, B, carry). Whenever the inputs 39, 40 are either ("0", "0") or ("1", "1"), the selectors 50, 51 output the input 39 as the carry, i.e., Cout=A and the Boolean operation

number

[0052] Whenever the inputs 39, 40 are odd "1" parity, either ("1", "0") or ("0", "1"), the output of the selectors 50, 51 is the input carry, i.e., the Boolean operation

number

[0053] The sum and output carry are provided at the output of a second block (the restore block) of transistors 52-59 to compensate for voltage level loss when the output is in a high or low logic state. The restore block can consist of a standard CMOS inverter, a standard CMOS buffer, a Schmitt trigger, or any combination thereof.

[0054] The second block is arranged to restore the sum and carry signals generated by the first block and output the sum and carry at an acceptable voltage level. In one embodiment of the full adder, the threshold voltages and channel widths of transistors 42-49 may be different from those of transistors 50-51 (implementing the selector) and transistors 52-59. In another embodiment of the adder depicted in FIG. 4, transistors 42, 43 or transistors 46, 47 have threshold voltages different from those of transistors 44, 45 or 48, 49 or 50, 51. The use of multiple threshold voltages as well as multiple channel widths is done to tune the full adder to output an acceptable voltage and reduce power loss. A drive voltage Vdd provides the supply voltage to the adder.

[0055] 5 is another implementation of a 1-bit full adder according to the present invention, including first and second blocks including 22 transistors based on equations (3)-(4) and using single-transistor logic. Two 1-bit binary numbers A (62) and B (63) are added including a carry 64 from the previous stage. The first block consists of multiple single-type transistors to perform the addition of two 1-bit binary numbers. Transistors 65-70 perform an XOR operation on inputs and (i.e.,

number

[0056] Transistors 75-82 act as AND-OR gates that determine the carry result according to equation (4). Transistors 75-78 perform a logical AND function between inputs A 62 and B 63, and transistors 79-82 perform a logical AND function between the carry 64 and

number

[0057] 6 is another implementation of a 1-bit full adder according to the present invention, including 16 transistors using transmission gates 90, 91, and 94, 95, and 96-99, and based on equations (3)-(4). Two 1-bit binary numbers A 85 and B 86 are added, including a carry 87 from the previous stage. Transistors 88-91 perform an XOR operation on inputs A 85 and B 86 (i.e.,

number

[0058] Transmission gate transistors 96-99 act as AND-OR gates that determine the carry result according to equation (4). Transmission gate transistors 96-97 perform a logical AND function between inputs A and B, and transmission gate transistors 98-99 perform a logical AND function between Cin and

number

[0059] FIG. 7 is a block diagram of a three-input AND gate as described in PCT / IL2022 / 050981 (of the same applicant). The embodiment of the multi-input AND gate of FIG. 7 is used in some of the multi-bit full adders described in this invention. In one embodiment of the circuit of FIG. 7, the inputs 102-104 are fed into the gates of an n-type transistor stack operating as a logical AND gate. When all transistors are in the "ON" state, the supply voltage Vdd is transferred to wire 105. Restore block 106b compensates for the threshold voltage drop of stack 102-104. Pull-down block 106a pulls the voltage on wire 105 to ground when any of the inputs 102-104 is a "0".

[0060] FIG. 8 is a generalized block diagram of a 4-bit carry propagate adder (CRA architecture) as described in US Pat. No. 4,439,835 and US Pat. No. 6,978,290, which includes four 1-bit full adders 122-125 in series. The carry input 108 of the first adder is "0" (i.e., ground) but can also be "1". The carry input of any other adder in the series is fed with the carry output of the preceding adder. Two 4-bit numbers are added. The first added bits are 109, 111, 113, 115 (109 is the LSB and 115 is the MSB), the second added bits are 110 (LSB), 112, 114, 116 (MSB). The augend bits are 117 (LSB), 118, 119, 120 (MSB) and the carry is 121. Prior art elements 122-125 include the known CMOS 1-bit full adder of Figure 3. In one embodiment of the present invention, various combinations of single or multiple arrangements of the known CMOS 1-bit full adder of Figure 3 and the 1-bit full adders of Figures 4-6 result in a CRA topology with fewer transistors, reduced latency, and reduced power dissipation. In another embodiment of the present invention, a CRA including all elements 122-125 of the full adders of Figures 4-6 results in fewer transistors, reduced latency, and reduced power dissipation.

[0061] FIG. 9 (PRIOR ART) presents a 4-bit carry-save adder (CSA) as described in US Pat. No. 7,111,033. Two 4-bit numbers are added. The first added bits are 134-137 (134 being the LSB and 137 being the MSB) and the second added bits are 138 (LSB), 139, 140, 141 (MSB). The augend bits are 142 (LSB), 143, 144, 145 (MSB) and the carry is 146. Elements 126-130 consist of known CMOS 1-bit half adders (i.e. the full adder of FIG. 3 with the carry grounded) and elements 131-133 consist of the known CMOS 1-bit full adder of FIG. 3. In one embodiment of the present invention, the arrangement of one or more of various combinations of the inventive half and full adders of Figures 1-2 and 3-6, respectively, results in a CRA with fewer transistors, reduced latency, and reduced power dissipation. In another embodiment of the present invention, a CSA that includes all elements 126-130 of the half adders of Figures 1-2 and the full adders of Figures 4-6 results in a CRA topology with fewer transistors, reduced latency, and reduced power dissipation.

[0062] A basic parallel prefix adder of 4-bit carry-ahead adder (CLA) as described in US Pat. No. 5,964,827 is depicted in FIG. 10. The first added bits are 147-150 (147 is the LSB and 150 is the MSB), the second added bits are 151 (LSB), 152, 153, 154 (MSB). The carry bit is C0 (155). The augend bits are 156 (LSB), 157, 158, 159 (MSB), and the carry is 160. Gates 161-163 are high fan-in CMOS AND gates. In one embodiment of the present invention, various combinations of single or multiple AND gates of FIG. 7 are substituted for the known CMOS AND gates 161-163 to reduce the number of transistors, thus saving area, shortening the critical path of the adder, as well as reducing power dissipation. Five, four or three input AND gates can be constructed as presented in PCT / IL2022 / 050981 (of the same applicant). In yet another embodiment of the present invention, all AND gates 161-163 are replaced with equivalent gates of the AND gates of Figure 7 to further save area, shorten the critical path of the adder, as well as reduce power dissipation.

[0063] FIG. 11 presents a different block diagram of the same 4-bit CLA of FIG. 10 using half adders and full adders implemented in accordance with the present invention. The input carry bit is 182. Two 4-bit numbers A and B (A inputs 164-167 and B inputs 168-171) are summed. The augend bits are 183 (LSB), 184, 185, 186 (MSB) and the carry is 187. Gates 175-177 are high fan-in CMOS AND gates of 3 or more inputs. Prior art elements 172-174 are known CMOS 1-bit half adders and 178-181 are known CMOS 1-bit full adders.

[0064] In one embodiment of the present invention, various combinations of one or more of the inventive half adders of Figures 1-2, the full adders of Figures 3-6, and the equivalent AND gates of Figure 7 are variously combined with known CMOS circuits to reduce transistor count, thereby saving area, shortening the critical paths of the adders, and reducing power dissipation. In another embodiment of the present invention, all the half adders 172-174, all the high fan-in AND gates 175-177, and all the full adders 178-181 are replaced by the inventive half adders of Figures 1-2, the full adders of Figures 4-6, and the equivalent AND gates of Figure 7.

[0065] According to another embodiment, additions using a higher number of bits (such as 8-bit addition, 16-bit addition, 32-bit addition, and the like) are implemented by using any combination of 1-bit adders and / or 4-bit adders to form adders having a higher number of bits, as well as adders connected in a hierarchical architecture (used to reduce delay). In another embodiment, a series of two, four, or eight 4-bit adders of Figures 8-11 may result in an 8-bit adder, a 16-bit adder, and a 32-bit adder, respectively. In another embodiment, a suitable series of adders of Figures 1-6 may form any adder of any size. In another embodiment, a series of adders of Figures 1-6 with adders of Figures 8-11 may form any adder of any size. In another embodiment, the adders of the present invention may be used in any multi-bit adder architecture.

[0066] In one embodiment, the multi-bit binary adder includes a combination of two or more parallel or series connected 1-bit and / or 4-bit binary adders having sum and carry outputs, each 1-bit and / or 4-bit adder including a logic block for performing summation between binary inputs of said logic block and a restore block connected between an output of the logic block and an output of the binary adder circuit for compensating for voltage level loss when the output is in a high or low logic state.

[0067] Although the above embodiment relates to addition operations, the present invention may be used for subtraction operations as well, as will be appreciated by those skilled in the art. For example, subtraction of two binary numbers can be accomplished by adding two's complements (two's complement is a mathematical operation for reversibly converting a positive binary number to a negative binary number with an equivalent value, using the binary number with the most significant digit value to indicate whether the binary number is positive or negative). In a first step, a given decimal number is converted to a binary number. In a next step, the one's complement of the binary number is taken by converting "0" to "1" and "1" to "0", respectively. In a next step, a "1" is added to the one's complement. When the most significant bit is "1", the number is marked as the negative value of the subtrahend relative to the minuend, and the final carry (if any) is ignored. If the MSB bit in the result of the addition is "0", the result of the addition is the correct answer. If the MSB bit is "1", this suggests that the answer has a negative sign. In this case, the true digit is obtained by the two's complement of the result of the addition.

[0068] In one embodiment, a logic circuit employing a combination of a binary adder with sum and carry outputs and an AND gate is implemented by replacing at least one CMOS implemented binary adder with an improved binary adder consisting of a logic block for performing a summation between the binary inputs of the logic block and a restoration block connected between the output of the logic block and an output of the binary adder circuit to compensate for voltage level loss when the output is at a high logic state or a low logic state, and replacing at least one CMOS AND gate having a high fan-in AND gate above a predefined threshold with an improved AND gate consisting of a logic block for performing an AND operation between the binary inputs of the logic block and a restoration block connected between the output of the logic block and an output of the AND gate to compensate for voltage level loss when the output is at a high logic state or a low logic state.

[0069] In one embodiment, a logic circuit employing a combination of a binary adder with sum and carry outputs and an AND gate is implemented by replacing at least one CMOS implemented binary adder with an improved binary adder consisting of a logic block for performing a summation between the binary inputs of the logic block and a restore block connected between the output of the logic block and an output of the binary adder circuit to compensate for voltage level loss when the output is at a high logic state or a low logic state, and replacing at least one CMOS AND gate having a high fan-in AND gate above a predefined threshold with an improved AND gate consisting of a logic block for performing an AND operation between the binary inputs of the logic block and a restore block connected between the output of the logic block and an output of the AND gate to compensate for voltage level loss when the output is at a high logic state or a low logic state.

[0070] It should be understood that certain embodiments of the invention that are described for clarity in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various embodiments of the invention that are described for brevity in the context of a single embodiment may also be provided separately or in any suitable subcombination or as suitable in any other described embodiment of the invention. Certain features described in the context of various embodiments are not to be construed as essential features of those embodiments, unless the embodiment is inoperative without those elements.

[0071] While the present invention has been described in conjunction with specific embodiments thereof, it is evident that many alternatives, modifications, and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications, and variations that fall within the spirit and broad scope of the appended claims.

[0072] All publications, patents, and patent applications mentioned in this specification are incorporated herein by reference in their entirety to the same extent as if each individual publication, patent, or patent application was specifically and individually indicated to be incorporated herein by reference. In addition, citation or identification of any reference within this application shall not be construed as an admission that such reference is available as prior art to the present invention. To the extent section headings are used, they should not be necessarily construed as limiting.

Claims

1. 1. A 1-bit binary adder with a reduced number of transistors and semiconductor area having sum and carry outputs, comprising: a) a logic block for performing summation between binary inputs of said logic block; b) a restore block connected between the output of said logic block and the output of said binary adder circuit for compensating for voltage level loss when said output is in a high or low logic state; A 1-bit binary adder including:

2. 2. A multi-bit adder implemented by a combination of several 1-bit binary adders of claim 1.

3. 2. The 1-bit binary adder of claim 1, wherein the voltages at the sum and carry outputs are compatible with a "1" logic level or a "0" logic level.

4. 2. The 1-bit binary adder of claim 1, wherein the number of transistors required to implement the binary adder is less than 28.

5. 2. The 1-bit binary adder of claim 1, wherein the number of transistors required to implement the binary adder is 18.

6. 2. The 1-bit binary adder of claim 1 implemented as a full adder (FA).

7. 2. The 1-bit binary adder of claim 1 implemented as a half adder (HA).

8. The recovery block is - standard CMOS inverter, - standard CMOS buffer, - Schmitt trigger, - combinations of these 2. The 1-bit binary adder of claim 1, comprising:

9. 10. A multi-bit adder implemented by a combination of the 1-bit binary adder of claim 1 and at least one high fan-in AND gate.

10. The 1-bit half adder is a) connecting two 1-bit inputs to multiple gates of single type transistors which compute binary addition; b) generating a sum with a first block of said one-bit half adders comprising a first group of transistors; c) generating a carry output by a second block of said one-bit half adders comprising a second group of transistors.

2. The 1-bit binary adder of claim 1 implemented by:

11. the 1-bit full adder includes a first block and a second block using single transistor logic; - two 1-bit binary numbers are added together with a carry from the previous stage, said first block consists of a number of single type transistors for performing an addition of two 1-bit binary numbers; - performing an XOR operation on said inputs; 2. The 1-bit binary adder of claim 1, further comprising: performing successive XOR operations with a carry input to obtain the sum of said inputs.

12. A multi-bit binary adder with reduced number of transistors and semiconductor area having sum and carry outputs, comprising a combination of two or more parallel or series connected 1-bit and / or 4-bit binary adders, each 1-bit and / or 4-bit adder having: a) a logic block for performing summation between binary inputs of said logic block; b) a restore block connected between the output of said logic block and the output of said binary adder circuit for compensating for voltage level loss when said output is in a high or low logic state; 2. A multi-bit binary adder comprising:

13. 14. The multi-bit binary adder of claim 13, wherein the addend comprises any number of bits.

14. 14. The multi-bit binary adder of claim 13, wherein the 1-bit binary adders are connected in a hierarchical architecture.

15. 14. A 1-bit binary adder according to claim 1 or 13, used to perform a subtraction operation.

16. 17. The 1-bit binary adder of claim 16, wherein the subtraction operation is performed using two's complement numbers.

17. 1. A method for implementing a logic circuit employing a combination of binary adders with sum and carry outputs and AND gates, comprising: a) replacing at least one CMOS implemented binary adder with an improved binary adder, said improved binary adder comprising: a. 1) a logic block for performing summation between binary inputs of said logic block; a.2) a restore block connected between the output of the logic block and the output of the binary adder circuit for compensating for voltage level loss when the output is in a high or low logic state; b) replacing at least one CMOS AND gate having a high fan-in AND gate above a predefined threshold with an improved AND gate, said improved AND gate having: b. 1) a logic block for performing an AND operation between binary inputs of said logic block; and b. 2) a restore block connected between the output of the logic block and the output of the AND gate for compensating for voltage level loss when the output is in a high or low logic state; A method comprising:

18. 1. A method for implementing a logic circuit employing a combination of binary adders with sum and carry outputs and AND gates, comprising: a) replacing at least one CMOS implemented binary adder with an improved binary adder, said improved binary adder comprising: a. 1) a logic block for performing summation between binary inputs of said logic block; a.2) a restore block connected between the output of the logic block and the output of the binary adder circuit for compensating for voltage level loss when the output is in a high or low logic state; a. 3) replacing at least one CMOS AND gate having a high fan-in AND gate above a predefined threshold with an improved AND gate, said improved AND gate having: b. 1) a logic block for performing an AND operation between binary inputs of said logic block; and b. 2) a restore block connected between the output of the logic block and the output of the AND gate to compensate for voltage level loss when the output is in a high or low logic state.

19. 20. The method of claim 18, wherein the AND gate further includes a pull-down block connected between the logic block and an output of the AND gate for further discharging a voltage corresponding to the high logic state to ground following a logic operation involving a low logic state in addition to discharging via an inherent leakage path.

20. The pull-down block includes: -diode, a transistor configured to act as a diode; - a number of transistors configured to operate as diodes; - A combination of PMOS and NMOS transistors acting as a diode 20. The method of claim 19, wherein the compound is selected from the group consisting of:

21. 20. The method of claim 18, wherein the logic block of the AND gate is a stack of connected transistors that implement the AND gate, or a parallel connection of transistors that implement the AND gate, or a combination thereof.

22. The method of any one of claims 18 to 20, wherein the predefined fan-in threshold is three.

23. 20. The method of claim 18 or 19, wherein the binary adder is a full adder (FA), or a half adder (HA), or a combination thereof.

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