Interposer and package device structure and IC manufacturing method

Abstract

An improved interposer apparatus and method is provided. [Solution] The improved interposer is a wide bandgap semiconductor interposer, such as silicon carbide (SiC). It includes multiple connectors in situ within the interposer to connect the integrated circuit die to the substrate. The multiple connectors may include carbon electrical connectors and angled waveguide connectors within the interposer. The integrated circuit die sits within the recess and is thermally coupled to the silicon carbide (SiC) interposer, thereby providing a heat sink for the integrated circuit die. First and second recesses are formed on separate sides of the silicon carbide (SiC) interposer, and multiple interposers can be stacked on top of each other.

Description

[Technical field]

[0001] This invention relates to integrated circuit (IC) technology, and more particularly to improvements in interposers and packages and processes that improve density, electrical conductivity, signal transfer rates, power and heat dissipation. [Background technology]

[0002] As the packaging density of electrical components in ICs continues to increase, silicon interposers are increasingly being used to interconnect ICs to substrates and circuit boards. Silicon interposers can be used to contiguously support ICs (die or chip) on the silicon interposer with the ICs interconnected by vertical through conductors called through silicon vias (TSVs) and horizontal conductors called redistribution layers (RDLs). Silicon interposers also contain active components that provide electrical communication between the ICs and the substrate.

[0003] During my doctoral dissertation research, I had the opportunity to work with Dr. Aravinda Carr and Dr. Nathaniel R. Quick on the properties and possible applications of laser processed silicon carbide. The results of my work with Dr. Carr and Dr. Quick were published in my doctoral dissertation entitled "Wide Bandgap Materials: Laser Doping and Metallization of SiC, GaN, and AlN" by the Center for Research and Education in Optics and Lasers (CREOL) at the University of Central Florida in Spring 2003.

[0004] Additionally, a technical paper entitled "Analysis of Microstructural Electrical Resistance of Laser Processed SiC for Wide Bandgap Semiconductor Materials" was published by I. Salama, N.R. Quick and Carr in the Journal of Materials Science 40 (2005) 3969-3980.

[0005] Finally, based on the above work, U.S. Patent No. 7,268,063 was issued. U.S. Patent No. 7,268,063 to Carr, Quick and Salama shows a method for in-situ fabrication of semiconductors in a substrate. A first laser beam removes the substrate to form a void therein. A second laser beam forms a first conductive element in the void in the substrate. A third laser beam deposits or deposits a semiconductor material on the first conductive element in the presence of a deposition atmosphere. A fourth laser beam forms a second conductive element on the first semiconductor material. Using this process, Schottky barrier diodes or junction field effect transistors and the like can be fabricated.

[0006] Dr. Carr and Dr. Quick continued their work on silicon carbide and other different wide band gap semiconductors. The following U.S. patents represent the results of continued work by Dr. Carr and Dr. Quick and other collaborators:

[0007] Quick, U.S. Patent No. 5,145,741, shows a technique for forming electrically conductive or semiconductive ceramic passages or regions on carbide and nitride ceramic substrates at room temperature. The process used is controlled oxidation by localized thermal heating (e.g., laser heating) to trace the desired passages on the substrate, and the source of oxygen is air. In another example, carbide and nitride ceramic substrates are converted to electrically conductive or semiconductive ceramics. The substrates are provided with features such as whiskers, fibers, flakes or platelets in the micron range in size by the previously described controlled oxidation by a laser beam process. The resulting conductive or semiconductive passages or surfaces of the substrates comprise electrically conductive or semiconductive non-stoichiometric alumina nitride oxide ceramics when the starting ceramic substrate material is aluminum nitride (AlN), and electrically conductive or semiconductive non-stoichiometric silicon carbide oxide ceramics when the starting ceramic substrate material is silicon carbide (SiC). The channels that penetrate the surface of the flat substrate can act as electrical interconnects, similar to the printed circuits on a printed circuit board, and the resulting semiconductor patterns can act as semiconductor devices, similar to rectifiers, for example. In the case of whiskers, fibers, flakes or platelets, the electrically conductive surfaces can be used directly or in reinforcement, for example by coating the surfaces with other conductive metals or alloys, for example as composites combined with the matrix at the microstructural level.

[0008] Quick's U.S. Patent No. 5,837,607 shows a laser apparatus and method for synthesizing regions of ceramic substrates or thin films, such as in ceramics such as silicon carbide or aluminum nitride, to fabricate electronic devices and circuits as components of ICs. For example, circuit components such as conductive tabs, interconnects, wiring patterns, resistors, capacitors, insulating layers, and semiconductors are synthesized on or within such ceramic bodies. By selecting groups and arrangements of such electronic circuit components in the substrate or thin film, a wide range of circuit applications can be achieved, such as digital logic elements and circuits, transistors, sensors for measuring and monitoring chemical or physical reactions, and interactions of materials, gases, devices, or circuits useful in sensors. Electronic elements and components have the advantage of being thermally compatible with the substrate because they are integrated into the substrate and have compatible thermal expansion coefficients and thermal dissipation.

[0009] Quick's U.S. Patent No. 6,025,609 shows a laser apparatus and method for synthesizing regions of ceramic substrates or thin films, such as in ceramics such as silicon carbide or aluminum nitride, to fabricate electronic devices and circuits as components of ICs. For example, circuit components such as conductive tabs, interconnects, wiring patterns, resistors, capacitors, insulating layers, and semiconductors are synthesized on or within such ceramic bodies. By selecting groups and arrangements of such electronic circuit components within the substrate or thin film, a wide range of circuit applications can be achieved, such as digital logic elements and circuits, transistors, sensors for measuring and monitoring chemical or physical reactions, and interactions of materials, gases, devices, or circuits useful in sensors. Electronic elements and components have the advantage of being thermally compatible with the substrate because they are integrated into the substrate and have compatible thermal expansion coefficients and thermal dissipation.

[0010] Quick's U.S. Patent No. 6,054,375 shows a laser apparatus and method for synthesizing regions of ceramic substrates or thin films, such as in ceramics such as silicon carbide or aluminum nitride, to fabricate electronic devices and circuits as components of ICs. For example, circuit components such as conductive tabs, interconnects, wiring patterns, resistors, capacitors, insulating layers, and semiconductors are synthesized on or within such ceramic bodies. By selecting groups and arrangements of such electronic circuit components within the substrate or thin film, a wide range of circuit applications can be achieved, such as digital logic elements and circuits, transistors, sensors for measuring and monitoring chemical or physical reactions, and interactions of materials, gases, devices, or circuits useful in sensors. Electronic elements and components have the advantage of being thermally compatible with the substrate because they are integrated into the substrate and have compatible thermal expansion coefficients and thermal dissipation.

[0011] Quick's U.S. Patent No. 6,271,576 shows a laser apparatus and method for synthesizing regions of ceramic substrates or thin films, such as silicon carbide or aluminum nitride, to fabricate electronic devices and circuits, such as sensors, as components of ICs. Circuit components, such as conductive tabs, interconnects, wiring patterns, resistors, capacitors, insulating layers, and semiconductors, are synthesized on or within such ceramic bodies. By selecting groups and arrangements of these electronic circuit components within the substrate or thin film, a wide range of circuit applications can be achieved, such as digital logic elements and circuits, transistors, sensors for measuring and monitoring chemical or physical reactions, and interactions of materials, gases, devices, or circuits useful in sensors. The electronic elements and components have the advantage of being thermally compatible with the substrate, since they are integrated into the substrate and have compatible thermal expansion coefficients and thermal dissipation.

[0012] Quick's U.S. Patent No. 6,670,693 shows a laser apparatus and method for synthesizing regions of wide bandgap semiconductor substrates or thin films, such as silicon carbide, aluminum nitride, gallium nitride, and diamond, for fabricating electronic devices and circuits as circuits and components of integrated circuits.

[0013] Quick's U.S. Patent No. 6,930,009 shows a laser apparatus and method for synthesizing wide bandgap semiconductor substrates or thin film regions, such as silicon carbide, aluminum nitride, gallium nitride, and diamond, for fabricating electronic devices and circuits as circuits and components of integrated circuits.

[0014] Quick's U.S. Patent No. 6,939,748 shows a method for fabricating nano-sized semiconductor components within a wide bandgap semiconductor substrate. A first thermal energy beam is directed at a first portion of the wide bandgap semiconductor substrate to transform the structure of the wide bandgap semiconductor substrate into a semiconductor first element that includes a process directed at the thermal energy component. A second thermal energy beam is directed at a second portion of the wide bandgap semiconductor substrate adjacent to the first portion to transform the structure into a semiconductor second element.

[0015] U.S. Patent No. 7,419,887 to Quick and Carr shows an apparatus and method for forming nanostructures with nanoparticles on a substrate. The nanoparticles are attached or deposited on the substrate through nano-sized holes. A laser beam is focused into a nano-sized beam through a concentrator and directed at the particles deposited on the substrate. The apparatus and method are suitable for fabricating nano-linewidth patterns of conductors, semiconductors and insulators on semiconductor wafers by direct nano-deposition of materials.

[0016] U.S. Patent No. 7,811,914 to Quick and Carr shows an apparatus and method for improving thermal conductivity in a substrate of a non-wide bandgap material. A beam is directed onto the substrate in the presence of a first doping gas to convert a region of the substrate to a wide bandgap material, thereby increasing the thermal conductivity of the substrate and cooling the non-wide bandgap material. In one example, this is applied to a carbon-rich layer formed within the wide bandgap material. In another example, a carbon-rich layer formed within the wide bandgap material, but with a bottom portion extending outwardly to the outer surface of the substrate, is applied to improve cooling of the substrate.

[0017] U.S. Patent No. 7,897,492 to Quick shows a method for forming a layer of wide band gap material in a non-wide band gap material. The method comprises providing a substrate of non-wide band gap material and converting the layer of non-wide band gap material to a layer of wide band gap material. A further conversion process can form an improved component, such as a wide band gap semiconductor device, within the wide band gap material.

[0018] The invention is an improvement over existing techniques for forming electrical conductors and fabricating wide bandgap materials using energetic beams such as laser beams.

[0019] SUMMARY OF THE PRESENT EMBODIMENT It is therefore an object of the present invention to provide an improved interposer and packaged device which represents a significant advancement in solid-state technology to accommodate improvements in the above mentioned techniques.

[0020] Another object of the present invention is to provide an improved interposer that exhibits superior interconnect density, electrical conductivity, and heat dissipation for ICs.

[0021] The foregoing has outlined some of the objects associated with the present invention. These objects can be understood through the illustrative examples which illustrate the features and applications associated with the present invention. Many other advantages can be obtained by modifying the present invention within the scope of the inventive concept. Thus, further objects of the present invention can be better understood by reference to the following detailed description including the summary of the invention and the preferred embodiment, together with the inventive concept defined in the claims taken in conjunction with the accompanying drawings. Summary of the Invention

[0022] The invention is defined by the appended claims, with specific embodiments illustrated in the accompanying drawings. Briefly, the invention relates to an improved interposer and package device for connecting multiple IC chips to each other and to a substrate to form a package device, as well as techniques for connecting IC chips to a substrate. The improved interposer comprises a silicon carbide (SiC) interposer having first and second exterior surfaces. A plurality of in situ connectors are formed within the silicon carbide (SiC) interposer for connecting the IC chips to the substrate and for connecting the chips to each other.

[0023] In an embodiment of the invention, the plurality of connectors are carbon electrical connectors. In another embodiment of the invention, the plurality of connectors are optical waveguide connectors. In yet another embodiment, at least one of the plurality of in situ connectors within the silicon carbide (SiC) interposer is at a controlled angle relative to the first exterior surface.

[0024] Preferably, the improved interposer is a wide bandgap semiconductor selected from silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AIN), synthetic diamond, glass, and compounds and alloys that enhance the quantum conversion process described in this invention. The connectors are carbon electrical connectors formed by laser irradiation of silicon carbide (SiC). Similarly, the connectors are optical waveguide connectors formed by laser irradiation of silicon carbide (SiC).

[0025] The improved interposer can include a recess formed in the first exterior surface with an IC chip. The IC chip is located in the recess and is thermally coupled to the silicon carbide (SiC) interposer, thereby providing a heat sink for the IC chip. The recess can be formed in the first exterior surface by a laser ablation process. First and second recesses can be formed in separate surfaces of the silicon carbide (SiC) interposer, allowing multiple interposers to be stacked or adjacent to one another.

[0026] An improved interposer can be formed with a hybrid material structure, where, for example, a glass material can be bonded to silicon carbide and laser irradiation can be used to form the interposer. Laser irradiation can be applied to one or more regions of both, or two or more of the hybrid material structures. Hybrid material structures can be made by bonding, matching, embedding or stacking different (one or more) materials together.

[0027] The present invention can also be incorporated into an improved packaging device that directly connects an IC chip to a circuit board, the improved packaging device acting as an interposer as well as a substrate that directly connects an IC chip to a circuit board.

[0028] The present invention may also be incorporated into an improved package substrate core, comprising a high density interconnect laminate, glass or ceramic substrate, which serves as a power source and heat dissipation device for the packaged device and IC chip.

[0029] The above is a rather broad description of the important features related to the present invention. The detailed description that follows will provide a better understanding and a fuller appreciation of the present invention's contribution to the art. Additional features of the present invention are described below, which form part of the inventive concept as set forth in the claims. Those skilled in the art will be able to achieve the same objectives of the present invention by modifying or designing other configurations based on the concepts and specific examples shown herein. Those skilled in the art will also appreciate that such equivalent configurations do not depart from the spirit and concept of the invention as set forth in the claims. [Brief description of the drawings]

[0030] In order to understand the characteristics of the present invention in detail, reference can be made to the embodiments of the individual descriptions of the general outline set forth above. Some embodiments are illustrated in the accompanying drawings. However, the accompanying drawings show only typical embodiments, and therefore do not limit the present invention, and other similarly useful embodiments can be obtained. [Figure 1] 1 shows a laser beam from a laser contacted silicon carbide (SiC) substrate. [Diagram 2] FIG. 2 is a view similar to FIG. 1 showing a laser beam from a laser contacted silicon carbide (SiC) substrate. [Diagram 3] FIG. 3 is a cross-sectional view of FIG. 2. [Figure 3A] FIG. 1 is a cross-sectional view showing a state-of-the-art interconnect. [Figure 3B] FIG. 3B is a top view of layer 2 in FIG. 3A. [Figure 3C] FIG. 2 is a cross-sectional view of the laser conversion interconnect of the present invention. [Figure 3D] FIG. 3C is a top view. [Figure 3E] Illustrates the different geometric shapes that a laser beam can create. [Figure 3F] The first and second laser beams have a circular cross section. [Figure 3G] A shutter element disposed in the optical path of the beam. [Figure 3H] It is a top-hat laser beam with a uniform intensity profile. [Figure 3I] A similar configuration is produced in silicon carbide (SiC) by direct writing of a Gaussian laser beam using galvanometer-optical elements. [Figure 3J] The resulting carbon-rich conductive serpentine structure produced by the laser in Figure 3I. [Figure 3K] FIG. 4 is a perspective view of FIG. 3 showing the in situ laser transformed 3D monolithic pathway. [Figure 3L] FIG. 1 is a perspective view of one large contact split into three different monolithic paths. [Figure 4] A laser conversion process is shown, used through the entire thickness. [Figure 4A] The state of the art of semi-additive interconnect fabrication processes is presented. [Figure 4A1] The second state of the art in semi-additive interconnect fabrication processes is presented. [Figure 4A2] The state-of-the-art of semi-additive interconnection processing and dual damascene patterning processing are presented. [Figure 4B] This is an example of a 3DR configuration with laser thickness processing without drilling. [Figure 4C] It is a layer of silicon carbide (SiC) structure, directly 3D structured at different angles across the entire thickness by laser quantum transformation patterning. [Diagram 5] A silicon carbide (SiC) substrate with grooves to accommodate multiple chips / chiplets with different functions is shown. [Figure 5A]2.5D Interconnect Configurations,We present the first state-of-the-art in the 2.5D bridge architecture landscape. [Figure 5A1] 2.5D Interconnect Configuration,We present the second state of the art in the 2.5D bridge architecture landscape. [Figure 5A2] It presents the state-of-the-art of 2.5D interconnect configurations, 2.5D bridge architecture landscape, and TSMC silicon interposers. [Figure 5B] This shows how silicon carbide (SiC) interposers can be customized to fit the specifications of each chip. [Figure 6] A laser converted silicon carbide (SiC) interposer and 3D integration on a silicon carbide (SiC) thermochip are shown. [Figure 6A] Architectural options are presented, including laser converted silicon carbide (SiC) interposer, laser converted silicon carbide (SiC) thermo chip and substrate. [Figure 6B] An alternative architectural option is presented, a compact configuration that uses a processed silicon carbide (SiC) interposer to eliminate the need for a SiC thermo chip. [Figure 6C] We demonstrate the first co-fabrication of a QCIA (Quantum Transformation Integrated Architecture) architecture, which can accelerate run rates and improve yields. [Figure 6C1] A second co-fabrication of the QCIA (Quantum Transformation Integrated Architecture) architecture is demonstrated, which can accelerate run rates and improve yields. [Figure 6C2] Completed fabrication of the QCIA (Quantum Transformation Integrated Architecture) architecture is demonstrated, enabling accelerated run rates and improved yields. [Figure 6D] A customized point-to-point connection is demonstrated, using the QCIA (Quantum Transform Integrated Architecture) architecture and laser transform patterning or quantum transform patterning (QCP). [Figure 6E] FIG. 7 is a perspective view of FIG. 6 showing 3D integration of multiple IC chips connected on different sides of a silicon carbide (SiC) interposer. [Figure 6F1] 1 is a first illustration showing the current state of the packaging proposed for chip stacking; [Figure 6F2] 2 is a second illustration showing the current state of the packaging for attempted chip stacking. [Figure 6F3] 3 is a third illustration showing the current state of the packaging for attempted chip stacking. [Figure 6F4] 4 is a fourth illustration showing the current state of the packaging for attempted chip stacking. [Figure 7] The option of in situ deposition and patterning of QCIA on organic substrates is presented. [Figure 8] An improved interposer architecture option, with multiple distinct redistribution layers on either side of the interposer's outer surface. [Figure 9] An improved packaged device architecture option further incorporates an improved interposer, shown in FIG. 8, on top of the high density interconnect substrate. [Figure 9A] FIG. 10 is an enlarged portion of FIG. [Figure 9B] FIG. 9B is an enlarged portion of FIG. 9A. [Figure 10] Assembling the different layers shown in FIG. 9 illustrates a first parallel processing feature. [Figure 10A] Assembling the different layers shown in FIG. 9 illustrates a second parallel processing feature. [Figure 11] The fabrication of an improved interposer with multiple redistribution layers is presented using two different fabrication processes. [Figure 12] FIG. 1 is a schematic diagram showing a single unit QCIA interconnect configuration. [Figure 13]1 is a schematic diagram illustrating a core substrate configuration that can be fabricated using the proposed quantum transform patterning process and material set. To facilitate understanding, wherever possible, like elements common to the figures have been numbered the same. Elements and features of one embodiment will be understood to be usefully incorporated in other embodiments without further description. Detailed Description

[0031] 1-4, 4B-5, 5B-6E and 7 show an improved interposer 10 for connecting an IC chip 12 or multiple chips to a substrate 14. The interposer 10 may be comprised of a silicon carbide (SiC) interposer 16. The interposer 10 has a first exterior surface 20 and a second exterior surface 22, and a number of connectors 30 formed within the silicon carbide (SiC) interposer 16 that connect the IC chip 12 to the substrate 14.

[0032] The plurality of connectors 30 can include carbon electrical connectors 32. The plurality of connectors 30 can include optical waveguide connectors 34. Each optical waveguide connector 34 can comprise a tunnel 36 formed in the silicon carbide (SiC) 16 with carbon-rich tunnel walls 38.

[0033] The plurality of connectors 30 formed within the silicon carbide (SiC) interposer 16 may be formed at an angle 40 relative to the first exterior surface 20. The plurality of connectors 30 formed within the silicon carbide (SiC) interposer 16 may be angular monolithic 42 paths formed at an angle 40 relative to the first exterior surface 20. The plurality of connectors 30 may include carbon electrical connectors 32 formed by laser irradiation 50 of the silicon carbide (SiC) 16.

[0034] The plurality of connectors 30 may include optical waveguide connectors 34 formed by laser irradiation 50 of silicon carbide (SiC) 16 .

[0035] The present invention may further include a recess 60 formed in the first exterior surface 20. The IC chip 12 may be disposed within the recess 60 and thermally coupled to the silicon carbide (SiC) interposer 16, thereby providing a heat sink 62 for the IC chip 12. The recess 60 may be formed by a laser ablation process 52 in the first exterior surface 20. The IC chip 12 may then be disposed within the recess 60 and thermally coupled to the silicon carbide (SiC) interposer 16, thereby providing a heat sink 62 for the IC chip 12.

[0036] The present invention is an improved interposer 10 for connecting an IC chip 12 to a substrate 14, the interposer including a wide bandgap interposer 18 having a first outer surface 20 and a second outer surface 22. A plurality of connectors 30 are formed in situ within the wide bandgap interposer 18 to connect the IC chip 12 to the substrate 14. The IC chip 12 can include Si, SiGe, GaN, SiC, and combinations of two or more of Si, SiGe, GaN, SiC, or other chips.

[0037] The present invention is an improved interposer 10 for connecting an IC chip 12 to a substrate 14, including a wide band gap interposer 18 having a first outer surface 20 and a second outer surface 22, and multiple redistribution layers 70 above the first outer surface 20 and below the second outer surface 22. A plurality of connectors 30 are formed in situ within the wide band gap interposer 18 to connect the IC chip 12 to the substrate 14. A plurality of connectors 30 are also formed within the redistribution layers 70 to connect the IC chip 12 to the substrate 14, and also to interconnect the redistribution layers 70 between each other across both the first outer surface 20 and the second outer surface 22 of the interposer 10.

[0038] The present invention is an improved interposer 10 for connecting an IC chip 12 to a substrate 14, including a wide band gap interposer 18 having a first outer surface 20 and a second outer surface 22, and multiple redistribution layers 70 above the first outer surface 20 and below the second outer surface 22. The number, material type and size of the redistribution layers 70 on both outer surfaces 20 and 22 of the interposer 10 need not be the same. A plurality of connectors 30 are formed in situ within the wide band gap interposer 18 to connect the silicon IC chip 12 to the substrate 14. A plurality of connectors 30 are also formed within the redistribution layers 70 to connect the silicon IC chip 12 to the substrate 14, and also interconnect the redistribution layers 70 between each other across both outer surfaces 20 and 22 of the interposer 10. The multiple connectors 30 can be different sizes and configured with multiple different angles 40.

[0039] The wide bandgap interposer 18 is selected from silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AIN), synthetic diamond, glass, and other composite and alloy types that enhance the quantum conversion process described in this invention.

[0040] The wide bandgap interposer 18 can be a combination of constituents from a select group of silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AIN), synthetic diamond, glass, and compounds and alloy types that enhance the quantum conversion process described in this invention.

[0041] The plurality of connectors 30 may include carbon electrical connectors 32 formed in the wide bandgap material 18. The plurality of connectors 30 may also include optical waveguide connectors 34 formed in the wide bandgap material 18. The plurality of connectors 30 are optical waveguide connectors 34, each of which comprises a tunnel 36 formed in the wide bandgap material 18 with carbon rich tunnel walls 38.

[0042] A recess 60 may be formed in the first exterior surface 20. The IC chip 12 may be disposed within the recess 60 and thermally coupled to the wide bandgap material 18, thereby providing a heat sink 62 for the IC chip 12.

[0043] A recess 60 may be laser ablated into first exterior surface 20. IC chip 12 may then be placed into recess 60 and thermally coupled to wide band gap material 18, thereby providing a heat sink 62 for IC chip 12.

[0044] The present invention further includes an improved packaging device 100 for connecting an IC chip 12 to a circuit board 110 comprising a silicon carbide (SiC) material 16 having a first outer surface 20 and a second outer surface 22. A recess 60 is formed in the first outer surface 20, and the IC chip 12 is disposed in the recess 60 and thermally coupled to the silicon carbide (SiC) material 16, thereby providing a heat sink 62 for the IC chip 12. A plurality of connectors 30 are formed within the silicon carbide (SiC) material 16 to connect the IC chip 12 to the second outer surface 22. The second outer surface 22 of the silicon carbide (SiC) interposer 16 is directly connected to the circuit board 110.

[0045] The present invention further includes an improved packaging device 100 for connecting a plurality of IC chips 12 comprised of a silicon carbide (SiC) material 16 having a first outer surface 20 and a second outer surface 22. A recess 60 is formed in the first outer surface 20. A first IC chip 112 is disposed within the recess 60 and thermally coupled to the silicon carbide (SiC) material 16, thereby providing a heat sink 62 for the IC chip 12. A second recess 64 is formed in the second outer surface 22. A second IC chip 114 is disposed within the second recess 64 and thermally coupled to the silicon carbide (SiC) material 16, thereby providing a heat sink 62 for the second IC chip 114. A plurality of connectors 30 are formed within the silicon carbide (SiC) material 16 for connecting the first IC chip 112 and the second IC chip 114 to a third outer surface 24 of the silicon carbide (SiC) interposer 16.

[0046] The present invention further includes an improved interposer system 120. The system includes a silicon carbide (SiC) interposer 122 having a first outer surface 124 and a second outer surface 126. The first outer surface 124 and the second outer surface 126 are associated with a first recess 60 and a second recess 64. The first IC chip 112 and the second IC chip 114 are disposed within the first recess 60 and the second recess 64 and are thermally coupled to the silicon carbide (SiC) interposer 112, thereby providing a heat sink 62 for the first IC chip 112 and the second IC chip 114. A second silicon carbide (SiC) interposer 132 has a third outer surface 134 and a fourth outer surface 136. The third outer surface 134 and the fourth outer surface 136 are associated with a third recess 66 and a fourth recess 68. The third IC chip 116 and the fourth IC chip 118 are disposed in the third recess 66 and the fourth recess 68 and are thermally coupled to the second silicon carbide (SiC) interposer 132, thereby providing a heat sink 62 for the IC chips 116 and 118. The first silicon carbide (SiC) interposer 122 is stacked on or adjacent to the second silicon carbide (SiC) interposer 132 and interconnects the IC chips 112, 114, 116 and 118.

[0047] The present invention further includes an improved package substrate core 160 for constructing a high density interconnect substrate 162 with multiple build-up layers 164 on both sides of the core 160. The core 160 comprises a silicon carbide (SiC) material 16 having a first outer surface 20 and a second outer surface 22. The silicon carbide (SiC) material 16 has plated through holes 170 and a plurality of connectors 172 formed within the core material construction 160 by laser irradiation conversion 50 and / or laser drilling 54.

[0048] FIG. 1 shows a laser beam 56 contacting a silicon carbide (SiC) substrate, where the laser converts the silicon carbide (SiC) substrate to create a conductive material 19, rather than insulating or semiconductive silicon carbide (SiC). FIG. 1 also shows a cross section of the laser converted material 19A that is thermally and electrically conductive. The location, size and shape of the conductive features 19 are manipulated by the laser beam 56 profile, laser processing parameters and processing environment.

[0049] FIG. 2 is a cross-sectional view similar to FIG. 1 and illustrates that the shape, position, size and thickness of the laser converted features 19 can be controlled by the laser beam 56 profile, the laser irradiation conditions, and the relative motion between the beam 56, the substrate 14 and the work surface 20.

[0050] 3 shows a cross-sectional view of a silicon carbide (SiC) substrate 14, where L1-L4 are different interconnect layers 180 created simultaneously without adding metallization to the substrate material 14 (in situ). By laser conversion, a conversion region 19 overlying or underlying structure 30 shows both an electrical interconnect structure 182 and a thermal interconnect structure 184.

[0051] FIG 3A is a cross-sectional view of the state of the art interconnect. FIG 3B is a top view of layer 2 in FIG 3A showing copper plated power plane 190, copper plated and embedded conductive copper tracer 194, and microvias 196. FIG 3B is the top view of FIG 3A, while FIG 3C is a cross-sectional view of the invention showing laser converted interconnect 39. FIG 3D is a top view of FIG 3C showing the laser converted 3D configuration 39 across all layers. FIG 3D further shows the laser converted material 39 through the laser converted power plane 200.

[0052] 3E illustrates various geometric shapes 210 that can be produced by laser beam 56. For example, geometric shapes 210 can include a circle 212, a square 214, a cylinder 216, an ellipse 218, a rectangle 220, a triangle 220, or other shapes. More specifically, the present invention uses different optical elements, which can include, but are not limited to, lenses, diffraction gratings, diffusers, collimators, and various beam shaping techniques.

[0053] 3F shows a first laser beam 56 and a second laser beam 57 with a circular cross-section. In addition, the energy intensity profile 236 of the beam 56 can also be controlled, either independently or simultaneously with the beam shape 238, to control the intensity distribution 239 within the cross-section of the beam 56. For example, including a Gaussian intensity distribution 232 or a top-hat beam energy distribution 234 for the laser beam 56.

[0054] FIGURE 3G shows a shutter element 240 placed in the beam path that can be used to optimize and transform the uniform laser beam 56 into a variety of different patterns. For example, FIGURE 3G shows a top-hat laser beam energy distribution 234 with a uniform intensity profile 248 throughout a square cross section 242 to create a serpentine shaped shutter 244.

[0055] FIGURE 3H shows a top-hat laser beam 234 with a uniform intensity profile 248, but shaping the desired serpentine structure 244. Additionally, FIGURE 3H shows a top view of a silicon carbide (SiC) interposer 10 or substrate 14 after irradiation with laser beam 56 creating a carbon-rich conductive serpentine structure 246.

[0056] Figure 3I shows a similar configuration, but using a galvanometer-optical element 250 to directly write a Gaussian laser beam into silicon carbide (SiC) 15. In this case, one or more optical beams 56 can be used. Figure 3J shows the resulting carbon-rich conductive serpentine structure 246 produced by the laser of Figure 3I without deposition or plating.

[0057] FIG. 3K is an angled monolithic via 260 and a monolithic 3D 261 interconnect to connect between all different sides of the interposer device 10. More specifically, FIG. 3K is a perspective view of FIG. 3 showing an in-situ laser converted 3D monolithic via 261, for example, an angled monolithic via 260 and a monolithic 3D 261 interconnect to connect between all different sides of the interposer device 10. FIG. 3L is a schematic diagram of one large contact split 262 that is split into three different monolithic vias 260, namely, layer 1 (264), layer 2 (266) and layer 3 (268). Each monolithic via 260 can be created with a different size, different angle, and terminate on a different layer.

[0058] FIG. 4 shows laser conversion 39 processing used over the entire layer and on the surface of substrate 14. What is created is a fan-out configuration 270 indicated by reference signs a-a1, b-b1 (where the a-b pitch << a1-b1, through path configuration a-a11), as well as a surface-to-surface connection and a heat dissipation configuration d-d1. FIGS. 4A and 4A1 show the state of the art of the semi-additive interconnect processing process 280. More specifically, FIG. 4A shows a damascene pattern processing process 282, with a substrate 290, copper 291, and a dielectric 292, and includes steps 1, 2a, 2b, 3, 4, 5, and 6. FIG. 4A1 shows a semi-additive pattern processing process 284, including steps of preparing a substrate 290, plating a thin layer of copper 291, attaching a film 294, exposing 296, developing 298, plating through holes (PTH) 300, removing an excess film 302, and etching 304. FIG. 4A2 shows the state of the art of the semi-additive interconnect processing process 280, a dual damascene pattern processing process 310. More specifically, there are steps of SiC deposition (film formation) 312, SiO deposition (film formation) 314, path pattern 316, path etching 318, metal pattern 320, metal etching 322, seed deposition 324, Cu plating 326, and Cu CMP (planarization) 328.

[0059] FIG. 4B shows an example of a 3DR configuration with laser thickness processing without drilling. The laser conversion 39 pattern processing corresponds to quantum conversion pattern processing (QCP) 330. FIG. 4B includes a silicon carbide (SiC) layer 332 of total thickness “T”. The layer 15 can be specified with different layer thicknesses designated as tn1, tn2, tn3, tn. The laser beam 56 state can be adjusted in beam profile, focal plane, intensity, etc. to enable conversion processing at the required depth of tn1. Simultaneously or subsequently, a second laser beam is defined and irradiated to cause conversion in the next layer tn2. Similarly, layers tn3, tn are created. All steps are formed without plating, deposition, or doping of external materials. In addition to the layers created sequentially or simultaneously by the laser, a direct-to-face conducting 3D configuration is created at different angles 40 throughout the entire thickness of the silicon carbide (SiC) layer 332. A first laser beam 334 creates features with thickness tn1, a second laser beam 336 creates features with thickness tn2, and a third laser beam 338 creates features with thicknesses tn3 and tn4.

[0060] 4C shows a silicon carbide (SiC) layer configuration "A" 332 using laser quantum transfer patterning 330 to create a full thickness direct 3D configuration 19 at an arbitrary angle. The flexibility to define an arbitrary angle 40 and create a direct 3D interconnect configuration 19 results in higher volumetric interconnect density, smaller overhauls, seamless interconnects without interlayer interfaces reducing parasitic resistance and improving performance.

[0061] 5 shows a wide bandgap material with machined grooves to receive multiple chips / chiplets of different functions. More specifically, FIG. 5 shows a silicon carbide (SiC) substrate 14 with machined grooves 60 to receive multiple chips / chiplets 340 of different functions, such as Si chips 341, memory chips 342, optical switches 344, etc. The silicon carbide (SiC) substrate 14 can include optical engines 343 connected through 2.5D 19 and / or 3D integration architectures 19 using laser converted silicon carbide (SiC) 15. Additionally, the substrate 14 may include optical waveguides 36 connecting through the silicon carbide (SiC) 15 using laser conversion, thermal paths through the silicon carbide 345, chip-to-chip electrical connections 346 through the silicon carbide (SiC) 15, a fan-out configuration 347 through the silicon carbide (SiC) 15, and thermal connections 350 in the silicon carbide (SiC) 15 for cooling the chips 340 on the sides of the grooves 60.

[0062] Figure 5A shows the state of the art of 2.5D interconnect configuration, substrate embedded 2.5D or 2.5D bridge architecture landscape. Intel has embedded multi-die interconnect bridge (EMIB) technology, which is a technology for high density integration of heterogeneous chips. Instead of using a large Si interposer commonly found in other technologies, EMIB uses a very small bridge die with multiple routing layers. EMIB technology is an example of a 2.5D packaging solution. Figure 5A includes HGM die 1 (360) and GPU die 2 (362). Intel's EMIB or bridge die 364 provides localized interconnect, bridge technology, and better electrical localized parasitic capacitance.

[0063] FIG. 5A1 shows the state of the art of 2.5D interconnect configurations, Elevated Fan-out Bridge 2.5D or 2.5D Bridge architecture landscape. The AMD Elevated Fan-out Bridge is a variant of the original Intel EMIB where a very small bridge die is placed inside a fan-out layer fabricated on the top surface of the substrate, rather than inside the package substrate. Both the EMIB (FIG. 5A) and the Elevated Fan-out Bridge are very similar in functionality, with slightly different manufacturing processes. FIG. 5A1 includes HGM Die 1 (370) and GPU Die 2 (372), Mold 1 (374), EFB (376), copper pillars (378), first side buildup layers (380), substrate core (382), and second side buildup layers (384). The AMD Elevated Bridge 386 offers scalable solutions, lithographic clarity, standard substrates, low cost, standard flip chip technology and low complexity wafer bumping technology.

[0064] FIG. 5A2 shows the state of the art of 2.5D interconnect configurations, 2.5D bridge architecture landscape, TSMC silicon interposer. This refers to silicon interposer architecture, used by multiple device manufacturers and first fabricated at TSMC (Taiwan Semiconductor Manufacturing Company). The technology in this diagram uses many silicon components with through silicon via interconnects (through silicon electrodes) that connect many different chiplets. The through silicon electrodes are fabricated with traditional damascene processes. The configuration is state of the art in packaging technology, but shows the limitations of silicon interposer architecture as 2.5D due to the die stacking limitations compared to that of the present invention. FIG. 5A2 includes a first substrate 390 with chip 1 (392) and a second substrate 394 with chip 2 (396). Microbumps 398 separate chip 1 (392) and chip 2 (396) from silicon interposer 400 with decap 402 and tier 1 (404). FIG. 5A2 further includes a substrate 406 with TSVs 408 , flip chip bumps 410 and a package substrate 412 .

[0065] FIG. 5B shows how the silicon carbide (SiC) interposer is customized according to the specifications of each chip. Multiple layers can actually be created throughout the entire thickness of the interposer. For example, the routing for chip 4 (426) is defined using five layers, the routing for chip 3 (424) is defined using two layers, and the routing for chip 1 (420) requires a mixture of multiple solutions, including ramp paths a-a1, staggered six layer paths b-b1, die-to-die connections c-c1, and heat dissipation interconnects d-d1. Chip 2 (422) is shown with various passive elements, which are created using laser conversion patterning or quantum conversion patterning (QCP). The internal configuration of the silicon carbide (SiC) interposer shown in FIG. 5B also includes resistors, inductors, and capacitors. Depending on the specifications of each chip, the silicon carbide (SiC) interposer can be customized with the number of layers. All layers are actually fabricated through the entire thickness of the interposer structure (in one embodiment of the invention).

[0066] 6 shows 3D integration on a laser converted silicon carbide (SiC) interposer 430 and a silicon carbide (SiC) thermo chip 432 coupled to a package substrate 440. The conversion or transformation system includes multiple chips with various functions, including but not limited to a silicon chip 434, a memory chip 436, an optical chip, a switch or component 438, a thermo chip 432, and various other examples.

[0067] 6A is an architecture option that includes a laser converted silicon carbide (SiC) interposer 450, a laser converted silicon carbide (SiC) thermo chip 452, and a substrate 458. HBM 454 includes memory chips 456, optical 460 includes optical chips / engine 462, and SoC 464, SoC 466, and SoC 468 include logic chips 464, 466, and 468, respectively.

[0068] 6B is an alternative architecture option, showing a compact configuration using substrate 482 and processed silicon carbide (SiC) interposer 470 to eliminate the need for a silicon carbide (SiC) thermo chip. HBM 472 contains memory chips, Optical contains optical chip / engine 474, and SoC 476, SoC 478, and SoC 480 contain logic chips 476, 478, and 480, respectively.

[0069] Figures 6C, 6C1 and 6C2 show the simultaneous fabrication of QCIA (Quantum Transformation Integrated Architecture) architectures, which can accelerate run rates and improve yields on substrate 504. Figure 6C shows two different QCIA designs (QCIA1 490 in Figure 6C1 and QCIA2 492 in Figure 6C2) that combine to form the 3D stacked QCIA architecture shown in Figure 6B. The process, materials and approach proposed in this invention allow the two separate parts of Figures 6C1 and 6C2 to be fabricated in parallel and then assembled on top of each other to obtain the 3D architecture shown in Figure 6B. This is a unique and distinctive feature compared to the state of the art packaging technology shown in Figures 5A, A1 and A2. QCIA1 490 in Figures 6C1 and 6C2 includes HBM 494, SoC1 496 and SoC2 498. Also, QCIA2 492 in FIGS. 6C1 and 6C2 includes an optical chip / engine 500 and SoC3 502.

[0070] FIG. 6D shows a customized point-to-point connection, using QCIA (Quantum Conversion Integrated Architecture) architecture and laser conversion patterning or quantum conversion patterning (QCP). The result is a power-efficient and thermally enhanced integrated architecture with a compact footprint design and high-speed interconnects. Every chiplet is independently cooled and thermally managed to maximize the energy efficiency of the system. This architecture allows for a significant increase in density (connections / mm3). The ability to create 3D angular monolithic paths brings a new metric to 3D integration, volumetric density (connections / mm3) over standard industry density (connections / area). QCIA 510 in FIG. 6D includes SoC1 512, SoC2 514, SoC3 516, optical chip / engine 518, HBM 520, and substrate 522.

[0071] FIG. 6E is a perspective view of FIG. 6, showing 3D integration of multiple IC chips connected on different sides of a silicon carbide (SiC) interposer. Microchip 1 530 sits inside a recess made to hold microchip 1 530 on one side of the interposer 10. Microchip 2 532 sits inside a recess made to hold microchip 2 532 on the other side of the interposer 10. A first angular monolithic via 540 connects microchip 1 530 to microchip 2 532. A second angular monolithic via 542 connects microchip 1 530 to microchip 3 534. A third angular monolithic via 544 connects microchip 2 532 to microchip 3 534.

[0072] Figures 6F1, 6F2, 6F3 and 6F4 show the state of the art of 3D interconnect configurations. Figures 6F1, 6F2, 6F3 and 6F4 are schematic illustrations showing the current state of the art implementations for chip stacking. All four different architectures shown in the illustrations have the same limitation of only two die stacking. This is a fundamental distinction from the proposed invention. Our invention uses materials and proposed processes that allow for stacking of more than two dies and provides thermal and power delivery solutions to support the high die stack design.

[0073] FIG. 7 shows an option for in-situ deposition and patterning of QCIA on organic substrates. More specifically, FIG. 7 shows forming a redistribution layer directly on a package substrate for heterogeneous integration applications. Each layer is deposited and then patterned by laser conversion before depositing the substrate layer. The steps in FIG. 7 include providing a package substrate 550, low temperature depositing a material (SiC) or diamond-like carbide on the package substrate 550, laser converting the deposited layer 554, depositing a next layer 556, laser converting the next layer 558, depositing a third layer 560, converting the third layer to complete the entire redistribution layer or fan-out configuration 562.

[0074] FIG. 8 is an architectural option for an improved interposer with multiple different redistribution layers on either side of the outer surface of the interposer. In the option shown in FIG. 8, the multiple redistribution layers on either side of the outer surface of the interposer vary in number, size, function, and material type. More specifically, the interposer 10 in FIG. 8 includes IC chiplets 570, chiplet routing / redistribution layers 572, QCI interposer 574, fan-out and redistribution layers 576, and QCI interposer fan-out pitch 578.

[0075] FIG. 9 is an architecture option for the improved packaged device, further incorporating the improved interposer shown in FIG. 8 on top of the high density interconnect substrate. The high density interconnect shown in FIG. 9 is composed of multiple build-up layers on either side of the SiC core structure formed by laser irradiation conversion process and laser drilling. The QCIA performance is optimized for energy efficient high performance computing. FIG. 9 includes Optical Xvr 580, XPU2 582, DRAM 584, QCIA interconnect structure 586, Si Ivr II 588, XPU1 590, 2nd DRAM 592, BIST / Control 594, PowerFET 1 596, QCIA Substrate 598, Si IVR I 600 and System PBC 602.

[0076] Figures 9A and 9B are greatly enlarged and detailed views of the QCIA interconnect configuration 586 shown in Figure 9. In this view, the QCIA interconnect configuration 586 is comprised of a SiC interposer 604 with QCP interconnects 606, featuring a die-to-die interconnect layer on the top surface 608 and five fan-out build-up layers on the bottom surface 610. Figures 10 and 10A illustrate the parallel processing nature of assembling the different layers shown in Figure 9.

[0077] FIG. 11 illustrates the fabrication of an improved interposer with multiple redistribution layers using two different fabrication processes. One embodiment of the fabrication process uses SiC in wafer form 620 and another embodiment of the fabrication process uses SiC in quarter panel size form 622. FIG. 11 illustrates the specific process of converting SiC in wafer form 620 and quarter panel form 622 to full panel size, thereby allowing the fabrication infrastructure of high density interconnect substrates to be compatible with widely available panel manufacturing processes.

[0078] 12 is a schematic diagram illustrating a single unit QCIA interconnect configuration 630. The configuration includes a hybrid glass-SiC interposer featuring three chiplets 632 connected side-by-side on top of the QCIA interconnect configuration 630 with a die-to-die interconnect layer on top of the SiC interposer and five fan-out build-up layers underneath. The QCIA interconnect configuration 630 further includes an RDL layer 640 on top of both the glass-SiC hybrid interposer and a TGV through glass via 642.

[0079] FIG. 13 is a schematic diagram showing a core substrate configuration that can be fabricated using the proposed quantum conversion patterning process and material set. The core module configuration features embedded power, active and passive device elements. The QC-Core has an interconnect through-hole configuration fabricated using the quantum conversion patterning process. By combining a highly conductive laser conversion configuration along with the choice of substrate material (SiC, Si3N4, AlN or hybrid configuration of all three), the QC-Core module provides a unique power delivery and thermal management circuit element; that is, it can function on its own as a power package device or subsequently be integrated into organic package devices or silicon-based devices for further system level integration. More specifically, the QC-Core 650 configuration can include a control device 652, a power device 654, a polymer material layer 656, a QCIA substrate core material 658 such as SiC, Si3N4 or hybrid, a QCIA interconnect 660 fabricated within the SiC or Si3N4, passives 662, and copper metallization 664.

[0080] The present invention further includes the following.

[0081] A compact electronic interposer with double-sided redistribution layers (QCIA interposer) used for multi-chip interconnection and electronic circuit fan-out.

[0082] Stackable and reconfigurable miniature electronic systems featuring the above QCIA interposers and high density interconnect substrates fabricated using this invention (3D Heterogeneous Integration Architectures created using this invention).

[0083] A substrate with power delivery and thermal management modules fully integrated into the substrate structure and manufactured with a QCP process that eliminates the need for electroless metallization.

[0084] Thermal Chip: A wide bandgap material such as SiC with in-situ engineered thermal pathways through its thickness to conduct heat across the surface and edges of the chip, and to dissipate the thermal energy generated at multiple levels of the system.

[0085] Power delivery modules, such as power converters, integrated in wide bandgap materials, such as SiC, using quantum transformation patterning for integration and deployment in multiple stacking positions in a miniature electronic system.

[0086] Thermal management modules, such as power converters, embedded in wide bandgap materials, such as SiC, using quantum transformation patterning for integration and deployment in multiple stacking positions in a miniature electronic system.

[0087] Substrate core devices using SiC or other wide bandgap materials with interconnects formed within the core structure using a laser irradiation conversion process and / or laser drilling.

[0088] A substrate core device using SiC or other wide bandgap material with interconnects formed within the core structure using a laser irradiation conversion process and / or laser drilling. The core device incorporates a power delivery module and a thermal management module.

[0089] Example of laser process parameters for quantum transformation patterning. To fabricate nanoribbon / SiC structures, we use single crystal 4H-SiC wafers with polished 0001-Si faces. The wafers are lightly doped (531015 cm23 625%), n-type, 10 mm-thick epitaxial layers grown onaxis @ (0001) 60.25° on 50.8 mm diameter 4H-SiC substrates. To fabricate carbon-rich SiC nanoribbons, the laser irradiation was performed using a Q-switched Nd:YAG laser with a wavelength of 1064 nm. A 1 mm wide and 7 mm long area was irradiated with a repetition rate f of 535 kHz, pulse duration ~ on-time t P of 5260 ns, pulse energy EP of 50.6 mJ / pulse, laser beam diameter D of 51 mm, and laser scanning speed V of 55 mm / s. Before removing the sample from the process chamber, the area was irradiated three times in a nitrogen atmosphere at ~1 atm. The incident fluence of a single pulse was determined as fP5Ep / Ai, where Ai is the irradiated area, and Ai5(pd2 / 4)IDVtP for a circular spot was 76.4 mJ / cm2. The pulse intensity was determined as Ip5(fP / tP), which was 293.3 kW / cm2. However, part of this energy was absorbed by the workpiece, since the transmittance and reflectance of the 4H-SiC sample used in this example were 0.4 and 0.15, respectively, measured at a wavelength of 1064 nm. A 14 Focused Ion Beam ~FIB! milling machine was used to prepare 5 mm38 mm31200 Å pieces of laser-irradiated 4H-SiC wafers for microscopic study. A high-resolution transmission electron microscope (HRTEM), Techni F 30 equipped with a Windless Link Energy Dispersive Spectroscopy (EDS) analyzer, is used to study the laser-processed nanostructures and also to obtain selected area electron diffraction (SAED) patterns for different regions of the laser-treated wafers.

[0090] Additional experiments were also performed to create the converted silicon-SiC material using different laser wavelengths, such as 193 nm, 532 nm, and 532 nm with femtosecond pulse widths.

[0091] Commercially available build-up polymer films were used to fabricate the redistribution and / or build-up layers used on the top and bottom of the QCIA interposer. The most used microfilm material for fabricating build-up circuits in advanced packages is Ajinomoto Build-up Film (trademark, https: / / ajinomoto.com / innovation / action / buildupfilm). In fact, Ajinomoto Build-up Film (ABF) can be found in the heart of personal computers worldwide, where it provides electrical insulation for the complex circuit boards of high performance central processing units (CPUs). These films come in many different variants across a wide range of electrical material properties, thermo-mechanical properties, and geometric dimensions (i.e., film thickness, film thickness variation, width).

[0092] The following description gives some examples of the variations available in these materials. Ajinomoto Build-up Film (trademark, ABF) Type Features GX-92 standard GX-T31 Low surface roughness, low CTE GZ-41 Low surface roughness, low CTE, high Tg GL-102 Low surface roughness, low dielectric tangent, low CTE, high Tg

[0093] The foregoing is the subject matter of the present invention, but further examples of that subject matter may be made without departing from the spirit and scope of the basic invention, which spirit and scope are defined by the separate claims.

[0094] Comparison of this invention with the current state of the art: Latest Technology This invention Build-up substrate packaging process 3D monolithic substrate packaging process Semi-additive pattern processing Quantum conversion pattern processing Subtractive Pattern Processing Damascene and double damascene patterning Additive Manufacturing 3D In-Situ Manufacturing 3D In-Situ Interconnect Manufacturing In-situ 3D interconnect fabrication Stacked Path Interconnects Angular Monolithic Paths Copper Metallization Conductor C3-Interconnect Conductive Carbon Connection Converted Carbon Connection

[0095] This invention is shown in a complex 2X3X5 matrix: Integration Scheme Device Type Connection Type Made with Quantum Conversion Pattern Processing Interposer Package Electrical Optical Hybrid 2D XXXXX 2.5D …… XXXX 3D X……XXX 3D Interleaved SiC XXXXX Combining 2D, 2.5D and 3D (SiC cubic interconnect shown in Figure 6d) X……XXX

Claims

1. An improved interposer for connecting an integrated circuit die or multiple dies to a substrate, the improved interposer comprising: a silicon carbide (SiC) interposer having first and second outer surfaces; and - A plurality of connectors formed in situ within the silicon carbide (SiC) interposer and connecting the integrated circuit die to the substrate.

2. 10. The improved interposer of claim 1, wherein said plurality of connectors are carbon electrical connectors.

3. 10. The improved interposer of claim 1, wherein said plurality of connectors are optical waveguide connectors.

4. the plurality of connectors are optical waveguide connectors; 10. The improved interposer of claim 1, wherein each of those optical waveguide connectors comprises a tunnel defined by carbon-rich tunnel walls within said silicon carbide (SiC).

5. 10. The improved interposer of claim 1, wherein at least one of a plurality of in situ connectors within said silicon carbide (SiC) interposer is shaped at an angle relative to said first exterior surface.

6. 10. The improved interposer of claim 1, wherein at least one of said plurality of in situ connectors within said silicon carbide (SiC) interposer is an angular monolithic via formed at an angle relative to said first exterior surface.

7. 2. The improved interposer of claim 1, wherein said plurality of connectors are carbon electrical connectors formed by laser irradiation of said silicon carbide (SiC).

8. 2. The improved interposer of claim 1, wherein said plurality of connectors are optical waveguide connectors formed by laser irradiation of said silicon carbide (SiC).

9. a recess formed in the first outer surface; and 10. The improved interposer of claim 1, wherein the integrated circuit die is positioned within the recess and is thermally coupled to the silicon carbide (SiC) interposer, thereby providing a heat sink for the integrated circuit die.

10. the first exterior surface includes a laser ablated recess; and 10. The improved interposer of claim 1, wherein the integrated circuit die is positioned within the recess and is thermally coupled to the silicon carbide (SiC) interposer, thereby providing a heat sink for the integrated circuit die.

11. An improved interposer for connecting a silicon integrated circuit die to a substrate, the improved interposer comprising: a wide bandgap interposer having first and second outer surfaces; and - A plurality of connectors formed in situ within the wide bandgap interposer, connecting the silicon integrated circuit die to the substrate.

12. The wide band gap interposer comprises:

12. The improved interposer of claim 11, wherein the interposer is selected from the group consisting of silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AIN), synthetic diamond, glass, and compounds and alloy species that enhance the quantum conversion process described in this invention.

13. The wide band gap interposer comprises:

12. The improved interposer of claim 11, which is a combination of components selected from the group consisting of silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AIN), synthetic diamond, glass, and compounds and alloy species that enhance the quantum conversion process described in this invention.

14. 10. The improved interposer of claim 1, wherein said plurality of connectors are carbon electrical connectors fabricated from said wide bandgap material.

15. 10. The improved interposer of claim 1, wherein said plurality of connectors are optical waveguide connectors fabricated from said wide bandgap material.

16. the plurality of connectors are optical waveguide connectors; 2. The improved interposer of claim 1, wherein each of those optical waveguide connectors comprises a tunnel defined by carbon rich tunnel walls within said wide bandgap material.

17. a recess formed in the first outer surface; and 10. The improved interposer of claim 1, wherein the integrated circuit die is positioned within the recess and is thermally coupled to the wide bandgap material, thereby providing a heat sink for the integrated circuit die.

18. the first exterior surface includes a laser ablated recess; and 10. The improved interposer of claim 1, wherein the integrated circuit die is positioned within the recess and is thermally coupled to the wide bandgap material, thereby providing a heat sink for the integrated circuit die.

19. An improved package device for connecting an integrated circuit die to a circuit board, comprising: a silicon carbide (SiC) material having first and second outer surfaces; - a recess formed in the first outer surface; an integrated circuit die is positioned within the recess and thermally coupled to the silicon carbide (SiC) material, thereby providing a heat sink for the integrated circuit die; a plurality of connectors formed in situ within the silicon carbide (SiC) material and connecting the integrated circuit die to the second exterior surface; and - the second exterior surface of the silicon carbide (SiC) material is directly connected to the circuit board;

20. An improved package device for connecting an integrated circuit die, comprising: a silicon carbide (SiC) material having first and second outer surfaces; - a recess formed in the first outer surface; a first integrated circuit die is positioned within the recess and thermally coupled to the silicon carbide (SiC) material, thereby providing a heat sink for the integrated circuit die; - a second recess formed in the second outer surface; a second integrated circuit die is positioned within the second recess and is thermally coupled to the silicon carbide (SiC) material, thereby providing a heat sink for the integrated circuit die; and A plurality of connectors formed in situ within said silicon carbide (SiC) material and connecting said first and second integrated circuit dies to a third exterior surface of said silicon carbide (SiC) material.

21. An improved interposer system comprising the following technical features: a first silicon carbide (SiC) interposer having first and second outer surfaces with first and second recesses defined in the first and second outer surfaces; a first and second integrated circuit die positioned within the first and second recesses and thermally coupled to the first silicon carbide (SiC) interposer, thereby providing a heat sink for the first and second integrated circuit die; a second silicon carbide (SiC) interposer having third and fourth outer surfaces with third and fourth recesses defined therein; third and fourth integrated circuit dies are positioned within the third and fourth recesses and are thermally coupled to the second silicon carbide (SiC) interposer, thereby providing a heat sink for the integrated circuit dies; and The first silicon carbide (SiC) interposer is stacked on or adjacent to the second silicon carbide (SiC) interposer and interconnects the first through fourth integrated circuit die.

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