Electrical Improvements for 3D NAND

Abstract

An exemplary semiconductor processing method may include delivering a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed in the processing region of the semiconductor processing chamber. Alternating layers of material may be formed on the substrate. One or more recesses may be formed in the alternating layers of material. The method may include forming a first silicon-containing material. The first silicon-containing material may extend into one or more recesses formed in the alternating layers of material. The method may include delivering a halogen-containing precursor to a processing region of the semiconductor processing chamber. The method may include forming a silicon-halogen-containing material. The silicon-halogen-containing material may overlie the first silicon-containing material. The method may include forming a second silicon-containing material. The second silicon-containing material may overlie the silicon-halogen-containing material.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of and priority to U.S. patent application Ser. No. 17 / 705,135, entitled "ELECTRICAL IMPROVEMENTS FOR 3D NAND," filed Mar. 25, 2022, the entire contents of which are incorporated herein by reference.

[0002]

[0002] The present technology relates to semiconductor processes and materials. More specifically, the present technology relates to the formation and manipulation of memory holes in layered memory structures. [Background technology]

[0003]

[0003] Integrated circuits are made possible by processes that form intricately patterned layers of material on a substrate surface. Forming patterned materials on a substrate requires controlled methods of forming and removing exposed materials. Stacked memories such as vertical NAND or 3D NAND may include the formation of a series of alternating dielectric material layers into which multiple memory holes or apertures may be etched. A material layer may then be deposited and processed within the memory holes to form polycrystalline silicon channels. The material properties of the material layers may affect device performance and may lead to final device defects or reduced performance. As the number of alternating layers increases, continued innovation in 3D NAND technology is required to meet the requirements for high string current and reduced device variability.

[0004]

[0004] Accordingly, there is a need for improved systems and methods that can be used to manufacture high quality devices and structures. These and other needs are addressed by the present technique. Summary of the Invention

[0005] An exemplary semiconductor processing method may include delivering a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed in the processing region of the semiconductor processing chamber. Alternating layers of material may be formed on the substrate. One or more recesses may be formed in the alternating layers of material. The method may include forming a first silicon-containing material. The first silicon-containing material may extend into one or more recesses formed in the alternating layers of material. The method may include delivering a halogen-containing precursor to a processing region of the semiconductor processing chamber. The method may include forming a silicon-halogen-containing material. The silicon-halogen-containing material may overlie the first silicon-containing material. The method may include forming a second silicon-containing material. The second silicon-containing material may overlie the silicon-halogen-containing material.

[0006] In some embodiments, the temperature in the semiconductor processing chamber may be maintained at about 700° C. or less. The pressure in the semiconductor processing chamber may be maintained at about 300 Torr or less. The silicon-containing precursor may be or may include silane, disilane, dichlorosilane, or trisilane. The halogen-containing precursor may include fluorine. The silicon-halogen-containing material may include a silicon-fluorine-containing material. The halogen-containing precursor may be or may include nitrogen trifluoride or silicon tetrafluoride. The method may include forming a first silicon-containing material prior to forming the silicon-halogen-containing material. The first silicon-containing material may extend into one or more recesses formed in the alternating layers of material. The method may include forming a second silicon-containing material. The second silicon-containing material may overlie the silicon-halogen-containing material. The method may include forming both the first silicon-containing material and the second silicon-containing material. The silicon-halogen-containing material may be characterized by a thickness of about 60 nm or less. The method can include annealing the substrate after forming the second silicon-containing material, during which halogen material in the silicon-halogen-containing material can diffuse into the first silicon-containing material, the second silicon-containing material, or both.

[0007] Some embodiments of the present technique may include a semiconductor processing method. The method may include forming a first material layer in one or more recesses defined in alternating layers of material on a substrate in a processing region of a semiconductor processing chamber. The first material layer may be a first silicon-containing material. The method may include forming a second material layer on the first material layer. The second material layer may be a silicon-fluorine containing material. The method may include forming a third material layer on the second material layer. The third material layer may be a second silicon-containing material.

[0008] In some embodiments, the temperature in the semiconductor processing chamber may be maintained at about 700° C. or less. The pressure in the semiconductor processing chamber may be maintained at about 300 Torr or less. The alternating layers of materials may include alternating oxide and nitride material layers. The substrate may include more than 16 alternating layers of materials. The second material layer may be characterized by a thickness greater than a thickness of the first material layer and the third material layer. The second material layer may be characterized by a thickness of about 2 nm to about 30 nm. The method may include annealing the substrate after forming the first material layer, the second material layer, and the third material layer. The first material layer, the third material layer, or both may include amorphous silicon. The annealing may transform at least a portion of the amorphous silicon to polycrystalline silicon. The method may include removing a portion of the first silicon-containing material, the silicon-halogen-containing material, and the second silicon-containing material after annealing the substrate.

[0009] Some embodiments of the present technology include a semiconductor structure. The structure may include a substrate having alternating layers of material formed thereon. One or more recesses may be formed within the alternating layers of material. The structure may include a polycrystalline silicon material extending into the one or more recesses. A second side of the polycrystalline silicon material opposite the first side of the polycrystalline silicon material may overly the alternating layers of material. The polycrystalline silicon material may include a halogen. A portion of the polycrystalline silicon material disposed intermediate the first side and the second side may have a higher halogen atomic concentration compared to the first side and the second side.

[0010] In some embodiments, the polycrystalline silicon material is characterized by a thickness of about 30 nm or less.

[0011]

[0011] The above techniques may provide many advantages over conventional systems and techniques. For example, the processes and structures may improve channel formation in polycrystalline silicon. Additionally, steps of embodiments of the techniques may improve the electrical performance of the final device or structure. These and other embodiments, as well as their many advantages and features, are described in more detail in conjunction with the following description and accompanying figures.

[0012] A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remaining portions of the specification and the drawings. [Brief description of the drawings]

[0013] [Figure 1] 1 is a schematic cross-sectional view of an exemplary processing chamber in accordance with some embodiments of the present technique; [Diagram 2] 1A-1D illustrate selected steps in a forming method according to some embodiments of the present technology. [Figure 3A] 1A-1D show schematic cross-sectional views of exemplary structures including and formed from layers of material in accordance with some embodiments of the present technology. [Figure 3B]1A-1D show schematic cross-sectional views of exemplary structures including and formed from layers of material in accordance with some embodiments of the present technology. [Figure 3C] 1A-1D show schematic cross-sectional views of exemplary structures including and formed from layers of material in accordance with some embodiments of the present technology. [Figure 3D] 1A-1D show schematic cross-sectional views of exemplary structures including and formed from layers of material in accordance with some embodiments of the present technology. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014]

[0016] Some figures are included as schematics. It should be understood that the figures are for illustrative purposes and should not be considered to scale unless scale is explicitly stated. Furthermore, as schematics, the figures are provided to aid in understanding and may not include all aspects or information as compared to realistic representations and may include redundant or exaggerated material for illustrative purposes.

[0015]

[0017] In the accompanying figures, similar components and / or features may be labeled with the same reference label. Additionally, various components of the same type may be distinguished by following the reference label with a letter that distinguishes the similar components. If only a first reference label is used herein, the description is applicable to any one of the similar components having the same first reference label, regardless of the letter.

[0016]

[0018] In the transition from 2D NAND to 3D NAND, the process options may change from vertical to horizontal applications. During 3D NAND processing, stacks of placeholder layers and dielectric materials may form inter-electrode dielectric or copolymer dielectric ("tyIPD") layers. These placeholder layers may undergo various steps before the material is completely removed and replaced with metal to place structures. When memory holes are formed, they may extend through all the alternating layers of material before accessing the underlying substrate. Subsequent processing may form staircase structures for contacts, and the placeholder material may also be exposed laterally, forming conductive material within the recesses.

[0017]

[0019] 3D NAND structures have an increased aspect ratio of memory holes and other structures, sometimes dramatically, as the number of cells formed increases. The increased number of cells formed may result in degradation of string current. Furthermore, a smaller threshold voltage variation may require a thinner polysilicon channel formed in the memory hole. When forming a polysilicon channel, the thinner the deposited silicon material, the lower the string current may be. Furthermore, an increased number of interelectrode dielectric layers and IPD layers may further sacrifice string current.

[0018]

[0020] Conventional techniques can struggle to balance the properties associated with the thickness of the polysilicon channel. A thinner thickness reduces defect variability and lowers threshold voltage variation. However, as discussed above, a thinner thickness also reduces string current. The present technique overcomes these issues by tailoring the materials used to form the polysilicon channel, which can reduce the tradeoff in electrical properties when reducing the thickness of the polysilicon channel. For example, the present technique can employ a three-layer structure of materials when forming the polysilicon channel. Instead of using only amorphous materials, the present technique can deposit an intermediate layer of halogen-doped material between two layers of amorphous material. The use of halogen-doped materials can improve electrical properties by allowing the halogen to passivate trap states and increase carrier mobility, resulting in increased string current compared to conventional techniques.

[0019]

[0021] While the remaining disclosure will always identify specific materials and semiconductor structures using the disclosed technology, it will be readily understood that the systems, methods, and materials are equally applicable to numerous other structures that may benefit from aspects of the technology. Thus, the technology should not be considered limited to use with only 3D NAND processes or materials. Additionally, while an exemplary chamber has been described to provide a foundation for the technology, it should be understood that the technology may be applied to virtually any semiconductor processing chamber that may enable the steps described.

[0020]

[0022] FIG. 1 is a cross-sectional view of an exemplary semiconductor processing chamber system 100 according to some embodiments of the present technology. The semiconductor processing chamber 100 can be used to form film layers according to some embodiments of the present technology, but it should be understood that the method can be similarly performed in any chamber in which film formation can occur. The semiconductor processing chamber 100 can include a chamber body 102, a substrate support 104 disposed within the chamber body 102, and a lid assembly 106 coupled to the chamber body 102 and enclosing the substrate support 104 within a processing region 120. The substrate 103 can be delivered to the processing region 120 through an opening 126, which can be sealed using a slit valve or door for conventional processing. The substrate 103 can be seated on a surface 105 of the substrate support during processing. The substrate support 104 can be rotatable along an axis 147 along which a shaft 144 of the substrate support 104 is disposed, as indicated by arrow 145. Alternatively, the substrate support 104 can be elevated to rotate as needed during the deposition process.

[0021]

[0023] A plasma profile modulator 111 may be disposed in the semiconductor processing chamber 100 to control plasma distribution across a substrate 103 disposed on a substrate support 104. The plasma profile modulator 111 may include a first electrode 108 that may be disposed adjacent to the chamber body 102 and may separate the chamber body 102 from other components of the lid assembly 106. The first electrode 108 may be part of the lid assembly 106 or may be a separate sidewall electrode. The first electrode 108 may be an annular or ring-shaped member or may be a ring electrode. The first electrode 108 may be a continuous loop around the circumference of the semiconductor processing chamber 100 surrounding the processing region 120 or may be discontinuous at selected locations as desired. Additionally, the first electrode 108 may be a perforated electrode, such as a perforated ring electrode or mesh electrode, or may be a plate electrode, such as a secondary gas distributor.

[0022]

[0024] One or more isolators 110a, 110b, which may be a dielectric material such as a ceramic or metal oxide, e.g., aluminum oxide and / or aluminum nitride, may contact the first electrode 108 and electrically and thermally isolate the first electrode 108 from the gas distributor 112 and from the chamber body 102. The gas distributor 112 may define an aperture 118 for distributing the process precursors into the processing region 120. The gas distributor 112 may be coupled to a first power source 142, such as an RF generator, an RF power supply, a DC power supply, a pulsed DC power supply, a pulsed RF power supply, or any other power supply that may be coupled to a processing chamber. In some embodiments, the first power source 142 may be an RF power supply.

[0023]

[0025] The gas distributor 112 may be a conductive gas distributor or a non-conductive gas distributor. The gas distributor 112 may also be formed of conductive and non-conductive components. For example, the body of the gas distributor 112 may be conductive while the faceplate of the gas distributor 112 may be non-conductive. The gas distributor 112 may be powered, such as by a first power source 142 as shown in FIG. 1, or the gas distributor 112 may be coupled to ground in some embodiments.

[0024]

[0026] The first electrode 108 may be coupled to a first tuned circuit 128 that may control a ground path of the semiconductor processing chamber 100. The first tuned circuit 128 may include a first electronic sensor 130 and a first electronic controller 134. The first electronic controller 134 may be or may include a variable capacitor or other circuit element. The first tuned circuit 128 may be or may include one or more inductors 132. The first tuned circuit 128 may be any circuit that allows for a variable or controllable impedance under plasma conditions present in the processing region 120 during processing. In some illustrated embodiments, the first tuned circuit 128 may include a first circuit leg and a second circuit leg coupled in parallel between ground and the first electronic sensor 130. The first circuit leg may include a first inductor 132A. The second circuit leg may include a second inductor 132B coupled in series to the first electronic controller 134. The second inductor 132B may be disposed between the first electronic controller 134 and a node connecting both the first and second circuit legs to the first electronic sensor 130. The first electronic sensor 130 may be a voltage sensor or a current sensor and may be coupled to the first electronic controller 134, which may allow for some closed-loop control of the plasma conditions in the processing region 120.

[0025]

[0027] A second electrode 122 may be coupled to the substrate support 104. The second electrode 122 may be embedded in the substrate support 104 or may be coupled to a surface of the substrate support 104. The second electrode 122 may be a plate, a perforated plate, a mesh, a wire screen, or any other distributed arrangement of conductive elements. The second electrode 122 may be a tuning electrode and may be coupled to a second tuning circuit 136 by a conduit 146, such as a cable having a selected resistance, for example 50 ohms, disposed on a shaft 144 of the substrate support 104. The second tuning circuit 136 may include a second electronic sensor 138 and a second electronic controller 140, which may be a second variable capacitor. The second electronic sensor 138 may be a voltage sensor or a current sensor and may be coupled to the second electronic controller 140 to provide further control of the plasma conditions in the processing region 120.

[0026]

[0028] A third electrode 124, which may be a bias electrode and / or an electrostatic chuck electrode, may be coupled to the substrate support 104. The third electrode may be coupled to a second power source 150 through a filter 148, which may be an impedance matching circuit. The second power source 150 may be DC power, pulsed DC power, RF bias power, pulsed RF source or bias power, or a combination of these or other power sources. In some embodiments, the second power source 150 may be RF bias power.

[0027]

[0029] The lid assembly 106 and substrate support 104 of FIG. 1 can be used in any processing chamber for plasma or thermal processing. In operation, the semiconductor processing chamber 100 can enable real-time control of plasma conditions in the processing region 120. The substrate 103 can be placed on the substrate support 104, and process gases can be flowed through the lid assembly 106 using the inlet 114 according to any desired flow scheme. The gases can exit the semiconductor processing chamber 100 through the outlet 152. Power can be coupled to the gas distributor 112 to establish a plasma in the processing region 120. The substrate can be electrically biased using the third electrode 124 in some embodiments.

[0028]

[0030] When a voltage is applied to the plasma in the processing region 120, a potential difference may be established between the plasma and the first electrode 108. A potential difference may also be established between the plasma and the second electrode 122. The electronic controllers 134, 140 may then be used to adjust the flow characteristics of the ground paths represented by the two tuned circuits 128 and 136. Set points may be delivered to the first tuned circuit 128 and the second tuned circuit 136 to provide independent control of center-to-edge deposition rate and plasma density uniformity. In an embodiment where the electronic controllers may both be variable capacitors, the electronic sensors may independently adjust the variable capacitors to maximize deposition rate and minimize thickness non-uniformity.

[0029]

[0031] Each of the tuning circuits 128, 136 may have a variable impedance that may be adjusted using the respective electronic controller 134, 140. If the electronic controller 134, 140 is a variable capacitor, the capacitance range of each variable capacitor and the inductance of the first inductor 132A and the second inductor 132B may be selected to provide an impedance range. This range may depend on the frequency and voltage characteristics of the plasma and may have a minimum value for the capacitance range of each variable capacitor. Thus, when the capacitance of the first electronic controller 134 is at a minimum or maximum, the impedance of the first tuning circuit 128 may be high, resulting in a plasma shape that has minimal aerial or lateral coverage above the substrate support. When the capacitance of the first electronic controller 134 approaches a value that minimizes the impedance of the first tuning circuit 128, the aerial coverage of the plasma may be maximized, effectively covering the entire working area of ​​the substrate support 104. As the capacitance of the first electronic controller 134 deviates from the minimum impedance setting, the plasma shape may shrink from the chamber walls and reduce aerial coverage of the substrate support. The second electronic controller 140 may have a similar effect, and aerial coverage of the plasma above the substrate support may increase and decrease as the capacitance of the second electronic controller 140 changes.

[0030]

[0032] Electronic sensors 130, 138 can be used to regulate the respective circuits 128, 136 in a closed loop. Depending on the type of sensor used, a current or voltage set point can be set for each sensor, which may be equipped with control software that determines the adjustments to each electronic controller 134, 140 to minimize deviations from the set point. As a result, the plasma shape can be selected and dynamically controlled during processing. Although the above description is based on electronic controllers 134, 140 being variable capacitors, it should be understood that any electronic components having adjustable characteristics can be used to obtain regulation circuits 128 and 136 with adjustable impedance.

[0031]

[0033] 2 is a diagram illustrating steps of an exemplary method 200 of semiconductor processing according to some embodiments of the present technology. The method may be performed in a variety of processing chambers, including the semiconductor processing chamber 100 described above, as well as any other chamber in which plasma deposition may be performed. The method 200 may include a number of optional steps prior to mimicking the method 200, including front-end processing, deposition, etching, polishing, cleaning, or any other steps that may be performed prior to the steps described. For example, the method may begin after a number of pairs of layers have been deposited to fabricate a 3D NAND memory.

[0032]

[0034] Method 200 may include a number of optional steps as shown that may or may not be specifically related to some embodiments of the method of the present technology. For example, many of the steps are described to provide a broader scope of structure formation, but are not critical to the present technology or may be performed by alternative methodologies as further described below. Method 200 is a description of the steps shown generally in Figures 3A-3D, which are described in conjunction with the steps of method 200. It should be understood that Figures 3A-3D are only partial schematic illustrations, and that a substrate may include any number of structural sections having the aspects illustrated in the figures, as well as alternative structural aspects that may still benefit from the steps of the present technology.

[0033]

[0035] Method 200 may or may not include optional steps for developing the semiconductor structure into a particular manufacturing process. It should be understood that method 200 may be performed on any number of semiconductor structures or substrates 305, such as those illustrated in FIG. 3A, including exemplary structures on which selective deposition materials may be formed. As illustrated in FIG. 3A, substrate 305 may have multiple layers of material deposited overlying the substrate. Substrate 305 may have a substantially flat or textured surface in embodiments. Substrate 305 may be a material such as crystalline silicon, silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, silicon-on-insulator, carbon doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, sapphire, or other substrate materials. The substrate 305 may have a variety of dimensions, such as a 200 mm or 300 mm diameter wafer, a rectangular or square panel, etc.

[0034]

[0036] Structure 300 may, in some embodiments, depict a partial view of a stack of alternating layers of materials that may be used in 3D NAND memory formation. The alternating layers of materials may be formed by any number of methods, including plasma enhanced chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermally enhanced chemical vapor deposition, or any other formation technique. In some embodiments, plasma enhanced chemical vapor deposition may be performed in a processing chamber, such as processing chamber 100 described above. Although the remaining disclosure generally describes a stack of alternating oxide and nitride layers, embodiments of the present technology may use combinations of different materials, such as silicon oxide and silicon nitride, silicon oxide and silicon, silicon nitride and silicon, silicon and doped silicon, or any number of other materials. Additionally, any number of layers of materials may be formed in the stack, or in any portion of any stack, and various portions of the stack may include more, less, or a similar number of layers than any other portion of the stack, in accordance with embodiments of the present technology.

[0035]

[0037] As shown in FIG. 3A, the structure 300 may include a substrate 305 having a stack of alternating layers of materials. The illustrated stack may include multiple portions 310, each of which may include at least one layer of oxide material 317 and at least one layer of nitride material 319. Each portion may also include multiple pairs of layers, including about 2 pairs or more, about 10 pairs or more, about 50 pairs or more, about 100 pairs or more, or more pairs of layers. In total, the structure 300 may include at least 16 alternating layers of oxide material 317 and nitride material 319, and may include at least 32 layers, at least 64 layers, at least 128 layers, or more. Any specific number of pairs falling within any of these described ranges should be understood as specifically described herein. Although three portions 310A, 310B, and 310C are illustrated, more or fewer portions may be included in accordance with some embodiments of the present technology.

[0036]

[0038] In some embodiments, the multiple portions 310, including all of the portions 310, may be formed during a single deposition sequence. Additionally, in some embodiments, the multiple portions may be formed in multiple steps. A mask material 315 may be formed over any portion of the stack prior to forming a portion of the memory hole or other feature through the structure. Once the layer is formed and the mask material 315 is deposited on the structure, as shown in FIG. 3B, a memory hole may be etched through the structure. The etching process may be any type of etch, and in some embodiments may be or include a reactive ion etching process. The etching process may extend through the third portion 310C of the stack, the second portion 310B of the stack, and at least partially through the third portion 310A of the stack. Although the structures according to the present technology may be characterized by any aspect ratio or height to width ratio of the structure, in some embodiments, the material may be characterized by a large aspect ratio. For example, in some embodiments, the aspect ratio of exemplary structures, such as the depth of an aperture or memory hole to its cross-sectional diameter, may be about 10:1 or more, about 20:1 or more, about 30:1 or more, about 40:1 or more, about 50:1 or more, or more.

[0037]

[0039] Referring to FIG. 3C, the method 200 may include, in step 205, supplying a silicon-containing precursor to a processing region of a semiconductor processing chamber. The silicon-containing precursor that may be used may include, but is not limited to, silane (SiH4), disilane (Si2H6), trisilane (Si3H8), silicon tetrafluoride (SiF4), silicon tetrachloride (SiCl4), dichlorosilane (SiH2Cl2), tetraethyl orthosilicate (TEOS), as well as any other silicon-containing precursor that may be used in silicon-containing film formation. In an embodiment, the method 200 may also include forming a plasma of the silicon-containing precursor in the processing region. In an embodiment, the plasma of the silicon-containing precursor may be formed by supplying RF power to a face plate to generate a plasma in the processing region, although any other processing chamber capable of generating a plasma may be used as well.

[0038]

[0040] The method 200 may include, in optional step 210, forming a first silicon-containing material 320 on the substrate. The first silicon-containing material 320 may simply be referred to as a first material layer. The first material layer may include a silicon-containing material such as amorphous silicon. The first material layer may include other components and may not be a pure silicon material. The first material layer may extend into one or more recesses formed in the alternating layers of material on the substrate 305. The first silicon-containing material 320 may reduce or prevent materials, such as halogen materials in silicon-halogen-containing materials described below, from penetrating into the portions 310 of the alternating layers, such as dielectric materials. Penetration of a large amount of halogen materials into the portions 310 of the alternating layers may damage or destroy the device due to high leakage and / or instability.

[0039]

[0041] After depositing the first silicon-containing material 320 to a sufficient thickness, the method may include, in step 215, supplying a halogen-containing precursor to a processing region of the semiconductor processing chamber. The halogen-containing precursor may include fluorine, chlorine, bromine, or any other halogen, or combination of halogens. Halogen-containing precursors that may be used may include, but are not limited to, nitrogen trifluoride (NF3) and silicon tetrafluoride (SiF4), as well as any other halogen-containing precursor that may be used in silicon-halogen-containing film formation. In an embodiment, the method 200 may also include forming a plasma of the halogen-containing precursor in the processing region. As previously mentioned, the plasma of the halogen-containing precursor may be formed by supplying RF power to a face plate to generate a plasma in the processing region, although any other processing chamber capable of generating a plasma may be used as well. The halogen-containing precursor may be supplied together with the silicon-containing precursor. It is contemplated that the silicon-containing precursor supplied together with the halogen-containing precursor may be the same precursor as that supplied in step 205, or may be a different precursor. It is also envisioned that the halogen-containing precursor may contain sufficient silicon content, thus obviating the need to co-feed a silicon-containing precursor with the halogen-containing precursor.

[0040]

[0042] The method 200 may include forming a silicon-halogen containing material 325 on the substrate at step 220. The silicon-halogen containing material 325 may also be referred to simply as a second material layer. The second material layer may include a silicon-halogen containing material. In an embodiment, the silicon-halogen containing material may include a silicon-fluorine containing material, a silicon-chlorine containing material, a silicon-bromine containing material, or any other halogen material. The silicon-halogen containing material 325 may extend into one or more recesses formed in the alternating layers of material. The silicon-halogen containing material 325 may overlie the first silicon-containing material 320.

[0041]

[0043] In an embodiment, the method 200 may include decreasing or stopping the flow of the halogen-containing precursor following the formation of the silicon-halogen-containing material 325 in step 225. The flow of the silicon-containing precursor from step 205 may be maintained, increased, or resumed if decreased or paused during steps 215 and 220. The silicon-containing precursor used to form the first silicon-containing material 320 may be the same precursor used to form the second silicon-containing material 330, as described further below. However, it is contemplated that different silicon-containing precursors may be used to form the first silicon-containing material 320 and the second silicon-containing material 330.

[0042]

[0044] The method 200 may include forming a second silicon-containing material 330 in an optional step 230. The second silicon-containing material 330 may simply be referred to as a third material layer. The third material layer may include a silicon-containing material such as amorphous silicon. The second material layer may include other components and may not be a pure silicon material. The second silicon-containing material 330 may extend into one or more recesses formed in the alternating layers of material. The second silicon-containing material 330 may overlie the silicon-halogen-containing material 325. The second silicon-containing material 330 may protect the first silicon-containing material 320, the silicon-halogen-containing material 325, or both from moisture and oxygen. The second silicon-containing material 330 may act as a protective layer to improve process stability.

[0043]

[0045] Both the first silicon-containing material 320 and the second silicon-containing material 330 may have substantially similar thicknesses. For example, the first silicon-containing material 320 and the second silicon-containing material 330 may be characterized by thicknesses that are within about 5 nm of each other, may have thicknesses that are within about 4 nm of each other, within about 3 nm of each other, within about 2 nm of each other, within about 1 nm of each other, or less. In embodiments, the first material layer, the second material layer, or both, may be characterized by a thickness of about 10 nm or less, e.g., about 8 nm or less, about 6 nm or less, about 5 nm or less, about 4 nm or less, about 3 nm or less, or less.

[0044]

[0046] The silicon-halogen containing material 325 may be characterized by a thickness that is greater than the thicknesses of the first silicon-containing material 320 and the second silicon-containing material 330. In embodiments, the silicon-halogen containing material 325 may be characterized by a thickness of about 60 nm or less. The thickness of the silicon-halogen containing material 325 may depend on the desired amount of halogen material between the first silicon-containing material 320 and the second silicon-containing material 330. Thus, in embodiments, the silicon-halogen containing material 325 may be characterized by a thickness of about 55 nm or less, e.g., about 50 nm or less, about 45 nm or less, about 40 nm or less, about 37 nm or less, about 35 nm or less, about 32 nm or less, about 30 nm or less, about 25 nm or less, about 20 nm or less, about 15 nm or less, about 10 nm or less, about 5 nm or less, about 4 nm or less, about 3 nm or less, or less.

[0045]

[0047] The deposition in steps 210, 220, and 230 may be carried out at a chamber, substrate, or pedestal temperature of about 700° C. or less. Thus, in some embodiments, the deposition may be carried out at a temperature of about 675° C. or less, about 650° C. or less, about 625° C. or less, about 600° C. or less, about 575° C. or less, about 550° C. or less, about 525° C. or less, about 500° C. or less, about 475° C. or less, about 450° C. or less, about 425° C. or less, about 400° C. or less, about 375° C. or less, about 350° C. or less, about 325° C. or less, about 300° C. or less, about 275° C. or less, about 250° C. or less, about 225° C. or less, about 200° C. or less, or less.

[0046]

[0048] Additionally, deposition in steps 210, 220, and 230 can be performed at a pressure of about 300 Torr or less, e.g., about 280 Torr or less, about 260 Torr or less, about 240 Torr or less, about 220 Torr or less, about 200 Torr or less, about 180 Torr or less, about 160 Torr or less, about 140 Torr or less, about 120 Torr or less, about 100 Torr or less, about 80 Torr or less, about 60 Torr or less, about 40 Torr or less, about 20 Torr or less, about 15 Torr or less, about 10 Torr or less, about 7 Torr or less, about 5 Torr or less, about 3 Torr or less, or less.

[0047]

[0049] Steps 210, 220, and 230 may be performed under the same or similar process conditions. For example, the temperature and / or pressure may be maintained during each of the formation of first silicon-containing material 320, silicon-halogen containing material 325, and second silicon-containing material 330. Conversely, the temperature and / or pressure may be changed or adjusted during the formation of first silicon-containing material 320, silicon-halogen containing material 325, and second silicon-containing material 330.

[0048]

[0050] 3D, an optional anneal of the substrate 305 and the formed film can be performed in step 235 to increase the temperature of the formed film. The anneal can be performed following the formation of the second silicon-containing material 330. The anneal can include increasing the temperature of the structure 300 to about 500° C. or more, and can increase the temperature of the structure 300 to about 550° C. or more, about 600° C. or more, about 650° C. or more, about 700° C. or more, about 750° C. or more, about 800° C. or more, about 850° C. or more, about 900° C. or more, or more. During the anneal, at least a portion of the first silicon-containing material 320 and the second silicon-containing material 330 can transform, for example, from amorphous silicon to polycrystalline silicon. During the anneal, about 95.0% by volume or more of the amorphous silicon can transform to polycrystalline silicon, for example, about 97.0% or more, about 99.0% or more, about 99.9% or more, or more. Polycrystalline silicon may contain regions of non-crystalline silicon or grains of crystalline silicon separated by grain boundaries. Depending on the channel depth, polycrystalline silicon may contain anywhere from one to about five grain boundaries. However, it is contemplated that polycrystalline silicon may contain more than five grain boundaries depending on the dimensions. The grain boundaries may act as scattering centers and reduce the channel conductance and string current. Additionally, halogen material in silicon-halogen containing material 325 may diffuse into first silicon-containing material 320 and second silicon-containing material 330. First silicon-containing material 320, silicon-halogen containing material 325, and second silicon-containing material 330 may collectively be referred to as annealing materials.

[0049]

[0051] By incorporating the silicon-halogen containing material 325 between the first silicon-containing material 320 and the second silicon-containing material 330, the halogen material may diffuse into the first silicon-containing material 320, the second silicon-containing material 330, or both during the anneal in step 235. Depending on the conditions of the anneal in step 235, the halogen material may be uniformly distributed within the first silicon-containing material 320, the second silicon-containing material 330, or both. However, it is contemplated that the halogen material may not be completely uniformly distributed and a concentration gradient may exist between the silicon-halogen containing material 325 and the first silicon-containing material 320, the second silicon-containing material 330, or both. If a concentration gradient exists, a higher concentration may exist in locations where the silicon-halogen containing material 325 was present prior to the anneal than in locations where the first silicon-containing material 320, the second silicon-containing material 330, or both were present prior to the anneal. Diffusion of halogen material into polysilicon may improve the thin film transistor characteristics of polysilicon. The halogen can bond to silicon and passivate trap states in the band gap of silicon, resulting in a more strongly bonded polysilicon channel compared to the prior art. In the prior art, a greater amount of silicon in the polysilicon channel may be bonded with hydrogen and have a lower bond energy than silicon bonded with halogen. Increasing the bond energy between silicon and halogen may reduce the trap state density through passivation, breaking the tradeoff between string current and threshold voltage variation in polysilicon channels with reduced thickness. Furthermore, increasing the bond energy between silicon and halogen may increase the operating life of the device, since the bond is less likely to be broken by electrons passing through during processing.

[0050]

[0052] Following annealing the substrate, the method 200 may include removing a portion of the annealed material 335, which may include a polycrystalline silicon material, at step 240. As previously described, the annealed material 335 may include the first silicon-containing material 320, the silicon-halogen-containing material 325, and the second silicon-containing material 330. The process used to remove the portion of the annealed material 335 may be any type of etch, and in some embodiments may be or include a wet etch. As the annealed material becomes thicker, the grain size may become larger and the grain boundaries may decrease in the annealed material 335, such as polycrystalline silicon. As the grain size becomes larger and therefore the grain boundaries decrease, the string current of the final device may increase. As the annealed material becomes thinner and an etching process to remove the portion of the annealed material is not required, the grain size in the annealed material may become smaller, thereby sacrificing the conductive path and decreasing the string current. Additionally, the thinner channel through removal of some of the annealed material 335 may improve threshold voltage variation due to reduced defect variation in the thinner channel.

[0051]

[0053] Referring again to FIG. 3D, some embodiments of the present technology are directed to a semiconductor structure. As previously described, the structure may include a substrate 305 having alternating layers of materials, such as oxide material 317 and nitride material 319, formed thereon. One or more recesses may be formed within the alternating layers of materials. A polycrystalline silicon material 335 may extend into the one or more recesses. The polycrystalline silicon material 335 may include a first surface 337. A second surface 339 of the polycrystalline material opposite the first surface 337 of the polycrystalline silicon material 335 may overlie and contact the alternating layers of materials. The polycrystalline silicon material 335 may include a halogen. A portion of the polycrystalline silicon material 335 disposed intermediate the first surface 337 and the second surface 339 may have a higher halogen atomic concentration compared to the first surface 337 and the second surface 339. For example, a portion of the polycrystalline silicon material 335 disposed intermediate the first side 337 and the second side 339 may have a halogen concentration that is about 1 atomic % to about 5 atomic % higher than the halogen concentration at the first side 337 and / or the second side 339. However, it is contemplated that the halogen concentration difference between the first side 337 and / or the second side 339 and the portion of the polycrystalline silicon material 335 intermediate between the first side 337 and the second side 339 may be about 5 atomic % or more. The polycrystalline silicon material 335 may be characterized by a thickness of about 30 nm or less, e.g., about 28 nm or less, about 26 nm or less, about 24 nm or less, about 22 nm or less, about 20 nm or less, about 18 nm or less, about 16 nm or less, about 14 nm or less, about 12 nm or less, about 10 nm or less, about 8 nm or less, about 6 nm or less, about 4 nm or less, about 2 nm or less, or less.

[0052]

[0054] By using one or more of the described processes, electrical performance in 3D NAND can be improved, thereby reducing the difficulties associated with scaling and increasing layers in the 3D NAND stack, resulting in improved manufacturing and devices with better performance than prior art.

[0053]

[0055] In the above description, for purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to one skilled in the art that certain embodiments may be practiced without some of these details or with additional details.

[0054]

[0056] Although several embodiments have been disclosed, it will be recognized by those skilled in the art that various modifications, alternative structures, and equivalents can be used without departing from the spirit of the embodiments. Moreover, some well-known processes and elements have not been described to avoid unnecessarily obscuring the present technology. Thus, the above specification should not be interpreted as limiting the scope of the present technology. Furthermore, although a method or process may be described sequentially or stepwise, it should be understood that the steps may be performed simultaneously or in an order different from that listed.

[0055]

[0057] Where a range of values ​​is provided, it is understood that each intervening value between the upper and lower limit of that range, to the smallest fraction of the unit of the lower limit, is also specifically disclosed, unless the context clearly dictates otherwise. Any narrower range between any stated value or unstated intervening value in a stated range and any other stated or intervening value in that stated range is included. The upper and lower limits of these smaller ranges may be independently included or excluded, and each range in which either or both limits are included in the smaller ranges is also included within the technology, subject to any specifically excluded limit in the stated range. Where a stated range includes one or both limits, ranges excluding either or both of those included limits are also included.

[0056]

[0058] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Thus, for example, reference to a "silicon-containing precursor" includes a plurality of such precursors, reference to a "first layer of material" includes a reference to one or more layers and equivalents thereof known to those skilled in the art, and so forth.

[0057]

[0059] Additionally, the terms "comprise," "comprising," "contain," "containing," "include," and "including," as used in this specification and the following claims, specify the presence of stated features, integers, components, or steps, but they do not exclude the presence or addition of one or more other features, integers, components, steps, operations, or groups.

Claims

1. 1. A semiconductor processing method comprising: providing a silicon-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate is disposed in the processing region of the semiconductor processing chamber, alternating layers of material are formed on the substrate, and one or more recesses are formed in the alternating layers of material; delivering a halogen-containing precursor to a processing region of the semiconductor processing chamber; forming a silicon-halogen containing material, the silicon-halogen containing material extending into the one or more recesses formed in the alternating layers of material and overlying the alternating layers of material; The method includes:

2. 10. The semiconductor processing method of claim 1, wherein the temperature within said semiconductor processing chamber is maintained at or below about 700 degrees Celsius.

3. 10. The semiconductor processing method of claim 1, wherein the pressure in said semiconductor processing chamber is maintained at or below about 300 Torr.

4. 10. The semiconductor processing method of claim 1, wherein the silicon-containing precursor comprises silane, disilane, dichlorosilane, or trisilane.

5. the halogen-containing precursor comprises fluorine; The silicon-halogen containing material comprises a silicon-fluorine containing material.

10. The semiconductor processing method of claim 1.

6. 10. The semiconductor processing method of claim 1, wherein the halogen-containing precursor comprises nitrogen trifluoride or silicon tetrafluoride.

7. forming a first silicon-containing material prior to forming the silicon-halogen containing material, the first silicon-containing material extending into the one or more recesses formed in the alternating layers of material; forming a second silicon-containing material, the second silicon-containing material overlying the silicon-halogen-containing material; or forming both the first silicon-containing material and the second silicon-containing material; The semiconductor processing method of claim 1 further comprising:

8. 2. The semiconductor processing method of claim 1, wherein said silicon-halogen containing material is characterized by a thickness of about 60 nm or less.

9. annealing the substrate after forming the second silicon-containing material. The semiconductor processing method of claim 7 further comprising:

10. During the anneal, the halogen material in the silicon-halogen containing material diffuses into the first silicon-containing material, the second silicon-containing material, or both.

10. The semiconductor processing method of claim 9.

11. 1. A semiconductor processing method comprising: forming a first material layer within one or more recesses defined in alternating layers of material on a substrate in a processing region of a semiconductor processing chamber, the first material layer being a first silicon-containing material; forming a second layer of material on the first layer of material, the second layer of material being a silicon-fluorine containing material; forming a third material layer on the second material layer, the third material layer being a second silicon-containing material; The method includes:

12. a temperature within the semiconductor processing chamber is maintained at or below about 700° C.; The pressure within the semiconductor processing chamber is maintained at or below about 300 Torr.

12. The semiconductor processing method of claim 11.

13. the alternating layers of material include alternating layers of oxide and nitride materials; the substrate comprises more than 16 alternating layers of materials; 12. The semiconductor processing method of claim 11.

14. 12. The semiconductor processing method of claim 11, wherein said second layer of material is characterized by a thickness greater than a thickness of said first layer of material and said third layer of material.

15. 12. The semiconductor processing method of claim 11, wherein the second layer of material is characterized by a thickness of about 2 nm to about 30 nm.

16. annealing the substrate after forming the first layer of material, the second layer of material, and the third layer of material. The semiconductor processing method of claim 11 further comprising:

17. the first material layer, the third material layer, or both, comprise amorphous silicon; By annealing, at least a portion of the amorphous silicon is transformed into polycrystalline silicon.

17. The semiconductor processing method of claim 16.

18. removing a portion of the first silicon-containing material, the silicon-halogen-containing material, and the second silicon-containing material after annealing the substrate; 20. The semiconductor processing method of claim 16 further comprising:

19. 1. A semiconductor structure comprising: a substrate having alternating layers of material formed thereon, the alternating layers of material having one or more recesses formed therein; a polycrystalline silicon material extending into the one or more recesses, a second side of the polycrystalline silicon material opposite a first side of the polycrystalline silicon material overlying the alternating layers of the material, the polycrystalline silicon material including a halogen, and a portion of the polycrystalline silicon material disposed intermediate the first side and the second side having a higher concentration of halogen atoms compared to the first side and the second side; 1. A semiconductor structure comprising:

20. 20. The semiconductor structure of claim 19, wherein the polycrystalline silicon material is characterized by a thickness of about 30 nm or less.

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