Memory and its manufacturing method, electronic device

Abstract

According to an embodiment of the present disclosure, a memory, a manufacturing method thereof, and an electronic device are provided. [Solution] A memory having a substrate, and word lines, bit lines, and memory cells on one side of the substrate, the memory cells including transistors, the transistors including a semiconductor layer formed by sequentially connecting a source contact region, a semiconductor region, and a drain contact region, a main gate electrode electrically connected to the word line, a source electrode electrically connected to the bit line and the source contact region of the semiconductor layer, a drain electrode electrically connected to the drain contact region of the semiconductor layer, and an auxiliary gate electrode electrically connected to the drain electrode, the orthogonal projection of the main gate electrode onto the substrate and the orthogonal projection of the auxiliary gate electrode onto the substrate at least partially overlap with the orthogonal projection of the semiconductor region in the semiconductor layer onto the substrate. The present disclosure provides a transistor having a main gate electrode, and an auxiliary gate electrode electrically connected to the drain electrode, the auxiliary gate electrode obtaining a fixed potential synchronized with the drain electrode, and providing replenishment control to the semiconductor layer by the fixed potential, thereby optimizing the read / write performance of the memory.

Description

Technical Field

[0001] This application claims priority based on Patent Application No. 202210351082.9 filed in China on April 2, 2022, and this application is incorporated herein by reference.

[0002] This disclosure relates to the field of memory technologies, and in particular, Dynamic memory and its manufacturing method, memory device, and electronic devices.

Background Art

[0003] Random Access Memory (RAM) typically includes a memory structure of transistors and, for example, capacitors, where the transistors control read or write tasks for the memory structure. Thus, the performance of the transistors significantly affects the read / write performance of the entire memory.

Summary of the Invention

Problems to be Solved by the Invention

[0004] This disclosure proposes Dynamic memory and its manufacturing method, memory device, and electronic devices for improving the read / write performance of memory.

Means for Solving the Problems

[0005] The memory according to the first aspect Dynamic has a substrate, a word line, a bit line, and a memory cell on one side of the substrate, and the memory cell includes a transistor, and the transistor an active layer including a source electrode, a drain electrode, and a channel positioned between the source electrode and the drain electrode, has a main gate electrode electrically connected to the word line, a source electrode electrically connected to the bit line channel and respectively, and a drain electrode electrically connected to channel and a drain electrode electrically connected to backincluding a gate electrode, and the orthographic projection of the main gate electrode onto the substrate covers the orthographic projection of the channel onto the substrate, and the back The orthographic projection of the gate electrode onto the substrate orthographic projection of the active layer onto the substrate and overlaps. In some forms, the main gate electrode is provided between the substrate and a layer, or the main gate electrode is located on the side of the layer farther from the substrate. active In some forms, the main gate electrode and a certain element are located on opposite sides of a specific component respectively. active In some forms, the main gate electrode is located on the side of the layer farther from the substrate. In some forms, the main gate electrode and a certain element are located on opposite sides of a specific component respectively. back gate electrode are active layer located on opposite sides of a specific component respectively. In some forms, the memory cell further has a memory structure, and the memory structure includes a capacitive memory structure formed between a certain element and the first electrode. back gate electrode In some forms, the first electrode is a source electrode, and the orthographic projection of the source electrode onto the substrate and the orthographic projection of a certain element onto the substrate partially overlap. In some forms, the main gate electrode is located on the side of the layer farther from the substrate, a certain element is located between the substrate and a layer, and the first electrode is located between the substrate and a layer. back gate electrode In some forms, the main gate electrode is located between the substrate and a layer, a certain element is located on the side of the layer farther from the substrate, and the first electrode is located on the side of the layer farther from the substrate.

[0006] In some forms, the main gate electrode active layer is located on the side of the layer farther from the substrate, back gate electrode a certain element is located between the substrate and a layer, active layer and the first electrode is located between the substrate and a layer. back gate electrode In some forms, the main gate electrode is located between the substrate and a layer,

[0007] a certain element is located on the side of the layer farther from the substrate, and the first electrode is located on the side of the layer farther from the substrate. active layer In some forms, the main gate electrode is located between the substrate and a layer, back gate electrode a certain element is active layer located on the side of the layer farther from the substrate, and the first electrode is back gate electrode located on the side of the layer farther from the substrate.

[0008] In some forms, the transistor further includes a dielectric layer located between a certain element and the main gate electrode, and a dielectric layer located between a certain element and a certain component, and between a certain element and the source electrode. The orthographic projection of the source electrode onto the substrate and the orthographic projection of a certain element onto the substrate partially overlap. active layer a dielectric layer located between a certain element and the main gate electrode top gate and a dielectric layer back gate electrode between a certain element and a certain component active layer and between a certain element and the source electrode. The orthographic projection of the source electrode onto the substrate and the orthographic projection of a certain element onto the substrate partially overlap. back gate electrode In some forms, the main gate electrode is located between the substrate and a layer, a certain element is located on the side of the layer farther from the substrate, and the first electrode is located between the substrate and a layer. The orthographic projection of the source electrode onto the substrate and the orthographic projection of a certain element onto the substrate partially overlap. back gate electrode In some forms, the main gate electrode is located between the substrate and a layer, a certain element is located on the side of the layer farther from the substrate, and the first electrode is located on the side of the layer farther from the substrate. The orthographic projection of the source electrode onto the substrate and the orthographic projection of a certain element onto the substrate partially overlap. back gate including a dielectric layer.

[0009] In some forms, the main gate electrode is located on the side far from the substrate, active layer is located between the substrate and back gate electrode and the transistor includes an insulating layer, a first through hole, and a second through hole. The insulating layer is located on the side far from the substrate of the main gate electrode. The bit line is located on the side far from the main gate electrode of the insulating layer. The first through hole penetrates the insulating layer and active layer the dielectric layer respectively, and is connected to the bit line and the source top gate respectively. The second through hole penetrates the insulating layer, electrode the dielectric layer and top gate the dielectric layer respectively, and is connected to the drain back gate and electrode and back gate electrode respectively. In some forms, a part of the orthographic projection of the back gate electrode onto the substrate is located outside the orthographic projections of the source electrode, the drain electrode, and the channel onto the substrate, and this part is electrically connected to the drain electrode.

[0010] In some forms, the main gate electrode is located between the substrate and active layer and is back gate electrode located on the side far from the substrate of active layer . The transistor includes an insulating layer, a first through hole, and a second through hole. The insulating layer is located on the side far from the substrate of back gate electrode . The bit line is located on the side far from the back gate electrode of the insulating layer. The first through hole penetrates the insulating layer and back gate the dielectric layer respectively, and is connected to the bit line and the source electrode respectively. The second through hole penetrates the insulating layer and back gate the dielectric layer, and is connected to back gate electrode and the drain electrode respectively. In some forms, the word line is provided in the same layer as the main gate electrode and is in a different layer from the bit line.

[0011] In some forms, active layer includes at least one of a metal oxide semiconductor, single crystal silicon, polycrystalline silicon, and amorphous silicon. The metal oxide semiconductor includes indium gallium zinc oxide .

[0012] In some forms, a plurality of The memory cells are stacked and arranged perpendicular to the substrate, and a plurality of The memory cells are arrayed on one side of the substrate, and in the each memory cells in the same row, the main gate electrodes of the transistors are electrically connected to the same word line, and in the each memory cells in the same column, the source electrodes of the transistors are electrically connected to the same bit line. The electronic device according to the second form includes a Dynamic memory of any of the forms.

[0013] Regarding the third form Dynamic The manufacturing method of the memory is as follows: on one side of the substrate, back gate electrode, back gate a medium layer, active layer, top gate a medium layer, a main gate electrode, a word line connected to the main gate electrode, and an insulating layer are sequentially fabricated, active layer is, the source electrode, channel, and drain electrode are sequentially connected, and the insulating layer and top gate the medium layer are sequentially etched to obtain a first hole, the insulating layer, top gate the medium layer and back gate the medium layer are sequentially etched to obtain a second hole, and a first via connecting the source electrode is formed in the first hole, back gate electrode and the drain electrode are connected, and a second via is formed in the second hole such that the first bit line is fabricated on the depositing via materials respectively so as to electrically connect the source electrode and the bit line, first via.

[0014] In some forms, on one side of the substrate, back gate electrode, back gate dielectric layer, active layer, top gate fabricating the medium layer, the main gate electrode, the word line connected to the main gate electrode, and the insulating layer sequentially is equivalent to fabricating back gate electrode on one side of the substrate, back gate electrode and on the exposed substrate, back gate fabricating the medium layer, channel of the active layer the orthographic projection of source electrode of the active layer onto the substrate and the orthographic projection of back gate electrode onto the substrate partially overlap the orthographic projection portion of the active layer is formed on the back gate dielectric layer, and the source electrode and the drain electrode of the active layerIt becomes conductive.

[0015] In some forms, the insulating layer and top gate the dielectric layer are sequentially etched to obtain a first hole that exposes at least a part of the source electrode and the insulating layer and top gate the dielectric layer back gate and the dielectric layer are sequentially etched to active layer obtain a second hole that exposes at least a part of the drain electrode and back gate electrode of a part of the drain, and these are performed synchronously.

[0016] The manufacturing method of the memory according to the fourth form Dynamic is to manufacture a main gate electrode, a word line connected to the main gate electrode, top gate a dielectric layer, active layer, back gate a dielectric layer, back gate electrode and an insulating layer sequentially on one side of the substrate, active layer which is formed by connecting the source electrode, channel and the drain electrode in order, and the insulating layer and back gate the dielectric layer are sequentially etched to obtain a first hole that exposes at least a part of the source electrode and the insulating layer and the back gate dielectric layer are sequentially etched to back gate electrode obtain a second hole that exposes a part of the drain electrode and at least a part of the drain, a first via connecting the source electrode is formed in the first hole, back gate electrode and a second via connecting the drain electrode is formed in the second hole, and conductive materials are respectively formed in the first hole and the second hole so that a bit line is fabricated on the first via.

[0017] In some forms, on one side of the substrate, a main gate electrode, a word line connected to the main gate electrode, top gate a dielectric layer, active layer, back gate a dielectric layer, back gate electrode, the sequential manufacture of the first insulating layer involves manufacturing a main gate electrode and a word line connected to the main gate electrode on one side of the substrate, and on the main gate electrode, the word line connected to the main gate electrode, and the exposed substrate, top gate a dielectric layer is manufactured, channel of the active layer such that the orthographic projection of the substrate onto the substrate and the orthographic projection of the main gate electrode onto the substrate partially overlap, top gate on the dielectric layer, active layer is fabricated, active layer the source of electrode and the drain electrode are made conductive, active layer and on the exposed top gate dielectric layer, back gate a dielectric layer is fabricated, back gate electrode the orthographic projection of the substrate onto the substrate is channel of the active layer the orthographic projection of the substrate onto the substrate and active layer the orthographic projection of the source of electrode the substrate onto the substrate respectively overlap, back gate on the dielectric layer back gate electrode is fabricated.

[0018] In some forms, the insulating layer and back gate the dielectric layer are sequentially etched to obtain a first hole exposing at least a portion of source electrode of the active layer , and the insulating layer and back gate the dielectric layer are sequentially etched to obtain a second hole exposing at least a portion of a part of the back gate electrode and the active layer the drain of electrode , and these are performed synchronously.

Advantages of the Invention

[0019] Some aspects and advantages of the present disclosure are provided in part from the following description, and these will also become apparent from the following description or will be made clear by the practice of the present application.

Brief Description of the Drawings

[0020] The above-described present disclosure and / or additional aspects and advantages will become apparent from the description of the embodiments based on the accompanying drawings.

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Figure 22

Embodiments for Carrying Out the Invention

[0021] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. It should be noted that the embodiments described below with reference to the drawings are exemplary descriptions for explaining the embodiments of the present disclosure, and it goes without saying that they do not limit the technical idea according to an embodiment of the present disclosure.

[0022] Unless otherwise specified, those skilled in the art can also understand that the singular forms of "one", "a", "the foregoing", and "said" used herein include plural forms. Further, the term "including" used in the specification of the present disclosure means the presence of the features, integers, steps, operations, elements, and / or components, but does not exclude other features, information, data, steps, operations, elements, components, and / or combinations thereof supported in the technical field. When one element is referred to as being "connected" or "coupled" to another element, it may mean that one element is directly connected or coupled to the other element, or it may mean that a connection relationship is established between one element and the other element through an intermediate element. Also, the "connection" or "coupling" used herein can include either a wired connection or a wireless connection. The "and / or" used herein means at least one of the items defined by the term. For example, "A and / or B" may be implemented as "A", may be implemented as "B", or may be implemented as "A and B".

[0023] As shown in FIG. 1, the idea of the present disclosure is that the memory cell 10 of a DRAM is usually a 1T1C configuration composed of one transistor and one capacitor. Due to the leakage of the current across the channel when the transistor is in the off state, the charge stored in the capacitor is gradually lost, and usually, frequent refreshing is required to guarantee the validity of the stored data.

[0024] The currently mainstream DRAM needs to be designed with a sufficiently large capacity to reduce the refresh rate. However, this results in a non-compact structure and a low integration degree of the DRAM.

[0025] In an embodiment of the present disclosure, the memory 1 is an access memory (Access Memory) including a memory array including one memory cell 10. For example, one memory cell 10 in one memory array of DRAM (Dynamic Random Access Memory) or other types of memory 1 is used. Of course, it is not limited to the memory cell 10 in the memory array, and at least any one of a plurality of memory cells 10 not in the array format may be used.

[0026] Each memory array includes at least memory cells 10 distributed in a row and column manner, and each memory cell 10 includes at least one transistor, at least one word line 30, and at least one bit line 20.

[0027] In some embodiments, the memory cell 10 can include one transistor, one memory 1, one word line 30, and one bit line 20. In some other embodiments, the memory cell 10 includes only one transistor, but may include two bit lines 20. Also, in some embodiments, the number of transistors may not be one.

[0028] In the memory cell 10 proposed by the present disclosure, the transistor Active layer is provided with a main gate electrode 105 capable of conductivity control with respect to 103, Active layer and also provides conductivity control to 103 Back gate electrode introduces 101, and this Back gate electrode 101 is electrically connected to the drain electrode. Thereby, Back gate electrode 101 can obtain a fixed potential synchronized with the drain electrode, and this fixed potential Active layer provides replenishment control to 103. Also, Back gate electrode since 101 is not electrically connected to the source electrode, it can function as a negative bias of the threshold voltage in the readout stage. The performance of the transistor can be improved, and the read / write performance of the memory 1 can be further optimized. Hereinafter, the concept of the invention of the present application will be described with specific examples.

[0029] This application is made to solve the above problems of the prior art, and provides a memory, a method for manufacturing the same, and an electronic device. The memory 1 according to an embodiment of the present disclosure includes a substrate 200, a word line 30, a bit line 20, and a memory cell 10 on the substrate 200 side, as shown in FIGS. 2 to 8.

[0030] The memory cell 10 includes a transistor, and the transistor Active layer has a main gate electrode 105, a source electrode, a drain electrode, Back gate electrode and 101. Active layer 103 is a source Electrode 1031, Channel 1033, and a drain Electrode 1032 are sequentially connected. The main gate electrode 105 is electrically connected to the word line 30. The source electrode is electrically connected to the bit line 20 and Channel 1033 respectively. The drain electrode is Channel 1033 electrically connected to. Back gate electrode 101 is electrically connected to the drain electrode.

[0031] Here, the orthographic projection of the main gate electrode 105 onto the substrate 200, and Back gate electrode the orthographic projection of 101 onto the substrate 200 each Active layer overlap at least a part of the orthographic projection of Channel 1033 of 103 onto the substrate 200. In some embodiments, the orthographic projection of the main gate electrode onto the substrate covers the orthographic projection of the channel onto the substrate, and the orthographic projection of the back gate electrode onto the substrate overlaps with the orthographic projection of the active layer onto the substrate.

[0032] The memory 1 provided by this embodiment optimizes the configuration of the memory 1. Specifically, the transistor has a main gate electrode 105 capable of realizing conductivity control with respect to Active layer 103, and Active layer introduces 101 that also provides conductivity control to Back gate electrode 103. With this Back gate electrode101 is electrically connected to the drain electrode. As a result, Back gate electrode 101 can obtain a fixed potential synchronized with the drain electrode, and by this fixed potential Active layer a replenishment control is applied to 103. Also Back gate electrode since 101 is not electrically connected to the source electrode, it can function as a negative bias of the threshold voltage in the readout stage. The performance of the transistor can be improved, and the read / write performance of the memory 1 can be optimized.

[0033] Note that in this embodiment Back gate electrode 101 is electrically connected to the drain electrode and a fixed potential synchronized with the drain electrode is obtained, so it is not a floating gate.

[0034] In some embodiments, as shown in FIGS. 6 and 8, the main gate electrode 105 is located between the substrate 200 and Active layer 103. That is, the transistor can adopt a bottom gate structure.

[0035] In some other embodiments, as shown in FIGS. 5 and 7, the main gate electrode 105 is located on the side far from the substrate 200 of Active layer 103. That is, the transistor can adopt a top gate structure.

[0036] Based on the above possible embodiments, in a further embodiment, as shown in FIGS. 5 to 8, the main gate electrode 105 and Back gate electrode 101 are Active layer respectively arranged on both sides of 103. Thereby, the mutual interference between the main gate electrode 105 and Back gate electrode 101 can be reduced, and the effective areas where the main gate electrode 105 and Back gate electrode 101 act on 103 respectively are improved, which is advantageous for improving the performance of the transistor. Specifically, when the transistor has a bottom gate structure, the main gate electrode 105 is located between the substrate 200 and Active layer 103, Active layer and Back gate electrode 101 isActive layer It is located on the side far from the substrate 200 of 103. When the transistor has a top gate structure, Back gate electrode 101 is between the substrate 200 and Active layer 103, and the main gate electrode is Active layer located on the side far from the substrate 200 of 103.

[0037] The idea of the present disclosure is further that a memory cell of a dynamic random access memory 1 (DRAM) generally includes a memory structure of a transistor and a capacitor realized by a capacitive electrode, usually having a structure such as 1T1C. There is a current leakage phenomenon across the channel when the transistor is in the off state, and at least a part of the charge stored in the capacitor gradually flows out due to the leakage current, so the stored data must be frequently refreshed to ensure the validity of the stored data. In DRAM products, the storage capacity can be increased and the refresh rate can be lowered by increasing the area of the capacitive electrode, but the integration degree of the DRAM product will be lowered due to the increase in the area of the capacitive electrode. Therefore, the present disclosure enables the following realization for the memory 1.

[0038] As shown in FIGS. 7 and 8, in some embodiments of the present disclosure, the memory cell 10 further includes a memory structure. The memory structure Back gate electrode includes a capacitive memory structure formed between 101 and the first electrode 110 and.

[0039] In this embodiment, the memory cell 10 Back gate electrode includes a capacitive memory structure formed between 101 and the first electrode 107, can realize data writing, and can improve the problem of current leakage in the transistor off state. Using Back gate electrode as a part of the capacitive memory structure is advantageous for making the integration degree of the device relatively high.

[0040] As an option, the first electrode 110 is Back gate electrodeIt may be a dedicated conductive structure that forms the 101 and the capacitive memory structure, or the first electrode 110 has conductivity to other electrical structures in the memory 1, Back gate electrode It may be a conductive structure capable of forming the 101 and the capacitive memory structure.

[0041] In some embodiments, as shown in FIG. 7, the main gate electrode 105 Active layer is located on the side far from the substrate 200 of the 103, Back gate electrode the 101 is between the substrate 200 and Active layer the 103, and the first electrode 110 is between the substrate 200 and Back gate electrode the 101. That is, Active layer the main gate electrode 105 and Back gate electrode the 101 are respectively located on both sides of the 103, and when the transistor has a top gate structure, the first electrode 110 is Back gate electrode arranged closer to the substrate 200 than the 101.

[0042] In some embodiments, as shown in FIG. 8, the main gate electrode 105 is between the substrate 200 and Active layer the 103, Back gate electrode the 101 is Active layer located on the side far from the substrate 200 of the 103, and the first electrode 110 is Back gate electrode located on the side far from the substrate 200 of the 101. That is, Active layer the main gate electrode 105 and Back gate electrode the 101 are respectively located on both sides of the 103, and when the transistor has a bottom gate structure, the first electrode 110 is Back gate electrode arranged on the side further away from the substrate 200 with respect to the 101.

[0043] In some embodiments, as shown in FIGS. 5 and 6, the first electrode 110 is the source electrode, and the orthographic projection of the source electrode onto the substrate 200 Back gate electrode partially overlaps with the orthographic projection of the 101 onto the substrate 200.

[0044] In this embodiment, a source electrode is used as another part of the capacitive memory structure, Back gate electrode and in cooperation with 101, realizes data writing, further increasing the integration degree of Memory 1. That is, data reading and writing can be realized only by providing one transistor in the memory cell 10 of Memory 1, without the need to separately provide transistors and capacitive elements, greatly simplifying the configuration of the memory cell 10, which is advantageous for improving the integration degree and storage density of Memory 1.

[0045] Note that in FIGS. 2 and 3, although a storage capacitor is shown in both, actually, this storage capacitor is composed of Back gate electrode 101 and the source electrode and drain electrode of the transistor. Back gate electrode There is a back-gate effect in 101, that is, Back gate electrode since the potential of 101 affects the threshold voltage of the transistor, the magnitude of the voltage for turning on the transistor during the reading of the stored data is between the threshold voltage when the transistor stores "1" and the threshold voltage when the transistor stores "0".

[0046] In Memory 1 provided in this embodiment, a first level is applied to the main gate electrode 105 via the word line 30 during the write operation. A storage signal is transmitted to the source electrode of the memory cell 10 to be written via the bit line 20, and the source electrode transmits the storage signal to the drain electrode. The drain electrode transmits the storage signal to Back gate electrode 101, Back gate electrode and the node capacitor of 101 and the drain electrode becomes the storage capacitor of the memory cell 10. Thereby, data writing is realized. During the read operation, the influence of the voltage on Back gate electrode 101 on the transistor threshold voltage is utilized. Main gate electrode 105A second level is applied via the word line 30, and then data is read by detecting the magnitude of the transistor output current. Therefore, the memory cell 10 can read and write data by simply providing one transistor, without the need to separately provide a transistor and a capacitive element. This simplifies the configuration of the memory cell 10 extremely, which is advantageous for improving the integration degree and storage density of the memory 1.

[0047] The memory cell 10 in the memory 1 provided by this embodiment only needs to include one transistor. However, in the following embodiments, the film layer structure of the memory 1 will be described in detail. In some embodiments, as shown in FIGS. 5 to 8, the transistor Top gate further includes a medium layer 104 and Back gate a medium layer 102. Top gate The medium layer 104 Active layer is located between 103 and the main gate electrode 105.

[0048] Back gate The medium layer 102 Back gate electrode is located between 101 and Active layer 103, and the orthogonal projection of the source electrode onto the substrate 200 and Back gate electrode the orthogonal projection of 101 onto the substrate 200 partially overlap.

[0049] In the memory 1 provided by this embodiment, Back gate the medium layer 102 is used as the dielectric material of the holding capacitor serving as the auxiliary gate electrode 101 and the source electrode. Top gate The medium layer 104 realizes the insulating layer 106 between the main gate electrode 105 and the source electrode and drain electrode.

[0050] In some embodiments, as shown in FIGS. 5 to 8, the memory 1 according to this embodiment further includes a buffer layer 300 between the substrate 200 and the film layer closest to the substrate 200 of the transistor (for example, Back gate electrode 101 in FIG. 5). As an option, the material of the substrate 200 is silicon or glass, and the buffer layer 300 is an insulating material.

[0051] In some embodiments, as shown in FIG. 5, Active layer main gate electrodes 105 are located on both sides of 103, Back gate electrode and 101 are respectively positioned, and the specific film layer structure of the transistor using a top gate structure is as follows. The main gate electrode 105 Active layer is located on the side of 103 far from the substrate 200, Back gate electrode and 101 is located Active layer between the substrate 200 and 103. The transistor has an insulating layer 106, a first through hole 107, and a second through hole 108. The insulating layer 106 is located on the side of the main gate electrode 105 far from the substrate 200. The bit line 20 is located on the side of the insulating layer 106 far from the main gate electrode 105.

[0052] The first through hole 107 respectively penetrates the insulating layer 106 and Top gate the medium layer 104, and is respectively connected to the bit line 20 and the source Electrode 1031.

[0053] The second through hole 108 respectively penetrates the insulating layer 106, Top gate the medium layer 104, Back gate the medium layer 102, and is respectively connected to the drain Electrode 1032 and Back gate electrode 101.

[0054] As shown in FIG. 5, in the memory 1 according to this embodiment, the bit line 20 is electrically connected to the source Top gate 1031 of 103 through the first via 107 penetrating the insulating layer 106 and Active layer the medium layer 104. Electrode The drain Active layer 1032 of 103 Electrode is Back gate electrically connected to 101 through the second through hole 108 penetrating the medium layer 102.Back gate electrode It may be electrically connected to 101.

[0055] Here, at least a part of the entire source 1031 including the first through-hole 107 may be used as a source electrode. For example, a part or all of the first through-hole 107 may be used as the source electrode. Electrode At least a part of the entire source 1031 including the first through-hole 107 may be used as a source electrode. For example, a part or all of the first through-hole 107 may be used as the source electrode. Active layer The source of 103 that has been made conductive Electrode A part or all of 1031 may be used as the source electrode.

[0056] Similarly, at least a part of the entire drain 1032 including the second through-hole 108 may be used as a drain electrode. For example, a part or all of the second through-hole 108 may be used as the drain electrode. Electrode At least a part of the entire drain 1032 including the second through-hole 108 may be used as a drain electrode. For example, a part or all of the second through-hole 108 may be used as the drain electrode. Active layer The drain of 103 that has been subjected to a conductor formation process Electrode A part or all of 1032 may be used as the drain electrode.

[0057] Note that the second through-hole 108 also penetrates the insulating layer 106 (similar to the first through-hole 107). The first through-hole 107 and the second through-hole 108 can be manufactured using the same etching process, contributing to further process reduction and reducing production costs.

[0058] As an option, Active layer 103 may be made of the same material for forming the second through-hole 108 and the same material for forming the first through-hole 107. In this way, the first through-hole 107 and the second through-hole 108 can be manufactured using the same deposition process, contributing to further process reduction and reducing production costs.

[0059] In some embodiments, as shown in FIG. 6, Active layer The main gate electrodes 105 are located on both sides of 103 and Back gate electrode 101 are respectively positioned, and the specific film layer structure of the transistor having a bottom gate structure is as follows. The main gate electrode 105 is connected to the substrate 200 and Active layeris located between 103 and Back gate electrode 101 is Active layer 103 is located on the side farther from the substrate 200. The transistor has an insulating layer 106, a first through-hole 107, and a second through-hole 108. The insulating layer 106 is Back gate electrode located on the side of 101 farther from the substrate 200. The bit line 20 is on the Back gate electrode side of 101 farther from it.

[0060] The first through-hole 107 penetrates through the insulating layer 106 and Back gate the medium layer 102 respectively, and is connected to the bit line 20 and the source Electrode 1031 respectively.

[0061] The second through-hole 108 penetrates through the insulating layer 106 and Back gate the medium layer 102, and Back gate electrode is connected to 101 and the drain Electrode 1032 respectively. In some embodiments, the word line 30 is provided in the same layer as the main gate electrode 105 and is located in a layer different from the bit line 20.

[0062] As shown in FIG. 6, in the memory 1 according to the present embodiment, the word line 30 and the bit line 20 are in different layers, which is advantageous for mutual insulation between them. The fact that the word line 30 is provided in the same layer as the main gate electrode 105 is advantageous for further process reduction, and further reduction of production costs becomes possible. In some embodiments, Active layer 103 includes at least one of materials such as metal oxide semiconductor, single crystal silicon, polycrystalline silicon, and amorphous silicon. Here, the metal oxide semiconductor includes at least one element among indium, gallium, zinc, tin, and tungsten.

[0063] In the memory 1 provided in the present embodiment, Active layer the material of 103 includes a metal oxide. Due to the inherent characteristics of the metal oxide semiconductor (factors such as low electron mobility),Active layer When a metal oxide is used as the material of 103, the leakage current of the transistor can be reduced. By reducing the speed at which charges are lost on the storage capacitor, the data retention time of Memory 1 can be extended. This is advantageous for reducing the refresh frequency and power consumption of Memory 1.

[0064] Specifically, the metal oxide material may be indium gallium zinc oxide (IGZO). When the metal oxide material is IGZO, the leakage current of the transistor is small (the leakage current is less than 10 -15 A), thereby ensuring a low refresh rate for Memory 1. Note that the metal oxide materials include ITO, IWO, ZnO x , InO x , In2O3, InWO, SnO2, TiO x , InSnO x , Zn x O y N z , Mg x Zn y O z , In x Zn y O z , In x Ga y Zn z O a , Zr x In y Zn z O a , Hf x In y Zn z O a , Sn x In y Zn z O a , Al x Sn y In z Zn a O d , Si x In y Zn z O a , Zn x Sn y O z , Alx Zn y Sn z O a 、Ga x Zn y Sn z O a 、Zr x Zn y Sn z O a Materials such as InGaSiO may also be used, as long as it is guaranteed that the leakage current of the transistor meets the requirements, and specifically, it is adjusted according to the actual situation.

[0065] In order to further improve the integration degree of Memory 1, Memory 1 may have a plurality of memory cells 10. However, in some embodiments, at least two memory cells 10 are stacked and arranged in a direction perpendicular to the substrate 200.

[0066] Alternatively, as shown in FIGS. 4 to 8, the memory 1 according to the present embodiment further includes a planarization layer 109 located on the side of the bit line 20 far from the substrate 200. By fabricating the upper memory cell group 101 on the planarization layer 109 of the lower memory cell group 100, the superposition of the memory cell groups 100 in the direction perpendicular to the substrate 200 becomes possible, and a high-density and high-integration memory 1 can be obtained. Back gate electrode 101, the superposition of the memory cell groups 100 in the direction perpendicular to the substrate 200 becomes possible, and a high-density and high-integration memory 1 can be obtained.

[0067] In some embodiments, at least two memory cells 10 are arranged in an array on one side of the substrate 200. Among at least two memory cells 10 in the same row, the main gate electrode 105 of the transistor is electrically connected to the same word line 30. Among at least two memory cells 10 in the same column, the source electrode of the transistor is electrically connected to the same bit line 20.

[0068] As shown in FIG. 4, the memory 1 according to this embodiment includes a substrate 200 on which a plurality of word lines 30, a plurality of bit lines 20, and a plurality of memory cells 10 are provided on the substrate 200 side. The plurality of memory cells 10 are divided into a plurality of memory cell groups 100 arranged in a direction perpendicular to the substrate 200. The memory cell group 100 includes a plurality of memory cells 10 arranged in a direction parallel to the substrate 200. Here, the gate electrodes of the transistors in each memory cell 10 in the same row are electrically connected to the same word line 30. The source electrodes of the transistors in each memory cell 10 in the same column are electrically connected to the same bit line 20.

[0069] In a specific implementation, according to specific storage capacity requirements and spatial constraints on the memory 1, different layouts, that is, adjusting the number of memory cell groups 100 and the number of memory cells 10 in each memory cell group 100 (including adjusting the number of memory cells 10 for each row and / or each column), a layout that realizes an optimized design of storage capacity and storage space can be selected.

[0070] Based on the same inventive concept, according to an embodiment of the present disclosure, as shown in FIG. 9, there is provided an electronic device 2 including the memory 1 of any of the above embodiments. Since the functions and effects of the memory 1 of the above embodiments are achieved, the description thereof is omitted.

[0071] Alternatively, the electronic device in the embodiment of the present disclosure may include a memory device, a smartphone, a computer, a tablet, an artificial smart device, a wearable device, or a mobile power supply, etc.

[0072] According to an embodiment of the present disclosure, based on the same inventive concept, as shown in FIG. 10, there is provided a method for manufacturing a memory 1 including the following steps S101 to S105.

[0073] In S101, on one side of the substrate, Back gate electrode , Back gate a medium layer, Active layer, top gateA medium layer, a main gate electrode, a word line connected to the main gate electrode, and an insulating layer are manufactured sequentially. Active layer is the source Electrode and Channel and the drain Electrode are sequentially connected.

[0074] In some embodiments, in step S101, on one side of the substrate, Back gate electrode, back gate the medium layer, Active layer, top gate Manufacturing the medium layer, the main gate electrode, the word line connected to the main gate electrode, and the insulating layer sequentially includes the following.

[0075] On one side of the substrate Back gate electrode is manufactured. Optionally, a first metal layer is formed, and by patterning this first metal layer, Back gate electrode 101 is formed. Back gate electrode And on the exposed substrate, Back gate the medium layer is manufactured. Optionally, the medium layer 102 may be manufactured by a full-surface coating method. Back gate

[0076] Back gate On the medium layer, Active layer of Channel the orthographic projection onto the substrate, and Active layer of the source Electrode the orthographic projection of the substrate, respectively Back gate electrode so as to partially overlap the orthographic projection onto the substrate of Active layer is formed. Optionally, Back gate after forming a metal oxide layer on the medium layer 102, this metal oxide layer is patterned to Active layer 103 may be formed. Active layer The source Electrode with respect to Electrode and the drain are made conductive.

[0077] In S102, the insulating layer and Top gate the medium layer are etched sequentially, Active layer of the source Electrode ​Obtain a first hole that exposes at least a part of . Step S104 is then executed.

[0078] In S103, the insulating layer, Top gate the dielectric layer, and Back gate the dielectric layer are etched sequentially to Active layer obtain a second hole that exposes at least a part of the drain of Electrode and a part of Back gate electrode . Step S104 is then executed.

[0079] In some embodiments, the insulating layer and Top gate the dielectric layer are etched sequentially to obtain a first hole that exposes at least a part of the source Electrode , and the insulating layer, Top gate the dielectric layer, and Back gate the dielectric layer are etched sequentially to obtain a second hole that exposes at least a part of the drain Electrode and a part of Back gate electrode , and these are performed synchronously. As a result, the first through-hole 107 and the second through-hole 108 can be manufactured using the same etching process, contributing to further process reduction and reducing production costs.

[0080] Note that the present disclosure does not limit the order of execution between step S102 and step S103, and step S102 may be executed first, or step S103 may be executed first.

[0081] In S104, a first via for connecting the source Electrode is formed in the first hole, and a second via for connecting Back gate electrode to the drain Electrode is formed in the second hole, respectively, by forming a conductive material in the first hole and the second hole. In some embodiments, the conductive materials in the first through-hole and the second through-hole may be the same metal material, for example, the same metal material. In S105, a bit line is formed on the first through-hole.

[0082] In some embodiments, this step S105 may include forming a third metal layer and patterning the third metal layer to form a plurality of bit lines 20 that are electrically connected to the first through hole 107 and the source electrode through the first through passage.

[0083] By going through the above steps S101 to S105, Active layer a memory using a top gate structure transistor in which a main gate electrode and Back gate electrode are respectively located on both sides of can be obtained.

[0084] Since the memory cell 10 in the memory according to this embodiment includes only one transistor, the number of film layers can be reduced, which is advantageous for reducing the number of processes and production costs. Data can be read and written simply by providing one transistor in the memory cell 10. There is no need to separately provide a transistor and a capacitive element, the configuration of the memory cell 10 is extremely simplified, which is advantageous for improving the integration degree and storage density of the dynamic memory.

[0085] According to an embodiment of the present disclosure, based on the same inventive concept, as shown in FIG. 11, as another method for manufacturing a memory, it includes the following steps S201 to S205.

[0086] In S201, on one surface of the substrate, a main gate electrode, a word line connected to the main gate electrode, Top gate a dielectric layer, Active layer, back gate a dielectric layer, Back gate electrode and an insulating layer are provided in this order, Active layer is formed by sequentially connecting the source Electrode, channel and the drain Electrode .

[0087] In some embodiments, in step S201, the main gate electrode, the word line connected to the main gate electrode, Top gate a dielectric layer, Active layer and Back gate a dielectric layer, Back gate electrodeManufacturing the insulating layer and others sequentially on one side of the substrate includes the following.

[0088] Manufacture a main gate electrode and a word line connected to the main gate electrode on one side of the substrate. Optionally, by depositing and patterning a second metal layer, form the main gate electrode and the word line connected to the main gate electrode.

[0089] Top gate The medium layer is manufactured on the main gate electrode, the word line connected to this main gate electrode, and the exposed substrate, and optionally, it can also be fabricated by an all-over coating process.

[0090] Channel of active layer such that the orthographic projection onto the substrate of Top gate is partially overlapped with the orthographic projection of the main gate electrode onto the substrate, Active layer manufacture Top gate on the medium layer. Optionally, Active layer after depositing a metal oxide layer on the medium layer, pattern this metal oxide layer to Source electrode and drain electrode of active layer is made conductive. Active layer , and the exposed Top gate manufacture a medium layer on the medium layer. Optionally, Back gate the medium layer may be fabricated by an all-over coating process. Back gate

[0091] Back gate Back gate electrode In the medium layer, Active layer such that the orthographic projection onto the substrate of Channel of Active layer the orthographic projection onto the substrate of the source of Electrode and Back gate electrode partially overlap respectively, Back gate electrode is manufactured. Optionally, 101 is formed by manufacturing a first metal layer and patterning this first metal layer.

[0092] Back gate In S202, the insulating layer and Back gateEtch the dielectric layer sequentially to obtain a first hole that exposes at least a part of the source Electrode Thereafter, step S204 is executed.

[0093] In S203, the insulating layer and Back gate the dielectric layer are etched sequentially to Back gate electrode and drain Electrode to obtain a second hole that exposes at least a part thereof. Thereafter, step S204 is executed.

[0094] In some embodiments, etching the insulating layer and Back gate the dielectric layer sequentially to expose at least a part of the source Electrode and etching the insulating layer and Back gate the dielectric layer sequentially to Back gate electrode and drain Electrode are performed synchronously to expose at least a part thereof. As a result, the first through hole 107 and the second through hole 108 can be manufactured using the same etching process, contributing to further process reduction and reducing production costs.

[0095] Note that the present disclosure does not limit the order of execution between step S202 and step S203, and step S202 may be executed first, or step S203 may be executed first.

[0096] In S204, a first via for connecting the source Electrode is formed in the first hole, and Back gate electrode and a second via for connecting to the drain Electrode are formed in the second hole, respectively, and a conductive material is formed in the first hole and the second hole. In some aspects, the conductive materials in the first hole and the second hole may be the same metal material, for example, the same metal material. In S205, a bit line is formed on the first through hole.

[0097] In some embodiments, this step S 205A third metal layer may be manufactured and patterned to form a plurality of bit lines 20 electrically connected to the first through hole 107 and the source electrode through the first through path.

[0098] After the above steps S201 to S205, a transistor having a bottom gate structure can be fabricated, and another memory disposed on both sides of the main gate electrode and Back gate electrode and Active layer can be manufactured.

[0099] For ease of understanding, the specific manufacturing method of the memory for fabricating a memory adopting a top gate structure in this embodiment includes steps S301 to S310. In S301, a substrate 200 is supplied, and a buffer layer 300 is formed on the substrate 200. The film layer structure after this step S301 is shown in FIG. 12. In S302, a plurality of Back gate electrode 101 are formed on the substrate 200 by a patterning process, and the film layer structure after this step S302 is shown in FIG. 13. In S303, Back gate electrode a medium layer 102 is formed on Back gate 101, and the film layer structure after this step S303 is shown in FIG. 14.

[0100] In S304, Back gate a metal oxide is deposited as Active layer 103 on the medium layer 102, and the orthographic projection of Active layer in Channel onto the substrate, and the orthographic projection of Active layer the source in Electrode onto the substrate are each partially overlapped with the orthographic projection of Back gate electrode onto the substrate. The film layer structure after this step S304 is shown in FIG. 15. In S305, Active layer a medium layer 104 is formed on Top gate 103, and the film layer structure after this step S305 is shown in FIG. 16.

[0101] In S306, Top gateOn the medium layer 104, a plurality of main gate electrodes 105 and a word line 30 connected to the main gate electrode 105 are formed by patterning. The film layer configuration after this step S306 is shown in FIG. 17. In S307, an insulating layer 106 is formed on the main gate electrode 105, and the film layer structure after this step S307 is shown in FIG. 18.

[0102] In S308, a first through hole 107 penetrating the insulating layer 106 and Top gate the medium layer 104, and a drain electrode of a second through hole 108 penetrating the insulating layer 106, Top gate the medium layer 104, Active layer 103 and Back gate the medium layer 102 are formed. The film layer configuration after this step S308 is shown in FIG. 19.

[0103] In S309, a plurality of bit lines 20 are formed by a patterning process, and the bit lines 20 are electrically connected to the Active layer source electrode through the first through hole 107. The configuration of the film layer after this step S309 is shown in FIG. 20. In S310, a planarization layer 109 is formed on the side of the bit line 20 far from the substrate 200. The film layer configuration after this step S310 is shown in FIG. 21.

[0104] Note that by repeating steps S302 to S310 on the planarization layer 109, a dynamic memory including a plurality of memory cells stacked in a direction perpendicular to the substrate is obtained. Here, when forming the lowermost memory cell, a plurality of Back gate electrode 101 are formed by a patterning process on the buffer layer 300, and when forming other memory cells, a plurality of Back gate electrode 101 are formed by a patterning process on the planarization layer 109 of the next-layer memory cell.

[0105] The read / write method according to an embodiment of the present disclosure is a read / write method for performing read / write of the memory in each of the above embodiments based on the same inventive concept, and includes T1 - T2.

[0106] At T1, in the writing state, a first level is applied via the word line 30 to the main gate electrode 105 of the memory cell 10 to be written, turning on the transistor, and a memory signal is transferred via the bit line 20 to the source electrode of the memory cell 10 to be written, and the memory signal is written as stored data in the memory cell 10 to be written.

[0107] When the dynamic memory is in the write operation mode, a first level (for example, 5V, and the specific value can be adjusted according to the actual situation) is applied via the word line 30 to the main gate electrode 105 so that the transistor is in the on state, and the magnitude of the first level is related to factors such as the structure of the transistor and the material of 103 in the transistor, and specifically can be adjusted according to the actual situation. Active layer 103 and is specifically adjustable according to the actual situation.

[0108] When the transistor is turned on, based on the externally input data, a voltage is applied to the source electrode via the bit line 20, and the source electrode and the drain electrode are Active layer conducted through 103, and the drain electrode and Back gate electrode 101 are electrically connected. Therefore, the magnitudes of the voltages at the source electrode and the drain electrode are Back gate electrode the same as the magnitude of the voltage at 101 (the potentials of the drain electrode and Back gate electrode 101 are the same). Back gate electrode The node capacitance between 101 and the drain electrode constitutes the storage capacitance of the memory cell 10, Back gate electrode and the magnitude of the charge amount in the storage capacitance is determined by the high or low voltage at 101, and further, whether the binary number of the data signal stored in the memory cell 10 is 0 or 1 is determined. When a high voltage (for example, 5V) is applied to the source electrode via the bit line 20, data "1" is written into the memory cell 10, and when a low voltage (for example, 0V) is applied to the source electrode via the bit line 20, data "0" is written into the memory cell 10.

[0109] At T2, in the read state, by applying a second level to the main gate electrode 105 of the memory cell 10 to be read via the word line 30, the stored data of the memory cell 10 to be read is sensed on the bit line 20.

[0110] When the dynamic memory is in the read operation mode, a second level is applied to the main gate electrode 105 via the word line 30, a voltage difference is generated between the main gate electrode 105 and the source electrode, and the magnitude of the current on the bit line 20 (i.e., the output current of the transistor) is detected, thereby realizing data reading.

[0111] Specifically, when data "1" is stored in front of the memory cell 10, Back gate electrode the potential of the 101 and the drain electrode is high, and due to the combined action of the first level and the second level, the transistor is in the on state, so a clear current is measured via the bit line 20. When a clear current is measured, it is determined that the read data is "1". When data "0" is stored in front of the memory cell 10, Back gate electrode the potential on the 101 and the drain electrode is low, and even after the second level is applied to the main gate electrode 105, the transistor is in the off state, so the current measured by the bit line 2032 is very weak, and at this time it is determined that the read data is "0".

[0112] Note that the magnitude of the threshold voltage of the transistor Back gate electrode is correlated with the magnitude of the potential on the 101 and the drain electrode. For an N-type field-effect transistor (when the transistor is on, the carrier is an electron), Back gate electrode the higher the potential on the 101 and the drain electrode, the smaller the threshold voltage, that is, even when the differential pressure between the main gate electrode 105 and the source electrode is small, the transistor is turned on. Back gate electrode The lower the potential on the 101 and the drain electrode, the larger the threshold voltage.

[0113] As shown in FIG. 21, the horizontal axis in FIG. 21 is the voltage applied to the main gate electrode 105 (i.e., the second level), and the vertical axis is the output current of the transistor. When the second level applied to the main gate electrode 105 is a specific value (the position of the dotted line in FIG. 21), Back gate electrode The high or low voltage at 101 and the drain electrode (i.e., whether the data written by the transistor is "1" or "0") has a significant difference in the magnitude of the output current of the transistor (i.e., the current measured through the bit line 20). Reading data from the memory cell 10 can be realized by detecting the current on the bit line 20. When the transistor writes the data "1", since the output current of the transistor is large, the read data is also "1". When the data written by the transistor is "0", since the output current of the transistor is extremely weak, the read data is also "0".

[0114] The value of the second level can be determined by the parameters of the transistor and the magnitude of the voltage applied to 101 and the drain electrode during the write operation. Note that the numerical value of the second level needs to be appropriate (necessary between the threshold voltage when the transistor stores "1" and the threshold voltage when the transistor stores "0"). If the value of the second level is not appropriate, when storing data "1" (i.e., the potential on the drain electrode and Back gate electrode 101 is high), the output current of the transistor and when storing data "0" (i.e., the potential on the drain electrode and Back gate electrode 101 is low), the magnitudes of the output currents of the transistor become very close. Therefore, when the read operation is performed, it becomes difficult to determine whether the read data is "0" or "1", which affects the performance of the dynamic memory. The optimal value of the second level can be obtained through experiments or simulations so that the difference in the output current when the transistor is read in different states is maximized, and the read performance can be improved. Back gate electrode 101 is low). By applying the embodiments of the present disclosure, at least the following effects can be achieved.

[0115] 1. The memory cell according to the present disclosure, the transistor includes a main gate electrode capable of realizing conductivity control for Active layer and is further provided with a back gate electrode for providing conductivity control for Active layer . When this Back gate electrode is electrically connected to the drain electrode, Back gate electrode a fixed potential synchronized with the drain electrode can be obtained, and this fixed potential provides supplementary control for Active layer . Also, Back gate electrode since it is not electrically connected to the source electrode, it can function as a negative bias of the threshold voltage in the readout stage. The performance of the transistor can be improved, and the read / write performance of the memory can be optimized.

[0116] 2. Regarding the improvement of read and write performance by connecting the back gate electrode to the drain electrode, the back gate electrode is not connected to any electrode other than the drain electrode, is on the other side of the active layer but is located on both sides of the active layer with respect to the main gate electrode. Since the back gate electrode of the present application is not a floating gate electrode, a fixed potential is required, but the potential must be synchronized with the drain electrode, and it is suitable for the read and write scenes of the memory. The back gate electrode of the present application is not connected to the source electrode. This back gate electrode acts as a negative bias of Vth in the read stage.

[0117] 3 . The memory cell according to the present disclosure Back gate electrode is provided with a capacitive memory structure formed between Back gate electrode and the first electrode, can realize data writing, and can improve the problem of current leakage when the transistor is in the off state. Using 4 as a part of the capacitive memory structure is advantageous for making the integration degree of the device relatively high. 4 . In the memory cell according to the present disclosure, the source electrode of the transistor is used as another part of the capacitive memory structure, Back gate electrode cooperates with

[0118] to realize data writing, and further increases the integration degree of the memory. That is, data reading and writing can be realized only by providing one transistor in the memory cell of the memory, without the need to separately provide a transistor and a capacitive element, which simplifies the configuration of the memory cell extremely and is advantageous for improving the integration degree and storage density of the memory.It should be understood by those skilled in the art that the steps, measures, and solutions in various operations, methods, and flows contemplated in this disclosure can be alternated, changed, combined, or deleted. Furthermore, those including other steps, measures, and solutions in various operations, methods, and flows contemplated in this disclosure can be alternated, changed, rearranged, disassembled, combined, or deleted. Also, those including the steps, measures, and solutions in various operations, methods, and flows disclosed in this disclosure in the prior art can be alternated, changed, rearranged, disassembled, combined, or deleted.

[0119] In the description of this disclosure, the directions or positional relationships indicated by terms such as "upper", "lower", "vertical", "horizontal", etc. are based on the exemplary directions or positional relationships shown in the drawings, and are for the purpose of conveniently or briefly explaining the embodiments of this disclosure, and do not necessarily mean that the devices or members pointed to must be configured and operate in a specific direction or a specific orientation, and should not be understood as limiting this disclosure.

[0120] It should be understood that the terms "first" and "second" are only used to explain the purpose, and do not mean to indicate relative importance, suggest, or indicate the number of technical features shown. Thus, the features defined by "first" and "second" may explicitly or implicitly include one or more features. In this disclosure, the meaning of "plural" means two or more unless otherwise specified.

[0121] In the description of this disclosure, the terms "implementation", "related", and "connection" should be understood in a broad sense unless specifically defined and limited. For example, it may be a fixed connection, a removable connection, an integrally connected one, a directly connected one, an indirectly connected one through an intermediate medium, or a communication inside two elements. The above terms are specifically understood by those skilled in the art as the specific meanings in this disclosure. In the description of this specification, specific features, structures, materials, or characteristics may be appropriately combined in any one or more embodiments or examples.

[0122] It should be understood that each step in the flowchart of the drawings is sequentially displayed according to the indication of the arrow, but the execution order of these steps is not limited to the order indicated by the arrow. In some implementation scenarios of an embodiment of the present disclosure, the steps in each flow may be executed in other orders as needed, unless explicitly described in this document. In addition, a part or all of each flowchart may include a plurality of sub-steps or a plurality of steps based on the actual implementation scenario. Some or all of these sub-steps or phases may be executed at the same timing, or may be executed at different timings, and may be executed in scenarios with different execution times. The execution order of these sub-steps or phases can be flexibly configured according to needs, but the embodiments of the present disclosure do not limit this.

[0123] The above are only some embodiments of the present disclosure. Without departing from the technical idea of the present disclosure, it should be pointed out that for those of ordinary skill in the technical field, adopting other similar implementation modes based on the technical idea of the present disclosure also belongs to the protection scope of the embodiments of the present disclosure.

Description of Reference Numerals

[0124] 10… Memory cell, 101… Back gate electrode 、102… Back gate Medium layer, 103… Active layer 、1031… Source Electrode 、1032… Drain Electrode 、1033… Channel 、104… Top gate Medium layer, 105… Main gate electrode, 106… Insulating layer, 107… First through hole, 108… Second through hole, 109… Planarization layer, 110… First electrode, 20… Bit line, 30… Word line, 100… Memory cell group, 200… Substrate, 300… Buffer layer, 1… Memory, 2… Electronic device

Claims

1. A memory having a substrate, a word line, a bit line, and a memory cell on one side of the substrate, The memory cell includes only one transistor, The transistor includes An active layer including a source electrode, a drain electrode, and a channel located between the source electrode and the drain electrode, A main gate electrode electrically connected to the word line, A source electrode electrically connected to the bit line and the channel respectively, A drain electrode electrically connected to the channel, A back gate electrode electrically connected to the drain electrode, and includes The orthographic projection of the main gate electrode onto the substrate covers the orthographic projection of the channel onto the substrate, The orthographic projection of the back gate electrode onto the substrate overlaps with the orthographic projection of the active layer onto the substrate, a dynamic memory.

2. The memory cell further has a memory structure, the memory structure includes a back gate electrode, In the writing state, the storage capacitance stores data of "1" or "0", and in the reading state, according to the magnitude of the current on the bit line, it is determined to store "1" or "0". The dynamic memory according to claim 1, wherein the node capacitance between the back gate electrode and the drain electrode is used as the storage capacitance of the memory cell.

3. The main gate electrode is located on the side far from the substrate of the active layer, and The main gate electrode and the back gate electrode are respectively located on opposite sides of the active layer. The dynamic memory according to claim 2.

4. The memory structure further includes a source electrode, and the storage capacitance is formed between the back gate electrode and the source electrode, The orthographic projection of the source electrode onto the substrate and the orthographic projection of the back gate electrode onto the substrate partially overlap, the dynamic memory according to claim 1.

5. The main gate electrode is located on the side of the active layer far from the substrate, The back gate electrode is located between the substrate and the active layer, The source electrode and the drain electrode are located on the side of the back gate electrode far from the substrate, the dynamic memory according to claim 4.

6. The transistor further includes, A top gate dielectric layer located between the active layer and the main gate electrode, and A back gate dielectric layer located between the back gate electrode and the active layer and between the back gate electrode and the source electrode, and the orthographic projection of the source electrode onto the substrate and the orthographic projection of the back gate electrode onto the substrate partially overlap, the dynamic memory according to claim 1.

7. The main gate electrode is located on the side of the active layer far from the substrate, The back gate electrode is located between the substrate and the active layer, The transistor includes an insulating layer, a first through hole, and a second through hole, The insulating layer is located on the side of the main gate electrode far from the substrate, The bit line is located on the side of the insulating layer far from the main gate electrode, The first through hole penetrates the insulating layer and the top gate dielectric layer respectively, and is connected to the bit line and the source electrode respectively, The second through hole penetrates the insulating layer, the top gate dielectric layer, and the back gate dielectric layer respectively, and is connected to the drain electrode and the back gate electrode respectively, the dynamic memory according to claim 6.

8. The dynamic memory according to claim 1, wherein a part of the orthographic projection of the back gate electrode on the substrate is located outside the orthographic projections of the source electrode, the drain electrode, and the channel on the substrate, and this part is electrically connected to the drain electrode.

9. The dynamic memory according to claim 1, wherein the word line is provided in the same layer as the main gate electrode and is in a different layer from the bit line.

10. The active layer includes a metal oxide semiconductor, The dynamic memory according to claim 1, wherein the metal oxide semiconductor includes indium gallium zinc oxide.

11. A plurality of the memory cells are stacked and arranged in a direction perpendicular to the substrate, and a plurality of the memory cells are arrayed on one side of the substrate. In each of the memory cells in the same row, the main gate electrode of the transistor is electrically connected to the same word line, and in each of the memory cells in the same column, the source electrode of the transistor is electrically connected to the same bit line. The dynamic memory according to claim 1.

12. A dynamic memory device comprising the memory according to claim 1.

13. On one side of the substrate, a memory cell including only one transistor is formed. The forming includes sequentially fabricating a back gate electrode, a back gate dielectric layer, an active layer, a top gate dielectric layer, a main gate electrode, a word line connected to the main gate electrode, and an insulating layer. The active layer is formed by sequentially connecting a source electrode, a channel, and a drain electrode, The insulating layer and the top gate dielectric layer are sequentially etched to obtain a first hole, The insulating layer, the top gate dielectric layer, and the back gate dielectric layer are sequentially etched to obtain a second hole, A first via for connecting the source electrode is formed in the first hole, and a via material is deposited in each of the first hole and the second hole such that a second via for connecting the back gate electrode and the drain electrode is formed in the second hole. A method of manufacturing a dynamic memory, in which a bit line is formed on the first via so as to electrically connect the source electrode and the bit line.

14. The memory cell further has a memory structure, and the memory structure includes a back gate electrode. The method of manufacturing a dynamic memory according to claim 13, wherein, in a writing state, data of "1" or "0" is stored in the storage capacitance, and in a reading state, it is determined to store "1" or "0" according to the magnitude of the current on the bit line, and the node capacitance between the back gate electrode and the drain electrode is used as the storage capacitance of the memory cell.

15. On one side of the substrate, a back gate electrode, a back gate dielectric layer, an active layer, a top gate dielectric layer, a main gate electrode, a word line connected to the main gate electrode, and an insulating layer are sequentially formed. The back gate electrode is formed on one side of the substrate. The back gate dielectric layer is formed on the back gate electrode and the exposed substrate. The active layer is formed on the back gate dielectric layer such that a front projection of a channel of the active layer onto the substrate and a front projection of a source electrode of the active layer onto the substrate each partially overlap a front projection portion of the back gate electrode onto the substrate. The method of manufacturing a dynamic memory according to claim 13, wherein the source electrode and the drain electrode of the active layer are made conductive.

16. Etching the insulating layer and the top gate dielectric layer sequentially to obtain a first hole exposing at least a part of the source electrode, and etching the insulating layer, the top gate dielectric layer, and the back gate dielectric layer sequentially to obtain a second hole exposing at least a part of the drain electrode of the active layer and a part of the back gate electrode are performed synchronously. The method for manufacturing a dynamic memory according to claim 13.

17. An electronic device including the dynamic memory according to claim 1.

Images