Semiconductor memory device and its manufacturing method, reading and writing method, electronic device, and memory circuit

Abstract

According to the embodiments of the present disclosure, a semiconductor memory device, a manufacturing method thereof, a read / write method, an electronic device, and a memory circuit are provided. [Solution] A transistor is provided for each memory cell in a semiconductor memory device, a gate and an auxiliary electrode are provided for the transistor, and the auxiliary electrode is electrically connected to the drain. During a write operation, a first voltage is applied to the gate via a word line, and then an electrical signal is applied to the source via a bit line based on external input data. During a read operation, a second voltage (the magnitude of the second voltage is between the threshold voltage when the transistor stores "1" and the threshold voltage when the transistor stores "0") is applied to the auxiliary electrode via the word line by utilizing the effect of the voltage on the auxiliary electrode on the threshold voltage of the transistor, and then the magnitude of the output current of the field effect transistor is detected to read data.

Description

[Technical field]

[0001] The present disclosure relates to the technical field of semiconductor devices, and in particular to a semiconductor memory device and a manufacturing method thereof, a read / write method, electronic equipment, and a memory circuit. [Background technology]

[0002] This application claims priority to a Chinese patent application with application number 202210351841.1 filed with the State Intellectual Property Office on April 2, 2022, the entire contents of which are incorporated herein by reference.

[0003] Dynamic Random Access Memory (DRAM) is a semiconductor memory device that has the advantages of simple structure, low manufacturing costs, and high capacity density compared to static semiconductor memory devices. As technology advances, the applications of DRAM semiconductor memory devices are becoming more and more widespread. However, conventional DRAM semiconductor memory devices have the drawbacks of being complicated in structure and low in integration, which limits the application of DRAM semiconductor memory devices. Summary of the Invention [Problem to be solved by the invention]

[0004] The present disclosure provides a semiconductor memory device, a manufacturing method thereof, a read / write method, electronic equipment, and a memory circuit, which aim to reduce leakage current that may occur in a read / write state while ensuring high integration of the device, thereby compacting the structure of the semiconductor memory device and improving memory performance. [Means for solving the problem]

[0005] According to one embodiment of the present disclosure, a semiconductor memory device is provided that includes a substrate and a plurality of memory cells provided on the substrate, the memory cells including transistors, bit lines, and word lines, in which the transistor includes a drain provided on the substrate, a gate provided above the drain, insulated from the drain, and electrically connected to the word line, an auxiliary electrode provided above the drain and surrounding an outer wall of the gate, insulated from the gate, does not overlap with the gate in a first direction perpendicular to an upper surface of the substrate, and is electrically connected to the drain, a semiconductor layer that surrounds the gate, is insulated from the gate and the auxiliary electrode, and is electrically connected to the drain, and a source provided above the auxiliary electrode and surrounding the outer wall of the gate, is electrically connected to the semiconductor layer and the bit line, and is insulated from the gate and the auxiliary electrode. In one embodiment, the auxiliary electrode may at least partially overlap the source in the first direction. In one embodiment, the auxiliary electrode may at least partially overlap the drain in the first direction. In one embodiment, an orthogonal projection of an outer wall of the auxiliary electrode onto a plane parallel to the top surface of the substrate may be located outside an orthogonal projection of the source onto said plane and within an orthogonal projection of the drain onto said plane. In one embodiment, the semiconductor layer may be provided between the gate and the auxiliary electrode. In one embodiment, the semiconductor device may further include a conductive connecting member, and the auxiliary electrode may be electrically connected to the drain via the conductive connecting member. In one embodiment, the conductive connecting member may surround the auxiliary electrode. In an embodiment, the semiconductor layer may include a single crystal semiconductor material, a polycrystalline semiconductor material, or a metal oxide semiconductor. In one embodiment, the metal oxide semiconductor may include at least one of In, Ga, Zn, Sn, and W. In one embodiment, the memory cell array includes a plurality of array modules that are stacked and arranged, and the array module includes a plurality of the memory cells arranged in an array, and the gates of the transistors in each row are all connected to one of the word lines, and the sources of the transistors in each column are all connected to one of the bit lines.

[0006] According to another embodiment of the present disclosure, there is provided a semiconductor memory device including: a pillar-shaped gate provided on a substrate, extending in a first direction perpendicular to an upper surface of the substrate, and electrically connected to a word line; a semiconductor layer at least partially surrounding a sidewall of the gate; a source provided to surround an outer wall of the semiconductor layer, electrically connected to the semiconductor layer, and electrically connected to a bit line; a drain provided at a lower part of the semiconductor layer, electrically connected to the semiconductor layer, and spaced apart from the source in the first direction; a first insulating layer provided between the gate and the semiconductor layer and between the gate and the drain; an auxiliary electrode provided to surround the outer wall of the semiconductor layer between the source and the drain in the first direction; and a second insulating layer located between the auxiliary electrode and the semiconductor layer and between the auxiliary electrode and the source so as to insulate the auxiliary electrode from both the semiconductor layer and the source. In one embodiment, the auxiliary electrode may extend from the source towards the drain in the first direction. In one embodiment, the auxiliary electrode may at least partially overlap the drain in the first direction. In one embodiment, an orthogonal projection of an outer wall of the auxiliary electrode onto a plane parallel to the top surface of the substrate may be located outside an orthogonal projection of the source onto the plane and within an orthogonal projection of the drain onto the plane. In one embodiment, the semiconductor layer may be formed in a U-shape to surround the sidewalls and a bottom surface of the gate, and the first insulating layer may be formed in a U-shape between the semiconductor layer and the gate to insulate the semiconductor layer from the gate. In one embodiment, the drain may be disposed to surround and contact a lower portion of the outer sidewall of the semiconductor layer. In one embodiment, the drain may be located between the substrate and the semiconductor layer and contact a bottom surface of the semiconductor layer. In one embodiment, the drain includes a first portion located between the substrate and the semiconductor layer and a second portion extending outward from the first portion in a second direction parallel to the top surface of the substrate, and the second portion of the drain can at least partially overlap the auxiliary electrode in the first direction. In one embodiment, the second portion of the drain may directly contact the auxiliary electrode. In one embodiment, the auxiliary electrode can be separated from the second portion of the drain in the first direction via the second insulating layer, and can be electrically connected to the second portion of the drain via a conductive connecting member. In one embodiment, the conductive connection member may annularly surround the outer wall of the semiconductor layer and extend in the first direction to connect to the second portion of the drain. In one embodiment, an orthogonal projection of the conductive connecting member onto a plane parallel to the top surface of the substrate may lie within an orthogonal projection of the auxiliary electrode onto the plane. In one embodiment, the conductive connection member electrically connects a portion of the outer wall of the auxiliary electrode and an end of the second portion of the drain, and an orthogonal projection of the conductive connection member onto a plane parallel to the top surface of the substrate can be located outside the orthogonal projection of the auxiliary electrode onto the plane. In one embodiment, the word line and the bit line may both be located above the gate and may be insulated from each other by different layers. In one embodiment, the source and auxiliary electrodes may at least partially overlap in the first direction. In one embodiment, the light emitting device may further include an additional electrode at least partially overlapping the auxiliary electrode in the first direction.

[0007] According to another embodiment of the present disclosure, there is provided a memory circuit comprising a gate, an auxiliary electrode, a source, a drain, a word line, and a bit line, wherein the gate is electrically connected to the word line, the source is electrically connected to the bit line, the drain is electrically connected to the auxiliary electrode, the gate and the auxiliary electrode are insulated from each other, the gate is insulated from the source and the drain, respectively, the auxiliary electrode is insulated from the source and the drain, respectively, and a node capacitance between the auxiliary electrode and the drain constitutes a storage capacitance.

[0008] According to another embodiment of the present disclosure, there is provided an electronic device including the semiconductor memory device.

[0009] According to another embodiment of the present disclosure, there is provided a method for manufacturing a semiconductor memory device, including: providing a substrate; forming a drain above the substrate by a patterning process; sequentially forming a source, a semiconductor layer and a gate on the drain; and forming an auxiliary electrode and a conductive connection member above the drain, wherein the auxiliary electrode does not overlap with the gate in a first direction perpendicular to an upper surface of the substrate, and the conductive connection member is electrically connected to the auxiliary electrode and the drain, respectively.

[0010] In one embodiment, sequentially forming a source, a semiconductor layer, and a gate above the drain may include forming a sacrificial layer above the drain, the sacrificial layer covering the drain, forming a source above the sacrificial layer by a patterning process, forming a first medium layer on the source, the first medium layer covering the source and the drain, opening a through hole sequentially penetrating the first medium layer, the source, and the sacrificial layer, the drain being exposed at a bottom of the through hole and the source being exposed at a hole wall of the through hole, and sequentially forming a semiconductor layer, a first insulating layer, and a gate within the through hole, the semiconductor layer being electrically connected to the source and the drain, respectively.

[0011] In one embodiment, forming an auxiliary electrode and a conductive connecting member on the side of the drain farther from the substrate may include removing a portion of the first medium layer and the sacrificial layer by a patterning process to expose both ends of the drain; removing the remaining sacrificial layer to expose the drain, the source and the semiconductor layer and form a receiving space; forming a second insulating layer by deposition, the second insulating layer covering the exposed semiconductor layer, the source and the drain; forming an auxiliary electrode on the second insulating layer by deposition, filling the receiving space with the auxiliary electrode; and forming a conductive connecting member on both ends of the drain exposed by deposition, and connecting the conductive connecting member to the drain and the auxiliary electrode, respectively.

[0012] In one embodiment, after forming an auxiliary electrode and a conductive connecting member on the side of the drain farther from the substrate, the method further includes forming a word line by a turning process, electrically connecting the word line and the gate, and forming a bit line by a patterning process, electrically connecting the bit line and the source.

[0013] According to another embodiment of the present disclosure, there is provided a method for reading and writing the semiconductor memory device, in which, in a write state, a word line applies a first voltage to the gate to turn on the transistor, and a bit line applies a data signal to the source, and the data signal is stored in a storage capacitor connected to the drain and the auxiliary electrode by the on transistor, and in a read state, the word line applies a second voltage to the gate, and the bit line measures a current at the source to read out the data signal.

[0014] The semiconductor memory device according to the present disclosure provides the following advantages.

[0015] In the semiconductor memory device of the present disclosure, one transistor is provided in each memory cell, the transistor is provided with a gate and an auxiliary electrode, and the auxiliary electrode is electrically connected to the drain. When performing a write operation, a first voltage is applied to the gate via a word line, and then an electric signal is applied to the source via a bit line based on external input data, the source transmits the electric signal to the drain, and the drain transmits the electric signal to the auxiliary electrode, and the node capacitor between the auxiliary electrode and the drain is used as the memory capacitor of the memory cell, thereby realizing data writing. When performing a read operation, a second voltage (the magnitude of the second voltage is between the threshold voltage when the transistor stores "1" and the threshold voltage when the transistor stores "0") is applied to the auxiliary electrode via the word line by utilizing the effect of the voltage on the auxiliary electrode on the threshold voltage of the transistor, and then data reading is realized by detecting the magnitude of the output current of the transistor. Therefore, data reading and writing can be realized by simply providing one transistor in the memory cell, and there is no need to provide a separate transistor and capacitor element, which greatly simplifies the structure of the memory cell and is advantageous for improving the integration degree and memory density of the semiconductor memory device. [Brief description of the drawings]

[0016] The above and / or additional aspects and advantages of the present disclosure will become apparent and will be more readily understood from the following detailed description of the embodiments with reference to the drawings, in which: [Figure 1] 1 is a schematic cross-sectional view of a memory cell of a semiconductor memory device according to an embodiment of the present disclosure; [Diagram 2] 1 is a schematic planar structure diagram of a memory cell of a semiconductor memory device according to an embodiment of the present disclosure; [Diagram 3] 1 is a schematic cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure; [Figure 4] FIG. 2 is a structural schematic diagram of a memory circuit according to an embodiment of the present disclosure; [Diagram 5] FIG. 2 is a schematic diagram of a circuit structure of a semiconductor memory device according to an embodiment of the present disclosure; [Figure 6]11 is a graph showing transfer characteristics of a transistor of a semiconductor memory device when different data are written. [Figure 7] 1 is a schematic flowchart of a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure. [Figure 8a] 1A to 1C are structural schematic diagrams of different processes for manufacturing a semiconductor memory device according to an embodiment of the present disclosure. [Figure 8b] 1A to 1C are structural schematic diagrams of different processes for manufacturing a semiconductor memory device according to an embodiment of the present disclosure. [Figure 8c] 1A to 1C are structural schematic diagrams of different processes for manufacturing a semiconductor memory device according to an embodiment of the present disclosure. [Figure 8d] 1A to 1C are structural schematic diagrams of different processes for manufacturing a semiconductor memory device according to an embodiment of the present disclosure. [Figure 8e] 1A to 1C are structural schematic diagrams of different processes for manufacturing a semiconductor memory device according to an embodiment of the present disclosure. [Figure 8f] 1A to 1C are structural schematic diagrams of different processes for manufacturing a semiconductor memory device according to an embodiment of the present disclosure. [Figure 8g] 1A to 1C are structural schematic diagrams of different processes for manufacturing a semiconductor memory device according to an embodiment of the present disclosure. [Figure 8h] 1A to 1C are structural schematic diagrams of different processes for manufacturing a semiconductor memory device according to an embodiment of the present disclosure. [Figure 8i] 1A to 1C are structural schematic diagrams of different processes for manufacturing a semiconductor memory device according to an embodiment of the present disclosure. [Figure 8j] 1A to 1C are structural schematic diagrams of different processes for manufacturing a semiconductor memory device according to an embodiment of the present disclosure. [Figure 8k] 1A to 1C are structural schematic diagrams of different processes for manufacturing a semiconductor memory device according to an embodiment of the present disclosure. [Figure 8l] 1A to 1C are structural schematic diagrams of different processes for manufacturing a semiconductor memory device according to an embodiment of the present disclosure. [Figure 8m] 1A to 1C are structural schematic diagrams of different processes for manufacturing a semiconductor memory device according to an embodiment of the present disclosure. [Figure 8n]1A to 1C are structural schematic diagrams of different processes for manufacturing a semiconductor memory device according to an embodiment of the present disclosure. [Figure 8o] 1A to 1C are structural schematic diagrams of different processes for manufacturing a semiconductor memory device according to an embodiment of the present disclosure. [Figure 8p] 1A to 1C are structural schematic diagrams of different processes for manufacturing a semiconductor memory device according to an embodiment of the present disclosure. [Figure 8q] 1A to 1C are structural schematic diagrams of different processes for manufacturing a semiconductor memory device according to an embodiment of the present disclosure. [Figure 8r] 1A to 1C are structural schematic diagrams of different processes for manufacturing a semiconductor memory device according to an embodiment of the present disclosure. [Figure 8s] 1A to 1C are structural schematic diagrams of different processes for manufacturing a semiconductor memory device according to an embodiment of the present disclosure. [Figure 9] 1 is a flowchart of a method for reading and writing to a semiconductor memory device according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] The present disclosure will be described in detail below, and examples of the embodiments of the present disclosure will be shown in the drawings, in which the same or similar reference numerals indicate the same or similar components or components having the same or similar functions. In addition, when a detailed description of the known technology is unnecessary for the illustrated features of the present invention, the description will be omitted. The embodiments described below with reference to the drawings are illustrative and are merely for the purpose of explaining the present disclosure, and do not limit the present disclosure.

[0018] Those skilled in the art will appreciate that the singular forms "a," "one," "said," and "the" as used herein may include the plural, unless otherwise specified. It is further understood that the term "comprising" as used in the specification of this disclosure means the presence of features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. When an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or intermediate elements may be present. Furthermore, "connected" or "coupled" as used herein may include wireless connections or couplings. The term "and / or" as used herein includes all or any units and all combinations of one or more associated listed items.

[0019] The inventor of the present disclosure considered that a memory cell in a conventional DRAM semiconductor memory device usually includes a transistor and a capacitor, and its main operating principle is to store electric charge by the capacitor and determine whether one binary bit is 1 or 0 according to the number of electric charges stored in the capacitor. In a memory cell configured with a transistor / capacitor (1T / 1C), the capacitor C is used to store electric charges representing the numbers "1" and "0" for the transistor to perform write and read operations. In a memory cell adopting a 1T / 1C configuration, the drain current becomes large, which may affect the memory performance of the memory cell. In addition, in order to improve the data storage time and reduce the refresh rate, a capacitor with a large capacitance value is usually required, so that the area of ​​the electrode of the capacitor is usually increased to increase the capacitance value of the capacitor, thereby increasing the area occupied by the memory cell on the substrate and reducing the integration degree of the semiconductor memory device.

[0020] Conventionally, in order to improve the integration level of semiconductor memory devices, there is a method of providing two transistors / zero capacitors in a memory cell (2T / 0C), that is, a method of using the gate capacitance of one of the two transistors as a storage capacitance. However, in semiconductor memory devices arranged in the 2T / 0C method, the structure of the memory cell is still not compact, and there is room for further improvement in the integration level and memory density of semiconductor memory devices.

[0021] The semiconductor memory device, its manufacturing method, reading and writing method, electronic device, and memory circuit according to the present invention aim to reduce leakage current while ensuring high integration.

[0022] The present invention adds an auxiliary electrode electrically connected to the drain, located on one side of the channel, with an insulating layer between the drain and the channel, and a gate on the other side of the channel, which functions as a back gate and a storage electrode at the same time, and can control the small off-current of the transistor and play the role of storing charge, without adding an additional capacitor, and can realize relatively low-frequency refresh, and adding an additional capacitor can ensure a larger charge storage capacity.

[0023] Various embodiments of a semiconductor memory device, a manufacturing method thereof, a reading and writing method, an electronic device, and a memory circuit according to the present invention will be described in detail below with reference to the drawings.

[0024] Fig. 1 is a cross-sectional view of a memory cell of a semiconductor memory device 10 according to an embodiment of the present disclosure. Fig. 1 shows only one memory cell among a plurality of memory cells arranged in an array in the semiconductor memory device 10. Fig. 2 is a planar projection view of a part of an area of ​​some components of the memory unit shown in Fig. 1.

[0025] 1, the semiconductor memory device 10 includes a substrate 110 and a plurality of memory cells 101 provided on the substrate 110. The memory cells 101 include a transistor 11, a bit line 32, and a word line 31. The transistor 11 has a drain 112, a gate 115, an auxiliary electrode 116, a semiconductor layer 114, and a source 113.

[0026] The substrate 110 may be, but is not limited to, a silicon substrate, a glass substrate, a flexible substrate, etc. The substrate 110 may have an upper surface and a lower surface opposed to each other.

[0027] The gate 115 may be called a first gate, and the auxiliary electrode 116 may be called a second gate. The gate 115 is connected to the word line 31 to control the on / off of the transistor 11, and the auxiliary electrode 116 is located on the front surface of the semiconductor layer channel, and the auxiliary electrode 116 is located on the back surface of the semiconductor layer channel, with respect to the gate 115. Both the gate 115 and the auxiliary electrode 116 are used to control the transistor current, and both have the role of a gate, but the role of the auxiliary electrode 116 is not to control the on / off of the transistor, but to control the transistor to reduce leakage current loss, and the gate 115 controls the on / off of the transistor by the action of the word line voltage.

[0028] In some embodiments, the gate 115 is disposed on the substrate 110, extends in a first direction perpendicular to a top surface of the substrate 110, and may have a pillar shape. The gate 115 may be electrically connected to a word line 31.

[0029] An interlayer insulating layer 111 may be provided on the upper surface of the substrate 110 , and a drain 112 may be provided on the interlayer insulating layer 111 .

[0030] The semiconductor layer 114 may be provided on the interlayer insulating layer 111 , and at least a portion of the semiconductor layer 114 may surround a sidewall of the gate 115 .

[0031] The semiconductor layer 114 may be formed of a single crystal semiconductor material, a polycrystalline semiconductor material, or a metal oxide semiconductor. The metal oxide semiconductor may contain at least one of In, Ga, Zn, Sn, and W.

[0032] The source 113 may be provided to surround the outer wall of the semiconductor layer 114 and may be electrically connected to the semiconductor layer 114. The source 113 may be electrically connected to the bit line 32.

[0033] The drain 112 may be provided below the semiconductor layer 114 so as to be electrically connected to the semiconductor layer 114. In addition, the drain 112 is spaced apart from the source 113 in the first direction.

[0034] The first insulating layer 117 a may be provided between the gate 115 and the semiconductor layer 114 and between the gate 115 and the drain 112 .

[0035] The auxiliary electrode 116 may be provided to surround the outer wall of the semiconductor layer 114 between the source 113 and the drain 112 in the first direction.

[0036] The second insulating layer 117b may be provided between the auxiliary electrode 116 and the semiconductor layer 114 and between the auxiliary electrode 116 and the source 113 so that the auxiliary electrode 116 is insulated from both the semiconductor layer 114 and the source 113. In addition, the auxiliary electrode 116 may be electrically connected to the drain 112.

[0037] Specifically, the auxiliary electrode 116 may extend in a first direction from the source 113 toward the drain 112. In one embodiment, the auxiliary electrode 116 may at least partially overlap the drain 112 in the first direction. That is, an orthogonal projection of the auxiliary electrode 116 onto a plane parallel to the top surface of the substrate 110 and an orthogonal projection of the drain 112 onto a plane parallel to the top surface of the substrate 110 may overlap.

[0038] In one embodiment, the orthogonal projection of the outer wall of the auxiliary electrode 116 onto a plane parallel to the top surface of the substrate 110 may be located outside the orthogonal projection of the source 113 onto said plane and may be located within the orthogonal projection of the drain 112 onto said plane.

[0039] As shown in FIG. 1, the semiconductor layer 114 can surround the sidewalls and the lower surface of the gate 115 in a U-shape, and the first insulating layer 117a can also be formed in a U-shape between the semiconductor layer 114 and the gate 115 so as to insulate the semiconductor layer 114 and the gate 115.

[0040] As shown in FIG. 1, the drain 112 is provided between the substrate 110 and the semiconductor layer 114 and is in contact with the lower surface of the semiconductor layer 114.

[0041] In FIG. 1, the drain 112 is shown to be provided between the substrate 110 and the semiconductor layer 114. However, unlike FIG. 1, the drain 112 may surround the lower portion of the outer sidewall of the semiconductor layer 114 and be provided in contact with the lower portion of the outer sidewall of the semiconductor layer 114.

[0042] 1, the drain 112 may include a first portion located between the substrate 110 and the semiconductor layer 114, and a second portion extending outward from the first portion in a second direction parallel to the top surface of the substrate 110. In addition, the second portion of the drain 112 may at least partially overlap with the auxiliary electrode 116 in the first direction.

[0043] In one embodiment, not shown, the second portion of the drain 112 may be in direct contact with the auxiliary electrode 116 .

[0044] In another embodiment, as shown in FIG. 1, the auxiliary electrode 116 may be separated from the second portion of the drain 112 in the first direction via a second insulating layer 117b, and the auxiliary electrode 116 may be electrically connected to the second portion of the drain 112 via a conductive connecting member 119.

[0045] Specifically, the auxiliary electrode 116 may be electrically connected to an end of the second portion of the drain 112 via a conductive connector 119 .

[0046] Although not shown, the conductive connection member 119 may extend downward in the first direction (for example, may extend through the second insulating layer 117b) to annularly surround the outer wall of the semiconductor layer 116 and be connected to the second portion of the drain 112. In addition, the orthogonal projection of the conductive connection member 119 onto a plane parallel to the upper surface of the substrate 110 is located within the orthogonal projection of the auxiliary electrode 116 onto the plane.

[0047] In another embodiment, the conductive connection member 119 may electrically connect a portion of the outer wall of the auxiliary electrode 116 to an end of the second portion of the drain 112. In this case, as shown in FIG. 2, the orthogonal projection of the conductive connection member 119 onto a plane parallel to the top surface of the substrate 110 may be located outside the orthogonal projection of the auxiliary electrode 116 onto the plane.

[0048] The word line 31 and the bit line 32 are both located above the gate 115 and are insulated from each other by different layers.

[0049] 1, the source 113 and the auxiliary electrode 116 may at least partially overlap in a first direction, i.e., an orthogonal projection of the source 113 onto a plane parallel to the top surface of the substrate 110 may overlap an orthogonal projection of the auxiliary electrode 116 onto that plane.

[0050] Furthermore, the semiconductor memory device 10 may further include an additional electrode (not shown) that at least partially overlaps with the auxiliary electrode 116 in the first direction, and the additional electrode may form two opposing electrodes of the capacitor together with the auxiliary electrode 116.

[0051] As shown in FIG. 1, the orthogonal projection of the gate 115 onto a plane parallel to the top surface of the substrate 110 overlaps with the orthogonal projection of the drain 112 onto a plane parallel to the top surface of the substrate 110, and the gate 115 may be insulated from the drain 112.

[0052] However, in other embodiments, the orthogonal projection of the gate 115 onto the substrate 110 and the orthogonal projection of the layer 112 onto the substrate 110 do not overlap.

[0053] 1, the auxiliary electrode 116 may be provided on an upper surface of the drain 112, away from the substrate 110. An orthogonal projection of the auxiliary electrode 116 onto the substrate 110 may overlap with an orthogonal projection of the drain 112 onto the substrate 110. The auxiliary electrode 116 may be insulated from the gate 115. An orthogonal projection of the auxiliary electrode 116 onto the substrate 110 may not overlap with an orthogonal projection of the gate 115 onto the substrate 110.

[0054] The semiconductor layer 114 may surround the gate 115. As shown in FIG. 1, the orthogonal projection of the semiconductor layer 114 onto the substrate 110 overlaps with the orthogonal projection of the drain 112 onto the substrate 110, the semiconductor layer 114 is insulated from the gate 115 and the auxiliary electrode 116, respectively, and the semiconductor layer 114 is electrically connected to the drain 112.

[0055] The source 113 may be electrically connected to the semiconductor layer 114 and the bit line 32, respectively, and the source 113 may be insulated from the gate 115 and the auxiliary electrode .

[0056] Specifically, as shown in FIGS. 1-5, a substrate 110 may include silicon or glass, and a plurality of memory cells 101 located on the substrate 110 are arranged in an array.

[0057] The drain 112 can be formed by a patterning process. On the upper surface of the drain 112, which is away from the substrate 110, a semiconductor layer 114, a gate 115, a first insulating layer 117a, a second insulating layer 117b, an auxiliary electrode 116, and a source 113 are provided.

[0058] The source 113 may be located on a surface of the auxiliary electrode 116 away from the substrate 110, i.e., the drain 112, the auxiliary electrode 116 and the source 113 are stacked in order along the first direction in Fig. 1. The gate 115 and the auxiliary electrode 116 extend upward along the first direction on the substrate 110. That is, the length of the gate 115 and the auxiliary electrode 116 in the first direction in Fig. 1 is longer than the lengths in other directions.

[0059] The gate 115 is insulated from the semiconductor layer 114, the source 113, and the drain 112 by a first insulating layer 117a, the auxiliary electrode 116 is insulated from the semiconductor layer 114, the source 113, and the drain 112 by a second insulating layer 117b, and the source 113 and the drain 112 are electrically connected to the semiconductor layer 114. The source 113, the drain 112, the gate 115, the auxiliary electrode 116, and the semiconductor layer 114 are stacked to form a three-dimensional transistor 11 (the semiconductor layer 114, the gate 115, and the auxiliary electrode 116 all extend in a direction perpendicular to the substrate 110), and the auxiliary electrode 116 is electrically connected to the drain 112. The memory cell 101 further includes a word line 31 electrically connected to the gate 115 and a bit line 32 electrically connected to the source 113.

[0060] When the semiconductor memory device 10 is in a write operation mode, a first voltage is applied to the gate 115 via the word line 31, the first voltage being an on-voltage (e.g., +5V), at this time, the channel of the transistor is in a conductive state, and the voltage of the source is approximately equal to the voltage of the drain. At the same time, a voltage input data signal is applied to the source 113 via the bit line 32, and the voltage of the drain 112 is equal to the voltage of the source input data signal. Since the drain 112 and the auxiliary electrode 116 are electrically connected, at this time, the magnitude of the voltages at the source 113 and the drain 112 and the magnitude of the voltage at the auxiliary electrode 116 are the same (the potentials of the drain 112 and the auxiliary electrode 116 are the same). The node capacitor between the auxiliary electrode 116 and the drain 112 constitutes the storage capacitor 103 of the memory cell 101, and the magnitude of the voltage at the auxiliary electrode 116 determines the magnitude of the charge amount in the storage capacitor, and further determines whether the binary of the data signal stored in the memory cell 101 is 0 or 1. When a high voltage (e.g., 5 V) is applied to the source 113 via the bit line 32, data "1" is written to the memory cell 101, and when a low voltage (e.g., 0 V) ​​is applied to the source 113 via the bit line 32, data "0" is written to the memory cell 101.

[0061] In the above embodiment, the node capacitance may be the potential difference between the auxiliary electrode 116 and infinity, or the voltage difference between the auxiliary electrode 116 and a peripheral electrode such as a source or gate.

[0062] When the semiconductor memory device 10 is in a read operation mode, a second voltage is applied to the gate 115 via the word line 31 to have a voltage difference between the gate 115 and the source 113, turning on the transistor, and the charge stored in the auxiliary electrode 116 is sensed by the sense bit line 32, and the magnitude of the current in the bit line 32 (i.e., the output current of the transistor 11) is detected, thereby realizing data reading. In some embodiments, the sense bit line 32 may be the bit line described above, in which case the input signal line and the data read line are the same line.

[0063] Specifically, if the data stored before in the memory cell 101 is "1", the auxiliary electrode 116 and the drain 112 have a high potential (e.g. +5V), and the transistor 11 is in an ON state due to the cooperation of the first voltage on the gate and the second voltage on the gate, so a significant current can be measured through the bit line 32. If a significant current is measured, it is determined that the data read is "1". If the data stored before in the memory unit 101 is "0", the potential on the auxiliary electrode 116 and the drain 112 is low, and after applying the second voltage to the gate 115, the transistor 11 is still in an OFF state, so the current measured through the bit line 32 is very weak, and it is determined that the data read is "0".

[0064] Note that the magnitude of the threshold voltage of the transistor 11 is related to the control of the auxiliary electrode 116. When there is only a gate, Vth is related to factors such as material and device structure. When the auxiliary electrode controls the semiconductor channel of the transistor, a negative bias is generated in the Vth of the transistor.

[0065] For an N-type field effect transistor (when the transistor is on, the carriers are electrons), the higher the potential on the auxiliary electrode 116 and the drain 112 (e.g., +5V), the smaller the on-voltage of the transistor's gate (i.e., the more negative the threshold voltage), i.e., when the voltage difference between the gate 115 and the source 113 is small, the transistor 11 is also turned on, and the lower the potential on the auxiliary electrode 116 and the drain 112, the weaker the control of the channel of the semiconductor layer by the auxiliary electrode, and the less the threshold voltage is influenced by the auxiliary electrode. Therefore, when the same second voltage is applied to the gate 115, refer to FIG. 6, where the horizontal axis in FIG. 6 is the voltage applied to the gate 115 (i.e., the second voltage), and the vertical axis is the output current of the transistor 11. When the voltage applied to the gate 115 is a certain value (the position of the dashed line in FIG. 6), the magnitude of the output current of the transistor 11 (i.e., the current measured via the bit line 32) differs significantly depending on whether the voltage at the auxiliary electrode 116 and the drain 112 is high (i.e., whether the data written to the transistor 11 is "1" or "0"). By detecting the current at the bit line 32, it is possible to read data from the memory cell 101. When the transistor 11 writes data "1", the output current of the transistor 11 is large, so the data that is read is also "1". When the data that the transistor 11 writes is "0", the output current of the transistor 11 is extremely weak, so the data that is read is also "0".

[0066] In this case, by increasing the control of the semiconductor channel by the auxiliary electrode, the transistor will obtain a large current with a small on-voltage and will be harder to turn off when the transistor is on. When the transistor is off, it will require a large voltage to turn on and will be harder to turn on. In this way, dark current when on or off is reduced, improving the device's ability to store and retain charge and, in some embodiments, reducing refresh frequency.

[0067] The value of the second voltage may be determined according to the parameters of the transistor and the magnitude of the voltage applied to the auxiliary electrode 116 and the drain 112 during the write operation. Note that the value of the second voltage needs to be appropriate (it needs to be between the threshold voltage when the transistor stores "1" and the threshold voltage when the transistor stores "0"). If the value of the second voltage is not appropriate, the magnitude of the output current of the transistor 11 when storing data "1" (i.e., the potential on the drain 112 and the auxiliary electrode 116 is high) and the magnitude of the output current of the transistor 11 when storing data "0" (i.e., the potential on the drain 112 and the auxiliary electrode 116 gate is low) are very close to each other, so that when performing a read operation, it is difficult to determine whether the read data is "0" or "1", which affects the performance of the semiconductor memory device 10. The optimal value of the second voltage can be determined by an experiment or a simulation method so that the difference in output current is maximized when the transistor 11 performs a read operation in different states in order to improve the read performance.

[0068] In the semiconductor memory device 10 according to the present disclosure, one transistor 11 is provided for each memory cell 101, the transistor 11 is provided with a gate 115 and an auxiliary electrode 116, and the auxiliary electrode 116 is electrically connected to the drain 112. During a write operation, after a first voltage is applied to the gate 115 via the word line 31, an electrical signal is applied to the source 113 via the bit line 32 in accordance with external input data, the source 113 transmits the electrical signal to the drain 112, the drain 112 transmits the electrical signal to the auxiliary electrode 116, and a node capacitor between the auxiliary electrode 116 and the drain 112 constitutes a memory capacitor of the memory cell 101, thereby realizing data writing (writing of "1" or "0"). This is advantageous in terms of the effect of the voltage at the auxiliary electrode 116 on the threshold voltage of the transistor 11 when performing a read operation, and data is read by applying a second voltage (the magnitude of the second voltage is between the threshold voltage when the transistor 11 stores "1" and the threshold voltage when the transistor 11 stores "0") to the auxiliary electrode 116 via the word line 31, and detecting the magnitude of the output current of the field effect transistor. Therefore, compared with the structure of the memory cell of the related art in which 2T1 C or 2T0 C is provided, the memory cell 101 in the embodiment of the present disclosure can realize data reading and writing by providing only one transistor 11, and does not need to provide other transistors and capacitive elements, greatly simplifying the structure of the memory cell 101 and advantageous in improving the integration degree and memory density of the semiconductor memory element 10. In addition, it becomes easy to form a semiconductor memory device 10 with a multi-layer structure by stacking the memory cells 101, and the process of forming the semiconductor memory device 10 is simplified.

[0069] In the embodiment of the present disclosure, the gate 115, the auxiliary electrode 116, the semiconductor layer 114 and the source 113 are all disposed on the side of the drain 112 farther from the substrate 110, and the specific positions of the gate 115, the auxiliary electrode 116, the semiconductor layer 114 and the source 113 can be adjusted according to the actual situation. In the embodiment, as shown in Figures 1 and 2, in the embodiment of the present disclosure, the orthogonal projections of the gate 115, the auxiliary electrode 116, the source 113 and the semiconductor layer 114 on the substrate 110 are all within the orthogonal projection of the drain 112 on the substrate 110, so that the area occupied by the transistor 11 can be reduced, the structural layout of the semiconductor memory device 10 becomes more compact, and the integration of the device is more favorable.

[0070] As shown in FIG. 1 and FIG. 2, in the embodiment, the auxiliary electrode 116 surrounds the gate 115, and the semiconductor layer 114 is disposed between the gate 115 and the auxiliary electrode 116. By surrounding the gate 115 with the auxiliary electrode 116, the area of ​​the overlapping region between the gate 115, the auxiliary electrode 116 and the semiconductor layer 114 can be maximized, so that the influence of the auxiliary electrode 116 on the threshold voltage of the transistor 11 can be increased, that is, when the voltages at the auxiliary electrode 116 are different, the output current of the transistor can have a large difference by applying the same threshold voltage. Therefore, it is advantageous to distinguish the read data when performing a read operation, and improve the accuracy of the read data. Note that the thickness of the layer of the gate 115 and the layer of the auxiliary electrode 116 in the first direction in FIG. 1 may be determined according to the actual situation, and is not limited here.

[0071] In this embodiment, the material of the semiconductor layer 114 includes a metal oxide semiconductor material. Due to the inherent characteristics of metal oxide semiconductors (such as low electron mobility), when a metal oxide is used as the material of the semiconductor layer 114, the leakage current of the transistor 11 can be reduced and the speed of charge flow in the storage capacitor can be reduced, so that the data storage time of the semiconductor memory device 10 can be extended, which is advantageous for reducing the refresh frequency and power consumption of the semiconductor memory device 10.

[0072] The metal oxide material may be indium gallium zinc oxide (IGZO). When the metal oxide material is IGZO, the leakage current of the transistor 11 is small (the leakage current is 10 -15 A or less), which ensures the operating performance of the semiconductor memory device. The metal oxide material is ITO, IWO, ZnO x , InO x , In2O3, InWO, SnO2, TiO x , InSnO x , Zn x O y N z , Mg x Zinc y O z , In x Zinc y O z , In x Ga y Zinc z O a , Zr x In y Zinc z O a , Hf x In y Zinc z O a , Sn x In y Zinc z O a , Al x Sn y In z Zinc a O d , Si x In y Zinc z O a , Zn x Sn y O z , Al x Zinc y Sn z O a , Ga x Zinc y Sn z O a , Zr x Zinc y Snz O a , InGaSiO, or other materials may be used as long as it is guaranteed that the leakage current of the transistor satisfies the requirements, and the specific details are adjusted according to the actual situation.

[0073] In addition, a specific manner for realizing the electrical connection between the auxiliary electrode 116 and the drain 112 can be determined according to the actual situation. In the embodiment, as shown in FIG. 1 and FIG. 2, the transistor 11 further includes a conductive connection member 119, which is provided on the side of the drain 112 far from the substrate 110, and the auxiliary electrode 116 is electrically connected to the drain 112 through the conductive connection member 119. In the process of forming the semiconductor memory device 10, after forming the drain 112 and the auxiliary electrode 116, the conductive connection member 119 can be formed by depositing a metal material on the drain 112, which is easy to process. The material of the conductive connection member 119 can be a material having good conductive performance such as copper, aluminum, etc., and is not limited here. The size and position of the conductive connection member 119 can be adjusted according to the actual situation. In an embodiment, as shown in FIGS. 1 and 2, the conductive connection member 119 surrounds the auxiliary electrode 116, thereby maximizing the contact area between the conductive connection member 119 and the auxiliary electrode 116 and the drain 112, which is advantageous for improving the previous electrical connection performance between the auxiliary electrode 116 and the drain 112.

[0074] 1-5, in the embodiment of the present disclosure, the semiconductor memory device 10 includes a plurality of array modules 102 arranged in a stacked manner, and the array module 102 includes a plurality of memory units 101 arranged in an array. Specifically, the word lines 31 (not shown in FIG. 3) of the plurality of memory cells 101 are connected to each other, and the bit lines 32 (not shown in FIG. 3) are connected to each other to form a single layer array module 102. The multi-array modules 102 are stacked to form the semiconductor memory device 10 having a three-dimensional structure, thereby improving the memory capacity of the semiconductor memory device 10 and reducing the area occupied by the semiconductor memory device 10, which is advantageous for device integration.

[0075] Based on the same inventive idea, an embodiment of the present disclosure further provides a memory circuit, as shown in FIG. 4 , including a gate 115, an auxiliary electrode 116, a source 113, a drain 112, a word line 31 and a bit line 32, wherein the gate 115 is electrically connected to the word line 31, the source 113 is electrically connected to the bit line 32, the drain 112 is electrically connected to the auxiliary electrode 116, the gate 115 and the auxiliary electrode 116 are insulated from each other, the gate 115 is insulated from the source 113 and the drain 112 respectively, the auxiliary electrode 115 is insulated from the source 113 and the drain 112 respectively, and a node capacitor between the auxiliary electrode 116 and the drain 112 constitutes a memory capacitor 103.

[0076] Based on the same inventive concept, the embodiment of the present disclosure further provides an electronic device including the semiconductor memory device 10 according to the embodiment of the present disclosure, or an electronic device including the memory circuit according to the embodiment of the present disclosure. Since the electronic device includes the semiconductor memory device 10 according to the embodiment of the present disclosure, it has the same beneficial effects as the semiconductor memory device 10, and therefore a description thereof will be omitted here.

[0077] Specifically, the electronic device according to the embodiment of the present disclosure includes a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, a mobile power source, etc., and can be determined according to the actual situation. The storage device may include a memory in a computer, etc., and is not limited thereto.

[0078] Based on the same inventive idea, the embodiment of the present disclosure further provides a manufacturing method for the semiconductor memory device 10. In S101, a substrate is provided. In S102, a drain is formed on one side of the substrate through a patterning process; In step S103, a source, a semiconductor layer, and a gate are sequentially formed on the side of the drain farther from the substrate; In S104, an auxiliary electrode and a conductive connection member are formed on the side of the drain farther from the substrate.

[0079] In a forming method according to an embodiment of the present disclosure, one transistor 11 is provided for each memory cell 101, and the transistor 11 is provided with a gate 115 and an auxiliary electrode 116, and the auxiliary electrode 116 is electrically connected to the drain 112. When performing a write operation, a first voltage is applied to the gate 115 via the word line 31, and then an electric signal is applied to the source 113 via the bit line 32 based on external input data, the source 113 transmits the electric signal to the drain 112, the drain 112 transmits the electric signal to the auxiliary electrode 116, and the node capacitance between the auxiliary electrode 116 and the drain 112 constitutes the storage capacitance of the memory cell 101, thereby realizing data writing, and when performing a read operation, a second voltage (the magnitude of the second voltage is between the threshold voltage when the transistor 11 stores "1" and the threshold voltage when the transistor 11 stores "0") is applied to the auxiliary electrode 116 via the word line 31, and then the magnitude of the output current of the field effect transistor is detected, thereby realizing data reading. Therefore, data can be read and written by simply installing one transistor 11 in the memory cell 101, and there is no need to install a separate transistor 11 and capacitor element. This greatly simplifies the structure of the memory cell 101 and is advantageous for improving the integration degree and memory density of the semiconductor memory device 10.

[0080] In one embodiment, the steps of sequentially forming the source 113, the semiconductor layer 114, and the gate 115 on the side of the drain 112 away from the substrate 110 include: forming a sacrificial layer on a side of the drain farther from the substrate, the sacrificial layer covering the drain; forming a source on a side of the sacrificial layer away from the substrate by a patterning process, the orthogonal projection of the source on the substrate being located within the orthogonal projection of the drain on the substrate; a first medium layer is formed on a side of the source farther from the substrate, the first medium layer covering the source and the drain; A through hole is formed through the first medium layer, the source, and the sacrificial layer in this order, the drain is exposed at the bottom of the through hole, and the source is exposed at the hole wall of the through hole; A semiconductor layer, a first insulating layer and a gate are sequentially formed in the through hole, and the semiconductor layer is electrically connected to the source and the drain, respectively.

[0081] In one embodiment, the step of forming the auxiliary electrode 116 and the conductive connecting member 119 on the side of the drain 112 away from the substrate 110 includes: removing a portion of the first medium layer and the sacrificial layer by a patterning process to expose both ends of the drain; removing the remaining sacrificial layer to form a containment space exposing the drain, source and semiconductor layer; depositing a second insulating layer to cover the exposed semiconductor layer, the source 113, and the drain with the second insulating layer; depositing an auxiliary electrode on a surface of the second insulating layer and filling the auxiliary electrode into the receiving space; depositing and forming a conductive connection member on both ends of the exposed drain, the conductive connection member being connected to the drain and the auxiliary electrode, respectively;

[0082] In the embodiment of the present disclosure, after forming the auxiliary electrode 116 and the conductive connection member 119 on the side of the drain 112 farther from the substrate 110, forming word lines by a patterning process and electrically connecting the word lines to the gates; forming bit lines by a patterning process and electrically connecting the bit lines to the sources.

[0083] Hereinafter, a manufacturing process of the semiconductor memory device 10 according to the embodiment of the present disclosure will be described in detail with reference to the drawings. Specifically, the patterning process in the embodiment of the present disclosure includes some or all of the processes of applying a photoresist, exposing, developing, etching, and removing the photoresist. As shown in Figure 8a, firstly, a substrate 110 is provided. The material of the substrate 110 includes silicon or glass. Next, an interlayer insulating layer 111 is formed on one side of the substrate 110, as shown in FIG. 8b. As shown in FIG. 8c, a patterning process is then performed to form the drain 112 on the side of the interlayer insulating layer 111 remote from the substrate 110. As shown in FIG. 8d, then, a sacrificial layer 100 is formed on the side of the drain 112 farther from the substrate 110, the sacrificial layer 100 covers the drain 112, and the material of the sacrificial layer 100 includes an organic material or an inorganic material. As shown in FIG. 8e, a source 113 is then formed on the side of the sacrificial layer 100 remote from the substrate 110 by a patterning process, such that the orthogonal projection of the source 113 on the substrate 110 is located within the orthogonal projection of the drain 112 on the substrate 110. 8f, a first medium layer 118a is then formed on the side of the source 113 remote from the substrate 110, so that the first medium layer 118a covers the source 113 and the drain 112. The material of the first medium layer 118a includes an inorganic material such as silicon oxide or silicon nitride. As shown in FIG. 8g, next, a portion of the first medium layer 118a is covered with a mask 23, and a through hole 20 is opened in the first medium layer 118a that is not covered by the mask 23. The through hole 20 passes through the first medium layer 118a, the source 113, and the sacrificial layer 100 in that order, so that the drain 112 is exposed at the bottom of the through hole 20 and the source 113 is exposed on the wall of the through hole 20. As shown in FIG. 8h, the semiconductor layer 114, the first insulating layer 117a and the gate 115 are then sequentially formed in the via hole 20 by processes such as atomic deposition, chemical vapor deposition and physical vapor deposition, and the semiconductor layer 114 is electrically connected to the source 113 and the drain 112, respectively. The material of the semiconductor layer 114 includes metal oxide such as IGZO, and the material of the first insulating layer 117a includes materials with good insulating performance such as aluminum oxide. The material of the gate 115 includes materials with good electrical conductivity such as titanium nitride and tungsten. Then, the surfaces of the semiconductor layer 114, the first insulating layer 117a and the gate 115 away from the substrate 110 are polished by a chemical mechanical polishing process, so that the semiconductor layer 114, the first insulating layer 117a, the gate 115 and the first medium layer 118a are made flush with each other. 8i, next, a patterning process is performed to remove a portion of the first medium layer 118a and the sacrificial layer 100 to expose both ends of the drain 112. Specifically, a mask 23 is used to shield the regions corresponding to the semiconductor layer 114, the first insulating layer 117a, and the gate 115, and the portions located at both ends of the first medium layer 118a and the sacrificial layer 100 are etched. As shown in FIG. 8j, the remaining sacrificial layer 100 is then removed by an etching process to form the receiving space 22 to expose the drain 112, the source 113 and the semiconductor layer 114. As shown in FIG. 8k, a second insulating layer 117b is then formed in the containing space 22 by a deposition process, and the second insulating layer 117b covers the exposed semiconductor layer 114, the source 113 and the drain 112. 8l, the auxiliary electrode 116 is then deposited on the surface of the second insulating layer 117b, and the auxiliary electrode 116 fills the receiving space 22. Then, an etching process is performed to etch the side surface of the auxiliary electrode 116, to ensure that the auxiliary electrodes 116 of adjacent memory cells are isolated from each other. As shown in FIG. 8m, a conductive connection member 119 is then deposited on both ends of the exposed drain 112 by a deposition process, and the conductive connection member 119 is connected to the drain 112 and the auxiliary electrode 116 respectively to complete the fabrication of the transistor 11. As shown in FIG. 8n, a second medium layer 118b is then formed on one side of the substrate 110 by a deposition process, so that the second medium layer 118b covers the transistor 11. Next, a through passage 21 is opened at a position corresponding to the source 113 in the second medium layer 118b, as shown in FIG. 8o. As shown in FIG. 8p, a patterning process is then performed to form the bit line 32 on the side of the second medium layer 118b remote from the substrate 110, and the bit line 32 is electrically connected to the source 113 through the through via 21. As shown in FIG. 8q, a third medium layer 118c is then deposited on the second medium layer 118b. Next, as shown in FIG. 8r, a through passage 21 is provided in the third medium layer 118c at a position corresponding to the gate 115. As shown in FIG. 8s, a patterning process is then performed to form the word line 31 on the side of the third medium layer 118c farther from the substrate 110, and the word line 31 is electrically connected to the gate 115 through the through via 21.

[0084] Based on the same inventive idea, the embodiment of the present disclosure further provides a method for reading and writing data from and to the semiconductor memory device 10 . In S201, in a write state, a first voltage is applied to the gate by the word line. In S202, an electrical signal is applied to the source via the bit line based on external input data to write data into the semiconductor memory device, or a second voltage is applied to the gate via the word line during a read state. In S203, the current at the source is measured by the bit line and data is read from the semiconductor memory device.

[0085] 1 and 2 (word lines and bit lines are not shown in FIG. 2), when the semiconductor memory device 10 is in a write operation mode, a first voltage (e.g., 5V) is applied to the gate 115 via the word line 31 to turn on the transistor 11, and the magnitude of the first voltage is related to factors such as the structure of the transistor 11 and the material of the semiconductor layer 114 in the transistor 11, and can be adjusted according to the actual situation. When the transistor 11 is turned on, a voltage is applied to the source 113 via the bit line 32 in response to external input data, the source 113 and the drain 112 are conductive via the semiconductor layer 114, and the drain 112 is electrically connected to the auxiliary electrode 116, so that the magnitude of the voltage at the source 113 and the drain 112 becomes the same as the magnitude of the voltage at the auxiliary electrode 116. The node capacitance between the auxiliary electrode 116 and the drain 112 constitutes the storage capacitance of the memory cell 101, and the level of the gate voltage of the auxiliary electrode 116 determines the amount of charge in the storage capacitance, which in turn determines whether the binary value of the data signal stored in the memory cell 101 is 0 or 1. When a high voltage (e.g., 5 V) is applied to the source 113 via the bit line 32, data "1" is written to the memory cell 101, and when a low voltage (e.g., 0 V) ​​is applied to the source 113 via the bit line 32, data "0" is written to the memory cell 101.

[0086] When the semiconductor memory device 10 is in a read operation mode, a second voltage is applied to the gate 115 through the word line 31, so that there is a voltage difference between the gate 115 and the source 113, and the magnitude of the current flowing through the bit line 32 (i.e., the output current of the transistor 11) is detected to realize data reading. Specifically, when the data previously stored in the memory cell 101 is "1", the auxiliary electrode 116 and the drain 112 have a high potential, and the transistor 11 is in an ON state due to the cooperation of the first voltage and the second voltage, so that a significant current can be measured through the bit line 32. If a significant current is measured, it is determined that the data read is "1". When the data previously stored in the memory unit 101 is "0", the voltage at the auxiliary electrode 116 and the drain 112 is low, and after applying the second voltage to the gate 115, the field effect transistor is still in an OFF state, so the current measured through the bit line 32 is very weak, and at this time, it is determined that the data read is "0".

[0087] It should be noted that the magnitude of the threshold voltage of the transistor 11 is related to the magnitude of the voltage at the auxiliary electrode 116 and the drain 112. For an N-type field effect transistor (i.e., the semiconductor layer 114 of the transistor 11 adopts an N-type semiconductor material), the higher the potential at the auxiliary electrode 116 and the drain 112, the smaller the threshold voltage; that is, when the voltage difference between the gate 115 and the source 113 is small, the transistor 11 can have a large output current; and the lower the potential at the auxiliary electrode 116 and the drain 112, the larger the threshold voltage; therefore, when the gate 115 has a similar voltage difference, the threshold voltage is large. When the second voltage is applied, as shown in Figures 1, 4 and 6, the magnitude of the output current of transistor 11 (i.e., the current measured by bit line 32) differs significantly depending on the voltage level at auxiliary electrode 116 and drain 112 (i.e., whether the data written by transistor 11 is "1" or "0"), and data can be read from memory cell 101 by detecting the current at bit line 32. When data "1" is written by transistor 11, the output current of transistor 11 is "1".

[0088] The value of the second voltage can be determined based on the parameters of the field effect transistor and the magnitude of the voltage applied to the auxiliary electrode 116 and the drain 112 when performing a write operation. The value of the second voltage needs to be appropriate (it needs to be between the threshold voltage when the transistor stores "1" and the threshold voltage when the transistor stores "0"). If the value of the second voltage is not appropriate, the magnitude of the output current of the transistor 11 when storing data "1" (i.e., the potential on the drain 112 and the auxiliary electrode 116 is high) is very close to the magnitude of the output current of the transistor 11 when storing data "0" (i.e., the potential on the drain 112 and the auxiliary electrode 116 gate is low), so that it is difficult to determine whether the read data is "0" or "1" when performing a read operation, which affects the performance of the semiconductor memory device 10. In practical applications, the optimal value of the second voltage can be determined by an experiment or a simulation method to maximize the difference in output current when the transistor 11 performs a read operation in different states, thereby improving the read performance.

[0089] By applying the embodiments of the present disclosure, at least the following beneficial effects can be realized: 1. In the semiconductor memory device 10 according to the present disclosure, one transistor 11 is provided for each memory cell 101, and the transistor 11 is provided with a gate 115 and an auxiliary electrode 116, and the auxiliary electrode 116 and the drain 112 are electrically connected. When performing a write operation, a first voltage is applied to the gate 115 via the word line 31. Then, based on external input data, an electrical signal is applied to the source 113 via the bit line 32. The source 113 transmits the electrical signal to the drain 112, which transmits the electrical signal to the auxiliary electrode 116. The node capacitance between the auxiliary electrode 116 and the drain 112 constitutes the storage capacitance of the memory cell 101, thereby realizing data writing. When performing a read operation, a second voltage (the magnitude of the second voltage is between the threshold voltage when the transistor 11 stores "1" and the threshold voltage when the transistor stores "0") is applied to the auxiliary electrode 116 via the word line 31 by utilizing the effect of the voltage on the auxiliary electrode 116 on the threshold voltage of the transistor 11. Then, data is read by detecting the magnitude of the output current of the field effect transistor. Therefore, data can be read and written by simply installing one transistor 11 in the memory cell 101, and there is no need to install a separate transistor 11 and capacitor element. This greatly simplifies the structure of the memory cell 101 and is advantageous for improving the integration degree and memory density of the semiconductor memory device 10. 2. In the embodiment of the present disclosure, the orthogonal projections of the gate 115, the auxiliary electrode 116 onto the substrate 110, the source 113, and the semiconductor layer 114 are all within the orthogonal projection of the drain 112 onto the substrate 110, thereby reducing the area occupied by the transistor 11, making the structural layout of the semiconductor memory device 10 more compact, and being more advantageous for device integration. 3. In the embodiment of the present disclosure, the auxiliary electrode 116 surrounds the gate 115, which can maximize the area of ​​the overlapping region between the gate 115, the auxiliary electrode 116 and the semiconductor layer 114, thereby increasing the influence of the auxiliary electrode 116 on the threshold voltage of the transistor 11, that is, when the voltages at the auxiliary electrode 116 are different, the output current of the field effect transistor can have a large difference by applying the same threshold voltage. Therefore, it is favorable to distinguish the read data when performing a read operation, and improve the accuracy of the read data. 4. When a metal oxide is used as the material for the semiconductor layer 114, the leakage current of the transistor 11 can be reduced (when the metal oxide is IGZO, the leakage current is 10 -15 A or less), the rate at which charges flow out of the storage capacitor can be reduced, so that the data retention time of the semiconductor memory device 10 can be extended, which is advantageous for reducing the refresh frequency and power consumption of the semiconductor memory device 10. 5. In the embodiment of the present disclosure, a plurality of memory cells 101 are arranged in an array to form an array module 102, and then the multi-layer array module 102 is stacked and installed to form a semiconductor memory device 10 having a three-dimensional structure, thereby improving the memory capacity of the semiconductor memory device 10 and reducing the area occupied by the semiconductor memory device 10, which is advantageous for device integration.

[0090] In describing the present disclosure, the orientations or positional relationships indicated by terms such as "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are based on the orientations or positional relationships shown in the drawings, and are merely for the convenience and simplification of the description of the present disclosure, and do not indicate or imply that a specified device or element must have a particular orientation or be constructed and operated in a particular orientation, and should not be understood as limiting the present disclosure.

[0091] The terms "first" and "second" are merely for descriptive purposes and are not to be understood as indicating or implying a relative importance or number of the technical features depicted. Thus, a feature qualified as "first" or "second" may explicitly or implicitly include one or more of said features. In the description of this disclosure, unless otherwise specified, "plurality" means two or more.

[0092] In the description herein, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

[0093] The above are only some embodiments of the present disclosure, and those skilled in the art may make some improvements and modifications without departing from the principles of the present disclosure, and these improvements and modifications should also be regarded as within the protection scope of the present disclosure.

Claims

1. A semiconductor memory device comprising: a substrate; and a plurality of memory cells provided on the substrate, the memory cells including transistors, bit lines, and word lines, The transistor is a drain provided on the substrate; a gate provided above the drain, insulated from the drain, and electrically connected to the word line; an auxiliary electrode provided above the drain and surrounding an outer wall of the gate, insulated from the gate, not overlapping with the gate in a first direction perpendicular to the top surface of the substrate, and electrically connected to the drain; a semiconductor layer surrounding the gate, insulated from the gate and the auxiliary electrode, and electrically connected to the drain; a source provided above the auxiliary electrode to surround the outer wall of the gate, electrically connected to the semiconductor layer and the bit line, and insulated from the gate and the auxiliary electrode.

2. The semiconductor memory device according to claim 1 , wherein said auxiliary electrode at least partially overlaps said source in said first direction.

3. The semiconductor memory device according to claim 2 , wherein said auxiliary electrode at least partially overlaps with said drain in said first direction.

4. 4. The semiconductor memory device according to claim 3, wherein an orthogonal projection of an outer wall of said auxiliary electrode onto a plane parallel to said top surface of said substrate is located outside an orthogonal projection of said source onto said plane and is located within an orthogonal projection of said drain onto said plane.

5. 2. The semiconductor memory device according to claim 1, wherein said semiconductor layer is provided between said gate and said auxiliary electrode.

6. 4. The semiconductor memory device according to claim 3, further comprising a conductive connecting member, said auxiliary electrode being electrically connected to said drain via said conductive connecting member.

7. 7. The semiconductor memory device according to claim 6, wherein said conductive connecting member surrounds said auxiliary electrode.

8. 8. The semiconductor memory device according to claim 1, wherein the semiconductor layer includes a single crystal semiconductor material, a polycrystalline semiconductor material, or a metal oxide semiconductor.

9. 9. The semiconductor memory device according to claim 8, wherein the metal oxide semiconductor contains at least one of In, Ga, Zn, Sn, and W.

10. a plurality of array modules arranged in a stack, the array modules including a plurality of the memory cells arranged in an array; The gates of the transistors in each row are all connected to one of the word lines; 10. The semiconductor memory device according to claim 1, wherein the sources included in the transistors in each column are all connected to one of the bit lines.

11. a gate included in a pillar-shaped transistor provided on a substrate, extending in a first direction perpendicular to an upper surface of the substrate, and electrically connected to a word line; a semiconductor layer at least partially surrounding a sidewall of the gate; a source provided so as to surround an outer wall of the semiconductor layer, electrically connected to the semiconductor layer, and electrically connected to a bit line; a drain electrically connected to the semiconductor layer at a lower portion of the semiconductor layer and spaced apart from the source in the first direction; a first insulating layer provided between the gate and the semiconductor layer and between the gate and the drain; an auxiliary electrode provided to surround an outer side wall of the semiconductor layer between the source and the drain in the first direction; a second insulating layer located between the auxiliary electrode and the semiconductor layer and between the auxiliary electrode and the source so as to insulate the auxiliary electrode from both the semiconductor layer and the source.

12. The semiconductor memory device according to claim 11 , wherein the auxiliary electrode extends from the source to the drain in the first direction.

13. The semiconductor memory device according to claim 12 , wherein the auxiliary electrode at least partially overlaps with the drain in the first direction.

14. 14. The semiconductor memory device according to claim 13, wherein an orthogonal projection of an outer wall of the auxiliary electrode onto a plane parallel to the top surface of the substrate is located outside an orthogonal projection of the source onto the plane and is located within an orthogonal projection of the drain onto the plane.

15. 12. The semiconductor memory device according to claim 11, wherein the semiconductor layer is formed in a U-shape so as to surround the sidewalls and a lower surface of the gate, and the first insulating layer is formed in a U-shape between the semiconductor layer and the gate so as to insulate the semiconductor layer from the gate.

16. 16. The semiconductor memory device according to claim 15, wherein the drain is provided so as to surround a lower portion of the outer sidewall of the semiconductor layer and to be in contact with the lower portion of the outer sidewall of the semiconductor layer.

17. 16. The semiconductor memory device according to claim 15, wherein the drain is located between the substrate and the semiconductor layer and in contact with a lower surface of the semiconductor layer.

18. 18. The semiconductor memory device of claim 17, wherein the drain includes a first portion located between the substrate and the semiconductor layer and a second portion extending outward from the first portion in a second direction parallel to the top surface of the substrate, the second portion of the drain at least partially overlapping with the auxiliary electrode in the first direction.

19. 20. The semiconductor memory device according to claim 18, wherein said second portion of said drain directly contacts said auxiliary electrode.

20. 20. The semiconductor memory device according to claim 18, wherein the auxiliary electrode is separated from the second portion of the drain in the first direction via the second insulating layer, and is electrically connected to the second portion of the drain via a conductive connecting member.

21. 21. The semiconductor memory device according to claim 20, wherein the conductive connecting member annularly surrounds the outer wall of the semiconductor layer and extends in the first direction so as to connect to the second portion of the drain.

22. 22. The semiconductor memory device according to claim 21, wherein an orthogonal projection of said conductive connection member onto a plane parallel to said top surface of said substrate is located within an orthogonal projection of said auxiliary electrode onto said plane.

23. the conductive connection member electrically connects a portion of the outer wall of the auxiliary electrode and an end of the second portion of the drain; 22. The semiconductor memory device according to claim 21, wherein an orthogonal projection of said conductive connection member onto a plane parallel to said top surface of said substrate is located outside an orthogonal projection of said auxiliary electrode onto said plane.

24. 12. The semiconductor memory device according to claim 11, wherein the word line and the bit line are both located above the gate and are insulated from each other by different layers.

25. The semiconductor memory device according to claim 11 , wherein the source and the auxiliary electrode at least partially overlap in the first direction.

26. The semiconductor memory device according to claim 11 , further comprising an additional electrode at least partially overlapping said auxiliary electrode in said first direction.

27. A memory circuit comprising a gate, an auxiliary electrode, a source, a drain, a word line, and a bit line, the gate being electrically connected to the word line, the source being electrically connected to the bit line, the drain being electrically connected to the auxiliary electrode, the gate and the auxiliary electrode being insulated from each other, the gate being insulated from the source and the drain, and the auxiliary electrode being insulated from the source and the drain, A node capacitance between the auxiliary electrode and the drain constitutes a storage capacitance.

28. 12. An electronic device comprising the semiconductor memory device according to claim 1.

29. Providing a substrate; forming a drain above the substrate by a patterning process; sequentially forming a source, a semiconductor layer, and a gate on the drain; a gate insulating film formed on the gate electrode and a gate insulating member formed on the drain electrode, the gate insulating film being electrically connected to the gate electrode and the drain electrode, the gate insulating film being electrically connected to the drain electrode and the drain electrode.

30. Sequentially forming a source, a semiconductor layer, and a gate above the drain, forming a sacrificial layer above the drain, the sacrificial layer covering the drain; forming a source above the sacrificial layer by a patterning process; forming a first medium layer on the source, the first medium layer covering the source and the drain; a through hole is formed through the first medium layer, the source, and the sacrificial layer in this order, the drain is exposed at a bottom of the through hole, and the source is exposed at a hole wall of the through hole; The method according to claim 29 , wherein a semiconductor layer, a first insulating layer and a gate are sequentially formed in the through hole, and the semiconductor layer is electrically connected to the source and the drain, respectively.

31. forming an auxiliary electrode and a conductive connection member on a side of the drain remote from the substrate, removing a portion of the first medium layer and the sacrificial layer by a patterning process to expose both ends of the drain; removing a remaining sacrificial layer to expose the drain, the source and the semiconductor layer and form a receiving space; forming a second insulating layer by deposition, the second insulating layer covering the exposed semiconductor layer, the source and the drain; forming an auxiliary electrode on the second insulating layer by deposition, and filling the accommodating space with the auxiliary electrode; The method of claim 30, further comprising forming conductive connection members on both ends of the exposed drain by deposition, the conductive connection members being connected to the drain and an auxiliary electrode, respectively.

32. forming an auxiliary electrode and a conductive connection member on the drain side away from the substrate, forming a word line by a patterning process and electrically connecting the word line and the gate; 30. The method of claim 29, further comprising: forming a bit line by a patterning process, and electrically connecting the bit line to the source.

33. 12. A method for reading and writing data from and to a semiconductor memory device according to claim 1, comprising: In a write state, a word line applies a first voltage to the gate to turn on the transistor, and a bit line applies a data signal to the source, the data signal being stored in a storage capacitor connected to the drain and the auxiliary electrode by the on transistor; A method of reading and writing, during a read state, applying a second voltage to the gate by the word line and measuring a current at the source by the bit line to read a data signal.

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