Dual chip clock synchronization

Abstract

When the first and second semiconductor circuits are both at a slow clock speed, the clocks of the two semiconductor circuits are set to a common clock source and the input / output (IO) at the interface between the first and second semiconductor circuits is allowed to operate at the slow clock speed. The divide counters of the two clocks are synchronized at the slow clock speed. The two semiconductor circuits are switched to a fast clock speed that is a multiple of the slow speed and the IO cannot operate at the fast clock speed. A pulse from the divide counter of the first circuit is sent to an auxiliary divide counter of the second circuit and then the primary divide counter of the second counter is aligned with the auxiliary divide counter to keep the two circuits synchronized at the fast clock speed.

Description

[Technical field]

[0001] The present disclosure relates generally to computer systems, and more particularly to logic devices with one clock source and several clock domains. [Background technology]

[0002] Computing systems are increasingly using a large number of semiconductor circuits. Given the speed and precision of these circuits, considerable attention is being paid to synchronizing these circuits so that all components can work together in unison. However, in many cases, synchronizing the circuits can be difficult because the components between devices cannot transmit and process data as fast as the circuits themselves can transmit and process data. Summary of the Invention

[0003] Aspects of the present disclosure relate to methods, systems, and computer program products related to synchronizing clocks of semiconductor circuits. For example, the method includes setting a first clock of the first semiconductor circuit and a second clock of the second semiconductor circuit to a common clock source when the first and second semiconductor circuits are both at a slow clock speed. An input / output (IO) at an interface between the first semiconductor circuit and the second semiconductor circuit is capable of operating at the slow clock speed. The method further includes synchronizing a first divided counter of the first clock and a second divided counter of the second clock at the slow clock speed. The method further includes simultaneously switching both the first and second semiconductor circuits to a fast clock speed that is a multiple of the slow clock speed, and the IO is not capable of operating at the fast clock speed. A system including two semiconductor circuits and an IO configured to perform the above method is also disclosed.

[0004] The present disclosure also includes a second method including the above features, the second method also including shadowing the first divided counter to a third divided counter on the second semiconductor circuit using a pulse of the first divided counter. The second method also includes comparing the third divided counter to the second divided counter. The second method also includes detecting a difference between the third divided counter and the second divided counter. The second method also includes stopping the function logic of the second semiconductor circuit. The second method also includes aligning the second divided counter and the third divided counter while the function logic is stopped. The second method also includes restarting the function logic after the second divided counter is aligned with the third divided counter such that each of the second divided counter and the third divided counter and the first divided counter are all synchronized.

[0005] The above summary is not intended to describe each illustrated embodiment or every implementation of the present disclosure.

[0006] The drawings contained in this application are incorporated in and form a part of this specification. These drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. These drawings are only illustrative of particular embodiments and are not intended to limit the disclosure. [Brief description of the drawings]

[0007] [Figure 1A] FIG. 2 illustrates two steps for synchronizing two semiconductor circuits. [Figure 1B] FIG. 2 illustrates three steps for synchronizing the divide counter of the second semiconductor circuit with the divide counter of the first semiconductor circuit. [Figure 1C] FIG. 2 illustrates three steps for synchronizing the divide counter of the second semiconductor circuit with the divide counter of the first semiconductor circuit. [Figure 1D] FIG. 2 illustrates three steps for synchronizing the divide counter of the second semiconductor circuit with the divide counter of the first semiconductor circuit. [Diagram 2] 1 is a flow diagram of synchronizing two semiconductor circuits at a slow clock speed and then verifying the synchronization at a fast speed. [Diagram 3] FIG. 1B is a more detailed flow diagram of synchronizing two semiconductor circuits at a slow clock speed with respect to FIGS. 1B-1D. [Figure 4] FIG. 1 is a diagram showing a logic device including a first semiconductor circuit and a second semiconductor circuit. [Diagram 5] FIG. 2 illustrates signal behavior for a first method of deskewing a second clock signal relative to a first clock signal. [Figure 6] FIG. 13 illustrates signal behavior for a second method of deskewing a second clock signal relative to a first clock signal. [Figure 7] 1 is a flow diagram illustrating a method for deskewing a second clock signal relative to a first clock signal. [Figure 8] FIG. 1 shows a first skew sensor. [Figure 9] FIG. 13 illustrates a second skew sensor. [Figure 10] FIG. 13 shows a third skew sensor. [Figure 11] FIG. 13 shows a fourth skew sensor. [Figure 12] FIG. 12 is a diagram showing the output of the skew sensor of FIGS. 8 to 11. [Figure 13] FIG. 1 illustrates a method for determining a clock tree response time of a logic device. [Figure 14] 4 is a flow diagram illustrating a method for successively deskewing a second clock signal relative to a first clock signal. [Figure 15] FIG. 15 illustrates the method of FIG. 14 in a first situation. [Figure 16] FIG. 15 illustrates the method of FIG. 14 in a second situation. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] The invention is susceptible to various modifications and alternative forms, details of which have been shown by way of example in the drawings and will be described in detail. It is to be understood, however, that the intention is not to limit the invention to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

[0009] Aspects of the present disclosure relate to a logic device with one clock source and several clock domains. Additionally, the present disclosure relates to a method for synchronizing clock domains of a logic device. The logic device may include a first semiconductor circuit and a second semiconductor circuit, each semiconductor circuit having an associated clock domain. To avoid data loss and / or data failure, the clock domains of the first semiconductor circuit and the second semiconductor circuit that exchange data must be synchronized.

[0010] In a conventional logic device, there may be a number of semiconductor circuits attempting to function together. The efficiency and accuracy of a conventional logic device may relate to how well these semiconductor circuits are synchronized. For example, a conventional logic device may contain two semiconductor circuits driven by a common clock source. However, even if the two semiconductor circuits are running at the same speed, the counter of one semiconductor circuit may be slower or faster than the counter of the other semiconductor circuit. The difference may be called "skew." If this skew increases to a certain amount, the quality and / or efficiency of data exchange between the semiconductor circuits may be degraded. However, in many conventional logic devices, each semiconductor circuit operates at a faster speed than the intervening components, making it difficult or impossible to calibrate / synchronize these counters to the desired degree. For example, two semiconductor circuits capable of functioning at 5.4 gigahertz (GHz) may be coupled through an input / output (IO) device that can function at "only" 675 megahertz (MHz), resulting in the conventional logic system lacking the ability to pass data back and forth at full speed to test / verify alignment.

[0011] Aspects of the present disclosure can improve or solve these problems of conventional logic systems. For example, aspects of the present disclosure relate to synchronizing semiconductor chips at a slow clock speed (e.g., below 1 GHz) at which intervening IO devices can operate and deskew is possible because at that slow speed there is only one clock in the common clock distribution pipeline that can be compared unambiguously between the two devices, and then switching to a faster speed that is a multiple of the slow clock speed (e.g., twice the speed, or four times the speed, or eight times the speed, etc.). In some examples, the semiconductor chips can be switched such that no cycles are lost in either semiconductor chip. Further aspects of the present disclosure detail methods for synchronizing semiconductor circuits at a slow clock speed, verifying continued synchronization at a fast speed, and deskewing the clock mesh of the semiconductor chip at both the slow and fast speeds.

[0012] For example, aspects of the present disclosure may relate to two semiconductor chips on a logic device (although other examples may include more semiconductor chips in a manner consistent with the present disclosure). The first and second clocks of the first and second semiconductor chips are set to a common clock source when the two semiconductor circuits are in a slow clock speed clock mode (referred to herein as the "slow clock speed"). The divide counters of each of the two semiconductor chips are synchronized.

[0013] Synchronization can include sending pulses from a first counter to a second counter. The pulses can be sent in a unique, predefined state to the counters so that each counter can recognize and quantify / classify the pulses (e.g., identify whether the pulses are early or late and / or identify the magnitude of the early or late pulses received). These pulses can be used to calibrate a "shadow counter" on one of the semiconductor chips, which can be a split counter that does not drive logic on the semiconductor chip, but is used to attempt to "shadow" a clock signal on the other semiconductor chip of the pair. The shadow counter can be synchronized in response to receiving a predefined number of clock cycles.

[0014] After the shadow split counter is fully synchronized to the other semiconductor chip, the logic of the semiconductor chip can be stopped. The state machine of this semiconductor circuit can continue throughout the process even though the logic is stopped. After the logic is stopped, the split counter that drives this logic is synchronized / aligned to the shadow counter, and the logic is subsequently restarted. At this point, the two semiconductor circuits can be considered fully aligned and therefore can be made to high speed with minimal / zero skew.

[0015] For example, FIGS. 1A-1D show exemplary semiconductor chips 10A-10B (collectively "semiconductor chips 10," hereafter interchangeable with semiconductor circuits), each semiconductor chip 10 including one or more respective divide-by counters 12A-12C (collectively "divide-by counters 12") connected together via IOs 14. For purposes of clarity, only two semiconductor chips 10 are shown, but in other examples, a logic device may include three or more semiconductor chips 10. Similarly, for purposes of illustration, a single IO 14 is shown, but in many embodiments of the present disclosure, there would be a substantial number of IOs 14. Flowchart 30 of FIG. 2 includes a first sub-method 32 of synchronizing a clock at a slow clock speed, and then a second sub-method 50 of verifying the synchronization at a fast clock speed. This flow chart 30 shown in FIG. 2 is discussed with reference to FIG. 1A. Additionally, a second flow chart 80 detailing the synchronization of a clock at a slow clock speed shown in FIG. 3 is discussed with reference to FIGS. 1B-1D.

[0016] Both semiconductor chips 10 are set to a shared clock source (34). As discussed herein, both semiconductor chips 10 reside on a logic device. In some examples, the logic device may include this clock source (not shown) that provides an associated clock signal, while in other examples, the clock signal is received from a component external to the logic device. All semiconductor chips 10 are set to a slow clock speed (36) so that the semiconductor chips 10 operate at the same clock speed as the IO 14. After the slow clock speed is reached, the clock mesh for both chips 10 is deskewed (38), as discussed herein.

[0017] After being deskewed, the divide counters 12 for both chips 10 are synchronized (40). Flow diagram 80 of FIG. 3 further details synchronizing the divide counters 12 of the chips 10. After being synchronized, the chips 10 are switched to the fast clock speed, while the IOs 14 still operate at a slow clock speed that is a multiple (such as a 2:1 ratio) below the fast clock speed (42, 40). Although the IOs 14 do not operate at the fast clock speed, in some examples, the semiconductor chips 10 remain synchronized for an extended period of time (e.g., the life of the semiconductor chip). As discussed, in some embodiments, the clock distribution between the two semiconductor chips 10 is common / shared. This common clock distribution makes it unlikely, if not impossible, for the two semiconductor chips 10 to deviate (and thus become unsynchronized) as a result of the two semiconductor chips 10 being deterministically intertwined.

[0018] However, in some instances, something may break logically or physically in the life cycle of a logic device such that one of the semiconductor chips 10 may deviate. Sub-method 50 relates to a process for verifying that the semiconductor chips 10 remain synchronized while they are operating at a fast clock speed. Flowchart 30, as it continues with sub-method 50, begins with deskewing the clock meshes of both semiconductor chips 10 while both chips are at the fast clock speed (52), as described below. Once deskewed, one semiconductor chip 10A may send a pulse to the other semiconductor chip 10B to verify alignment.

[0019] For example, as would be understood by one of ordinary skill in the art, divided clock pulses are compared. This begins with switching the divN multiplexers (Mux) to the respective divided counters 14 (54). After receiving the pulses, the semiconductor chip 10 that received the pulses verifies the alignment of the pulses (56). For example, a divided clock pulse can be sent from semiconductor chip 10B to semiconductor chip 10A, followed by a pulse sent from semiconductor chip 10A and then back again to semiconductor chip 10A. Following this, the semiconductor chip 10 can verify the alignment using a quantitative skew sensor as discussed herein.

[0020] Specifically, if the pulse is aligned and within the measurement range (58), then the divN clock pulse is determined to be aligned (the "yes" branch from 58). Given that the alignment is confirmed, the verification process for the divN clock pulse is complete (64). In such a case, the semiconductor chip 10 may verify the alignment of other divN clock pulses. Otherwise, if the pulse is determined to be outside the predetermined measurement range (the "no" branch from 58), then the semiconductor chip 10 may calculate the state by which the pulse is out of sync (60). For example, the semiconductor chip 10 may determine whether the pulse was early or late, or the semiconductor chip 10 may determine the amount by which the pulse was early or late, or both. From here, the thold (derived from the counter state / value) is adjusted (62) by ±1 (or whatever number is calculated to align the pulse). Once adjusted, the semiconductor chip 10 would repeat this process of verifying pulse alignment until it could be determined that the semiconductor chip 10 was aligned at the fast clock speed (56).

[0021] As discussed herein, flowchart 80 of FIG. 3 illustrates a method for synchronizing two semiconductor chips 10 at a slow clock speed. Flowchart 80 will be discussed with respect to FIGS. 1B-1D. Flowchart 80 begins with both chips 10 operating at the same slow clock mesh speed, but the divided counters 12A, 12C that drive the logic of each chip 10 are not synchronized (82). As shown, the current "state" of the divided counters 12 shown in FIGS. 1B-1D is depicted in a pattern such that divided counter 12A has a diagonal line pattern, while divided counters 12B, 12C have a mesh pattern, as shown.

[0022] Flow diagram 80 continues with the chip 10 entering a synchronous mode (84). This involves the first chip 10A sending sync data to the second chip 10B, which captures this sync data in a shadow partition counter 12B (86). The shadow partition counter 12B does not drive any logic on chip 10B, but may exist primarily / exclusively to capture this sync data sent from chip 10A. After this sync data is received by the second chip 10B, the semiconductor chip 10 turns off the synchronous mode (88).

[0023] Now that the shadow division counter 12B has been synchronized with the division counter 12A of the semiconductor chip 10A, the semiconductor chip 10B can attempt to synchronize the division counter 12C with the shadow division counter 12B. Towards this goal, the semiconductor chip 10B can pause / stop all functional logic of the semiconductor chip 10B (90). The functional logic is stopped, but other functions such as the state machines of the semiconductor chip 10B are maintained. After the functional logic is stopped, the semiconductor chip 10B sets the primary division counter 12C to be aligned with the shadow division counter 12B (92). Now that all of the division counters 12 are aligned, the semiconductor chip 10 sends a realignment signal to the functional logic in response to which functional logic of the semiconductor chip 10B is to be resumed (96) (94).

[0024] A programmable delay line may be provided between the clock source and the clock domain. The programmable delay line may be adjusted to vary the skew between the first and second clock domains. In particular, the skew may be minimized to ensure proper data exchange between the first and second semiconductor circuits. There may be further applications requiring two periodic digital signals with a well-defined skew. Thus, the term "clock signal" as used herein may relate to any periodic digital signal.

[0025] FIG. 4 shows a logic device including a first semiconductor circuit A000 and a second semiconductor circuit B000.

[0026] The first semiconductor circuit A000 and the second semiconductor circuit B000 may correspond to computer processor chips, each computer chip may comprise a number of processor cores and a number of caches enabling exchange of data between different processor cores of the respective computer processor chips.

[0027] The first semiconductor circuit A000 can be adapted to write data directly into the latches of the second semiconductor circuit B000, and vice versa. Conventionally, it may be required that the first semiconductor circuit A000 and the second semiconductor circuit B000 operate at the same frequency and with minimal skew to avoid data loss.

[0028] The first semiconductor circuit A000 includes a first clock source A001 and a first programmable delay line A002. The clock source A001 can transmit a first clock signal clk_A, which propagates through the multiplexer A003 and the first programmable delay line A002 to a first clock domain via a first clock distribution network tree A004, which can also be referred to as a first clock tree. The first semiconductor circuit A000 can further include a first skew sensor A005 and a first skew controller A006. The first skew controller A006 can be configured to adjust the delay caused by the programmable delay line A002 based on an output of the first skew sensor A005.

[0029] The second semiconductor circuit B000 may be configured similarly to the first semiconductor circuit A000 and may include a second clock source B001, a second programmable delay line B002, a multiplexer B003, a second clock distribution network B004, a second skew sensor B005, and a second skew controller B006, where the second clock distribution network B004 may also be referred to as a second clock tree.

[0030] During operation of the logic device, only one of the two clock sources A001 and B001 is used. The first semiconductor circuit A000 and the second semiconductor circuit B000 can be operated independently of each other. In this case, each semiconductor circuit A000 and B000 can use its own clock source A001 and B001, respectively. In these situations, direct connections A030 and B030 from the clock sources A001 and B001 to the respective multiplexers A003 and B003 can be used. Alternatively, the first semiconductor circuit A000 and the second semiconductor circuit B000 can be operated together. Conventionally, both semiconductor circuits A000 and B000 can exchange data synchronously and only one of the two clock sources A001 and B001 can be used.

[0031] For purposes of explanation, it can be assumed that clock source A001 is used.

[0032] The power supply voltages of the first semiconductor circuit A000 and the second semiconductor circuit B000 can be independent of each other. A first group A100 of differential drivers and differential receivers and a second group B100 of differential drivers and differential receivers can be used to exchange signals with other semiconductor circuits. In particular, a voltage level different from the power supply voltage levels of the first semiconductor circuit A000 and the second semiconductor circuit B000 can be used for transmitting signals between the first semiconductor circuit A000 and the second semiconductor circuit B000.

[0033] Typically, a first clock source A001 transmits a clock signal via a differential driver to a differential receiver of the first semiconductor circuit A000 and a differential receiver of the second semiconductor circuit B000. Thus, any delay caused by the differential driver A111 affects the first semiconductor circuit A000 and the second semiconductor circuit B000 essentially in the same way.

[0034] The clock signal is then propagated through multiplexers A003 and B003, programmable delay lines A002 and B002, clock distribution networks A004 and B004, respectively, to differential drivers A112 and B112. Skew sensor B005 receives the clock signal from differential driver A112 as a first clock signal clk_A via differential receiver B122, and receives the clock signal from differential driver B112 as a second clock signal clk_B via differential receiver B123. Correspondingly, skew sensor A005 receives the clock signal from differential driver B112 via differential receiver A122, and receives the clock signal from differential driver A112 via differential receiver A123.

[0035] 5 and 6 focus on the context of skew sensor B005, but the corresponding explanations apply to skew sensor A005. In particular, Figures 5 and 6 show a first clock signal clk_A and a second clock signal clk_B.

[0036] Both the first clock signal clk_A and the second clock signal clk_B have the same cycle time t_cycle. For example, the cycle time of the first clock signal clk_A and the second clock signal clk_B may be 200ps. As shown in Figures 5 and 6, the duty cycle time t_duty of the first clock signal clk_A and the second clock signal clk_B may be half the cycle time t_cycle (|tree_off|>t_cycle / 2).

[0037] As explained above, the propagation of a clock signal from a clock source through a clock distribution network tree requires a certain amount of time, which can be referred to as clock tree latency. As shown in situation a) of FIG. 5 and FIG. 6, a first clock tree latency tree_A of a first semiconductor circuit A000 can be different from a second clock tree latency tree_B of a second semiconductor circuit B000. In particular, a clock tree latency offset tree_off, i.e., a difference between the second clock tree latency tree_B and the first clock tree latency tree_A, can be greater than one-half the cycle time (t_cycle / 2).

[0038] In the example shown in Figures 5 and 6, the second clock tree latency, tree_B, is greater than the first clock tree latency, tree_A. For example, the second clock tree latency, tree_B, can be 1160ps and the first clock tree latency, tree_A, can be 1000ps.

[0039] Typically, the skew between two clocks, say clk_A and clk_B, is minimized by aligning edges of the same type, i.e., the rising edge of clk_A and the rising edge of clk_B, or the falling edge of clk_A and the falling edge of clk_B. Minimizing the skew between two clocks can also be called deskewing. The clock tree latency (here, tree_B) of the clock (here, clk_B) to be deskewed relative to the other clock (here, clk_A) is increased or decreased by the minimum amount required to align two edges of the same type. Using the minimum amount required can have the advantage that less time can be required to deskew the two clocks.

[0040] If a clock (here, clk_B) to be deskewed relative to another clock (here, clk_A) is early relative to the other clock (here, clk_A), then the clock tree latency (here, tree_B) of the clock (here, clk_B) to be deskewed relative to the other clock (here, clk_A) is increased by the minimum amount required to align two edges of the same type.

[0041] If the clock to be deskewed (here, clk_B) is slower relative to the other clock (here, clk_A), the latency of the other clock tree (here, tree_A) is increased by the minimum amount required to align to the same type of edge.

[0042] For example, deskewing can be performed by increasing or decreasing the second clock tree latency tree_B. As shown in situation a) of Figure 5, the rising edge of cycle 1 of the second clock signal clk_B is closest to the rising edge of cycle 2 of the first clock signal clk_A. Therefore, the second clock tree latency tree_B is increased by an amount Δ+ so that the edges of the clock signals clk_A and clk_B are aligned.

[0043] In order to optimize the computational power and power consumption, the frequency at which the first semiconductor circuit A000 and the second semiconductor circuit B000 operate during the operation of the logic device can be changed. Reducing the frequency corresponds to a longer cycle time t_cycle. In situation c) of FIG. 5, the cycle time t_cycle of the clock signals clk_A and clk_B is twice as long as in situations a) and b). The clock signals clk_A and clk_B are no longer deskewed. The skew between the clock signals clk_A and clk_B is even larger than in the original situation a). Therefore, the clock signals clk_A and clk_B must be deskewed again.

[0044] 6 shows that in situation b), the rising edges of the clock signals clk_A and clk_B of the same cycle can be aligned by decreasing the second clock tree latency tree_B by an amount Δ-, and that in this situation, the two clock signals remain essentially deskewed when the first semiconductor circuit A000 and the second semiconductor circuit B000 operate at a lower frequency. Nevertheless, a small amount of skew (not shown) may exist due to different frequency dependencies of the first clock tree latency tree_A and the second clock tree latency tree_B.

[0045] FIG. 7 is a flow diagram illustrating an exemplary method for deskewing a second clock signal clk_B relative to a first clock signal clk_A. Step 401 describes determining a first clock tree latency tree_A and a second clock tree latency tree_B. The first clock tree latency tree_A can be determined using results of a simulation of a first semiconductor circuit A000. Similarly, the second clock tree latency tree_B can be determined using results of a simulation of a second semiconductor circuit B000. Alternatively, a measurement method can be used to determine the first clock tree latency tree_A or the second clock tree latency tree_B or both. In step 402, a cycle time t_cycle is set to a measurement cycle time that is longer than the longer of the first clock tree latency tree_A and the second clock tree latency tree_B. After the cycle time is set to the measurement cycle time, deskewing is performed (step 403). Since the clock cycle time is longer than the first clock tree latency tree_A and the second clock tree latency tree_B, it becomes impossible to align two corresponding edges of different cycles. The proposed method allows deskewing the first clock signal clk_A and the second clock signal clk_B such that the deskew condition can be essentially maintained over varying cycle times. After the deskewing is performed, the cycle time can again be set to the operating cycle time (step 404).

[0046] In the embodiment shown in Fig. 4, the first clock source A001 may be a phase-locked loop (PLL) clock that varies in phase with an external clock signal (not shown). Typically, the first clock source A001 emits a first clock signal clk_A having a frequency that is a rational multiple greater than that of the frequency of the external clock signal. In particular, a divider setting may be provided that divides the cycle time of the external clock signal to obtain a cycle time t_cycle for operating the first semiconductor circuit A000.

[0047] Setting the cycle time to the aforementioned measurement cycle time t_meas may include bypassing the first clock source A001 and operating the first semiconductor circuit A000 directly with the external clock signal, thereby reducing the need for additional components to vary the cycle time t_cycle.

[0048] Alternatively, setting the cycle time to the aforementioned measurement cycle time t_meas may include varying a divider setting of the first clock source A001. This may allow the measurement cycle time t_meas to be set closer to the longer of the first clock tree latency tree_A and the second clock tree latency tree_B. Accordingly, the measurement cycle time t_meas may be closer to the operational cycle time t_cycle, which may reduce the skew change caused by changing the cycle time from the measurement cycle time t_meas to the operational cycle time t_cycle. Furthermore, no additional components are required.

[0049] In a further example, a clock divider may be provided after the first clock source A001. The clock divider may be programmable and may allow the measurement cycle time t_meas to be set closely to the longer of the first clock tree latency tree_A and the second clock tree latency tree_B.

[0050] Different skew sensors can be used to deskew the second clock signal clk_B with respect to the first clock signal clk_A. A very simple skew sensor can only detect whether the second clock signal clk_B is slow with respect to the first clock signal clk_A. A skew sensor that only detects whether the second clock signal clk_B is slow with respect to the first clock signal clk_A can also be called a skew detector. Such a skew detector can be very simple to implement and can have a very small footprint.

[0051] If the skew detector detects that the second clock signal clk_B is late / early, the delay caused by the second programmable delay line can be sequentially decremented / incremented until the skew detector detects that the second clock signal clk_B is no longer late / early, i.e., the second clock signal clk_B is early / late with respect to the first clock signal clk_A. If the skew detector alternately detects that the second clock signal clk_B is late and that the second clock signal clk_B is not late, the first clock signal clk_A and the second clock signal clk_B can be considered to be deskewed.

[0052] If the original skew between the first clock signal clk_A and the second clock signal clk_B is large, it may take a long time to bring about a deskew condition by sequentially decrementing / incrementing the delay caused by the second programmable delay line.

[0053] Figures 10-11 show further skew sensors 5000, 6000, 7000, 8000 that can be used to deskew a first clock signal clk_A and a second clock signal clk_B. The skew sensors 5000, 6000, 7000, 8000 shown in Figures 9-11 are not only adapted to detect the skew between the second clock signal clk_B and the first clock signal clk_A, but also adapted to measure the quantitative skew between the second clock signal clk_B and the first clock signal clk_A.

[0054] Each of the skew sensors 5000, 6000, 7000, 8000 includes at least two skew detectors 5101-5107, 6101-6107, 7101-7107, and 8101-8107, respectively. The skew detectors 5101-5107, 6101-6107, 7101-7107, and 8101-8107 detect the skew between two input signals. Each of the skew sensors 5000, 6000, 7000, 8000 includes one or more delay elements 5201-5203, 5205-5207, 6201-6203, 6205-6207, 7201-7203, 7205-7207, 8201-8203, 8205-8207. At least one skew detector 5101-5103, 5105-5107, 6101-6103, 6105-6107, 7101-7103, 7105-7107, 8101-8103, 8105-8107 receives either a first clock signal clk_A or a second clock signal clk_B as a first input signal, and receives the other of the first clock signal clk_A and the second clock signal clk_B delayed by a first delay difference caused by one or more delay elements as a second input signal. Another of the skew detectors 5101-5107, 6101-6107, 7101-7107, 8101-8107 receives either the first clock signal clk_A or the second clock signal clk_B as a first input signal, and receives the other of the first clock signal clk_A and the second clock signal clk_B optionally delayed by a second delay difference caused by one or more delay elements as a second input signal, where the second delay difference is different from the first delay difference.

[0055] The skew sensors 5000, 6000, 7000, 8000 make it possible to determine whether the skew between a first clock signal clk_A and a second clock signal clk_B is within a certain range.

[0056] Skew sensors 5000, 6000, 7000, 8000 use skew detectors 5101-5107, 6101-6107, 7101-7107, and 8101-8107. Skew detectors 5101-5107, 6101-6107, 7101-7107, and 8101-8107 detect whether an input signal at an input indicated by a small triangle is late relative to the other input signal. If this is true, skew detectors 5101-5107, 6101-6107, 7101-7107, and 8101-8107 transmit a "1". If not, skew detectors 5101-5107, 6101-6107, 7101-7107, and 8101-8107 transmit a "0".

[0057] Skew detectors 5101-5107, 6101-6107, 7101-7107, and 8101-8107 may correspond to D flip-flops. The inputs of skew detectors 5101-5107, 6101-6107, 7101-7107, and 8101-8107 indicated by small triangles may be referred to as clock inputs, and the other inputs of skew detectors 5101-5107, 6101-6107, 7101-7107, and 8101-8107 may be referred to as data inputs. Therefore, these names are used for the inputs of skew detectors 5101-5107, 6101-6107, 7101-7107, and 8101-8107 in the following description, even though skew detectors 5101-5107, 6101-6107, 7101-7107, and 8101-8107 do not necessarily correspond to D flip-flops.

[0058] The skew sensor 5000 comprises a first subset of delay elements 5201-5203 and a second subset of delay elements 5205-5207. Each delay element 5201-5203 of the first subset is disposed between the second clock signal clk_B and a clock input of a corresponding skew detector 5101-5103. For example, the delay element 5201 is disposed between the second clock signal clk_B and the skew detector 5101. Each delay element 5205-5207 of the second subset is disposed between the first clock signal clk_A and a data input of a corresponding skew detector 5105-5107.

[0059] The induced delay may increase from delay element 5203 to delay element 5201 and may increase from delay element 5205 to delay element 5207. In particular, the delay may increase by a delay increment D. The delay elements 5201-5203, 5205-5207 may comprise an even number of inverters.

[0060] In the example shown in Fig. 8, the delay caused by delay elements 5203-5201 and 5205 and 5207 always increases by the same increment D from the central skew detector 5104 to the next skew detector. However, it is also possible to select the delay steps differently. For example, the delay steps near the central skew detector 5104 can be smaller than the delay steps further away from the central skew detector 5104. Vice versa, the delay steps near the central skew detector 5104 can also be larger than the delay steps further away from the central skew detector 5104.

[0061] Seven skew detectors 5101-5107 are shown in Fig. 8. However, skew sensor 5000 can also be equipped with fewer or more skew detectors 5101-5107 to allow measuring the skew in finer or coarser steps. The same applies to skew sensors 6000, 7000 and 8000.

[0062] 11 shows a skew sensor 8000 that is very similar to skew sensor 5000. Instead of separate delay elements 5201-5203 and 5205-5207 being directly connected to the second clock signal clk_B and the first clock signal clk_A, respectively, a subset of delay elements 8201-8203 and 8205-8207 are provided as a chain. Delay element 8203 is directly connected to the second clock signal clk_B, delay element 8202 is connected to delay element 8203, and so on. Correspondingly, delay element 8205 is directly connected to the first clock signal clk_A, delay element 8206 is connected to delay element 8205, and so on. The clock inputs of skew detectors 8101-8104 and the data inputs of skew detectors 8105-8107 are connected to the nodes of the chains of delay elements 8201-8203 and 8205-8207, respectively.

[0063] Thus, each delay element 8201-8203, 8205-8207 defines an additional delay between two adjacent skew detectors 8105-8107. By using chains of delay elements 8201-8203 and 8205-8207, the total area required for the delay elements on the respective semiconductor circuit can be reduced.

[0064] The skew sensor 6000 shown in FIG. 9 comprises two subsets of delay elements 6201-6203 and 6205-6207 arranged as a chain as in the skew sensor 8000. The delay elements 6201-6203, 6205-6207 may comprise one inverter or an odd number of inverters. A single inverter may induce a particularly short delay. The use of inverters as the delay elements 6201-6203, 6205-6207 may require connecting the undelayed first clock signal clk_A and the undelayed second clock signal clk_B to the clock inputs of the skew detectors 6101-6103 and 6104-6107, respectively.

[0065] Provided that the same delays are caused by the delay elements 6201-6203, 6205-6207 and delay elements 8201-8203, 8205-8207, the inverter may be required to have a skew sensor 6000 transmitting the same output signal as the skew sensors 5000 and 8000, so that at the outputs of the skew detectors 6102, 6105, 6107 the second clock signal clk_B has the same skew relative to the first clock signal clk_A.

[0066] Fig. 10 shows a further example of a skew sensor 7000. The skew sensor 7000 is similar to the skew sensor 6000. In particular, a non-delayed first clock signal clk_A and a non-delayed second clock signal clk_B are connected to the clock inputs of the skew detectors 7101-7103 and 7104-7107, respectively. However, the delay elements 7201-7203, 7205-7207 do not invert the delayed signals. Accordingly, the outputs of the skew detectors 7101-7103 must be inverted, and the outputs of the skew detectors 7104-7107 remain non-inverted.

[0067] 12 shows output signals of skew sensors 5000, 6000, 7000, and 8000 for the indicated first and second clock signals clk_A and clk_B with different skew values ​​in situations a), b), c), d), and e). It is assumed that the value of the delay difference caused by the different delay elements between the two inputs of skew detectors 5102, 6102, 7102, 8102, 5106, 6106, 7106, and 8106 is smaller than half the cycle time, and that the value of the delay difference caused by the different delay elements between the two inputs of skew detectors 5101, 6101, 7101, 8101, 5107, 6107, 7107, and 8107 is larger than half the cycle time.

[0068] In situation a), the skew between the first clock signal clk_A and the second clock signal clk_B is essentially zero. In situation b), the second clock signal clk_B is slower than the first clock signal clk_A by a quarter (1 / 4) of the cycle time. In situation c), the second clock signal clk_B is faster than the first clock signal clk_A by a quarter (1 / 4) of the cycle time. In situation d), the second clock signal clk_B is slower than the first clock signal clk_A by just under one-half (1 / 2) of the cycle time. In situation e), the second clock signal clk_B is faster than the first clock signal clk_A by just under one-half (1 / 2) of the cycle time.

[0069] The skew detectors 5101-5107, 6101-6107, 7101-7107, and 8101-8107 can only detect which input signal is late with respect to the other input signal. These skew detectors cannot transmit an output signal indicating that the input signals arrive at exactly the same time. Thus, in hypothetical situation a), the skew detectors 5104, 6104, 7104, and 8104 can transmit as output signal out_0 of the skew sensors 5000, 6000, 7000, 8000 either a "0" indicating that the second clock signal clk_B is late with respect to the first clock signal clk_A, or a "1" indicating that the second clock signal clk_B is early with respect to the first clock signal clk_A. An "x" in this table indicates an undetermined value of the output signal out_0.

[0070] The skew detector 5103 receives the second clock signal clk_B with the additional delay caused by the delay element 5203. In response, the skew detector 5103 determines that the input signal associated with clk_B is now late with respect to the (non-delayed) first clock signal clk_A. Thus, the skew detector 5103 transmits a "0" as the output signal out_1.

[0071] Vice versa, the skew detector 5105 receives the first clock signal clk_A with the additional delay caused by the delay element 5205. Thus, the skew detector 5105 now determines that the input signal associated with the (non-delayed) second clock signal clk_B is early with respect to the (delayed) first clock signal clk_A. In response, the skew detector 5105 transmits a "1" as the output signal out_-1.

[0072] Correspondingly, skew sensor 5000 transmits a “1” for all output signals up to and including output signal out_-(n-1) and transmits a “0” for all output signals up to and including output signal out_(n-1).

[0073] The skew detector 5101 receives the second clock signal clk_B with an additional delay caused by the delay element 5201. The additional delay is greater than one-half of the cycle time of the second clock signal clk_B. Thus, the skew detector 5105 no longer compares the edge of the second clock signal clk_B with the edge of the first clock signal clk_A in the same cycle, but with the edge of the first clock signal clk_A in the next cycle. In response, the skew detector 5101 determines that the input signal associated with the second clock signal clk_B is early with respect to the first clock signal clk_A, and the skew detector 5101 transmits a "1" as the output signal out_n. Vice versa, the skew detector 5107 transmits a "0" as the output signal out_-n.

[0074] In situation b), the second clock signal clk_B is late with respect to the first clock signal clk_A. In response, the skew detector 5104 transmits a "0" as the output signal out_0. Further delaying the second clock signal clk_B by an amount less than one-quarter (1 / 4) of a clock cycle increases the skew between the second clock signal clk_B and the first clock signal clk_A. Thus, the skew detector 5103 also transmits a "0" as the output signal out_1. On the other hand, delaying the first clock signal clk_A by an amount less than one-quarter (1 / 4) of a cycle is not sufficient to make the input signal associated with the second clock signal clk_B of the skew detector 5105 early with respect to the first clock signal clk_A. Thus, the skew detector 5105 also transmits a "0" as the output signal out_-1.

[0075] Further delaying the first clock signal clk_A ultimately makes the first clock signal clk_A slower with respect to the second clock signal clk_B. Thus, the skew detector 5106 transmits a "1" as the output signal out_-(n-1). With further delay, the skew detector 5107 no longer compares the two edges of different clock cycles. Thus, the skew detector 5107 also transmits a "1" as the output signal out_-n.

[0076] However, if the second clock signal clk_B is delayed further, the skew detector compares edges of different clock cycles. Thus, the skew detector no longer transmits an output signal indicating that the second clock signal clk_B is late, but transmits an output signal indicating that the second clock signal clk_B is early. In response, the skew detectors 5101 and 5102 transmit a "1" as output signals out_(n-1) and out_n, respectively.

[0077] In situation c), the second clock signal clk_B is early with respect to the first clock signal clk_A. Thus, the skew detector 5104 transmits a "1" as the output signal out_0. Delaying the first clock signal clk_A by less than one-quarter (1 / 4) of a clock cycle increases the skew between the second clock signal clk_B and the first clock signal clk_A. In response, the skew detector 5103 also transmits a "1" as the output signal out_1. Delaying the second clock signal clk_B by less than one-quarter (1 / 4) of a cycle is not sufficient to make the input signal associated with the second clock signal clk_B of the skew detector 5105 late with respect to the first clock signal clk_A. Thus, the skew detector 5105 also transmits a "1" as the output signal out_-1.

[0078] Further delaying the second clock signal clk_B ultimately causes the first clock signal clk_A to be earlier with respect to the second clock signal clk_B. Thus, the skew detector 5102 transmits a "0" as the output signal out_-(n-1). With further delay, the skew detector 5101 no longer compares the two edges of different clock cycles. In response, the skew detector 5101 also transmits a "0" as the output signal out_-n.

[0079] On the other hand, if the first clock signal clk_A is delayed further, the skew detector will compare edges of different clock cycles. Thus, the skew detector will no longer transmit an output signal indicating that the second clock signal clk_B is early, but will transmit an output signal indicating that the second clock signal clk_B is late. In response, the skew detectors 5106 and 5107 will transmit "0" as output signals out_(n-1) and out_n.

[0080] In situation d), the skew detector 5104 determines that the second clock signal clk_B is late with respect to the first clock signal clk_A. In response, the output signal out_0 indicates "0". Further delaying the second clock signal clk_B leads to a situation where the skew detector 5103 determines the skew between different cycles, so that the output signal out_-1 indicates "1". This continues until the induced delay is greater than half the cycle time and the rising edge of the second clock signal clk_B reaches the rising edge of the next cycle of the first clock signal clk_A. In response, the output out_-n indicates "0".

[0081] The skew detector 5105 still transmits a "0" because the delay of the received signal relative to the first clock signal clk_A is not enough to make the received second clock signal clk_B earlier with respect to the received delayed first clock signal clk_A. Only when the induced delay becomes greater than half the cycle time does the output change and the output signal out_n indicates a "1".

[0082] In situation e), the skew detector 5104 determines that the second clock signal clk_B is early with respect to the first clock signal clk_A. Thus, the output signal out_0 indicates "1". The output signal remains "1" until the second clock signal clk_B is delayed by an amount greater than half the cycle time. Then, the output signal out_n transmits "0". On the other hand, by delaying the first clock signal clk_A, the skew detector 5105 compares the edges of different cycles. Thus, the skew detector transmits "0". This continues until a delay greater than half the cycle time is introduced, and the output out_n indicates "1" again.

[0083] 12 has been essentially described with reference to skew sensor 5000, the same reasoning applies to skew sensors 6000, 7000, and 8000.

[0084] A skew sensor that measures quantitative skew can make it possible to measure clock tree latency in a semiconductor circuit. Measuring clock tree latency can be particularly useful for the method of deskewing a second clock signal relative to a first clock signal described with reference to FIG.

[0085] FIG. 13 shows a simplified method for measuring clock tree latency in a semiconductor circuit, the semiconductor circuit comprising a clock source generating a clock signal, a programmable delay line, a clock tree, and a quantitative skew sensor measuring the skew between the delayed clock signal and the (original) clock signal propagated successively through the programmable delay line and the clock tree.

[0086] In the idle state of a semiconductor circuit, the clock tree latency varies by a bounded amount due to noise, and therefore the quantitative (signed) skew between the delayed and original clock signals, as measured by a quantitative skew sensor, also varies by a bounded amount.

[0087] In step 1001, a minimum skew, skew_min, is selected that is greater than 0 and sufficiently greater than the expected maximum variation in skew in the semiconductor circuit's idle state.

[0088] The current quantitative skew between the delayed clock signal and the original clock signal is measured and stored (step 1002).

[0089] The delay caused by the programmable delay line is changed by an amount dly_change and a counter is initialized (step 1003). The delay can be decreased or increased. Thus, the delay change dly_change can be a positive or negative value. The absolute value of the delay change dly_change is selected to be above the minimum skew skew_min and below the difference between the cycle times t_cycle and skew_min.

[0090] At the next clock cycle, the counter is incremented and the current quantitative skew skew_meas is measured (step 1004).

[0091] The measured skew_meas is compared to the stored skew_stored (step 1005). If the absolute value of the difference between the measured skew_meas and the stored skew_stored is less than or equal to the minimum skew_min, the method repeats steps 1004 and 1005. If the absolute value of the difference between the measured skew_meas and the stored skew_stored is greater than the minimum skew_min, the number of cycles t_cycle measured by the counter (step 1006) is determined to be a first control system response time (CSRT). The control system response time may indicate how long it takes from changing the delay caused by the programmable delay line prgdly until the change is observable by the associated skew sensor. The control system response time may essentially correspond to measuring the clock tree latency of the associated clock tree.

[0092] In one embodiment of the above-mentioned method, after determining the first control system response time, the currently measured skew skew_meas is stored as skew_stored, the delay caused by the programmable delay line prgdly is changed by an amount -dly_change, and the counter is reinitialized. The currently measured skew skew_meas is compared to the stored skew skew_stored. If the absolute value of the difference between the measured skew skew_meas and the stored skew skew_stored is less than or equal to the minimum skew skew_min, the method repeats measuring the skew and comparing the measured skew skew_meas to the stored skew skew_stored. If the absolute value of the difference between the measured skew skew_meas and the stored skew skew_stored is greater than the minimum skew skew_min, the number of cycles t_cycle measured by the counter is determined to be the second control system response time. The control system response time can then be determined to be the maximum of the first control system response time and the second control system response time. Alternatively, the control system response time may be determined to be an average of the first control system response time and the second control system response time.

[0093] Another embodiment may provide that changing the delay by an amount dly_change includes changing the delay caused by the programmable delay line by dly_change to cause a change in the direction of the skew, and comparing the measured skew skew_meas to the stored skew skew_stored includes detecting a change in the direction of the measured skew. Detecting a changing skew direction may reduce the number of bits compared per cycle.

[0094] During operation of the logic device, the second clock signal, clk_B, may need to be continuously deskewed with respect to the first clock signal, clk_A, because voltage droop, changes in cycle time, etc. may affect the first clock tree latency and / or the second clock tree latency.

[0095] If at a first time the second clock signal is to be deskewed relative to the first clock signal and the second clock signal is slow relative to the first clock signal, the skew control system can reduce a delay caused by a programmable delay line associated with the second clock signal.

[0096] Due to the second clock tree latency, the skew detector typically observes the change in delay caused by the programmable delay line only after a few clock cycles. Thus, during the next cycle, the skew sensor still measures the skew and further reduces the delay caused by the programmable delay line. This may result in a negative skew between the second clock signal and the first clock signal that has an even larger absolute value than the original (positive) skew between the second clock signal and the first clock signal.

[0097] 14 shows an example of an improved method for continuously adjusting the skew between the second clock signal clk_B and the first clock signal clk_A. Some steps of the method according to FIG. 14 may be optional and are described accordingly after the main steps.

[0098] First, the control system response time of the clock tree to be tuned is determined (step 1101), which may be determined using a simulation method or may be determined using the method described with respect to FIG.

[0099] Additionally, a history lookup unit is initialized (step 1102) which maintains history data relating to skew control commands.

[0100] A quantitative skew, skew_meas, between the second clock signal and the first clock signal is measured (step 1103).

[0101] A skew control command is generated based on the historical data, in particular the sum of the delay changes initiated within the time window preceding this measurement and the measured quantitative skew (step 1104). For example, if the measured quantitative skew skew_meas is greater than the inverse of the accumulated delay change forwardAdj as indicated by the history observation unit, the skew control command corresponds to a delay decrease. Otherwise, the skew control command corresponds to a delay increase.

[0102] The delay of the programmable delay lines in the clock tree is adjusted based on the skew control command (step 1105), and the history observation unit is updated with the current skew control command (step 1106). Steps 1103-1106 are repeated for every clock cycle to continuously adjust the skew.

[0103] The history observation unit maintains historical data relating to skew control commands within a particular time window, which may be dependent on the control system response time.

[0104] An optional step 1107 may set a target skew_target greater than 0 (skew_target>0). A skew having an absolute value below the target skew_target may correspond to a deskew state of the second clock signal clk_B and the first clock signal clk_A.

[0105] Furthermore, an optional step 1108 before step 1104 can check whether the absolute value of the difference between the measured quantitative skew skew_meas and the inverse of the accumulated delay change forwardAdj is below the target skew skew_target (|skew_meas-(-forwardAdj)| <skew_target)。

[0106] If this is the case, the skew control command does not change the delay caused by the programmable delay line (step 1109). If not, the method proceeds to step 1104. Using a target skew skew_target can avoid the delay caused by the programmable delay line being changed too frequently. This can help to avoid jitter and power consumption.

[0107] A further optional step 1110 can set an allowable skew_adm larger than the target skew_target. The allowable skew_adm can correspond to an absolute value to which the measured skew can rise after the first clock signal clk_A and the second clock signal clk_B have been deskewed before the two clock signals have to be deskewed again. Within step 1110 it is also possible to set a deskewed flag (set deskewed:=0?) that the first clock signal clk_A and the second clock signal clk_B are not deskewed.

[0108] After the measurement step 1103, optional step 1111 may determine whether the deskew flag indicates that the first clock signal clk_A and the second clock signal clk_B have been deskewed (deskewed=0?). If the first clock signal clk_A and the second clock signal clk_B have not been deskewed (deskewed=0), the method proceeds to step 1104 as described above. Otherwise, the method proceeds to step 1112.

[0109] Optional step 1112 may determine whether the absolute value of the difference between the measured skew skew_meas and the inverse of the accumulated delay change forwardAdj is greater than the allowable skew skew_adm (|skew_meas-(-forwardAdj)|>skew_adm).

[0110] If this is the case, then the deskewed flag is set in step 1113 to indicate that the first clock signal clk_A and the second clock signal clk_B are not deskewed (set deskewed:=0) and the skew control value (skew_ctr) is set to 0 (step 1109). If not, the deskewed flag is set to 1 (1114) and the method directly sets the skew control value (skew_ctr) to 0.

[0111] Steps 1101, 1106, and 1102 may be performed in a different order than that shown in Figure 14. For example, the method may begin with step 1102, followed by step 1101, and then step 1106.

[0112] 15 and 16 may provide a more detailed understanding of steps 1103, 1104, 1105, and 1106 of FIG.

[0113] Instantaneous changes in the programmable delay line prgdly during operation of the logic device may result in a very short (temporary) cycle time (cycle compression) t_cycle. In particular, the cycle time t_cycle may become too short to ensure proper computation, data propagation, etc. Thus, during operation of the semiconductor circuit, the two different clocks should not be deskewed immediately, but rather the skew should be reduced by gradually incrementing or decrementing the delays caused by the respective programmable delay lines. Accordingly, the following description is based on incremental or decremental delay changes. However, during initialization of the logic device, larger delay changes may also be used to facilitate fast deskew of the clock signals.

[0114] Figure 15 shows the skew measured by the skew sensor over several clock cycles. For simplicity, we assume that the skew is only affected by changing the delay caused by the programmable delay line. We further assume that the delay has not changed recently. At the beginning of the observation period, the measured skew is 6 units. The skew sensor measures the skew, and the skew control unit compares the measured skew, skew_meas, to past skew control commands. Because the delay has not changed recently, the skew control unit determines that the measured skew is greater than the inverse of the accumulated delay change, forwardAdj. More precisely, the difference between the measured skew and the inverse of the accumulated delay change, forwardAdj, is 6 units (see the bottom diagram of Figure 15). The skew control unit therefore controls the programmable delay line, prgdly, to reduce the delay caused by the programmable delay line, prgdly, by 1 unit. This is indicated by the "-1" for the next cycle down the x-axis of this diagram.

[0115] Furthermore, the history observation unit stores the information that the skew control unit controlled the programmable delay line prgdly to reduce the delay caused by the programmable delay line prgdly by one unit.

[0116] During the next cycle, the modified setting of the programmable delay line prgdly still does not change the skew. Due to the latency of the clock tree, the reduction becomes observable at the skew sensor only after a certain time, which in this example is assumed to be 6 cycles. In response, the skew sensor still measures a skew_meas of 6 units (see the top diagram of Figure 15). The skew control unit still determines that the measured skew skew_meas of 6 units is greater than the reciprocal of the accumulated delay change forwardAdj of 1 unit. Therefore, the skew control unit controls the programmable delay line prgdly to further reduce the delay caused by the programmable delay line prgdly by 1 unit and updates the history observation unit accordingly, which indicates "-2" in the next cycle.

[0117] During the next cycle, the difference between the measured skew skew_meas and the accumulated delay change forwardAdj continuously decreases until it reaches 0, and the skew control unit does not further change the delay caused by the programmable delay line prgdly even though the measured skew is still 6 units. Nevertheless, the measured skew skew_meas is still decreased by the previous delay changes propagating through the clock tree, and finally reaches 0.

[0118] If the skew control unit did not compensate for delay changes still propagating through the clock tree, but only considered the currently measured skew, the skew should be negative, as shown by the dotted line.

[0119] Figure 16 shows an example where the skew changes from the fourth cycle to the fifth cycle, i.e. before any changed delay caused by the programmable delay line prgdly can be observed by the skew sensor. Such a skew change can occur, for example, as a result of voltage droop. As a result, the measured skew skew_meas becomes smaller than the inverse of the accumulated delay change forwardAdj, and the skew control unit controls the programmable delay line prgdly to increment the delay caused by the programmable delay line prgdly. Thus, the clock signal can be quickly deskewed again.

[0120] A skew sensor is proposed comprising at least two skew detectors, each skew detector detecting a skew between two input signals, the first skew detector receiving either the first clock signal or the second clock signal as a first input signal and receiving the other of the first clock signal and the second clock signal delayed by a first delay difference caused by one or more delay elements as a second input signal, the second skew detector receiving either the first clock signal or the second clock signal as a first input signal and receiving the other of the first clock signal and the second clock signal optionally delayed by a second delay difference caused by one or more delay elements, the second delay difference being different from the first delay difference, and the skew control unit measures the skew between the first clock signal and the second clock signal using the skew sensor.

[0121] In one embodiment of the skew sensor, at least one of the delay elements comprises an inverter.

[0122] In another embodiment of the skew sensor, at least one delay element is a programmable delay line.

[0123] In a further embodiment of the skew sensor, the at least one skew detector comprises a D flip-flop.

[0124] In one embodiment of the skew sensor, the skew sensor comprises a first subset of skew detectors including a first skew detector and a second skew detector, the skew sensor comprises a first chain of delay elements, the first skew detector receives the other of the first clock signal and the second clock signal delayed by the first delay difference as a second input signal via a first node of the first chain of delay elements, and the second skew detector receives the other of the first clock signal and the second clock signal delayed by the second delay difference as a second input signal via a second node of the first chain of delay elements.

[0125] In another embodiment of the skew sensor, the delay elements are inverters, an odd number of inverters are provided between the first node and the second node, and an inverter is provided between the output of either the first skew detector or the second skew detector and the corresponding output of the skew sensor.

[0126] In a further embodiment of the skew sensor, the skew sensor comprises a first chain of one or more delay elements and a separate second chain of one or more delay elements, where the first skew detector and the second skew detector receive either the first clock signal or the second clock signal as a first input, the second skew detector receives the first clock signal as a first input, the first skew detector receives the other of the first clock signal and the second clock signal delayed by the first chain of delay elements, and the second skew detector receives the other of the first clock signal and the second clock signal delayed by the second chain of delay elements.

[0127] In one embodiment of the skew sensor, the first skew detector receives a first clock signal as a first input signal, the first skew detector receives a second clock signal delayed by a first delay as a second input signal, the second skew detector receives the second clock signal as a first input signal, and the second skew detector receives the first clock signal delayed by a second delay as a second input signal, and an inverter is provided between an output of either the first skew detector or the second skew detector and a corresponding output of the skew sensor.

[0128] In another embodiment of the skew sensor, a first skew detector receives a second clock signal as a first input signal, the first skew detector receives the first clock signal delayed by a first delay as a second input signal, and a second skew detector receives the second clock signal as the first input signal, and the second skew detector receives the first clock signal delayed by a second delay as the second input signal.

[0129] In a further embodiment of the skew sensor, the delay caused by a single delay element of the first chain of one or more delay elements increases from the nth delay element of the first chain of one or more delay elements to the mth delay element of the first chain of one or more delay elements, where m is greater than n.

[0130] In one embodiment of the skew sensor, the delay caused by a single delay element of the first chain of one or more delay elements decreases from the nth delay element of the first chain of one or more delay elements to the mth delay element of the first chain of one or more delay elements, where m is greater than n.

[0131] In another embodiment of the skew sensor, n is 1 and a first delay element in a first chain of one or more delay elements receives the second clock signal.

[0132] The description of various embodiments has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used in this specification have been selected to best explain the principles of the embodiments, practical applications, or technical improvements over the art found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. A method comprising: setting a first clock of the first semiconductor circuit and a second clock of the second semiconductor circuit to a common clock source when both first and second semiconductor circuits are at a slower clock speed, wherein an input / output (IO) at an interface between the first semiconductor circuit and the second semiconductor circuit is capable of operating at the slower clock speed; synchronizing a first divide counter of the first clock and a second divide counter of the second clock at the slower clock speed; and simultaneously switching both the first and second semiconductor circuits to a faster clock speed that is a multiple of the slower clock speed, wherein the IO is not capable of operating at the faster clock speed.

2. shadowing the first divided counter onto a third divided counter on the second semiconductor circuit using pulses of the first divided counter; 2. The method of claim 1, further comprising: comparing the third divide counter to the second divide counter.

3. 3. The method of claim 2, wherein the pulse is transmitted periodically from the first divided counter at a unique predetermined numerical state of the first divided counter.

4. Detecting a difference between the third divide-by counter and the second divide-by counter; Disabling the functional logic of the second semiconductor circuit; aligning the second divide counter and the third divide counter while the function logic is stopped; 3. The method of claim 2, further comprising: restarting the function logic after the second divide counter is aligned with the third divide counter such that each of the second divide counter, the third divide counter, and the first divide counter are all synchronized.

5. 5. The method of claim 4, wherein after the first and second divide counters are synchronized, data content is frozen for several cycles when the functional logic is stopped and restarted such that data content is maintained without loss.

6. 5. The method of claim 4, wherein a state machine of the second semiconductor circuit is operating while the functional logic is disabled.

7. 2. The method of claim 1, further comprising deskewing a clock mesh of both the first and second semiconductor circuits at the slower clock speed.

8. 2. The method of claim 1, further comprising deskewing a clock mesh of both said first and second semiconductor circuits at said faster clock speed.

9. 1. A system comprising: a first semiconductor circuit including a first clock and a first divide counter, the first semiconductor circuit configured to perform operations at both a slow clock speed and a fast clock speed, the fast clock speed being an even multiple of the slow clock speed; a second semiconductor circuit including a second clock and a second divide counter configured to perform operations at both the slower clock speed and the faster clock speed; and an input / output (IO) at an interface between the first semiconductor circuit and the second semiconductor circuit capable of operating at the slower clock speed but not the faster clock speed, the first and second semiconductor circuits comprising: setting the first and second clocks to a common clock source when the first and second semiconductor circuits are at the slow clock speed; synchronizing said first and second divide counters at said slower clock speed; the systems being configured to simultaneously switch to said faster clock speed.

10. The first and second semiconductor circuits include using a pulse of the first divided counter to shadow the first divided counter onto a third divided counter on the second semiconductor circuit; The system of claim 9 , further configured to compare the third division counter to the second division counter.

11. 11. The system of claim 10, wherein the pulse is transmitted periodically from the first divided counter at a unique predetermined numerical state of the first divided counter.

12. The first and second semiconductor circuits include Detecting a difference between the third divided counter and the second divided counter; Disabling the functional logic of the second semiconductor circuit; aligning the second divide counter and the third divide counter while the function logic is stopped; 12. The system of claim 11, further configured to restart the function logic after the second divide counter is aligned with the third divide counter such that each of the second divide counter, the third divide counter, and the first divide counter are all synchronized.

13. 13. The system of claim 12, wherein after the first and second divide counters are synchronized, data content is frozen for several cycles when the functional logic is stopped and restarted such that data content is maintained without loss.

14. 13. The system of claim 12, wherein a state machine of the second semiconductor circuit is operating while the functional logic is disabled.

15. 10. The system of claim 9, wherein the first and second semiconductor circuits are further configured to deskew a clock mesh of both the first and second semiconductor circuits at the slower clock speed.

16. 10. The system of claim 9, wherein the first and second semiconductor circuits are further configured to deskew a clock mesh of both the first and second semiconductor circuits at the faster clock speed.

17. 1. A method comprising: setting a first clock of the first semiconductor circuit and a second clock of the second semiconductor circuit to a common clock source when both first and second semiconductor circuits are at a slower clock speed, wherein an input / output (IO) at an interface between the first semiconductor circuit and the second semiconductor circuit is capable of operating at the slower clock speed; synchronizing a first divide counter of the first clock and a second divide counter of the second clock at the slower clock speed; simultaneously switching both the first and second semiconductor circuits to a faster clock speed that is a multiple of the slower clock speed, the IO being unable to operate at the faster clock speed; shadowing the first divided counter onto a third divided counter on the second semiconductor circuit using pulses of the first divided counter; comparing the third divide counter with the second divide counter; Detecting a difference between the third divide-by counter and the second divide-by counter; Disabling the functional logic of the second semiconductor circuit; aligning the second divide counter and the third divide counter while the function logic is stopped; and restarting the function logic after the second divide counter is aligned with the third divide counter such that each of the second divide counter, the third divide counter, and the first divide counter are all synchronized.

18. 18. The method of claim 17, wherein the pulse is transmitted periodically from the first divided counter at a unique predetermined numerical state of the first divided counter.

19. 20. The method of claim 17, wherein after the first and second divide counters are synchronized, data content is frozen for several cycles when the functional logic is stopped and restarted such that data content is maintained without loss.

20. deskewing the clock meshes of both the first and second semiconductor circuits at the slower clock speed; 20. The method of claim 17, further comprising: deskewing a clock mesh of both the first and second semiconductor circuits at the faster clock speed.

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