Method for producing polycrystalline silicon carbide usable in the manufacture of integrated circuit substrates, and silicon carbide thus obtained

Abstract

The invention relates to a method for producing a plate made of polycrystalline SiC doped on a graphite surface by chemical deposition, characterized in that a gas mixture is introduced into a heated chamber to generate a gas phase containing at least one gaseous precursor of silicon and / or carbon, at least one dopant gas containing at least one nitrogen atom, and a carrier gas, and the gas mixture is decomposed on the graphite surface to form a layer of polycrystalline SiC, the temperature in the reactor being between 1450 K and 1650 K and the total partial pressure of the gaseous precursors being less than 350 mbar. The plate has a texture coefficient C 422 is less than 30%, and (ii.a) the texture coefficient C 220 is greater than 60%, or (ii.b) the texture coefficient C 111 +C 222 +C 511 The sum of these is greater than 70%.

Description

[Technical field]

[0001] The present invention relates to the field of material science, more particularly to the field of materials that can be used to manufacture substrates for integrated circuits, and to the processes for manufacturing these materials. More specifically, it concerns polycrystalline silicon carbide. This material, like all materials for microelectronic substrates, is implemented in the form of thin pieces (those skilled in the art often use the English term "wafer" in French), whose shape is generally circular. SiC is particularly suitable for the manufacture of substrates for power electronic components. SiC wafers must meet very strict specifications regarding their flatness, uniformity of properties and freedom from defects.

[0002] The present invention provides a new type of multi-crystalline SiC wafer that can be used in the manufacture of integrated circuit substrates, these wafers having specific crystallographic properties.

[0003] Since integrated circuits are generally deposited on the surface of a single crystal semiconductor, in the case of a polycrystalline silicon carbide wafer, the electronically active surface (i.e., the surface on which the integrated circuits are to be deposited) must be specially prepared by transferring a layer of single crystal SiC, the method of which is not part of this invention.

[0004] The invention also relates to a new method for producing such polycrystalline silicon carbide wafers, which can receive a transfer of a monocrystalline SiC layer in a subsequent manufacturing step. [Background technology]

[0005] (Current state of the art) Since the beginning of microelectronics, the vast majority of microelectronic circuits have been fabricated on single-crystal silicon substrates. In some specialized applications, semiconducting silicon is not an ideal substrate, but is still used for the lack of a better one.

[0006] On the other hand, silicon carbide (abbreviated SiC) is a remarkable semiconductor material. SiC has a wide band gap, a high breakdown field, high charge carrier mobility at saturation and high thermal conductivity. This combination of exceptional physical properties allows for excellent voltage endurance and very high current densities even at high temperatures. The article "Power components in SiC technology" by D. Tournier, published in 2007 as part D-3120 of the Techniques de l'ingenieur collection, provides an introduction to the subject.

[0007] SiC is therefore the material of choice for the manufacture of power components required for the efficient conversion of electrical energy in applications such as power distribution, renewable energy, and electric vehicles. The use of SiC allows advantageously replacing silicon-based transistors such as IGBTs with power components such as MOSFET transistors, which have kilovolt-order voltage resistance and significantly reduced switching energy losses. In such power components, voltage resistance and heat resistance are limiting factors when designing electronic components and the electronic boards on which they are mounted. The recent development of electric vehicles would greatly benefit from the use of such SiC power components to improve the energy efficiency in converting direct current from the battery into usable alternating current for the motor. However, the cost and availability of these components remain obstacles to the adoption of this technology. For this reason, silicon is still widely used as a substrate in certain applications where SiC has a technical advantage.

[0008] According to the current state of the art, silicon carbide substrates intended to receive the deposition of microelectronic circuits are generally provided as circular wafers. They are industrially produced using the PVT (Physical Vapor Transfer) process, which consists in sublimating SiC powder at high temperatures (higher than 2200 °C) and condensing the vapor on a seed to obtain an ingot or "ball" of monocrystalline SiC. From this monocrystalline ingot, monocrystalline SiC substrates (wafers) are sliced. On one side of this substrate, a layer of crystalline SiC is epitaxially grown in order to obtain a crystal with as few defects as possible. After epitaxy, the wafer is ready for the manufacture of electronic components.

[0009] Improvements in the PVT industrial process over the past 30 years have significantly reduced the density of the main crystal defects in these substrates, such as dislocations and micropipes, which have a significant impact on the reliability of SiC components. In addition, it has become possible to scale up the size of the substrates (wafers) to a standard diameter of 150 mm, soon to evolve to 200 mm. Despite industrial efforts, the PVT process remains complex to master, has low productivity, and is very energy consuming, as it requires ovens to be kept at high temperature for around 100 hours.

[0010] Moreover, for power components, the lowest possible resistance value Ron in the conduction mode is a decision criterion to improve the energy efficiency of the system by limiting the heating caused by the Joule effect while the current is flowing. In these applications, the monocrystalline SiC is doped to allow the manufacture of the P / N junctions of the components and to reduce the resistivity at the drain contact. The addition of nitrogen allows the substrate to be doped during the crystal growth. Typically, the resistivity of an "n" doped wafer is of the order of 20 mOhm.cm. It becomes very difficult to reduce the resistivity below this threshold without degrading the quality of the crystal, since too much doping creates stresses in the crystal that promote further dislocations.

[0011] The new technology currently under development combines low-cost SiC substrates (wafers) with improved electrical performance with thin layers of high-quality single-crystal SiC for producing microelectronic components.

[0012] The monocrystalline SiC layer may also be attached to the substrate by a molecular bonding process, as described in WO 01 / 18873 (French Atomic Energy Commission), to ensure minimal contact resistance between the substrate and the attached monocrystalline layer. EP 3018696 A1 describes an embodiment of such a method for applying a layer of monocrystalline SiC to a polycrystalline SiC substrate (herein referred to as "P-SiC" or "P-SiC wafer").

[0013] These P-SiC substrates must meet stringent requirements for electrical resistance, thermal conductivity, flatness, etc. Currently, prototypes called "dummy wafers" are commercially available from Ferrotec Corporation and other companies. These wafers, which have a standard diameter of 150 mm and a thickness of 750 μm, are used to balance the full load of single crystal SiC wafers in a certain process and improve uniformity.

[0014] According to this technique, P-SiC wafers are obtained by depositing polycrystalline SiC by CVD on a cylindrical graphite substrate. After machining the SiC layer deposited around the cylinder and reaching the graphite, two SiC disks can be separated from the two faces of the cylinder by air oxidation of the graphite. This is described in JP1994-340994 and JP1997-296361.

[0015] However, it soon became clear that the disks (wafers) thus obtained exhibited deformations (Bow and Warp) that were not acceptable for the intended application. The Bow and Warp parameters describe the flatness of wafers for the semiconductor industry and are known to those skilled in the art of semiconductor substrates for microelectronics (here we use only the English words with capital letters for these parameters). The process described in the two Japanese documents cited above finds a solution to this problem by repeating several deposition steps with thin film thicknesses of less than 100 μm. In fact, in sufficiently thick deposits, internal compressive stresses arise due to the increasing diameter of the grains. The conical grains repel each other as they grow. This physical mechanism has been demonstrated by P. Chaudhari in “Grain growth and Stress relief in thin films” published in Journal of Vacuum Science and Technology 9,520,1972. The processes described in JP 1994-340994 and JP 1997-296361 make it possible to obtain thick layers of P-SiC of several hundred microns while suppressing the increase in internal compressive stress, and thus suppressing deformation after peeling from the graphite.

[0016] Japanese Patent No. 3648112 (JP3648112B2) describes a similar process in which layers with alternating tensile and compressive stresses are deposited to counteract the stress moment integrated over the thickness of the deposit. This mechanical moment is responsible for the deformation observed when removing a P-SiC disk from a graphite substrate.

[0017] However, it is important to note that such a process is disadvantageous in achieving low resistivity and good thermal conductivity through the thickness of the wafer due to the multiple interfaces separating the layers in thickness. It would be more advantageous to find a single layer solution to this problem.

[0018] US 10,934,634 B2 describes the obtaining of P-SiC wafers with excellent flatness from a monolayer of SiC deposited by CVD on a graphite substrate. A sufficiently thick deposit (usually 2 mm) has an upper part where the grain size variations stabilize. Since the compressive stresses no longer vary in this part (as demonstrated in the cited reference by Chaudhari), it is possible to extract slices with a thickness of 350 μm by machining. These slices exhibit a quasi-zero stress gradient similar to the grain size in the thickness, and therefore a quasi-zero mechanical moment can be integrated over the thickness. The expected effect is that the deformation of the wafer is very small. However, the costs and energy expended in such a process are probably disadvantageous, since about 1.65 mm of the 2 mm CVD deposit layer must be removed by grinding and polishing to obtain a wafer of the desired thickness of 350 μm with the desired flatness.

[0019] To reduce the manufacturing costs of doped P-SiC wafers, it is optimal to rapidly CVD grow the P-SiC layer to a thickness as close as possible to the final thickness at which the grain size stabilizes very quickly after the start of layer growth, thereby avoiding unnecessary extra thickness that would be required to reduce or eliminate the grain size gradient.

[0020] At the Transducers & Eurosensors 2007 conference, XA Fu et al. presented a paper titled “Nitrogen doped polycrystalline 3C-SiC films deposited by LPCVD for MEMS applications.”

[0021] In this paper, the authors study the deposition of SiC for dopant gas concentrations (NH3) varying from 2% to 12% mole fraction of silicon precursor (dichlorosilane). To obtain resistivity below 20 mohm.cm under these conditions, dopant fractions above 5% are required. Higher dopant fractions increase the residual stress without increasing the stress gradient. In this study, deposition was performed at low temperature of 900 °C and low pressure to ensure crystal growth only along the (111) axis, but the deposition rate is extremely slow at 0.6 μm / h. Under these conditions, significant doping does not appear to change the crystal orientation of the deposited thin film, as determined by X-ray diffraction (XRD) analysis.

[0022] In a paper by HKE Latha et al. published in the journal Mater.Express. 1 015902 in 2014, the effect of heavy doping of 3C-SiC obtained by CVD with methyltrichlorosilane (MTCS) as silicon and carbon precursor and NH3 as doping agent is studied. The deposition conditions are 1040 °C and low pressure. The deposition growth rate reaches about 5 μm / h, which is much higher than the previous cases, but is still insufficient to produce high film thicknesses (hundreds of microns) in an economically viable way. Under these conditions, the influence of the doping level on the crystal orientation and grain size was observed. High doping is accompanied by a coarsening of the grain size and a change in the crystal orientation axis according to X-ray diffraction (XRD) analysis. It seems that for certain CVD conditions, especially at high temperatures, here 1040 °C instead of 900 °C as described in the paper by Fu et al. cited above, high levels of doping can have a very significant effect on the crystal orientation of SiC deposits by CVD. Therefore, the resulting texture and grain size can modify the stress distribution in these deposits.

[0023] International Publication No. 2021 / 060515 (WO2021 / 060515) (Tokai Carbon) proposes a process to obtain P-SiC substrates with thicknesses between 500 μm and 6 mm at high deposition temperatures close to 1500 °C. The deposition times are between 5 and 15 h and the deposition rates are above 100 μm / h, which are particularly suitable for industrial production. Doping of the P-SiC is achieved by adding dinitrogen to the mixture. To obtain sufficiently flat substrates, the patent proposes a process in which the concentration of the SiC precursor is varied during deposition in order to reduce grain size gradients that are too accentuated in the deposit. The process is carried out at a nitrogen mass concentration of 200 ppm (2.8 × 10 19 atm / cm 3 ) and 1000 ppm (1.38 × 10 20 atm / cm 3 ) has been proposed. It has been pointed out that above 1000 ppm, the nitrogen concentration in P-SiC is too high, which leads to significant defects in the crystal and unwanted deformation of the substrate. This state-of-the-art document therefore indicates that a high concentration of nitrogen dopant in P-SiC material can be a limiting factor for obtaining good flatness, but is desirable for obtaining low electrical resistivity.

[0024] These opposing trends must be taken into account in order to produce green P-SiC substrates by CVD with low resistivity (e.g. less than 10 mOhm.cm) and sufficient flatness to be able to grind P-SiC wafers with as little material thickness as possible. With regard to the flatness of green substrates obtained by CVD, it must be borne in mind that grinding a hard surface like SiC to remove material is a long and expensive process and, moreover, the thickness of material removed by grinding corresponds to the material lost. In fact, the production costs of P-SiC wafers must reach a low enough level to allow their use as substrates in combination with thin layers of polycrystalline SiC in power electronics applications.

[0025] According to the state of the art in the industry, the nominal thickness of a finished P-SiC wafer is 350 μm for a nominal diameter of 150 mm. Thicker raw products (raw blanks) are produced using a CVD deposition process on a graphite substrate. For economic reasons, the P-SiC blanks detached from the graphite should not exceed a thickness of 1 mm. Typically 750 μm, preferably 600 μm, are targeted in order to obtain reasonable CVD deposition times and to reduce the thickness removed by grinding and polishing to a maximum of 650 μm, typically 400 μm, and preferably 250 μm, respectively.

[0026] To comply with microelectronic standards, a 6 inch diameter 350 μm thick wafer must have a warpage of less than 50 μm after grinding and polishing. To achieve this objective, an intermediate blank must first be prepared by grinding a green blank peeled off from the graphite. This intermediate blank serves as the starting point for preparing the P-SiC wafer, onto which a monocrystalline layer of SiC is then transferred, by precision grinding and subsequent polishing. The difference between the initial thickness of the green blank and the deformation measured on said green blank must not be less than the thickness of the intermediate blank. This means that the volume of the ground intermediate (cylindrical) blank must be included in the volume of the green blank (see Figure 1).

[0027] In the present invention, we use a material resistivity of typically less than 5×10 to achieve a material resistivity of typically less than 15 mOhm.cm, preferably less than 10 mOhm.cm. 19 atoms / cm 3 Larger, preferably 10 20 atoms / cm 3 We sought to optimize the production of raw SiC substrates with a higher N-dopant fraction. The thermal conductivity of the material is usually desired to be at least 200 W / mK, but values ​​of at least 250 W / m / K are preferred, despite the high content of N-dopants that can affect the thermal conductivity by creating additional crystal defects that are detrimental to the propagation of phonons. We also look for substrates with good surface uniformity of grain size, preferably with fine grains. [Prior art documents] [Patent documents]

[0028] [Patent Document 1] WO 01 / 018873 [Patent Document 2] European Patent Application Publication No. 03018696 [Patent Document 3] JP 1994-340994 A [Patent Document 4] JP 1997-296361 A [Patent Document 5] Patent No. 3648112 [Patent Document 6] U.S. Pat. No. 1,093,4634 [Patent Document 7] International Publication No. 2021 / 060515 [Non-patent literature]

[0029] [Non-Patent Document 1] P. Chaudhari, “Grain growth and Stress relief in thin films”, Journal of Vacuum Science and Technology 9,520, 1972 [Non-Patent Document 2] XAFu et al., “Nitrogen doped polycrystalline 3C-SiC films deposited by LPCVD for MEMS applications”, Transducers & Eurosensors 2007 Summary of the Invention

[0030] (Objective of the Invention) As a result of the work carried out by the inventors of the present application, it has been found that solid plates of polycrystalline SiC (herein denoted "P-SiC") can be obtained by chemical vapor deposition (CVD) operating in a temperature range of about 1300 K to about 1800 K on a substrate consisting of a graphite surface. This method, which forms a first object of the invention, comprises introducing a gas mixture into a heated enclosure so as to produce a gas phase comprising at least one gaseous precursor of silicon and / or carbon, at least one dopant gas comprising at least one nitrogen atom and a carrier gas, said gas mixture being decomposed on the surface of said graphite substrate to form a layer of polycrystalline SiC on said graphite surface of said substrate, said method being characterized in that the temperature in the reactor is between 1450 K and 1650 K and the total partial pressure of said gaseous precursors is less than 350 mbar, preferably less than 300 mbar. This deposition is carried out on the graphite surface of a substrate consisting of a graphite surface, said substrate being a graphite plate. The substrate, and in particular the graphite plate, is advantageously circular so as to allow the direct production of circular SiC disks.

[0031] According to an advantageous embodiment, said gas phase comprises trichloromethylsilane as precursor of silicon and carbon, preferably free of other precursors of silicon and / or carbon. The dopant gas is advantageously selected from the group formed by NH3, N2H4, N2, H2NCH3.

[0032] This process results in the formation of a polycrystalline silicon carbide (P-SiC) layer that can be separated from the graphite surface on which it is formed.

[0033] It is thus possible to produce a polycrystalline SiC plate, which is another object of the invention. This plate can be a green blank and then, after a conditioning step, an intermediate blank for the production of a polycrystalline SiC substrate which can undergo the transfer of a layer of monocrystalline SiC to form a wafer usable for the production of a substrate for the deposition of integrated circuits. Said plate, said green blank and said intermediate blank represent other objects of the invention, as will be explained later. They advantageously exhibit a particular microstructure and crystallographic texture, as will be explained below.

[0034] Said polycrystalline SiC plate has a specific crystallographic texture that can be obtained for specific doping and electrical conductivity properties. A second object of the invention is therefore a polycrystalline SiC plate having the following characteristics: (i) a texture coefficient C 422 is less than 30%, and (ii.a) the texture coefficient C 220 is greater than 60%, preferably greater than 80%, or (ii.b) the texture coefficient C 111 +C 222 +C 511 The sum of the texture coefficients C is greater than 70%, preferably greater than 80%. 422 is less than 20%, preferably less than 15%, and more preferably less than 10%.

[0035] This polycrystalline SiC plate according to the invention is advantageously doped with nitrogen. Another example of a doped polycrystalline SiC plate according to the invention is a plate doped with phosphorus.

[0036] Advantageously, the polycrystalline SiC plate has an electrical resistivity of less than 20 mOhm.cm, preferably less than 15 mOhm.cm, and even more preferably less than 10 mOhm.cm, and / or a nitrogen content of less than 5×10 19 atoms / cm 3 Larger, preferably 1×10 20 atoms / cm 3 Larger, preferably 1.5×10 20atoms / cm 3 Greater than.

[0037] Typically, in the field of microelectronic substrates, the doping percentage (eg, nitrogen percentage) can be determined by secondary ion mass spectrometry (SIMS).

[0038] A particularly preferred embodiment of this second object of the invention is a cellulose fiber having a nitrogen content of 5×10 or less as measured by secondary ion mass spectrometry. 19 atoms / cm 3 and a larger, nitrogen-doped polycrystalline SiC plate, said plate having an electrical resistivity of less than 15 mOhm.cm and a preferred crystallographic orientation, said plate having the following characteristics: (i) a texture coefficient C 422 is less than 20%, and (ii.a) the texture coefficient C 220 is greater than 80%, or (ii.b) the texture coefficient C 111 +C 222 +C 511 The sum is greater than 80%.

[0039] Said polycrystalline SiC plates typically have the shape of circular disks, characterized by good flatness and advantageously have diameters between 140 mm and 165 mm, or between 185 mm and 210 mm, these two diameter ranges including the sizes currently customary in the semiconductor industry, namely 6 inches and 8 inches.

[0040] Said polycrystalline SiC plate may be a raw blank obtained from a deposition process. It may also be an intermediate blank for the manufacture of wafers obtained by grinding such a raw blank. In one embodiment, the polycrystalline SiC plate according to the invention has a thickness of less than 550 μm, preferably less than 500 μm, more preferably less than 450 μm, even more preferably between 355 μm and 420 μm, this embodiment being particularly suitable for plates with a diameter between 140 mm and 165 mm. In another embodiment, the polycrystalline SiC plate according to the invention has a thickness of less than 850 μm, preferably less than 800 μm, more preferably less than 750 μm, even more preferably between 510 μm and 650 μm. This embodiment is particularly suitable for plates with a diameter between 185 mm and 210 mm.

[0041] In another embodiment, the polycrystalline SiC plate according to the present invention has a diameter between 140 mm and 165 mm, a thickness between 350 μm and 450 μm, and a deformation characterized by a warp of less than 50 μm, preferably less than 40 μm, and more preferably less than 30 μm. The thickness is preferably between 350 μm and 400 μm. For example, the plate may have a thickness between 350 μm and 400 μm and a warp of less than 40 μm (preferably less than 30 μm), or the thickness may be between 400 μm and 450 μm, with a warp of less than 50 μm (preferably less than 40 μm).

[0042] In yet another embodiment, the polycrystalline SiC plate according to the present invention has a diameter between 185 mm and 210 mm, a thickness between 500 μm and 650 μm, and a deformation characterized by a warp of less than 70 μm, preferably less than 50 μm, and more preferably less than 40 μm. The thickness is preferably between 500 μm and 600 μm. For example, the plate may have a thickness between 500 μm and 600 μm and a warp of less than 50 μm (preferably less than 40 μm), or the thickness may be between 600 μm and 650 μm, with a warp of less than 70 μm (preferably less than 50 μm).

[0043] Such plates can be manufactured by a CVD process. [Brief description of the drawings]

[0044] 1 to 13 show different embodiments of the present invention.

[0045] [Figure 1] 1 is a schematic diagram showing measurement of a parameter called "Warp" which represents one aspect of flatness defects of a semiconductor wafer. [Diagram 2] 1 is an image obtained by observing, with a scanning electron microscope, backscattered electrons from a cross section of a P-SiC layer obtained by the process according to Example 1. [Diagram 3] 1 is an image obtained by observing a cross section of a P-SiC layer similar to that of Example 1 with a direct mode scanning electron microscope. [Figure 4] 1 is an image obtained by observing, with a scanning electron microscope, backscattered electrons from a cross section of a P-SiC layer obtained by the process according to Example 2. [Diagram 5] 1 is an image obtained by observing a cross section of a P—SiC layer similar to that of Example 2 with a direct mode scanning electron microscope. [Figure 6] 13 is an image obtained by observing, with a scanning electron microscope, backscattered electrons from a cross section of a P-SiC layer obtained by the process according to Example 3. [Figure 7]13 is an image obtained by observing a cross section of a P—SiC layer similar to that of Example 3 with a direct mode scanning electron microscope. [Figure 8] 13 is an image obtained by observing, with a scanning electron microscope, backscattered electrons from a cross section of a P-SiC layer obtained by the process according to Example 4. [Figure 9] 13 is an image obtained by observing a cross section of a P-SiC layer similar to that of Example 4 with a direct mode scanning electron microscope. [Figure 10] 13 is an image obtained by observing, with a scanning electron microscope, backscattered electrons from a cross section of a P-SiC layer obtained by the process according to Example 5. [Figure 11] 13 is an image obtained by observing a cross section of a P-SiC layer similar to that of Example 5 with a direct mode scanning electron microscope. [Figure 12] FIG. 2 shows a schematic and simplified vertical section through a reactor according to the invention, allowing the manufacture of a blank of a polycrystalline SiC substrate according to the invention. [Figure 13] 13 is an image obtained by observing, with a scanning electron microscope, backscattered electrons from a cross section of a P-SiC layer obtained by the process according to Example 6.

[0046] The following reference numbers are used in FIG. 12 and herein: 1: Reactor according to the invention 2: Housing 3: Reaction space 4:Heating space 5: Exhaust space 6: Heating element 7: Graphite susceptor 8: Precursor gas inlet 9: Reactant gas outlet 10:Exit tip 11: Injector 12: Graphite disk (substrate) DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0047] (Detailed explanation) Those skilled in the art of semiconductor substrates for microelectronics know various methods for assessing the overall flatness of a wafer. These various parameters are known by the following terms or acronyms: Bow (distance between the surface and the plane corresponding to the best fit at the center of an unclamped wafer, see ASTM F534 "Standard Test Method for Bow of Silicon Wafers", section 3.1.2), Warp (sum of the maximum positive and negative deviations from the plane corresponding to the best fit of an unclamped wafer, see ASTM F1390 "Standard Test Method for Measuring Warp on Silicon Wafers by Automated Non-Contact Scanning"), TTV (Total Thickness Variation, i.e. the difference between the maximum and minimum thickness values ​​of a clamped wafer, see ASTM F657 "Standard Test Method for Measuring Warp and Total Thickness Variation on Silicon Slice and Wafers by Non-contact Scanning"), TIR (Total Indicated Reading, sum of the maximum positive and negative deviations from the plane corresponding to the best fit of a clamped wafer), SRAD (Spherical Reference Measurement, representing the radius of curvature of the sphere corresponding to the best fit), and other acronyms represent parameters characterizing the local flatness of the wafer, in particular LFPD (Local Flatness Profile). The Focal Plane Deviation (the maximum distance between the wafer surface for a given region and a plane (above or below the unclamped wafer surface) corresponding to the best fit) and the Local Thickness Variation (LTV) (the difference between the maximum and minimum thickness values ​​of the unclamped wafer for a given region) are known.

[0048] In the context of the present invention, the flatness of a wafer is characterized by a parameter commonly called "Warp". This parameter refers to the algebraic difference of the deviation of the wafer from a reference surface. Figure 1 shows a schematic diagram of how this parameter is determined from the surface profile by the algebraic difference between axes B and C of a disk placed on a base plane.

[0049] It is also possible to determine the mid-plane from the surface profile (typically using an algorithm implementing least squares fitting) and calculate Warp by the deviation from the mid-plane, but this will give the same result as long as the mid-plane is parallel to the base plane. If the mid-plane is not parallel to the base plane, the measurement relative to the base plane will outperform the measurement relative to the mid-plane.

[0050] We now describe a method according to the invention that makes it possible to solve the problem posed.

[0051] The method according to the invention uses a chemical vapor deposition (CVD) technique carried out in a heated enclosure. The method uses a gas mixture comprising at least one silicon precursor gas (such as silane or chlorosilane) and / or at least one carbon precursor gas (such as alkane or alkene), and / or at least one silicon and carbon precursor gas (such as methyltrichlorosilane, abbreviated MTCS), and at least one dopant gas containing nitrogen (e.g. NH3, N2H4, N2). The dopant gas may be a carbon and / or silicon precursor (e.g. an amine such as H2NCH3). These gases may be diluted with a carrier gas, which may be a reducing gas such as hydrogen and / or an inert gas such as argon.

[0052] As an example, a gaseous composition for carrying out a method according to the present invention may include a carbon precursor, a silicon precursor, a dopant gas, and a carrier gas.

[0053] Another example includes a gaseous composition that includes silicon and carbon precursors, a silicon precursor, a carbon precursor, a dopant gas, and a carrier gas.

[0054] This gas mixture is placed in a high-temperature reactor where the precursor gases decompose and react at the surface to form the 3C-SiC polytype. This material is particularly suitable for combining with a layer of single-crystal SiC due to its mechanical and heat-resistant properties, thermal expansion compatibility, and purity. It can also be doped with nitrogen to very high levels, typically 10 20 atoms / cm 3 and has a resistivity much lower than 20 Ohm.cm - after all, it is a material that can withstand the high temperature processes that the wafers are subjected to in manufacturing electronic components.

[0055] The temperature of the reactor during the CVD deposition of SiC should be between about 1300 K and about 1800 K, preferably between about 1350 K and about 1700 K, more preferably between about 1400 K and about 1650 K, even more preferably between about 1450 K and about 1650 K. The total pressure in the reactor advantageously does not exceed 350 mbar, preferably does not exceed 300 mbar.

[0056] In an advantageous embodiment of the method for producing P-SiC wafers according to the invention, the deposition is carried out by CVD route on the graphite surface of a substrate. Very advantageously, said substrate is of fine and purified isotropic graphite to avoid contamination and outgassing of impurities during the deposition. For example, to obtain wafers with a diameter of 150 mm, the deposition is carried out on a disk-shaped graphite cylinder with a diameter close to 150 mm nominally and a thickness of more than 2 mm to ensure sufficient flatness of the substrate. The reactor can contain several such disks, which may have the same or different diameters. Both sides of the disk preferably have a flatness of less than 15 μm, obtained by sufficiently precise machining. The thermal expansion coefficient of the isotropic graphite is carefully selected to match the SiC layer on cooling after the deposition. Substrates sold by the company MERSEN under the name "2303" can be used.

[0057] The course of a typical embodiment of the method according to the invention will now be described and a reactor in which the method according to the invention can be carried out will first be described by way of example and in connection with FIG. 12. The process according to the invention is carried out in a particular type of reactor 1. It comprises a reaction chamber 2, which comprises a reaction space 3, a heating space 4 and a space for exhausting the reaction gases 5. Said housing 2 is designed in such a way that low pressures, down to a few tens of millibars, can be reached by pumping the gases to a wastewater treatment device (not shown). Precursor gases are introduced into the reaction space 3 of the reactor 1 via several injectors 11, which are fed by a gas line 8, called precursor gas inlet. The reaction gases leave the reaction space 3 towards the exhaust space 5, from where they are sucked through an outlet nozzle 10 into a gas line 9, called reaction gas outlet. The heating space 4 comprises several heating elements 6, typically solenoids. A graphite cylinder or disk 12, also called here substrate, is loaded into the housing 2. For the sake of simplicity, in FIG. 12 the support holding the substrate 12 in the reactor 1 is not shown.

[0058] The deposition chamber 2 is heated by induction of a magnetic field in a graphite susceptor 7, in which precursor gases (e.g. silanes, alkanes and / or methylchlorosilanes), carrier gases (e.g. hydrogen and / or argon), dopant gases (e.g. NH3, amines and / or N2) circulate. A graphite substrate 12 is in thermal equilibrium in the reaction space 3, heated by the susceptor 7 to a temperature (measured by thermocouples) typically between 1300 K and 1700 K, more preferably between 1350 K and 1650 K. In this temperature range, the deposition rate can vary in a very wide range, from μm / h to more than 100 μm / h. The total partial pressure of said gaseous precursors is advantageously less than 350 mbar, preferably less than 300 mbar.

[0059] To achieve a minimum P-SiC deposition thickness of about 600 μm, the gas injection time can vary from a few hours to tens or even hundreds of hours, depending on the conditions selected. The control parameters given above can be adjusted to obtain a product according to the invention, as will be explained in more detail in connection with the examples. It is therefore possible to obtain high-quality P-SiC plates under economically satisfactory conditions, which can be used in electronic applications to replace monocrystalline SiC produced by conventional PVT processes.

[0060] Once the deposition thickness on the surface of the graphite substrate 12 is reached, the injection of precursor gases into the furnace is stopped and the enclosure is cooled to room temperature and vented. The graphite disk 12, now coated with a thick layer of SiC deposit, is then machined and then oxidized in air, typically at 900°C, to remove graphite residues. A raw SiC disk is collected on each side.

[0061] The deformation of the raw blank disk is measured using a white light confocal sensor that scans the surface of the SiC disk that was in contact with the graphite. To perform this measurement, the face of the disk with the CVD deposition side is placed on a support. The maximum and minimum height difference of the surface scanned by the sensor relative to the support surface of the measurement tool is measured. The graphite side surface is a flat reference before it is peeled off from the graphite. After the graphite is peeled off, this surface becomes warped due to the relaxation of the stresses in the deposition layer. This warped surface can be interpolated by a mid-plane using a least squares method. If this mid-plane is parallel to the support plane, the deformation measurement is equal to Warp. This method of measuring deformation is primarily the measurement of Warp in the general case.

[0062] If deformation measurements of the raw blank are in accordance with the objectives set out below, it can be adjusted to a thickness slightly greater than the nominal 350 μm, resulting in a final bow of less than 50 μm for a standard 6 inch size wafer.

[0063] In practice, it is first necessary to prepare an intermediate blank by grinding from the green blank detached from the graphite, which then serves as the starting point for preparing, by precision grinding and subsequent polishing, the P-SiC wafer onto which the monocrystalline layer of SiC is transferred. The difference between the initial thickness of the green blank and the deformation measured on said green blank must not be less than the thickness of the intermediate blank; that is, the volume of the ground intermediate (cylindrical) blank must be included in the volume of the green blank (see Fig. 1). The conditioning step also removes a sufficient thickness from the side of the surface in contact with the graphite, which removes the initial growth zone of the crystals and removes the strong stresses generated by the progression of this deposition.

[0064] The crystal growth orientation of P-SiC in the temperature range from 1373K to 1673K was studied by So and Chun in the paper “Growth and structure of chemical vapor deposited silicon carbide from methyltrichlorosilane and hydrogen in the temperature range of 1100 to 1400°C”, Journal of Vacuum Science & Technology, A6, 5, 1988. Figure 4 in this paper shows the transition of the texture index for this temperature range from a preferred orientation (111) at low temperatures to an orientation (220) at high temperatures. The texture index was measured using the method described in the publication by GB Harris (1952) “X. Quantitative measurement of preferred orientation in rolled uranium bars”, Philosophical Magazine Series 7, 43:336, 113-123.

[0065] The product obtained by the process according to the invention has not only excellent flatness (characterized by a low value of the Warp parameter), low electrical resistivity and good thermal conductivity, but also small grain sizes and good uniformity of said grain sizes at its upper surface (i.e. the surface remote from the growth substrate, obtained by removal of material by polishing).

[0066] (Example) Examples 1-6 illustrate certain aspects of the present invention but are not intended to limit its scope.

[0067] In these examples, diffraction peaks were collected over the angular range of 10° to 135° (scale 2θ) using the θ-2θ method on a PANalytical X'Pert PRO MPD X-ray diffractometer. In this range, ten diffraction peaks were considered for SiC 3C, as shown in Table 1, and classified according to increasing Miller indices (hkl). [Table 1] Diffraction peaks considered JPEG2025511063000002.jpg81151

[0068] Texture coefficient C hkl (For N=10 peaks) is the peak intensity I, which is proportional to the area under the peak of the sample. hkl , and the theoretical strength of powder obtained from the theoretical percent published by ICDD (International Center for Diffraction Data) I 0hkl is obtained from C hkl =(I hkl / I 0hkl ) / (1 / N ×Σ(I hkl / I 0hkl )).

[0069] The texture coefficient in this case ranges from 0 to 10. It can also be expressed as a percentage, which quantifies the average preferred orientation of the crystallites of the deposited layer with respect to the normal to the sample surface.

[0070] In these examples, the carbon and silicon sources were the same molecule, namely methyltrichlorosilane (abbreviated MTCS). The dopant gas for the nitrogen source was NH3. By modifying some key parameters of the CVD process (temperature, partial pressure of the precursors, proportion of the dopant gas), it is possible to vary the orientation of the deposited layer and its texture. This allows to influence the internal stress gradient of the deposit and to obtain tailored, blank warps.

[0071] (Example 1: Cone-shaped coarse grain texture with preferred orientation (422)) A 650 μm layer was deposited on a graphite substrate at a temperature of 1550 K, an MTCS partial pressure of 23 mbar, and an NH3 molar fraction of 3%.

[0072] Figure 2 is a scanning electron microscope image of backscattered electrons taken from a cross-section of the resulting P-SiC layer. The texture triangles are shown at the bottom, and for information purposes, the four different white symbolized facets are shown. Figure 3 is a similar image taken with a direct mode scanning electron microscope at higher magnification.

[0073] In these two micrographs, the substrate is at the bottom.

[0074] The observed orientation is a preferred orientation texture (422) with the texture coefficients in Table 2. [Table 2] Texture coefficient of P-SiC according to Example 1 JPEG2025511063000003.jpg17161

[0075] Figures 2 and 3 show that the grain size increases continuously over the first 200 microns. This increase in grain size can be assessed for each ordinate in the reference frame by counting the number of intersections between the grain boundaries on the EBSD image and a horizontal line of a given ordinate.

[0076] The resulting layer had a nitrogen concentration of 8×10 measured by SIMS. 19 Nitrogen atoms / cm 3The electrical resistivity measured by the four-point method was 16 mohm.cm.

[0077] The thermal conductivity of the layer was estimated from the thermal diffusivity measured using the laser flash method, and a value of 210 W / m / K was obtained.

[0078] Despite the physical properties being suitable for the intended purpose, the deformations measured on the raw disks are much larger than those for which they were intended. Of a total of 16 disks, the average deformation was 850 μm with a standard deviation of 140 μm. It is not possible to produce P-SiC wafers by the adjusted method from raw disks with a thickness of less than 1000 μm.

[0079] After several depositions under this condition, the observed texture is characterized by a texture coefficient C 422 >75%, with a very preferential orientation ( 422 ).

[0080] (Example 2: Emphasis on fine grain texture (111)) A 650 μm layer was deposited on a graphite substrate at a temperature of 1550 K, a MTCS partial pressure of 8 mbar, and an NH3 molar fraction of 6%. Figures 4 and 5 are micrographs similar to Figures 2 and 3 of Example 1 (the white bars in Figure 5 correspond to a length of 50 μm).

[0081] The observed orientation is a preferred orientation texture (111) whose texture coefficients are collected in Table 3. [Table 3] Texture coefficient of P-SiC according to Example 2 JPEG2025511063000004.jpg26160

[0082] Figure 5 shows grains whose size does not increase as the growth of the P-SiC layer progresses. These are thin, rod-like grains highly oriented according to the normal to the plane of the substrate. The grain size can be evaluated for each ordinate in the reference frame by counting the number of intersections between the grain boundaries on the EBSD image and a horizontal line of a certain ordinate.

[0083] The resulting deposit had a nitrogen concentration of 7×10 20 Nitrogen atoms / cm 3 The electrical resistivity measured by the four-point method was 1.1 mOhm.cm. The thermal conductivity of the layer was estimated by measuring the thermal diffusivity using the laser flash method. A value of 52 W / m / K was obtained, which is well below the target value. It seems that the microstructure strongly limits the thermal conductivity.

[0084] On the other hand, the deformation measured on the raw disks was very good: out of a total of 16 disks, the average deformation was 190 μm with a standard deviation of 72 μm. This allows the production of P-SiC wafers from raw disks with a thickness of less than 1000 μm at a reasonable cost.

[0085] After several depositions under these conditions, the observed orientation is consistent with the texture coefficient C 111 +C 222 +C 511 The total was over 80% and the texture was highly preferentially oriented (111).

[0086] (Example 3: Fine grain texture (220)) A 650 μm layer was deposited on a graphite substrate at a temperature of 1550 K, an MTCS partial pressure of 16 mbar, and an NH3 molar fraction of 4%.

[0087] 6 and 7 are micrographs similar to those of FIGS. 2 and 3 of Example 1. FIG.

[0088] The observed orientation is the preferred orientation texture (220) whose texture coefficients are collected in Table 4. [Table 4] Texture coefficient of P-SiC according to Example 3 JPEG2025511063000005.jpg23156

[0089] The resulting deposit had a nitrogen concentration of 1.8×10 20 Nitrogen atoms / cm 3The electrical resistivity measured by the four-point method was 5 mohm.cm. The thermal conductivity of the layer was estimated by measuring the thermal diffusivity using the laser flash method. A value of 270 W / m / K was obtained, which is above the target value. It seems that the tree-like texture promotes good thermal conductivity despite the small grain size and high doping.

[0090] The deformation measured on the green disks is also very good. Out of a total of 16 disks, the average deformation was 210 μm with a standard deviation of 82 μm. This allows the production of conditioned P-SiC wafers from green disks with a thickness of less than 1000 μm at reasonable cost.

[0091] After several depositions under these conditions, the observed texture is characterized by a texture coefficient C 220 >90%, C 422 <10% and is highly preferentially oriented ( 220 ).

[0092] (Example 4: Fine grain texture mainly oriented (220) mixed with large grain texture mainly oriented (422)) 8 and 9 are micrographs similar to those of FIGS. 2 and 3 of Example 1. FIG.

[0093] A layer of 800 μm was deposited on a graphite substrate at a temperature of 1600 K, a MTCS partial pressure of 16 mbar, and an NH3 molar fraction of 4%. The observed texture showed large grains that were preferentially oriented (220) and preferentially oriented (422), according to the texture indices collected in Table 5. [Table 5] Texture coefficient of P-SiC according to Example 4 JPEG2025511063000006.jpg20161

[0094] The figure shows two populations of grains with different dimensions. The (220) oriented grains have diameters between 1 and 10 μm. The other grains are mainly (422) oriented, cone shaped and grow up to 50 μm in diameter. The grain size can be evaluated for each ordinate of the reference frame by counting the number of intersections between the grain boundaries on the EBSD image and a horizontal line of a given ordinate. Here, the growth of the average grain size quickly stabilizes, since the large grains remain a minority in the texture.

[0095] The resulting deposit had a nitrogen concentration of 2.2 × 10 20 Nitrogen atoms / cm 3 The electrical resistivity measured by the four-point method was 3.3 mohm.cm. The thermal conductivity of the layer was estimated from the thermal diffusivity measurement using the laser flash method. A value of 215 W / m / K was obtained, which is above the target value.

[0096] The deformation measured on the green disks is also very good. Out of a total of 16 disks, the average deformation was 235 μm with a standard deviation of 90 μm. This allows the production of P-SiC wafers by the conditioned method from green disks with a thickness of less than 1000 μm at reasonable cost.

[0097] After several depositions under this condition, the observed texture is characterized by a texture coefficient C 220 >60% and C 422 <20% remained preferentially oriented (220).

[0098] (Example 5: A texture of large grains mainly oriented in (422) mixed with a fine texture of small grains mainly oriented in (220)) A layer of 800 μm was deposited on a graphite substrate at a temperature of 1600 K, a MTCS partial pressure of 16 mbar, and an NH3 mole fraction of 6%. The observed texture was preferentially (220) oriented, providing large grains with preferential (422) orientation, according to the texture coefficients collected in Table 5.

[0099] 10 and 11 are micrographs similar to those of FIGS. 2 and 3 of Example 1. FIG.

[0100] The observed texture showed very large grains that were preferentially oriented (422) and oriented according to the texture coefficients collected in Table 6. [Table 6] Texture coefficient of P-SiC according to Example 5 JPEG2025511063000007.jpg19154

[0101] The figure shows that the very large grains have a predominant (422) or minority (111) orientation and are cone-shaped up to 100 μm in diameter. There are only a few small grains (220) smaller than 10 μm. The figure shows a continuous growth in grain size over the first 500 microns. This growth in grain size can be evaluated for each ordinate in the reference frame by counting the number of intersections between the grain boundaries on the EBSD image and a horizontal line of a constant ordinate.

[0102] The resulting deposit had a nitrogen concentration of 6.8×10 20 Nitrogen atoms / cm 3 The electrical resistivity measured by the four-point method was 0.9 mohm.cm, which was well below the upper limit of the target. The thermal conductivity of the layer was also estimated by thermal diffusivity measurement using the laser flash method, and was 130 W / m / K, which was below the target value.

[0103] Of the total 16 disks, the average deformation was 650 μm with a standard deviation of 178 μm. It is not possible to produce P-SiC wafers by conditioning from raw disks with a thickness of less than 1000 μm.

[0104] After several depositions under this condition, the observed texture is characterized by a texture coefficient C 422 >50%, C 111 +C 222 +C 511 >15%, C 220 <10% remained preferentially oriented (422).

[0105] (Example 6: Texture obtained according to Example 3, but without adding dopant gas) Operating under similar conditions as in Example 3, i.e., a temperature of 1550 K, an MTCS partial pressure of 16 mbar, but with a NH3 molar fraction of 0%, an 800 μm layer was deposited on a graphite substrate.

[0106] FIG. 13 is a photomicrograph similar to FIG.

[0107] The observed orientations are mainly (422), followed by (111) textures, with very little (220) texture. The texture coefficients are shown in Table 7. [Table 7] Texture coefficient of P-SiC according to Example 6 JPEG2025511063000008.jpg19157

[0108] The nitrogen concentration in the resulting deposit was below the detection threshold of SIMS, 10 19 Nitrogen atoms / cm 3 The electrical resistivity measured by the four-point method was 56 Ω.cm, which is much lower than the value of the Cr-Si alloy. The thermal conductivity of the layer was estimated by measuring the thermal diffusivity using the laser flash method. A value of 130 W / m / K was obtained, which was below the target value.

[0109] The deformation measured on the raw discs was not as expected: out of a total of 16 discs, the average deformation was 530 μm with a standard deviation of 110 μm.

[0110] This makes it impossible to produce P-SiC wafers from raw disks less than 1000 μm thick at a reasonable cost.

[0111] After several depositions under these conditions, the observed texture was oriented primarily in (422) and then in (111) with a texture coefficient of: C 422 >35%, C 111 +C 222 +C 511 >20%, C 220<15%.

[0112] (Comparison of Examples 1 to 6) The main results obtained in relation to the above example are summarised in Table 7 below. [Table 7] Main results of Examples 1 to 6 JPEG2025511063000009.jpg135170

[0113] Examples 2, 3, and 4 show the two possible axes (C 220 >60% or C 111 +C 222 +C 511 >80%), showing a highly oriented texture along the C 422 The orientation contribution is always less than 20%. The elongated grains are continuous. The grain size is stable at a maximum of 10 μm and the length can reach 100 μm.

[0114] Example 6, which was produced under the conditions of Example 3 but did not contain dopant gas, was C 422 The orientation of the SiC film is strong, at 20% or more, and there is significant deformation such that P-SiC wafers cannot be produced by grinding from unprocessed blanks with a thickness of less than 1,000 μm. [Explanation of symbols]

[0115] 1: Reactor according to the invention 2: Housing 3: Reaction space 4:Heating space 5: Exhaust space 6: Heating element 7: Graphite susceptor 8: Precursor gas inlet 9: Reactant gas outlet 10:Exit tip 11: Injector 12: Graphite disk (substrate)

Claims

1. 1. A doped polycrystalline SiC plate having a preferred crystallographic orientation, said plate comprising: (i) its texture coefficient C ４２２ is less than 30%; (ii.a) its texture coefficient C ２２０ is greater than 60%, preferably greater than 80%, or (ii.b) its texture coefficient C １１１ +C ２２２ +C ５１１ A doped polycrystalline SiC plate having a preferred crystal orientation, characterized in that the sum of is greater than 70%, preferably greater than 80%.

2. 2. Polycrystalline SiC plate according to claim 1, characterized in that its electrical resistivity is less than 20 mOhm.cm, preferably less than 15 mOhm.cm, more preferably less than 10 mOhm.cm.

3. The nitrogen content measured by secondary ion mass spectrometry was 5×10 １９ atoms / cm ３ Larger, preferably 1×10 ２０ atoms / cm ３ More preferably, 1.5×10 ２０ atoms / cm ３ 3. A polycrystalline SiC plate according to claim 1, characterized in that it is doped with greater nitrogen.

4. Texture coefficient C ４２２ 4. Polycrystalline SiC plate according to claim 1, characterized in that the surface roughness is less than 20%, preferably less than 15%, and more preferably less than 10%.

5. The nitrogen content measured by secondary ion mass spectrometry was 5×10 １９ atoms / cm ３ doped with nitrogen greater than 15 mOhm.cm, said plate having an electrical resistivity and preferred crystallographic orientation less than 15 mOhm.cm, said plate having (i) its texture coefficient C ４２２ is less than 20%; (ii.a) its texture coefficient C ２２０ is greater than 60%, preferably greater than 80%, or (ii.b) its texture coefficient C １１１ +C ２２２ +C ５１１ The polycrystalline SiC plate according to any one of claims 1 to 4, wherein the sum of is greater than 80%.

6. A polycrystalline SiC plate according to any one of claims 1 to 5, characterized in that it is a green blank obtained from a deposition process.

7. A polycrystalline SiC plate according to any one of claims 1 to 5, characterized in that it is an intermediate blank for the production of wafers, obtained by grinding the unmachined blank according to claim 6.

8. 8. Polycrystalline SiC plate according to claim 7, characterized in that it has a thickness less than 550 μm, preferably less than 500 μm, more preferably less than 450 μm, even more preferably between 355 μm and 420 μm.

9. The polycrystalline SiC plate according to any one of claims 1 to 8, characterized in that it has a diameter between 140 mm and 165 mm, a thickness between 350 μm and 450 μm, and a warp characteristic with a deformation of less than 50 μm, preferably less than 40 μm, and more preferably less than 30 μm.

10. 10. The polycrystalline SiC plate according to claim 9, characterized in that it has a thickness between 350 and 400 μm.

11. The polycrystalline SiC plate according to any one of claims 1 to 7, characterized in that the polycrystalline SiC plate has a diameter between 185 mm and 210 mm, a thickness between 500 μm and 650 μm, and a deformation characterized in that the deformation has a Warp characteristic of less than 70 μm, preferably less than 50 μm, and more preferably less than 40 μm.

12. 12. The polycrystalline SiC plate according to claim 11, characterized in that it has a thickness between 500 and 600 μm.

13. Polycrystalline SiC plate according to any one of claims 1 to 12, characterized in that it is obtained by a CVD process.

14. A method for producing a polycrystalline SiC plate according to any one of claims 1 to 13, comprising the steps of chemical vapor deposition of a layer of polycrystalline SiC on a graphite surface of a substrate (12) comprising said graphite surface, introducing a gas mixture into a heated enclosure (2), at least one gaseous precursor of silicon and / or carbon, at least one dopant gas containing at least one nitrogen atom, - carrier gas, generating a gas phase comprising The gas mixture decomposes on the surface of the graphite substrate (12) to form a layer of polycrystalline SiC, and the method is characterized in that the temperature in the enclosure is between 1450K and 1650K and the total partial pressure of the gaseous precursors is less than 350mbar, preferably less than 300mbar.

15. 15. The method according to claim 14, characterized in that the gas phase comprises trichloromethylsilane and preferably does not contain other precursors of silicon and / or carbon.

16. The dopant gas is NH ３ , N ２ H ４ , N ２ , H ２ NCH ３ 16. The method according to claim 14 or 15, characterized in that it is selected from the group formed by

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