System and method for crest factor reduction that suppresses peak regrowth

Abstract

The present disclosure provides a crest factor reduction system and method for suppressing peak regrowth. The system receives a complex signal from the physical layer (PHY) of a base station equipped with an orthogonal frequency division multiplexing (OFDM) function. Further, the system uses a coordinate rotation digital computer (CORDIC) to convert the complex signal into polar form. Also, the system utilizes an advanced interpolation processing (AIP) technique to minimize the peak regrowth that may occur at x4 (digital upconversion (DUC)) in the latter half of the downlink chain. Thereby, the initial problem of peak regrowth associated with the DUC process can be suppressed by the proposed CFR design. Further, in the CFR design of the present invention, since multiple multiple-input multiple-output (MIMO) channels can be operated by multiplexing in the time domain, the resource utilization rate can be further reduced.

Description

Technical Field

[0001] (Reservation of Rights) Part of the disclosure of this patent document includes materials that are the subject of intellectual property rights owned by Jio Platforms Limited (JPL) or its related companies (hereinafter collectively referred to as the patentee), such as, but not limited to, copyrights, designs, trademarks, integrated circuit (IC) layout designs, and / or trade dress protection. The patentee does not object to third parties copying the patent documents or patent disclosures described in the patent files or records of the Patent and Trademark Office, but reserves all other rights. All rights to such intellectual property are fully reserved by the patentee.

[0002] Embodiments of the present disclosure generally relate to systems and methods for orthogonal frequency division multiplexing (OFDM)-based communication technologies in a telecommunications network. More specifically, the present disclosure relates to systems and methods for crest factor reduction that suppress peak regrowth.

Background Art

[0003] The following description of related art is intended to provide background information related to the field of the present disclosure. This section may include specific aspects of the technology that may be related to various features of the present disclosure. However, this section is only intended to deepen the reader's understanding of the present disclosure and does not admit prior art.

[0004] Orthogonal frequency division multiplexing (OFDM)-based communication technologies are widely adopted in Long-Term Evolution (LTE (R)) and 5th Generation New Radio (5G NR) to achieve high data rates, high throughput, and reliable network access.

[0005] In OFDM, since the envelope is not constant, the peak-to-average power ratio (PAPR) is higher compared to single-carrier systems. The main reason is that multiple sub-carriers are combined to form a composite signal, and at this time, due to the central limit theorem, the real and imaginary parts approach the Gaussian probability density function (PDF), and the amplitude approaches the Rayleigh distribution. When the PAPR increases, the efficiency of the power amplifier (PA) decreases. Therefore, the high PAPR of OFDM will limit the efficiency of the PA in conventional large-scale multiple-input multiple-output (MIMO) 5G NR systems.

[0006] In conventional systems, high resource utilization and PAPR performance in wide channel bandwidths such as 100 megahertz (MHz) are issues. Furthermore, in field-programmable gate arrays (FPGAs) with resource constraints, due to the large number of transmit chains related to large-scale MIMO systems used in 5G NR, additional problems may arise. Also, high-speed radio frequency (RF) data converters widely used in 5G NR designs may utilize higher sampling clocks to convert digital data into RF analog signals. In addition, in RF data converters, digital upconversion (DUC) of the data output obtained from the physical layer may be required, which leads to peak regrowth.

[0007] Therefore, there is a need in the art to provide systems and methods that can mitigate problems related to the prior art.

[0008] Some of the objectives of the present disclosure satisfied by at least one embodiment of this specification are listed below.

[0009] An objective of the present disclosure is to provide a system and method that use a hybrid and multiple-iteration signal distortion-based approach over a wide bandwidth from low bandwidth to up to 100 megahertz (MHz) for single-carrier cases and up to 200 MHz for multi-carrier cases for fifth-generation (5G) new radio (NR) signals.

[0010] An object of the present disclosure is to provide a system and method for reducing a high peak-to-average power ratio (PAPR) associated with orthogonal frequency division multiplexing (OFDM)-based communication technologies.

[0011] An object of the present disclosure is to provide a system and method for reducing PAPR using crest factor reduction (CFR) techniques.

[0012] An object of the present disclosure is to provide a system and method that operate at a low data rate using CFR techniques until before digital upconversion (DUC) and suppress peak regrowth when reducing PAPR with CFR processing.

[0013] An object of the present disclosure is to provide a system and method that can address various field programmable gate array (FPGA) implementation challenges and optimize CFR designs, including suppression of resource utilization.

[0014] An object of the present disclosure is to provide a system and method for implementing a hybrid peak cancellation (PC) and peak window (PW)-based CFR technique that can be utilized in a 5G NR digital front end (DFE) design through PAPR reduction performance, full bandwidth utilization, and negligible computational complexity.

[0015] An object of the present disclosure is to provide a system and method that employ a CFR design with a low-complexity solution to achieve effective PAPR performance and suppression of peak regrowth (up to a predetermined level).

[0016] An object of the present disclosure is to provide a system and method that employ advanced interpolation processing (AIP) techniques to remove peak regrowth observed in the DUC at a later stage of the downlink chain.

[0017] An object of the present disclosure is to provide a system and method capable of significantly reducing the resource usage of a block random access memory (BRAM) by storing a cancellation pulse coefficient in a dual-port read-only memory (ROM).

[0018] Another object of the present disclosure is to provide a system and method capable of operating a plurality of large-scale multiple-input multiple-output (MIMO) channels and further reducing resource utilization by multiplexing in the time domain.

SUMMARY OF THE INVENTION

[0019] In this section, specific objects and aspects of the present disclosure, which will be detailed in subsequent sections, are briefly described. This summary is not intended to identify key features or delimit the scope of the claimed subject matter.

[0020] In one aspect, the present disclosure relates to a crest factor reduction (CFR) system that suppresses peak regrowth. The system may include a processor operably coupled to a memory that stores instructions executed by the processor. The processor may receive a signal from a physical layer (PHY) of a new radio (NR) with orthogonal frequency division multiplexing (OFDM). The received signal may be based on a complex low peak-to-average power ratio (PAPR) signal. The processor may interpolate the received signal by an n factor to generate a received signal including a predetermined peak regrowth. The processor may generate one or more pulses to cancel peaks associated with the predetermined peak regrowth of the received signal to generate a modified n factor signal. The processor may generate a PAPR-reduced signal before digital upconversion (DUC) and may decimate the modified n factor signal to generate a CFR with suppressed peak regrowth.

[0021] In one embodiment, the processor may be configured to use coordinate rotation digital computer (CORDIC) technology to determine the magnitude and phase of the received signal.

[0022] In one embodiment, the processor may be configured to generate a peak search window (PSW) associated with the magnitude and phase of the received signal.

[0023] In one embodiment, the processor may be configured to multiplex the received signal and use peak cancellation (PC) techniques to generate the PSW.

[0024] In one embodiment, the processor may be configured to use advanced interpolation processing (AIP) techniques to generate a received signal that includes a predetermined peak regrowth.

[0025] In one embodiment, the AIP technique may use a finite impulse response (FIR)-based interpolator to generate a received signal that includes a predetermined peak regrowth.

[0026] In one embodiment, the processor may include a downsampler for decimating the modified n-factor signal.

[0027] In one embodiment, the downsampler may subtract the modified n-factor signal from the received signal to generate a PAPR-reduced signal.

[0028] In one embodiment, the processor may be configured to use window crest factor reduction (WCFR) techniques to remove the canceled peaks included in the received signal.

[0029] In one embodiment, the processor may be configured to include a dual-port read-only memory (DPROM) to store the removed peaks after cancellation.

[0030] In one aspect, the present disclosure relates to a method of CFR that suppresses peak regrowth. This method may include receiving a signal from the PHY of NR with OFDM by a processor. The received signal may be based on a complex PAPR signal. This method may include interpolating the received signal by a processor to an n-factor to generate a received signal with a predetermined peak regrowth. This method may include generating, by a processor, one or more pulses to cancel peaks associated with the predetermined peak regrowth of the received signal to generate a modified n-factor signal. This method may include decimating, by a processor, the modified n-factor signal to generate a PAPR-reduced signal before DUC and generating a CFR with suppressed peak regrowth.

[0031] In one embodiment, this method may include determining, by a processor, the magnitude and phase of a signal received via CORDIC technology.

[0032] In one embodiment, this method may include generating, by a processor, a PSW associated with the magnitude and phase of the received signal.

[0033] In one embodiment, this method may include multiplexing, by a processor, the received signal to generate a PSW via PC technology.

[0034] In one embodiment, this method may include generating, by a processor, a received signal with a peak regrowth predetermined by AIP technology.

[0035] In one aspect, the non-transitory computer-readable medium may include a processor having executable instructions that cause the processor to receive, from a NR PHY with OFDM, signals by the executable instructions. The received signals may be based on complex PAPR signals. The processor may interpolate the received signals by an n factor to generate a received signal including a predetermined peak regrowth. The processor may generate one or more pulses to cancel peaks associated with the predetermined peak regrowth of the received signal to generate a modified n factor signal. The processor may generate a PAPR-reduced signal before DUC and decimate the modified n factor signal to generate a CFR with suppressed peak regrowth.

[0036] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosed methods and systems, and like reference numerals refer to like parts throughout the different views. The components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the disclosure. In some of the drawings, block diagrams are used to show components, and may not represent the internal circuitry of each component. One of ordinary skill in the art will appreciate that such a disclosure of the drawings includes a disclosure of the electrical components, electronic components, or circuits commonly used to implement such components.

Brief Description of the Drawings

[0037]

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Best Mode for Carrying Out the Invention

[0038] The above content will be described in detail in the following disclosure. For the purpose of explanation below, various specific details are described so that the embodiments of the present disclosure can be fully understood. However, it is clear that the embodiments of the present disclosure can be implemented without these specific details. Some of the functions described below can be used independently or in combination with other functions. By themselves, the individual functions may not be able to solve all of the problems described above or may only be able to solve some of the problems described above. Some of the problems described above may not be completely solved by any of the functions described below.

[0039] The following description provides only exemplary embodiments and is not intended to limit the scope, applicability, or configuration of the present disclosure. Rather, it is intended to provide an effective explanation for those skilled in the art to implement the exemplary embodiments. It should be understood that various changes can be made to the functions and arrangements of the elements without departing from the spirit and scope of the described disclosure.

[0040] To fully understand the embodiments, specific details are set forth in the following description. However, one skilled in the art will understand that the embodiments can be practiced without these specific details. For example, circuits, systems, networks, processes, and other components may sometimes be presented in block diagram form so as not to obscure the embodiments with unnecessary detail. In other instances, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail so as not to obscure the embodiments.

[0041] It should also be noted that individual embodiments may sometimes be described as processes represented as flowcharts, flow diagrams, data flow diagrams, structure diagrams, or block diagrams. Although the operations are described in the flowcharts as sequential processes, many of the operations can be executed in parallel or simultaneously. Also, the order of the operations may be changed. A process ends when its operations are completed, but there may be additional steps not included in the figure. A process may refer to a method, function, procedure, subroutine, subprogram, etc. When a process refers to a function, its end refers to the function returning to the calling function or the main function.

[0042] As used herein, the terms "exemplary" and / or "illustrative" mean an example, instance, or illustration. To avoid doubt, the subject matter disclosed herein is not limited by such examples. Further, any aspect or design described herein as "exemplary" and / or "illustrative" should not necessarily be construed as more preferred (or advantageous) than other aspects or designs, nor is it intended to exclude equivalent exemplary structures and techniques known to those skilled in the art. Further, as long as the expressions "comprising," "having," "including," and other similar expressions are used in any of the detailed description or claims, such expressions are used in an inclusive sense without excluding additional elements or other elements.

[0043] Throughout this specification, references to "one embodiment", "an embodiment", "an example", or "one example" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Further, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0044] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting of the present disclosure. The terminology and expressions used herein are to be construed as including the plural unless otherwise indicated by the context. Further, the expressions "comprising" and / or "consisting of" used herein mean the presence of the described features, numbers, steps, operations, elements, or components, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and / or groups thereof. The expression "and / or" used herein includes any and all combinations of one or more of the associated listed items.

[0045] Various embodiments throughout the present disclosure will be described in more detail with reference to FIGS. 1-21.

[0046] FIG. 1 shows an example of a network architecture (100) of a system (110) in one embodiment of the present disclosure.

[0047] As shown in FIG. 1, the network architecture (100) may include a system (110). The system (110) can be connected to the digital front end (DFE) of a gNB base station (112). In one embodiment, the system (110) can receive signals from the physical layer (PHY) of a new radio (NR) / gNB base station (112) with orthogonal frequency division multiplexing (OFDM). The received signals can be based on complex low peak-to-average power ratio (PAPR) signals.

[0048] In one embodiment, the gNB base station (112) can include a 5G NR massive multiple-input multiple-output (MIMO) radio unit (MRU), which may be a high-output gNB operating in the macro class with 200 W (typically 6.25 W or 38 dBm per antenna port). The gNB base station (112) can provide a macro-level wide-area solution in terms of coverage and capacity, and is particularly useful in meeting the needs of dense urban configurations, high-traffic hot zones / hotspots, and quality of service (QoS). Further, the gNB base station (112) can further include a lower-layer PHY section and a commercial-grade field-programmable gate array (FPGA)-based radio frequency (RF) transceiver with transmit and receive chains. The gNB base station (112) can include an RF front-end module (RFEM) including an RF power amplifier, a low-noise amplifier (LNA), an RF switch, and an antenna filter unit (AFU).

[0049] In one embodiment, the digital upconversion (DUC) used to achieve the required high sample rate can cause peak regrowth even after reducing the peak-to-average power ratio (PAPR) as much as necessary by crest factor reduction (CFR) processing. Thus, the system (110) can operate at a low data rate before the DUC and incorporate a CFR method that can suppress peak regrowth.

[0050] In one embodiment, in the system (110), due to effective PAPR reduction performance, full bandwidth utilization, ease of implementation, and negligible computational complexity, a hybrid-base CFR technique (but not limited to this) of peak cancellation (PC) and peak window (PW) can be used for 5G NR DFE design.

[0051] In one embodiment, the system (110) can utilize coordinate rotation digital computer (CORDIC) technology to determine the magnitude and phase of the received signal. Further, the system (110) can generate a peak search window (PSW) associated with the magnitude and phase of the received signal. The system (110) can use peak cancellation (PC) technology that multiplexes the received signal to generate the PSW.

[0052] Furthermore, in one embodiment, the system (110) can interpolate the received signal by an n-factor to generate a received signal including a predetermined peak regrowth. The system (110) may use advanced interpolation processing (AIP) technology for generating a received signal including a predetermined peak regrowth. AIP may include a finite impulse response (FIR)-based interpolator for generating a received signal including a predetermined peak regrowth.

[0053] In one embodiment, the system (110) can generate one or more pulses to cancel peaks associated with a predetermined peak regrowth of the received signal to generate a modified n-factor signal. Further, in one embodiment, the system (110) may use window crest factor reduction (WCFR) technology to remove the canceled peaks included in the received signal.

[0054] In one embodiment, the system (110) can generate a PAPR-reduced signal before DUC and decimate the modified n-factor signal to generate a CFR with suppressed peak regrowth.

[0055] In one embodiment, the system (110) may use a downsampler for decimating the modified n-factor signal. Further, the downsampler can subtract the modified n-factor signal from the received signal to generate a PAPR-reduced signal.

[0056] In one embodiment, the system (110) can utilize coding-based CFR techniques such as, but not limited to, precoding, block coding, convolutional coding, concatenated coding, etc. Further, CFR techniques based on signal scrambling techniques or probabilistic techniques such as selective mapping, partial transmission sequences, tone injection, tone reservation, interleaving, insertion of dummy sequences, etc. can also be used. Also, the system (110) can incorporate CFR techniques based on signal distortion techniques such as, but not limited to, hard clipper-based CFR, clipping and filtering CFR, PW, PC, non-linear composites, etc.

[0057] FIG. 1 illustrates the components of the network architecture (100), but in other embodiments of the network architecture (100), the number, type, and arrangement of the components may be different from FIG. 1 or may include additional functions not shown in FIG. 1. Further (or alternatively), the functions described herein as being performed by one or more components of the network architecture (100) may be performed by one or more other components of the network architecture (100).

[0058] FIG. 2 shows an example of a block diagram (200) of the system (110) in one embodiment of the present disclosure.

[0059] According to FIG. 2, system (110) can include one or more processors (202) that can be implemented as one or more microprocessors, microcomputers, microcontrollers, digital signal processors, central processing units, logic circuits, and / or any device capable of processing data based on operating instructions. Among other functions, the one or more processors (202) can be configured to obtain and execute computer-readable instructions stored in the memory (204) of the system (110). The memory (204) may be configured to store one or more computer-readable instructions or routines on a non-transitory computer-readable storage medium, and these instructions or routines can be obtained and executed to create or share data packets via a network service. The memory (204) can include any non-transitory storage device, including, for example, volatile memory such as random access memory (RAM), or non-volatile memory such as erasable programmable read-only memory (EPROM), flash memory, etc.

[0060] In one embodiment, system (110) may include an interface (206). The interface (206) can include various interfaces, such as, for example, data input / output (I / O) devices and interfaces for storage devices. The interface (206) can also provide a communication path to one or more components of the system (110). Examples of such components include, but are not limited to, a processing engine (208) and a database (210). Examples of the processing engine (208) include, but are not limited to, a data acquisition engine (212).

[0061] The processing engine (208) may be implemented as a combination of hardware and programming (e.g., programmable instructions) to implement one or more functions of the processing engine (208). In the examples described herein, such a combination of hardware and programming can be implemented in several different ways. For example, the programming of the processing engine (208) may be processor-executable instructions stored on a non-transitory machine-readable storage medium, and the hardware of the processing engine (208) may include processing resources (e.g., one or more processors) for executing such instructions. In this embodiment, the machine-readable storage medium can store instructions that, when executed by the processing resources, implement the processing engine (208). In such an embodiment, the system (110) may include a machine-readable storage medium for storing instructions and processing resources for executing the instructions, or the machine-readable storage medium may be separate but accessible to the system (110) and the processing resources. In other embodiments, the processing engine (208) may be implemented by an electronic circuit.

[0062] In one embodiment, the processor (202) can use the data acquisition engine (212) to receive signals from the PHY of NR with OFDM. The processor (202) can store the information corresponding to the received signals in the database (210). The received signals may be based on complex low PAPR signals.

[0063] In one embodiment, the processor (202) can use the CORDIC technique to determine the magnitude and phase of the received signal. Further, the processor (202) can generate a PSW associated with the magnitude and phase of the received signal. The processor (202) can generate the PSW using the PC technique for multiplexing the received signal.

[0064] In one embodiment, the processor (202) can interpolate the received signal into n factors to generate a received signal including a predetermined peak regrowth. The processor (202) can utilize AIP technology to generate a received signal including a predetermined peak regrowth. AIP may include a FIR-based interpolator for generating a received signal including a predetermined peak regrowth.

[0065] In one embodiment, the processor (202) can generate one or more pulses to cancel the peaks related to the predetermined peak regrowth of the received signal to generate a modified n-factor signal. Further, the processor (202) can utilize WCFR technology to remove the canceled peaks included in the received signal. The processor (202) can use DPROM to store the canceled peaks after removal.

[0066] In one embodiment, the processor (202) can generate a PAPR-reduced signal before DUC and decimate the modified n-factor signal to generate a CFR with suppressed peak regrowth. Further, the processor (202) may use a downsampler for decimating the modified n-factor signal. The downsampler can subtract the modified n-factor signal from the received signal to generate a signal with reduced PAPR.

[0067] FIG. 2 illustrates the components of the system (110). However, in other embodiments, the system (110) may include a different number, type, and arrangement of components than those in FIG. 2, or additional functions not shown in FIG. 2. Further (or alternatively), the functions described herein as being performed by one or more components of the system (100) may be performed by one or more other components of the system (100).

[0068] FIG. 3 shows an example of a CFR design (300) combining PC and PW CFR in one embodiment of the present disclosure.

[0069] As shown in FIG. 3, the CFR design (300) may include cascade stages by conventional PC and PW CFR modules. In one embodiment, the CFR design (300) may include peak management means (302), clip stages (304-1 to 304-N), and PW CFR (306).

[0070] In one embodiment, the clip stages (304-1 to 304-N) can receive high PAPR input signals from a gNB base station (e.g., 112 in FIG. 1). In one embodiment, the peak management means (302) can acquire peak detection information and peak characteristics from the clip stages (304-1 to 304-N). Further, the peak management means (302) can generate peak cancellation pulses for the high PAPR input signals received from the clip stages (304-1 to 304-N), and further generate output signals. The peak management means (302) can generate a low PAPR signal via the PW CFR (306).

[0071] FIG. 4 shows an example of a clip stage (400) of PC CFR in one embodiment of the present disclosure.

[0072] As shown in FIG. 4, in one embodiment, the clip stage (400) can be composed of a CORDIC (402) followed by a peak detector (404). The delay estimator (406) circuit can delay the unscaled input before being subtracted by the cancellation pulses obtained from the peak management means (e.g., 302 in FIG. 3). The input of the clip stage (400) may be a polar-form complex 5G NR signal. This signal may be converted to a square shape to represent the peak. CORDIC (402) is a flexible iterative technique that can calculate several transcendental functions without the need for multipliers and can be used to minimize the footprint in hardware design.

[0073] In one embodiment, the output of the CORDIC (402) may be transferred to a peak detector (404), which can detect peaks within each interval of the samples (collectively referred to as PSW). Further, the peak characteristics may be passed to the peak management means (302) section. The peak detector (404) can also collect data regarding the height of the detected peaks, and this data may be used for statistical purposes, threshold adjustment, and measurement of the length of the PSW.

[0074] In one embodiment, the output signal can be processed by a PW CFR module (such as 306 in FIG. 3) to generate a low 5G PAPR signal.

[0075] FIG. 5 shows an example of a flow diagram (500) of an algorithm state machine (ASM) in one embodiment of the present disclosure.

[0076] As shown in FIG. 5, the ASM can include the following steps.

[0077] Step 502: Initialize the ASM.

[0078] Step 504: The ASM determines whether the magnitude of the received signal input is greater than a threshold.

[0079] Step 506: If it is determined in step 504 that the magnitude of the input is greater than the threshold, the ASM stores the input data / signal including the corresponding magnitude and phase. If it is determined in step 504 that the magnitude of the input is less than the threshold, the ASM returns to step 502.

[0080] Step 508: The ASM increments the PSW count.

[0081] Step 510: The ASM determines whether the current maximum peak is greater than the previous maximum peak.

[0082] Step 512: If it is determined in step 510 that the current maximum peak is greater than the previous maximum peak, the ASM updates the size, phase, and displacement details.

[0083] Step 514: If it is determined in step 510 that the current maximum peak is less than the previous maximum peak, the ASM determines whether the PSW has ended.

[0084] Step 516: If it is determined in step 514 that the PSW has ended, the ASM transmits the peak threshold, phase, and displacement details to the peak management means (e.g., 302) and further proceeds to step 502. If it is determined in step 514 that the PSW has not ended, the ASM resumes step 508.

[0085] FIG. 6 shows an example of the peak management means (600) of the PC CFR in one embodiment of the present disclosure.

[0086] As shown in FIG. 6, the peak management means (600) of the PC CFR may be a centralized unit that obtains the notifications and characteristics of the peaks detected from all clip stages (604 to 608), generates cancellation pulses accordingly, and sends them back to the appropriate clip stage to cancel the peaks. An important unit of the peak management means (600) is the peak cancellation unit (PCU) (602), and the efficiency of the PCU (602) determines the overall efficiency of the PC CFR unit. The PCU (602) operates in parallel and can generate cancellation pulses. These cancellation pulses may be subtracted later from the actual input signal that has not been scaled. Each time peak information is passed to the peak management means (600), the peak management means (600) determines whether any PCU (602) is available, enables the peak assignment, and can record the unassigned peaks in a peak list. The peak management means (600) may operate in a shared manner to reduce the resource utilization rate, that is, the same peak management means (600) may be shared among multiple clip stages.

[0087] FIG. 7 shows an example of PW CFR in one embodiment of the present disclosure.

[0088] As shown in FIG. 7, PW CFR can attenuate peaks exceeding a threshold value for the low PAPR 5G signal received from PC CFR. Also, PW CFR is independent of the carrier configuration of the input signal. The length of filter (704) affects the amount of signal spread on the side of the frequency domain. If the filter (704) is made very long, spatter will decrease, but the added error vector magnitude (EVM) may increase. Therefore, when selecting the window length, there may be a trade-off between adjacent channel leakage ratio (ACLR) and EVM. However, by using WCFR, unlike the pulse cancellation method, peak transmission can be prevented. However, the performance of WCFR may generally be lower than that of PC CFR. The degree of degradation is proportional to the number of peaks that need to be canceled. Therefore, WCFR can include an ideal processing stage with few peaks and little degradation even without peak escape cancellation. In the implementation of the present invention, WCFR is supported as a post-processing stage. This makes it easier to control peak EVM and reduce PC CFR iterations. If smart peak processing is enabled to clean up the remaining peaks after cancellation and improve PAPR, WCFR may be a necessary stage after processing.

[0089] In one embodiment, as shown in FIG. 7, detector (702) can receive a low PAPR 5G signal from PC CFR. The detector (702) can cancel the peaks included in the low PAPR 5G signal and process the low PAPR 5G signal based on a threshold value. Window filter module (704) can filter the processed low PAPR 5G signal. Further, by passing the unscaled low PAPR signal through delay module (706), a predetermined delay based on the unscaled low PAPR signal can be generated. The filtered / processed low PAPR 5G signal with the necessary gain correction can be subtracted from the unscaled low PAPR signal. Thereby, a low PAPR 5G signal with the necessary peak correction can be generated from WCFR.

[0090] FIG. 8 shows an example of a complementary cumulative distribution function (CCDF) plot (800) of the CFR output in one embodiment of the present disclosure.

[0091] As shown in FIG. 8, PC CFR can generate a correction of 4.4 decibels (dB) (from 9.93 dB to 7.5 dB in PAPR). Further, PW CFR can also eliminate the extra peaks and generate a correction up to 7.38 dB.

[0092] FIG. 9 shows an example of a comparison (900) of 5G signals before and after CFR in one embodiment of the present disclosure.

[0093] Here, various 5G signals before and after incorporating CFR are being compared. The impact of CFR incorporation can be analyzed by the amplitudes of various 5G signals.

[0094] FIG. 10 shows an example of a CCDF plot (1000) of the DUC output at X2 in one embodiment of the present disclosure.

[0095] As shown in FIG. 10, in order for the PA to operate at a high data rate, the input signal can be upscaled by a factor of x4 using a FIR-based interpolator. In this case, the PAPR of the CFR output signal indicates the effect of interpolation. Further, by analyzing the CCDF plot (1000) after DUC, the change in the average power sent to the PA can be observed.

[0096] FIG. 11 shows an example of a CCDF plot (1100) of the DUC output at X4 in one embodiment of the present disclosure.

[0097] As shown in FIG. 11, the PAPR of the signal output can be analyzed for both the x2 DUC output and the x4 DUC output. As shown in FIG. 11, peak regrowth may be observed after interpolation. Such peak regrowth causes an increase in the PAPR of the scaled and peak-removed CFR output signal.

[0098] FIG. 12 shows an example of peak analysis (1200) using the input signal and output signal when CFR is X1 in one embodiment of the present disclosure.

[0099] As shown in FIG. 12, the input signal can be upscaled to a higher data rate by interpolation. Further, two additional processes can also be used as the first upsampling and subsequent FIR filtering. In upsampling, zeros may be added between the input signals to increase the data rate. Also, by filtering, the zero values can be further processed to defined values. As shown in FIG. 12, 13731 input samples fall below the threshold and may be ignored by the peak detector (e.g., 404 or 702) during CFR processing. Although the output of CFR can also be observed, since there is no change in the amplitude of the samples, it can be seen that the peak regrowth does not depend on the CFR process. However, after the X2 DUC output, the amplitude of the input signal increases exponentially, and the interpolated component of the input signal shows regrowth. The peak of the X1 sample at 13763 rises adjacent to the X2 component at 27547. This peak regrowth is observed by interpolation.

[0100] FIG. 13 shows an example of peak analysis (1300) in the X2 and X4 DUC outputs according to an embodiment of the present disclosure.

[0101] As shown in FIG. 13, since the peak of the original signal of X1 at 13763 has the peak magnitude at 27548 retained, it may not regrow. Also, considering the delay coefficients generated by the FIR filter in interpolation, the calculation of the peak position may be considered. Thus, based on the necessary calculation [(13763 + 11)*2 = 27548], a delay of 11 samples may be observed. Regrowth is only observed after DUC and may not be detected in CFR. However, the peak may cause problems in both digital predistortion (DPD) and PA, and due to the high PAPR, the PA may move into the saturation region.

[0102] FIG. 14 shows an example of another form of clip stage (1400) using the AIP module in the CFR proposed according to an embodiment of the present disclosure.

[0103] As shown in FIG. 14, by directly using the X4 interpolation signal as the CFR input instead of using the X1 signal, the problem of regrowth can be avoided. However, when using the X4 signal, the entire CFR module operates at a higher data rate, and the hardware resources may increase four times compared to the previous X1 design. Thus, the possibility of a shortage of resources in the FPGA module is also considered.

[0104] In one embodiment, as shown in FIG. 14, an AIP interpolator (1402) can be introduced into the clip stage of the PC CFR module. The AIP interpolator (1402) is an X4 interpolator, and a high PAPR input signal can be directly supplied to the x4 AIP interpolator (1402). The interpolated signal can be converted from the orthogonal form to the polar form using a CORDIC converter (1404). The X4 AIP interpolator (1402) may cause peak regrowth similar to that seen during upsampling of the input signal by the DUC. Further, multiple peaks may be detected by the peak detection module (1406). The peak detection module (1406) can also transmit peak magnitude, peak phase, and displacement information to the peak management means (e.g., 302). The peak management means (302) can generate the necessary cancellation pulses, and the cancellation pulses may be scaled to the new peaks. The delay estimator (1408) can delay the unscaled original input signal. The cancellation pulses may affect the interpolated signal and the original input signal. The cancellation pulses can remove the peaks generated by interpolation. An AIP downsampler (1410) may be arranged to downsample the signal (i.e., downsample from X4 to the original X1) in order to subtract the interpolated signal from the original signal. The downsampler (1410) may be a simple module that selects the actual X1 data samples and discards all other data samples.

[0105] FIG. 15 shows an example of a CCDF plot (1500) of the CFR output at X1 when using AIP in one embodiment of the present disclosure.

[0106] As shown in FIG. 15, in the X1 DUC output using AIP, fluctuations in frequency (dB) with respect to the average power may be observed.

[0107] FIG. 16 shows an example of a CCDF plot (1600) of the DUC output at X4 when using AIP in one embodiment of the present disclosure.

[0108] As shown in FIG. 16, in the X4 DUC output using AIP, fluctuations in frequency (dB) with respect to the average power may be observed.

[0109] FIG. 17 shows an example of the comparison (1700) of 5G signals before and after CFR when using AIP in one embodiment of the present disclosure.

[0110] As shown in FIG. 17, 5G signals before and after CFR using AIP can be compared. Analyzing the amplitudes of various signals before and after CFR using AIP, significant changes due to the incorporation of AIP can be observed.

[0111] FIG. 18 shows an example of the peak analysis (1800) of the input signal and output signal at X1 when using AIP in one embodiment of the present disclosure.

[0112] As shown in FIG. 18, observing the input samples, the sample of 13731 may show a value below the threshold level. Therefore, by passing the input signal through the AIP module, peak regrowth can be identified and removed in advance.

[0113] FIG. 19 shows an example of the peak analysis (1900) in the X2 DUC output and X4 DUC output when using AIP in one embodiment of the present disclosure.

[0114] As shown in FIG. 19, the sample of 13763 has an amplitude smaller than the input signal by detecting and removing the peak component. By reducing the amplitude of the peak component by AIP interpolation, the possibility of peak regrowth in the x4 DUC can be eliminated.

[0115] FIG. 20 shows an example of the hardware block diagram (2000) of the AIP integrated CFR in one embodiment of the present disclosure.

[0116] As shown in FIG. 20, CORDIC (2004) can calculate the instantaneous magnitude and phase of the input 5G signal. The peak detector (2012) includes registers and comparators and can output a "1" when the peak magnitude is found. The output of the peak detector (2012) can also be connected to enable the ports of two latches that store the magnitude and phase of the corresponding peak. The interval locator block (2010) can generate an output "1" between two peaks when the interval between the peaks is shorter than the length of the cancellation pulse. The outputs of the peak detector (2012) and the interval locator block (2010) can be combined with an OR gate (2016). A fixed delay can be provided in the interval locator block (2010). Therefore, a delay block (2006) can be used to align these two types of signals. The cancellation pulse duration block (2014) can generate an enable signal for a counter that outputs the address of a dual-port random access memory (DPRAM). The counting direction of the counter can be controlled by a latch output that is inverted by the trigger output of the OR gate (2016). Further, the DPROM (2018) can be scaled and rotated by the latched magnitude and phase to form a cancellation pulse. The smoothed cancellation pulse is subtracted from the delayed original signal to form a PAPR-reduced signal.

[0117] FIG. 21 shows an example of a computer system (2100) in which the proposed system is implemented or implemented together with the proposed system. In one embodiment, the system (110) can also be implemented as a computer system (2100).

[0118] As shown in FIG. 21, a computer system (2100) can include an external storage device (2110), a bus (2120), a main memory (2130), a read-only memory (2140), a mass storage device (2150), a communication port (2160), and a processor (2170). Those skilled in the art will understand that the computer system (2100) may include multiple processors and communication ports. The processor (2170) can include various modules related to the embodiments of the present disclosure. The communication port (2160) can be an RS-232 port for use in a modem-based dial-up connection, a 10 / 100 Ethernet port, a 1 gigabit port or a 10 gigabit port using copper wire or optical fiber, a serial port, a parallel port, or any other existing or future port. The communication port (2160) can be selected according to any network to which the computer system (2100) is connected, such as a local area network (LAN) or a wide area network (WAN).

[0119] In one embodiment, the main memory (2130) can be a random access memory (RAM) or any other dynamic storage device generally known in the art. The read-only memory (2140) can be any static storage device, such as a programmable read-only memory (PROM) chip for storing static information such as the startup of the processor (2170) or basic input / output system (BIOS) instructions, but is not limited thereto. The mass storage device (2150) can be any current or future mass storage device solution capable of storing information and instructions. Mass storage solutions include, for example, but are not limited to, parallel advanced technology attachment (PATA) or serial advanced technology attachment (SATA) hard disk drives, or solid state drives (for internal use or external use with a universal serial bus (USB) and / or Firewire interface).

[0120] In one embodiment, the bus (2120) can couple the processor (2170) to communicate with other memories, storage, and communication blocks. The bus (2120) can be, for example, a Peripheral Component Interconnect (PCI) / PCI Extended (PCI-X) bus for connecting expansion cards, drives, and other subsystems, a Small Computer System Interface (SCSI), a Universal Serial Bus (USB), or other buses such as a Front Side Bus (FSB) that connects the processor (2170) to the computer system (2100).

[0121] In another embodiment, an operation / administration interface, such as a display, keyboard, cursor control device, is also connected to the bus (2120) to enable direct operation of the computer system (2100) by an operator. Other operation / administration interfaces can be connected via a network connected through the communication port (2160). The above components are only intended to illustrate various possibilities. The foregoing exemplary computer system (2100) is in no way intended to limit the scope of the present disclosure.

[0122] Although a considerable emphasis has been placed on the preferred embodiments in the present disclosure, the present invention can take many embodiments without departing from the disclosed principles. It will be understood that many changes may be made to the preferred embodiments. These and other changes to the preferred embodiments of the present disclosure will be apparent to those skilled in the art from the disclosure herein. It should be clearly understood that the foregoing description is merely illustrative of the present disclosure and not limiting.

[0123] The present invention provides a system and method that can perform Crest Factor Reduction (CFR) prior to Digital Up-Conversion (DUC) at a lower data rate while suppressing peak regrowth to a minimum (about 0.5 dB).

[0124] The present invention provides a system and method that can reduce the usage rate of field programmable gate array (FPGA) resources while performing CFR at a low data rate before DUC.

[0125] The present invention provides a system and method that utilize a dual-port read-only memory (ROM) that helps reduce the number of random access memory (RAM) blocks for storing cancellation pulse coefficients of multi-input multi-output (MIMO) chains.

[0126] The present invention provides a system and method that can reduce the resource utilization rate in multiple MIMO chains.

[0127] The present invention provides a system and method that can reduce the resource usage rate by operating multiple MIMO channels (4 channels in the case of a 4-fold operating clock) through multiplexing in the time domain.

Claims

1. A crest factor reduction (CFR) system (110) for suppressing peak regrowth, comprising a processor (202), a memory (204) operably coupled to the processor (202), and when instructions stored in the memory (204) are executed by the processor (202), receiving a signal from a physical layer (PHY) of a base station (112) having orthogonal frequency division multiplexing (OFDM), wherein the received signal is based on a complex low peak-to-average power ratio (PAPR) signal; interpolating the received signal by an n-factor to generate a received signal including a predetermined peak regrowth; generating one or more pulses to cancel peaks associated with the predetermined peak regrowth of the received signal to generate a modified n-factor signal; generating a PAPR-reduced signal prior to digital upconversion (DUC) and decimating the modified n-factor signal to generate a CFR with suppressed peak regrowth; The system (110) causes the processor (202) to execute.

2. The system (110) according to claim 1, wherein the processor (202) is configured using coordinate rotation digital computer (CORDIC) technology to determine the magnitude and phase of the received signal.

3. The system (110) according to claim 2, wherein the processor (202) is configured to generate a peak search window (PSW) associated with the magnitude and phase of the received signal.

4. The system (110) according to claim 3, wherein the processor (202) multiplexes the received signal and is configured using peak cancellation (PC) technology to generate the PSW.

5. The system (110) according to claim 1, wherein the processor (202) is configured using advanced interpolation processing (AIP) technology to generate the received signal including the predetermined peak regrowth.

6. The system (110) according to claim 5, wherein the AIP technology uses a finite impulse response (FIR)-based interpolator to generate a received signal including the predetermined peak regrowth.

7. The system (110) according to claim 1, including a downsampler for decimating the modified n-factor signal.

8. The downsampler subtracts the modified n-factor signal from the received signal to generate the PAPR-reduced signal, the system (110) according to claim 7.

9. The processor (202) is configured using window crest factor reduction (WCFR) technology to remove the cancellation peaks included in the received signal, the system (110) according to claim 1.

10. The processor (202) is configured to include a dual-port read-only memory (DPROM) to store the removed peaks after being canceled, the system (110) according to claim 9.

11. A crest factor reduction (CFR) method for suppressing peak regrowth, Receiving a signal by a processor (202) associated with a system (110) from a physical layer (PHY) of a base station (112) with orthogonal frequency division multiplexing (OFDM), wherein the received signal is based on a complex low peak-to-average power ratio (PAPR) signal, receiving the signal; Interpolating, by the processor (202), the received signal to an n-factor to generate a received signal including a predetermined peak regrowth; Generating, by the processor (202), one or more pulses to cancel peaks associated with the predetermined peak regrowth of the received signal to generate a modified n-factor signal; Generating, by the processor (202), a PAPR-reduced signal before digital upconversion (DUC) and decimating the modified n-factor signal to generate CFR with suppressed peak regrowth; A method including.

12. Determining, by the processor (202), the magnitude and phase of the received signal by means of coordinate rotation digital computer (CORDIC) technology, the method according to claim 11.

13. Generating, by the processor (202), a peak search window (PSW) associated with the magnitude and phase of the received signal, the method according to claim 12.

14. Multiplying, by the processor (202), the received signal for generating the PSW by means of peak cancellation (PC) technology, the method according to claim 13.

15. The method of claim 11, comprising generating, by the processor (202), the received signal including the predetermined peak regrowth using an advanced interpolation processing (AIP) technique. **Claim 16** A non-transitory computer-readable medium comprising a processor having executable instructions, the method comprising: Receiving a signal from a physical layer (PHY) of a base station (112) comprising orthogonal frequency division multiplexing (OFDM), wherein the received signal is based on a complex low peak-to-average power ratio (PAPR) signal; Interpolating the received signal by an n-factor to generate a received signal including a predetermined peak regrowth; Generating one or more pulses to cancel peaks associated with the predetermined peak regrowth of the received signal to generate a modified n-factor signal; Generating a PAPR-reduced signal prior to digital upconversion (DUC) and decimating the modified n-factor signal to generate a CFR with suppressed peak regrowth; A non-transitory computer-readable medium that causes the processor to perform the above.

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