Method and apparatus for etching a semiconductor substrate in a plasma etching chamber

Abstract

A method and apparatus for etching a substrate in a plasma etch chamber are provided. In one example, the method includes exposing a substrate disposed on a substrate support surface of a substrate support to a plasma within a processing chamber, and applying a voltage waveform to an electrode disposed within the substrate support while the substrate is being exposed to the plasma during a plurality of macro etch cycles. Each macro etch cycle includes a first macro etch period and a second macro etch period. The macro etch periods include a plurality of micro etch cycles. Each micro etch cycle has a bias power on (BPON) period and a bias power off (BPOFF) period, and the duration of the BPON period is less than the duration of the BPOFF period. Little bias power is applied to the electrode during the second macro etch period.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to systems and methods used in semiconductor device manufacturing. More particularly, the embodiments provided herein generally include apparatuses and methods for etching a semiconductor substrate in a plasma etch chamber.

Background Art

[0002] Ensuring the generation of high aspect ratio features is one of the important technical challenges related to next-generation semiconductor devices. One way to form high aspect ratio features is to use a plasma-assisted etching process, such as a reactive ion etch (RIE) plasma process, to form high aspect ratio openings in a material layer, such as a dielectric layer, of a substrate. In a typical RIE plasma process, a plasma is formed in a processing chamber, and ions from the plasma are accelerated towards the surface of the substrate to form an opening in a material layer disposed under a mask layer formed on the surface of the substrate.

[0003] A typical reactive ion etch (RIE) plasma processing chamber includes a radio frequency (RF) generator that supplies RF power to a power electrode, such as a metal plate disposed adjacent to an electrostatic chuck (ESC) assembly, more commonly referred to as a "cathode". The power electrode can be capacitively coupled to the plasma of the processing system by a thick layer of a dielectric material (e.g., a ceramic material) that is part of the ESC assembly. In a capacitively coupled gas discharge, the plasma is created by using an RF matching network ("RF match") that matches the skin depth load to 50 Ω to minimize reflected power and maximize power supply efficiency, and coupling it to the power electrode, or to a separate power electrode disposed outside the ESC assembly and within the processing chamber, of an RF generator.

[0004] In applications of high aspect ratio etching, it is often difficult to maintain the perpendicularity of the etched features. In particular, asymmetries in any one of the ground return path, RF power supply, pattern density, flow conductance, and substrate charging are often responsible for the loss of perpendicularity of the sidewalls of the features being etched (also known as tilting). In some cases, sidewall tilting can affect device performance and even lead to device failure.

[0005] Therefore, there is a need for improved methods and apparatus for plasma etching. SUMMARY OF THE INVENTION

[0006] A method and apparatus for etching a semiconductor substrate in a plasma etch chamber are provided. In one example, the method includes exposing a substrate disposed on a substrate support surface of a substrate support to a plasma in a processing chamber, and applying a voltage waveform to an electrode disposed in the substrate support while the substrate is being exposed to the plasma during a plurality of macro etch cycles. Each macro etch cycle includes a first macro etch period and a second macro etch period. The macro etch period includes a plurality of micro etch cycles. Each micro etch cycle has a bias power on (BPON) period and a bias power off (BPOFF) period, and the duration of the BPON period is less than the duration of the BPOFF period. Little bias power is applied to the electrode during the second macro etch period.

[0007] In another example, forming a plasma from a process gas containing carbon and at least one halogen, exposing a dielectric layer disposed on a semiconductor substrate in a plasma etching chamber to the plasma, and applying a bias power to the semiconductor substrate while it is being exposed to the plasma during a plurality of macro-etch cycles until an endpoint is reached. A method for etching a semiconductor substrate in a plasma etching chamber is provided. Each macro-etch cycle includes a first macro-etch period and a second macro-etch period. The macro-etch period includes a plurality of micro-etch cycles. Each micro-etch cycle has a bias power on period and a bias power off period. The duration of the BPON period is less than the duration of the BPOFF period. Little bias power is applied to the electrodes during the second macro-etch period. At least in the macro-etch cycle, the bias power on period is at least two orders of magnitude shorter in duration than the first macro-etch period, and the bias power off period is at least two orders of magnitude shorter in duration than the second macro-etch period.

[0008] In yet another example, a plasma etch chamber is provided. The plasma etch chamber includes a chamber body having an internal space, a substrate support disposed in the internal space of the chamber body, a bias power control system, a gas panel, and a controller. The substrate support is configured to hold a semiconductor substrate thereon during processing. The substrate support has a bias electrode. The bias power control system is coupled to the bias electrode. The gas panel is configured to supply a process gas to the internal space. The controller is configured to maintain a plasma formed from the process gas within the plasma etch chamber and to apply a bias power to the bias electrode while a semiconductor substrate disposed on the substrate support is exposed to the plasma during a plurality of macro etch cycles. Each macro etch cycle includes a first macro etch period and a second macro etch period. The macro etch period includes a plurality of micro etch cycles. Each micro etch cycle has a bias power on period and a bias power off period. The duration of the BPON period is less than the duration of the BPOFF period. Little bias power is applied to the electrode during the second macro etch period.

[0009] As can be appreciated in order to understand the features recited above of the present disclosure in detail, a more detailed description of the disclosure briefly summarized above can be obtained by reference to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings merely illustrate exemplary embodiments and should not be considered as limiting its scope, and other equally effective embodiments may be permitted.

Brief Description of the Drawings

[0010]

Figure 1

Figures 2A-2D

Figure 3

Figure 4

Figure 5

Best Mode for Carrying Out the Invention

[0011] For ease of understanding, where possible, the same reference numbers are used to designate equivalent elements common to the figures. It is contemplated that the elements and features of one embodiment may be advantageously incorporated into other embodiments without further recitation.

[0012] Embodiments of the present disclosure generally relate to systems used in semiconductor device manufacturing. More particularly, the embodiments provided herein generally include apparatuses and methods for etching a substrate in a plasma etch chamber in a manner that reduces tilting of the vertical sidewalls of features being etched. Such improvements are achieved by modulating the waveform used to apply bias power to the electrodes of a substrate support utilized to support a substrate during etching in both a macro regime and a micro regime. In the macro regime, multiple macro etch cycles are utilized to etch the substrate. The waveform includes a period during which the bias power is essentially stopped during a portion of each macro etch cycle to allow etch by-products to be exhausted from the plasma etch chamber. By periodically removing etch by-products from the chamber, the etchant can be more effectively supplied to features being etched using a vertical track. In the micro regime of the waveform, multiple micro etch cycles are utilized during a portion of each macro etch cycle. Each micro etch cycle includes a first period during which the bias power is on and a second period during which the bias power is essentially stopped. The duration of the second period is longer than the duration of the first period to provide time for etch by-products to exit from the features (holes, trenches, etc.) being etched. By periodically removing etch by-products from the features being etched, the etchant can be more effectively supplied to the bottom of the features being etched using a vertical track. When the number of collisions between the etchant and the etch by-products is reduced, the etchant can more substantially maintain a vertical track all the way to the bottom of the features being etched, thereby reducing sidewall etching and thus advantageously obtaining excellent verticality of the sidewalls of the features being etched. The improvement in verticality is particularly desirable when forming high aspect ratio features by etching.

[0013] Next, referring to FIG. 1, a flowchart of an example of a method 100 for etching a substrate is shown. Method 100 can be implemented in a plasma etch chamber, an example of which is shown later in FIG. 5. Method 100 can alternatively be implemented in other suitable plasma processing chambers. Method 100 will be best described with further reference to FIGS. 2A through 2D, which show partial cross-sectional views of the substrate 200 during various stages of the etching method 100. Method 100 can be utilized to etch, among other features, contact vias and trenches. Method 100 is particularly useful when etching high aspect ratio (height-to-width ratio greater than 10) features where the verticality of the etched features has a high impact on the performance of the device.

[0014] Method 100 begins, in operation 102, by exposing a substrate 200 disposed on a substrate support surface of a substrate support within a plasma etch chamber to a plasma. As shown in FIG. 2A, the substrate 200 generally includes a patterned mask 204 disposed on an upper surface 210 of a target material 202 to be etched. The mask 204 can be a photoresist, a hard mask, a combination thereof, or other suitable mask. The patterned mask 204 includes an opening 206 that leaves a portion 208 of the upper surface 210 of the target material 202 exposed to the plasma for etching. The substrate 200 can have one or more additional layers (not shown) disposed below a bottom surface 212 of the target material 202.

[0015] In one example, the target material 202 is a dielectric layer. For example, the target material 202 can be an oxide layer. In other examples, the target material 202 can be a metal or semiconductor material.

[0016] In other examples, the target material 202 can include multiple layers. In FIG. 2A, the target material 202 includes a first material 202 B disposed on a second material 202 A The first material 202 A and the second material 202B It is a different material. For example, one of the first materials 202 A is an oxide layer or a nitride layer, and the second material 202 B is the other of the oxide layer or the nitride layer. In yet another example, the target material 202 includes a plurality of pairs of alternating oxide layers and nitride layers.

[0017] The plasma is formed either within the plasma etch chamber or away from the plasma etch chamber and supplied into the plasma etch chamber. The plasma is generally formed from a suitable process gas for etching the target material 202. For example, when the target material 202 is a dielectric material, the process gas may include carbon and halogen containing the gas. Examples of suitable carbon and halogen containing the gas include C X H Y F Z in a modified form, where X, Y, and Z are integers. Other examples of suitable carbon and halogen containing the gas include C X F Z in a modified form, where X and Z are integers. In yet another example where the target material 202 includes one or more metals, the process gas may include Cl and / or oxygen. In yet another example where the target material 202 is silicon, the process gas may include Cl and / or fluorine such as carbon tetrachloride (CCl4), trifluoromethane (CHF3), etc. In any of the above examples, one or more polymer cleaning gases (O2, N2, NF3, etc.) and / or one or more inert gases (He, Ar, Kr, etc.) may optionally be provided as part of the process gas.

[0018] In operation 104, as shown in FIG. 2B, while the substrate 200 is being exposed to plasma during a plurality of macro-etch cycles to etch the substrate 200, a voltage waveform is applied to an electrode disposed in the substrate support. Each macro-etch cycle includes a first macro-etch period and a second macro-etch period. The first macro-etch period is generally used to etch a portion 208 of the target material 202 of the substrate 200 that is exposed through the opening 206 of the patterned mask 204. Each macro-etch cycle can have a duration of several milliseconds. Within a macro-etch cycle, the first macro-etch period is generally longer than the second macro-etch period. For example, the first macro-etch period can be three times or more longer than the second macro-etch period.

[0019] During the first macro-etch period, the voltage waveform includes a plurality of micro-etch cycles. Each micro-etch cycle can have a duration of several microseconds. Thus, the duration of the macro-etch period is generally of a larger order of magnitude than the duration of the micro-etch cycle, for example, two to three or more orders of magnitude larger.

[0020] Each micro-etch cycle includes a bias power-on period and a bias power-off period. During the bias power-on period, DC power is applied to an electrode disposed in the substrate support. During the bias power-off period, little DC power is applied to the electrode disposed in the substrate support, where applying little DC power is defined as not applying DC power from a DC power source coupled to the electrode between 0% and 10% of the duration of the bias power-off period. In one example, for the entire duration of the bias power-off period, essentially no DC power is applied to the electrode disposed in the substrate support.

[0021] The DC power applied to the electrodes during the bias power-on period effectively guides the etchant from the plasma vertically into the feature 224 to etch the exposed portion 208 of the target material 202. Similarly, if little DC power is applied to the electrodes during the bias power-off period, the target material 202 on the substrate 200 is not etched, and thus the etch by-products can exit from the feature 224 where they are etched. Advantageously, during the bias power-off period, it becomes possible to substantially remove the etch by-products from the feature 224, so that during the next bias power-on period, the DC power applied reduces the probability of collision with the by-products in the feature 224 while guiding the etchant vertically to the bottom 220 of the feature 224 being etched. As a result, the bottom 220 of the feature is etched vertically with little etching of the sidewalls 222 of the feature 224. When the etching of the sidewalls 222 of the feature 224 is reduced, a highly vertical sidewall 222 advantageously results.

[0022] Similarly, during the second macro-etch period, little DC power is applied to the electrodes disposed in the substrate support, and thus, between 0% and 10% of the duration of the second macro-etch period, no DC power is applied from the DC power source coupled to the electrodes. In one example, for the entire duration of the second macro-etch period, essentially no DC power is applied to the electrodes disposed in the substrate support.

[0023] Similar to the bias power off period of the second micro-etch cycle where little DC power is applied to the electrode, during the second macro-etch period, the target material 202 of the substrate 200 is also not etched. The millisecond duration of the second macro-etch period is such that it enables the removal of etch by-products from the region directly above the substrate 200 that emerged from the feature 224 etched during the bias power off period of the previously completed first macro-etch cycle, and to send them out of the plasma etch chamber. When the etch by-products are removed from the region directly above the substrate 200, the next macro-etch cycle is executed with a reduced number of collisions between the residual etch by-products and the etchant introduced into the feature 224, and thus, the verticality of the feature 224 being etched can be further improved. In comparison, since more time is required to send the by-products out of the chamber compared to sending the by-products out from the feature 224, the duration of the second macro-etch period is 100 to over 1000 times longer than the duration of the second micro-etch period.

[0024] The macro-etch cycle is repeated until it reaches the end point in operation 106, which is when the depth of the feature 224 being etched reaches a predefined depth D. As shown in Figure 2B, it is the end point of the process for etching the target material 202 at a depth D that does not penetrate the target material 202. The end point of the process for etching the target material 202 can be determined, among other techniques, by monitoring the optical spectrum of the plasma composition, interferometry, or timed etch.

[0025] The second material 202 B The first material 202 disposed thereon A In some examples where the target material 202 includes multiple layers, such as, as shown in Figure 2C, the end point depth D may exceed the thickness of the first material 202 A but is less than the thickness of the second material 202 BDo not break through. In still other examples where the target material 202 includes a single layer or multiple layers, as shown in FIG. 2D, when the feature 224 being etched breaks through the target material 202 such that the bottom 220 of the feature 224 is defined by a layer (not shown) beneath the target material 202, the depth D at each endpoint is reached.

[0026] FIG. 3 is an example of a bias power timing diagram showing a waveform 320 that includes a plurality of macro etch cycles 302 utilized to reach an endpoint at a time (T E ) during the execution of a method for etching a substrate 200, such as the method 100 described above or other similar etching processes. Although not shown in FIG. 3, for example, in operation 106 described above, when the endpoint is reached at time (T E ), the end of the plurality of macro etch cycles 302 can be truncated. In the bias power timing diagram shown in FIG. 3, the vertical axis represents the DC power applied to an electrode disposed in the substrate support, while the horizontal axis represents time. The total duration 310 of the etching process to reach the endpoint depth D spans from time (T0) to the endpoint at time (T E ).

[0027] Each macroetch cycle 302 generally has a duration of from 1 to 250 milliseconds, although not limited thereto. As described above, each macroetch cycle 302 includes a first macroetch period 304 and a second macroetch period 306. Although not essential, the first macroetch period 304 occurs before the second macroetch period 306. The first macroetch period 304 has a duration longer than that of the second macroetch period 306. In one example, the first macroetch period 304 has a duration that is at least 70 percent of the total duration of the macroetch cycle 302. In another example, the first macroetch period 304 has a duration that is at least 80 percent of the total duration of the macroetch cycle 302. In one example, the duration of the second macroetch period 306 is selected to be sufficient to expel most of the etch by-products in the process volume above the substrate support.

[0028] In some examples, the amount of etch by-products in the process volume above the substrate support can vary at different times over the duration 310 of the entire etch process. For example, as the feature 224 being etched becomes deeper, the amount of etch by-products in the process volume above the substrate support per unit time can decrease. Thus, the ratio of the duration of the first macroetch period 304 to the duration of the second macroetch period 306 can increase as the process proceeds over the duration 310, particularly as it approaches the end point at time (T E ). Alternatively, the ratio of the duration of the first macroetch period 304 to the duration of the second macroetch period 306 can be different for etching the first material 202 B compared to etching the second material 202 A .

[0029] The frequency of the macro-etch cycle 302 is generally in the range of one digit to several hundred Hz. For example, the frequency of the macro-etch cycle 302 can be, but is not limited to, from about 5 Hz to about 100 Hz. The frequency of the macro-etch cycle 302 may be constant or may vary over the entire duration 310 for etching the feature 224. For example, the frequency of the macro-etch cycle 302 can be higher in the portion of the waveform 320 closer to T0 than in the portion of the waveform 320 closer to T E It can be higher in the portion of the waveform 320 closer to T0 than in the portion of the waveform 320 closer to T. Using a lower frequency of the macro-etch cycle 302 at a deeper depth D has been proven to improve the perpendicularity of the sidewalls 222 of the feature 224 being etched by providing more time for by-product removal from the etching chamber during the active etching of the target material 202. Alternatively, the frequency of the macro-etch cycle 302 may be higher or lower in different portions of the duration 310 of the etching method 100.

[0030] As shown in FIG. 3, little DC power is applied to the electrodes of the substrate support during the second macro-etch period 306.

[0031] Referring again to the first macro-etch period 304, the first macro-etch period 304 includes a time when DC power is applied to an electrode disposed in a substrate support that supports a substrate in a plasma etching chamber. The etching of the target material 202 generally occurs when DC power is applied to the electrode, but does not occur when the DC power to the electrode is off. As will be further described below with reference to FIG. 4, DC power is cyclically applied to the electrode during the first macro-etch period 304.

[0032] FIG. 4 is an example of a bias power timing diagram that further details one macro etch cycle 302. In FIG. 4, the vertical axis represents the DC power applied to the electrodes disposed in the substrate support, while the horizontal axis represents time. Each macro etch cycle 302 (one of which is shown in FIG. 4) includes a single first macro etch period 304 and a single second macro etch period 306. Each first macro etch period 304 includes a plurality of micro etch cycles 402. Each micro etch cycle 402 includes a first micro etch period 404 and a second micro etch period 406.

[0033] As described above, the first macro etch period 304 is generally used to etch the portion 208 of the target material 202 of the substrate 200 that is exposed through the opening 206 of the patterned mask 204. To enable etching during each first macro etch period 304, bias power is applied to the electrodes of the substrate support during each first micro etch period 404. Since the first micro etch period 404 has a duration of several milliseconds, bias power is applied to the electrodes of the substrate support for many first micro etch periods 404 that include each first macro etch period 304 in order to effectively etch the target material 202.

[0034] The frequency of the bias power on period of the micro etch cycle 402 (e.g., DC power pulses) is generally in the range of one digit to several hundred kHz. For example, the frequency of the micro etch cycle 402 can be, but is not limited to, from about 25 kHz to about 600 kHz, e.g., from 25 kHz to about 500 kHz. The frequency of the micro etch cycle 402 may be constant over the duration of the macro etch cycle 302, may vary, and / or may be constant or vary over the duration 310 of the etching of the feature 224. For example, the frequency of the micro etch cycle 402 is T EIt can be higher in the portion of the waveform 320 closer to T0 than in the portion of the waveform 320 closer to T1. Using a lower frequency for the macro-etch cycle 402 at a deeper depth D gives more time for by-products to escape from the high aspect ratio feature 224 during the active etching of the target material 202 during each first micro-etch period 404, which has been proven to improve the verticality of the sidewall 222 of the feature 224 being etched. Alternatively, the frequency of the macro-etch cycle 402 may be higher or lower in different portions of the duration 310 of the etch method 100 to suit other needs.

[0035] During the micro-etch cycle 402, the voltage waveform 320 includes a first micro-etch period 404 and a second micro-etch period 406. The first micro-etch period 404 corresponds to a bias power on period, while the second micro-etch period 406 corresponds to a bias power off period. During the bias power on period of the first micro-etch period 404, DC power is applied to the electrodes disposed in the substrate support. During the bias power off period of the second micro-etch period 406, little DC power is applied to the electrodes disposed in the substrate support, where applying little DC power is defined as not applying DC power from the DC power source coupled to the electrodes between 0% and 10% of the duration of the bias power off period. In one example, for the entire duration of the bias power off period, essentially no DC power is applied to the electrodes disposed in the substrate support.

[0036] Thus, when DC power is applied to the electrode during the first micro-etch period 404, the bias power guides etchant from the plasma into the feature 224 being etched in the target material 202, so that the portion 208 of the target material 202 of the substrate 200 exposed through the opening 206 is effectively etched. Similarly, when little DC power is applied to the electrode during the second micro-etch period 406, the target material 202 of the substrate 200 is not etched, and thus, etch by-products can exit from the feature 224 being etched. Advantageously, during the second micro-etch period 406 (i.e., bias power off), it is possible to substantially remove etch by-products from the feature 224, so that the DC power applied during the next first micro-etch period 404 can direct the etchant vertically to the bottom 220 of the feature 224 being etched while reducing the probability of collision with by-products in the feature 224. The reduction of by-product collisions causes the bottom 220 of the feature to be etched vertically with little etching of the sidewalls 222 of the feature 224. When the etching of the sidewalls 222 of the feature 224 is reduced, a highly vertical sidewall 222 advantageously results.

[0037] Similar to the second macro-etch period 306, during the second micro-etch period 406, little DC power is applied to the electrode disposed in the substrate support. When DC power is not applied between 0% and 90% of the duration of the second micro-etch period 406, little DC power from the DC power source is applied to the electrode. In one example, for the entire duration of the second micro-etch period 406, essentially no DC power is applied to the electrode disposed in the substrate support.

[0038] By allowing sufficient time to remove by-products from feature 224, the ability to achieve extremely vertical sidewalls 222 is improved. Thus, the first micro-etch period 404 generally has a duration that is less than the duration of the second micro-etch period 406. In one example, the first micro-etch period 404 generally has a duration that is less than 45%, for example less than 30%, of the duration of the micro-etch cycle 402. In another example, the first micro-etch period 404 generally has a duration that is from about 10% to about 45%, for example less than 10% to about 15%, of the duration of the micro-etch cycle 402. Further, the time required to remove etch by-products from feature 224 may vary in different micro-etch cycles 402 within the same first macro-etch period 304 or between different first macro-etch periods 304. Thus, the ratio of the duration of the first micro-etch period 404 to the duration of the second micro-etch period 406 may decrease, increase, or remain constant over the course of the duration 310 of the etch process 100, and in particular, decreases as it approaches the end point at time (T E ). Alternatively, the ratio of the duration of the first micro-etch period 404 to the duration of the second micro-etch period 406 may differ for etching the first material 202 B compared to etching the second material 202 A . As an addition or alternative to adjusting the duration ratio between the first micro-etch period 404 and the second micro-etch period 406, the power applied to the bias electrode used to etch feature 224 in the target material 202 may vary in different micro-etch cycles 402 within the same first macro-etch period 304 or between different first macro-etch periods 304. For example, the power used in different micro-etch cycles 402 may decrease, increase, or be adjusted over the duration 310 of the etch process 100, within the same first macro-etch period 304 and / or within different first macro-etch periods 304. As an example, the first material 202 AThe power applied to the bias electrode during the first microetch period 404 used to etch can be different from the power during the first microetch period 404 used to etch the second material 202 B can be different from the power during the first microetch period 404 used to etch.

[0039] FIG. 5 is a schematic cross-sectional view of an exemplary plasma etch chamber 510 configured to perform the methods described above, such as method 100. In some embodiments, the plasma etch chamber 510 is configured for a plasma-assisted etching process, such as reactive ion etch (RIE) plasma processing. The plasma etch chamber 510 can also be used in other plasma-assisted processes, such as plasma deposition processes (e.g., plasma chemical vapor deposition (PECVD) processes, plasma physical vapor deposition (PEPVD) processes, plasma atomic layer deposition (PEALD) processes, plasma treatment processes, plasma-based ion implantation processes, or plasma doping (PLAD) processes). In one configuration, as shown in FIG. 5, the plasma etch chamber 510 is configured to form a capacitively coupled plasma (CCP). However, in some embodiments, the plasma can be alternately generated by an inductively coupled source disposed across the processing region of the plasma etch chamber 510. In this configuration, a coil can be disposed on the ceramic lid (vacuum boundary) of the plasma etch chamber 510. It is contemplated that the method 100 described above can be implemented in other types of plasma etch chambers.

[0040] The plasma etch chamber 510 includes a chamber body 513, a substrate support assembly 536, a gas panel 582, a DC power system 583, an RF power system 589, and a system controller 526. The chamber body 513 includes a chamber lid 523, one or more sidewalls 522, and a chamber base 524. The chamber lid 523, one or more sidewalls 522, and the chamber base 524 collectively define a processing space 529. The substrate 503 is loaded into and removed from the processing space 529 through an opening (not shown) in one of the sidewalls 522. The substrate 503 is the same as the substrate 200 described above. The opening is sealed by a slit valve (not shown) during plasma processing of the substrate 503.

[0041] The gas panel 582 coupled to the processing space 529 of the plasma etch chamber 510 includes a process gas panel 519 and a gas inlet 528 disposed through the chamber lid 523. The gas inlet 528 is configured to supply one or more process gases from the plurality of process gas panels 519 to the processing space 529. Exemplary process gases were described above.

[0042] The plasma etch chamber 510 further includes an upper electrode (e.g., the chamber lid 523) and a lower electrode (e.g., the substrate support assembly 536) disposed in the processing space 529. The upper electrode and the lower electrode are arranged to face each other. As seen in FIG. 5, in one embodiment, a radio frequency (RF) source is electrically coupled to the lower electrode. The RF source is configured to supply an RF signal to ignite and sustain a plasma (e.g., plasma 501) between the upper electrode and the lower electrode. In some alternative configurations, the RF source may also be electrically coupled to the upper electrode. For example, the RF source may be electrically coupled to the chamber lid. In another example, the RF source may also be electrically coupled to the support base 507.

[0043] The substrate support assembly 536 includes a substrate support 505, a substrate support base 507, an insulator plate 511, a ground plate 512, a plurality of lift pins 586, and a bias electrode 504. Each of the lift pins 586 is disposed through a through hole 585 formed in the substrate support assembly 536 and is used to facilitate the transfer of the substrate 503 to and from the substrate support surface 505A of the substrate support 505. The substrate support 505 is formed of a dielectric material. The dielectric material may include a bulk sintered ceramic material, a corrosion-resistant metal oxide (e.g., aluminum oxide (Al2O3), titanium oxide (TiO), yttrium oxide (Y2O3)), a metal nitride material (e.g., aluminum nitride (AlN), titanium nitride (TiN)), a mixture thereof, or a combination thereof.

[0044] The substrate support base 507 is formed of a conductive material. The substrate support base 507 is electrically insulated from the chamber base 524 by the insulator plate 511 and a ground plate 512 inserted between the insulator plate 511 and the chamber base 524. In some embodiments, the substrate support base 507 is configured to regulate the temperature of both the substrate support 505 and the substrate 503 disposed on the substrate support 505 during substrate processing. In some embodiments, the substrate support base 507 is fluidly coupled to a coolant source (not shown), such as a coolant source or a substrate source having a relatively high electrical resistance, and includes one or more cooling channels (not shown) disposed in the substrate support base 507 that are in fluid communication with the coolant source. In other embodiments, the substrate support 505 includes a heater (not shown) for heating the substrate support 505 and the substrate 503 disposed on the substrate support 505.

[0045] The bias electrode 504 is either embedded in the dielectric material or coupled to the substrate support 505. Generally, the bias electrode 504 is formed of one or more conductive components. The conductive components generally include a mesh, a foil, a plate, or a combination thereof. The bias electrode 504 can function as a chucking pole (i.e., an electrostatic chucking electrode) used to fix the substrate 503 to the substrate support surface 505A of the substrate support 505 (e.g., electrostatically chucking). Generally, the bias electrode 504 and a layer of dielectric material disposed between the bias electrode 504 and the substrate support surface 505A form a structure like a parallel plate. The layer of dielectric material can be aluminum nitride (AlN), aluminum oxide (Al2O3), or other suitable materials.

[0046] The bias electrode 504 is electrically coupled to a clamping network, whereby a chucking voltage is applied to the clamping network. The clamping network includes a DC voltage source 573 (e.g., a high voltage DC source) coupled to a filter 578A of a filter 578 disposed between the DC voltage source 573 and the bias electrode 504. In one example, the filter 578A is a low-pass filter configured to prevent RF frequency signals and pulse voltage (PV) waveform signals (e.g., waveform 320) applied by other bias components within the plasma etch chamber 510 from reaching the DC voltage supply source 573 during plasma processing. In one configuration, the static DC voltage is between about -5000V and about 5000V and is supplied using an electrical conductor (such as a coaxial power supply line 560). In some embodiments, the bias electrode 504 can also bias the substrate 503 with respect to the plasma 501 using one or more of the pulse voltage biasing methods described in more detail below.

[0047] In some configurations, the substrate support assembly 536 further includes an edge control electrode 515. The edge control electrode 515 is disposed under the edge ring 514, surrounds the bias electrode 504, and / or is disposed at a distance from the center of the bias electrode 504. Generally, in the case of a plasma etch chamber 510 configured to process a circular substrate, the edge control electrode 515 is annular in shape, manufactured from a conductive material, and configured to surround at least a portion of the bias electrode 504. As seen in FIG. 5, one or both of the bias electrode 504 and the edge control electrode 515 are disposed within the region of the substrate support 505 and are biased with a waveform 320 by use of a pulse voltage (PV) waveform generator 575. In one configuration, the edge control electrode 515 is biased by use of a PV waveform generator different from the PV waveform generator 575 used for the bias electrode 504. In another configuration, the edge control electrode 515 is biased by splitting a portion of the signal supplied from the PV waveform generator 575 to the bias electrode 504.

[0048] The DC power system 583 includes a DC voltage source 573, a pulse voltage (PV) waveform generator 575, and a current source 577. The RF power system 589 includes a radio frequency (RF) waveform generator 571, a matcher 572, and a filter 574. As described above, the DC voltage source 573 provides a constant chucking voltage while the RF waveform generator 571 supplies an RF signal to the processing region and the PV waveform generator 575 establishes a PV waveform (such as waveform 320) at the bias electrode 504. By applying a sufficient amount of RF power to the electrodes, such as the substrate support base 507, a plasma 501 is formed in the processing space 529 of the plasma etch chamber 510.

[0049] In some embodiments, the power system 583 further includes a filter assembly 578 for electrically insulating one or more of the components included within the power system 583. As shown in FIG. 5, the power supply line 563 electrically connects the output of the RF waveform generator 571 to the impedance matching circuit 572, the RF filter 574, and the substrate support base 507. The power supply line 560 electrically connects the output of the voltage supply source 573 to the filter assembly 578. The power supply line 561 electrically connects the output of the PV waveform generator 575 to the filter assembly 578. The power supply line 562 connects the output of the current source 577 to the filter assembly 578. In some embodiments, the current source 577 is selectively coupled to the bias electrode 504 by use of a switch (not shown) disposed in the supply line 562, such that the current source 577 can supply a desired current to the bias electrode 504 during one or more stages of the voltage waveform (e.g., the ion current stage) generated by the PV waveform generator 575. As seen in FIG. 5, the filter assembly 578 can include a plurality of separate filter processing components (i.e., individual filters 578A through 578C) each electrically coupled to an output node via a respective power supply line 564.

[0050] A system controller 526, also referred to herein as a process chamber controller, includes a central processing unit (CPU) 533, a memory 534, and support circuitry 535. The system controller 526 is used to control a process sequence (e.g., method 100) used to etch a substrate 503. The CPU is a general-purpose computer processor configured for use in an industrial environment for controlling a processing chamber and associated sub-processors. The memory 534, generally non-volatile memory, may include random access memory, read-only memory, hard disk drives, or other suitable forms of digital storage, local or remote, and may be used to store computer-readable instructions to enable method 100 to be executed by a plasma etch chamber 510. The support circuitry 535 is conventionally coupled to the CPU 533 and includes a cache, clock circuits, input / output subsystems, power supplies, etc., and combinations thereof. Software instructions (programs) and data may be coded and stored in the memory 534 to instruct the processor within the CPU 533. A software program (or computer instructions) readable by the CPU 533 in the system controller 526 determines which tasks, such as executing method 100 to etch the substrate 200 in the manner described above, are executable by components in the plasma etch chamber 510.

[0051] Generally, a program readable by the CPU 533 in the system controller 526 includes code that, when executed by the CPU 533, performs tasks related to the plasma processing method 100 described herein. The program may include instructions used to control various hardware and electrical components within the plasma etch chamber 510 to perform various process tasks and various process sequences used to implement the methods described herein. Thus, during operation, the plasma etch chamber 510 performs the method 100 on each substrate 200 in a manner that produces excellent verticality of the sidewalls 222 of the feature 224 to be etched.

[0052] In one example of the etch method 100 executed in the exemplary plasma etch chamber 510, the substrate 200 is disposed on the substrate support surface of the substrate support 505 relative to the plasma disposed within the etch chamber 510. The substrate includes a target layer to be etched. In one example, the target layer is a dielectric material such as an oxide or a nitride. A voltage waveform to an electrode (e.g., the bias electrode 504) disposed within the substrate support 505 while the substrate is exposed to the plasma during a plurality of macro etch cycles. The plasma is formed from a process gas suitable for etching the target layer as described above. For example, when etching a dielectric target material such as an oxide material or a nitride material, the process gas is one or both of CxFz and CxHyFz, where x, y, and z are integers.

[0053] In the presence of plasma in a chamber above a substrate, a target material is etched using a waveform having a plurality of macro-etch cycles, each macro-etch period including a plurality of micro-etch cycles. Each micro-etch cycle has a bias power on period and a bias power off period, and the duration of the bias power on period is less than the duration of the bias power off period. The macro-etch cycles are repeated until an end point is reached. When the end point is reached, the plasma is extinguished, the flow of process gas into the chamber is stopped, and the etched substrate is removed from the plasma etching chamber.

[0054] In this way, a method and apparatus for etching a substrate in a plasma etch chamber are disclosed that reduce the tilting of the vertical sidewalls of the features being etched as compared to conventional techniques. The novel etch method utilizes waveforms that are used to apply bias power to the electrodes of the substrate support utilized to support the substrate during etching in both the macro regime and the micro regime. In the macro regime, a plurality of macro etch cycles are utilized to etch the substrate. The waveform includes a period during which the bias power is essentially stopped during a portion of each macro etch cycle to enable the etch by-products to be exhausted from the plasma etch chamber. By periodically removing the etch by-products from the chamber, the etchant can be more effectively supplied to the features being etched using vertical trajectories. In the micro regime of the waveform, a plurality of micro etch cycles are utilized during a portion of each macro etch cycle. Each micro etch cycle includes a first period during which the bias power is on and a second period during which the bias power is essentially stopped. The duration of the second period is longer than the duration of the first period to provide time for the etch by-products to exit from the features being etched (such as holes, trenches, etc.). By periodically removing the etch by-products from the features being etched, the etchant can be more effectively supplied to the bottom of the features being etched using vertical trajectories. When the number of collisions between the etchant and the etch by-products is reduced, the etchant can more substantially maintain a vertical trajectory all the way to the bottom of the features being etched, thereby reducing sidewall etching and thus advantageously obtaining excellent verticality of the sidewalls of the features being etched. The improvement in verticality is particularly desirable when forming high aspect ratio features by etching.

[0055] The foregoing is directed to embodiments of the present disclosure, but other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof, and the scope of the present disclosure is determined by the following claims.

Claims

1. A method for etching a substrate in a plasma etching chamber, comprising: exposing the substrate disposed on a substrate support surface of a substrate support in a processing chamber to a plasma; applying a voltage waveform to an electrode disposed in the substrate support while the substrate is being exposed to the plasma during a plurality of macro-etch cycles, each macro-etch cycle including a first macro-etch period and a second macro-etch period, the macro-etch period including a plurality of micro-etch cycles, each micro-etch cycle having a bias power on (BPON) period and a bias power off (BP OFF) period, the duration of the BPON period being less than the duration of the BP OFF period, and substantially no bias power being applied to the electrode during the second macro-etch period. A method comprising the above steps.

2. The method according to claim 1, wherein one of the BPON periods of one of the micro-etch cycles is less than 45% of the BP OFF period.

3. The method according to claim 1, wherein one of the BPON periods of one of the micro-etch cycles is between about 10% and about 45% of the BP OFF period.

4. The method according to claim 1, wherein the plurality of macro-etch cycles includes a first macro-etch cycle that occurs before a second macro-etch cycle, and one of the BPON periods of one of the micro-etch cycles of the first macro-etch cycle is longer than one of the BPON periods of one of the micro-etch cycles of the second macro-etch cycle.

5. The method according to claim 1, wherein the frequency of the macro-etch cycles decreases as the substrate is etched.

6. The method according to claim 1, wherein the frequency of the macro-etch cycles is between about 2 Hz and about 100 Hz.

7. The method according to claim 1, wherein the frequency of the micro-etch cycles is between about 25 kHz and about 500 kHz.

8. The method according to claim 7, wherein the frequency of the macro-etch cycles is between about 2 Hz and about 100 Hz.

9. The method according to claim 1, wherein each micro-etch cycle is at least one order of magnitude smaller than the macro-etch cycle.

10. forming the plasma from a processing gas comprising carbon and at least one halogen The method according to claim 1, further comprising.

11. The method according to claim 10, wherein a dielectric material is removed from the substrate during the BPON period.

12. The method according to claim 11, wherein the dielectric material is an oxide material, a nitride material, or a stack of a pair of an oxide layer and a nitride layer.

13. The method according to claim 11, wherein the dielectric material comprises at least one oxide layer and at least one nitride layer.

14. The method according to claim 11, wherein the processing gas is one or both of CxFz and CxHyFz, and x, y, and z are integers.

15. A method for etching a substrate in a plasma etching chamber, comprising: forming a plasma from a processing gas containing carbon and at least one halogen; exposing a dielectric layer disposed on the substrate in the plasma etching chamber to the plasma; applying a bias power to an electrode disposed in a substrate support for supporting the substrate in the plasma etching chamber while the substrate is being exposed to the plasma during a plurality of macroetch cycles until an end point is reached, each macroetch cycle including a first macroetch period and a second macroetch period, the macroetch period including a plurality of microetch cycles, each microetch cycle having a bias power on (BPON) period and a bias power off (BP OFF) period, the duration of the BPON period being less than the duration of the BP OFF period, and during the second macroetch period, little bias power is applied to the electrode, and at least in one macroetch cycle, the BPON period is at least two digits shorter in duration than the first macroetch period; the BP OFF period is at least two digits shorter in duration than the second macroetch period; applying a bias power; and a method comprising.

16. The method according to claim 15, wherein one of the BPON periods of the microetch cycles is less than 45% of the BP OFF period.

17. The method according to claim 15, wherein one of the BPON periods of the microetch cycles is between about 10% and about 45% of the BP OFF period.

18. The method according to claim 15, wherein the plurality of macro-etch cycles includes a first macro-etch cycle that occurs before a second macro-etch cycle, and a BON period of one of the micro-etch cycles of the first macro-etch cycle is longer than a BON period of one of the micro-etch cycles of the second macro-etch cycle.

19. The method according to claim 15, wherein the frequency of the macro-etch cycles of the plurality of macro-etch cycles decreases as the substrate is etched.

20. A chamber body having an internal space; A substrate support disposed in the internal space of the chamber body, the substrate support being configured to hold a substrate thereon during processing, the substrate support having an electrode; A bias power control system coupled to the electrode; A gas panel configured to supply a processing gas to the internal space; A controller, Maintaining a plasma formed from the processing gas in the processing chamber; Applying a voltage waveform to the electrode while the substrate disposed on the substrate support is exposed to the plasma during a plurality of macro-etch cycles, each macro-etch cycle including a first macro-etch period and a second macro-etch period, the macro-etch period including a plurality of micro-etch cycles, each micro-etch cycle having a bias power on (BON) period and a bias power off (BOFF) period, a duration of the BON period being smaller than a duration of the BOFF period, and applying a voltage waveform in which bias power is hardly applied to the electrode during the second macro-etch period; A controller configured to perform; A plasma etching chamber comprising.

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