Semiconductor structure, dicing method thereof, and memory

Abstract

According to a first aspect of the present disclosure, a semiconductor structure is provided. The semiconductor structure can include a first wafer. The first wafer can include a plurality of first peripheral circuit chips, a first dicing lane between the first peripheral circuit chips, and a first mark at an edge of the first wafer. The direction indicated by the first mark can be the same as the extending direction of the first dicing lane. The cleavage plane of the first wafer can be parallel to the direction indicated by the first mark. The direction indicated by the first mark can be the extending direction of the symmetry line of the first wafer. The semiconductor structure can include a second wafer. The second wafer and the first wafer can be stacked and disposed. The second wafer can be a plurality of memory array chips.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, semiconductor structures, dicing methods thereof, and memories.

Background Art

[0002] In a semiconductor manufacturing process, a plurality of chips can be formed on a semiconductor substrate through a semiconductor process. The semiconductor structure can then be diced into individual separated chips through a dicing process. These chips can be packaged. In this way, usable semiconductor devices can be obtained.

Summary of the Invention

Means for Solving the Problems

[0003] According to a first aspect of the present disclosure, a semiconductor structure is provided. The semiconductor structure can include a first wafer. The first wafer can include a plurality of first peripheral circuit chips, a first dicing lane between the first peripheral circuit chips, and a first mark at an edge of the first wafer. The direction indicated by the first mark can be the same as the extending direction of the first dicing lane. The cleavage plane of the first wafer can be parallel to the direction indicated by the first mark. The direction indicated by the first mark can be the extending direction of the symmetry line of the first wafer. The semiconductor structure can include a second wafer. The second wafer and the first wafer can be stacked and arranged. The second wafer can be a plurality of memory array chips.

[0004] In some implementation forms, the semiconductor structure can be the third wafer. In some implementation forms, the third wafer can include a plurality of second peripheral circuit chips. In some implementation forms, a second dicing lane is between the second peripheral circuit chips, a second mark is at the edge of the third wafer, and the extending direction of the second dicing lane can be the same as the extending direction of the first dicing lane.

[0005] In some implementation forms, the included angle between the direction indicated by the second mark and the extending direction of the second dicing lane is a, where 0° < a < 90°. In some implementation forms, the characteristic size of the devices in the second peripheral circuit chips can be smaller than the characteristic size of the devices in the first peripheral circuit chips. In some implementation forms, the direction indicated by the second mark can be the extending direction of the symmetry line of the third wafer.

[0006] In some implementation forms, the direction indicated by the second mark can be the same as the extending direction of the second dicing lane. In some implementation forms, the cleavage plane of the third wafer can be parallel to the direction indicated by the second mark. In some implementation forms, the characteristic size of the devices in the first peripheral circuit chips can be the same as the characteristic size of the devices in the second peripheral circuit chips. In some implementation forms, the direction indicated by the second mark can be the extending direction of the symmetry line of the third wafer.

[0007] In some implementation forms, the third wafer can be positioned between the first wafer and the second wafer.

[0008] In some implementation forms, the second wafer can be positioned between the first wafer and the third wafer.

[0009] In some implementations, the memory array chip can be a 3D NAND memory array chip.

[0010] According to a second aspect of the present disclosure, a method of dicing a semiconductor structure is provided. The method can include providing a semiconductor structure to be diced. The semiconductor structure to be diced can include a first wafer and a second wafer. The first wafer can include a plurality of first peripheral circuit chips, a first dicing lane between the first peripheral circuit chips, and a first mark at an edge of the first wafer. The direction indicated by the first mark can be the same as the extending direction of the first dicing lane. The cleavage plane of the first wafer can be parallel to the direction indicated by the first mark. The second wafer and the first wafer can be stacked and arranged. The second wafer can include a plurality of memory array chips. The direction indicated by the first mark can be the extending direction of the symmetry line of the first wafer. The method can include dicing the first dicing lane of the first wafer from a surface of the first wafer away from the second wafer. The method can include a step of stretching the semiconductor structure to be diced such that the cleavage plane of the first wafer extends to the second wafer.

[0011] In some implementations, the step of dicing the first dicing lane of the first wafer from a surface of the first wafer away from the second wafer can include dicing the first dicing lane of the first wafer from a surface of the first wafer away from the second wafer by using a laser dicing process.

[0012] In some implementation forms, the semiconductor structure can include a third wafer. In some implementation forms, the third wafer can include a plurality of second peripheral circuit chips, a second dicing lane between the second peripheral circuit chips, and a second mark at the edge of the third wafer. In some implementation forms, the extending direction of the second dicing lane can be the same as the extending direction of the first dicing lane.

[0013] In some implementation forms, the included angle between the direction indicated by the second mark and the extending direction of the second dicing lane can be a, where 0° < a < 90°. In some implementation forms, the characteristic size of the devices in the second peripheral circuit chips can be smaller than the characteristic size of the devices in the first peripheral circuit chips. In some implementation forms, the direction indicated by the second mark can be the extending direction of the symmetry line of the third wafer. In some implementation forms, the step of stretching the semiconductor structure to be diced such that the cleavage plane of the first wafer extends to the second wafer can include the step of stretching the semiconductor structure to be diced such that the cleavage plane of the first wafer extends to the second wafer and the third wafer.

[0014] In some implementation forms, the direction indicated by the second mark can be the same as the extending direction of the second dicing lane, the cleavage plane of the third wafer can be parallel to the direction indicated by the second mark, and the characteristic size of the devices in the first peripheral circuit chip can be the same as the characteristic size of the devices in the second peripheral circuit chip. In some implementation forms, the direction indicated by the second mark can be the extending direction of the symmetry line of the third wafer. In some implementation forms, the second wafer can be positioned between the first wafer and the third wafer. In some implementation forms, the method can further include the step of dicing the second dicing lane from the surface of the third wafer away from the second wafer while dicing the first dicing lane from the surface of the first wafer away from the second wafer. In some implementation forms, the step of stretching the semiconductor structure to be diced such that the cleavage plane of the first wafer extends to the second wafer can further include the step of stretching the semiconductor structure to be diced such that the cleavage plane of the first wafer and the cleavage plane of the third wafer extend to the second wafer.

[0015] In some implementation forms, the direction indicated by the second mark can be the same as the extending direction of the second dicing lane, the cleavage plane of the third wafer can be parallel to the direction indicated by the second mark, and the characteristic size of the devices in the first peripheral circuit chip can be the same as the characteristic size of the devices in the second peripheral circuit chip. In some implementation forms, the direction indicated by the second mark can be the extending direction of the symmetry line of the third wafer. In some implementation forms, the third wafer can be positioned between the first wafer and the second wafer. In some implementation forms, the step of dicing the first dicing lane from the surface of the first wafer away from the second wafer can include the step of dicing the first dicing lane and the second dicing lane from the surface of the first wafer away from the second wafer. In some implementation forms, the step of stretching the semiconductor structure to be diced such that the cleavage plane of the first wafer extends to the second wafer can include the step of stretching the semiconductor structure to be diced such that the cleavage plane of the first wafer and the cleavage plane of the third wafer extend to the second wafer.

[0016] In some implementation forms, the step of stretching the semiconductor structure to be diced can include the step of stretching the semiconductor structure to be diced along a direction perpendicular to the cleavage plane of the first wafer.

[0017] In some embodiments, the step of providing a semiconductor structure to be diced can include the step of providing a first wafer including a plurality of first peripheral circuit chips. In some embodiments, the step of providing a semiconductor structure to be diced can include the step of providing a second wafer including a plurality of memory array chips. In some embodiments, the step of providing a semiconductor structure to be diced can include the step of bonding the first wafer to the second wafer to form a semiconductor structure to be diced.

[0018] According to a third aspect of the present disclosure, a method for forming a memory is provided. The method can include the step of providing a semiconductor structure to be diced. The semiconductor structure to be diced can include a first wafer and a second wafer. The first wafer can include a plurality of first peripheral circuit chips, a first dicing lane between the first peripheral circuit chips, and a first mark at an edge of the first wafer. The direction indicated by the first mark can be the same as the extending direction of the first dicing lane. The cleavage plane of the first wafer can be parallel to the direction indicated by the first mark. The second wafer and the first wafer can be stacked and arranged. The second wafer can include a plurality of memory array chips. The direction indicated by the first mark can be the extending direction of the symmetry line of the first wafer. The method can include the step of dicing the first dicing lane from a surface of the first wafer away from the second wafer. The method can include the step of stretching the semiconductor structure to be diced such that the cleavage plane of the first wafer extends to the second wafer.

[0019] In some embodiments, the step of dicing the first dicing lane of the first wafer from the surface of the first wafer remote from the second wafer may include the step of dicing the first dicing lane of the first wafer from the surface of the first wafer remote from the second wafer by using a laser dicing process.

[0020] In some embodiments, the semiconductor structure may include a third wafer. In some embodiments, the third wafer may include a plurality of second peripheral circuit chips, a second dicing lane between the second peripheral circuit chips, and a second mark at an edge of the third wafer. In some embodiments, the extending direction of the second dicing lane may be the same as the extending direction of the first dicing lane.

[0021] In some embodiments, the included angle between the direction indicated by the second mark and the extending direction of the second dicing lane may be a, where 0° < a < 90°. In some embodiments, the characteristic size of the devices in the second peripheral circuit chips may be smaller than the characteristic size of the devices in the first peripheral circuit chips. In some embodiments, the direction indicated by the second mark may be the extending direction of the symmetry line of the third wafer. In some embodiments, the step of stretching the semiconductor structure to be diced such that the cleavage plane of the first wafer extends to the second wafer may include the step of stretching the semiconductor structure to be diced such that the cleavage plane of the first wafer extends to the second wafer and the third wafer.

[0022] In some implementation forms, the direction indicated by the second mark can be the same as the extending direction of the second dicing lane, the cleavage plane of the third wafer can be parallel to the direction indicated by the second mark, and the characteristic size of the devices in the first peripheral circuit chip can be the same as the characteristic size of the devices in the second peripheral circuit chip. In some implementation forms, the direction indicated by the second mark can be the extending direction of the symmetry line of the third wafer. In some implementation forms, the second wafer can be positioned between the first wafer and the third wafer. In some implementation forms, the method can further include the step of dicing the second dicing lane from the surface of the third wafer away from the second wafer while dicing the first dicing lane from the surface of the first wafer away from the second wafer. In some implementation forms, the step of stretching the semiconductor structure to be diced such that the cleavage plane of the first wafer extends to the second wafer can further include the step of stretching the semiconductor structure to be diced such that the cleavage plane of the first wafer and the cleavage plane of the third wafer extend to the second wafer.

[0023] In some embodiments, the direction indicated by the second mark can be the same as the extending direction of the second dicing lane, the cleavage plane of the third wafer can be parallel to the direction indicated by the second mark, and the characteristic size of the devices in the first peripheral circuit chip can be the same as the characteristic size of the devices in the second peripheral circuit chip. In some embodiments, the direction indicated by the second mark can be the extending direction of the symmetry line of the third wafer. In some embodiments, the third wafer can be positioned between the first wafer and the second wafer. In some embodiments, the step of dicing the first dicing lane from the surface of the first wafer away from the second wafer can include the step of dicing the first dicing lane and the second dicing lane from the surface of the first wafer away from the second wafer. In some embodiments, the step of stretching the semiconductor structure to be diced such that the cleavage plane of the first wafer extends to the second wafer can include the step of stretching the semiconductor structure to be diced such that the cleavage plane of the first wafer and the cleavage plane of the third wafer extend to the second wafer.

Brief Description of the Drawings

[0024]

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Embodiments for Carrying Out the Invention

[0025] The implementation forms disclosed by the present disclosure will be described in more detail below with reference to the drawings. Although the implementation forms of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be realized in various forms and should not be limited by the specific implementation forms as described in this specification. Rather, these implementation forms are provided to more thoroughly understand the present disclosure and can completely convey the scope disclosed by the present disclosure to those skilled in the art.

[0026] In the following description, various details are presented to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, some technical features well known in the art are not described in order to avoid confusion with the present disclosure. That is, not all features of the actual examples are described in this specification, and well-known functions and structures are not described in detail.

[0027] In the drawings, for purposes of clarity, the size and relative sizes of layers, areas, and elements may be exaggerated. The same reference numerals in different drawings may indicate similar elements throughout.

[0028] When an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be one or more intervening elements or layers. In contrast, when an element is referred to as being "directly on," "immediately adjacent to," "directly connected to," or "directly coupled to" another element, there are no intervening elements or layers. Terms such as first, second, third, etc. may be used to describe various elements, components, areas, layers, and / or portions, but it should be understood that these elements, components, areas, layers, and / or portions are not to be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another. Thus, a first element, component, area, layer, or portion discussed below could be represented as a second element, component, area, layer, or portion without departing from the teachings of the present disclosure. When a second element, component, area, layer, or portion is discussed, it does not mean that a first element, component, area, layer, or portion must necessarily be present in the present disclosure.

[0029] For example, spatially relative terms such as "beneath", "below", "lower", "under", "over", and "upper" may be used herein to facilitate description of the relationship between one element or feature and another element or feature as illustrated in the figures. It should be understood that spatially relative terms are intended to further encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the drawings is turned over, an element or feature described as "below", or "under", or "beneath" another element or feature will be oriented "above" the other element or feature. Thus, the terms "below" and "beneath" can include orientations of both above and below. The device may be otherwise oriented (rotated 90 degrees or otherwise), and the spatial descriptive terms used herein are to be interpreted accordingly.

[0030] The terms used herein are intended only to describe particular examples and are not to be used as a limitation of the present disclosure. As used herein, unless the context clearly dictates otherwise, the singular forms "a", "an", and "the" are also intended to include the plural. The terms "consist of" and / or "comprise" as used herein, when determining the presence of a feature, integer, step, operation, element, and / or component, are not to be construed as excluding the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the listed associated items.

[0031] To facilitate a more detailed understanding of the features and technical content of the examples of the present disclosure, the implementation forms of the examples of the present disclosure are described in detail below in relation to the drawings, and the accompanying drawings are not used to limit the examples of the present disclosure, but are only used for reference and illustration.

[0032] With the rapid development of the electronics industry, the need for high-performance and low-cost semiconductor devices is increasing. The integration level of conventional two-dimensional memory or planar memory is mainly determined by the area occupied by the unit memory cell. Therefore, the integration level of conventional two-dimensional memory is greatly affected by the micro-patterning technology. However, in order to improve the fineness of the pattern, expensive process equipment is required, which limits the increase in the integration level of two-dimensional memory. Three-dimensional memory devices are a newly emerging type of flash memory developed by the industry. Three-dimensional memory devices solve the problem of limitations posed by two-dimensional or planar flash memory by stacking multiple layers of data storage cells vertically. Three-dimensional memory devices have excellent accuracy, support a larger storage capacity housed in a smaller space, have low cost and power consumption, and can sufficiently meet a number of use cases.

[0033] As the requirements for the performance of three-dimensional memory increase, the peripheral circuits and memory arrays of three-dimensional memory can be bonded after being formed on different wafers. When the semiconductor structure after bonding is diced, the wafer formed with peripheral circuits is generally selected as the wafer to be diced. As shown in FIG. 1, in some examples, a plurality of peripheral circuit chips 1015 are formed in the wafer to be diced. A first dicing lane 1003 extending along the Y-axis direction is disposed between the plurality of peripheral circuit chips 1015. A mark 1016 is disposed at the edge of the wafer. There is a specific included angle between the direction indicated by the mark 1016 and the extending direction of the first dicing lane 1003. The direction indicated by the mark 1016 is the extending direction of the symmetry line m of the wafer. The cleavage of the wafer occurs in the direction of the internal structure of the wafer with weak connection strength. Under an external force, fracture can easily occur along the direction of the cleavage plane, and a smooth plane can be formed by the fracture. The cleavage plane of the wafer is parallel to the direction indicated by the mark 1016 (for example, the extending direction of the symmetry line m). When there is a specific included angle between the extending direction of the symmetry line m and the extending direction of the first dicing lane 1003, there is a specific included angle between the cleavage plane of the wafer and the extending direction of the first dicing lane 1003. Therefore, the cleavage plane of the wafer (for example, at the position where the symmetry line m is located) passes through the inside of the peripheral circuit chip 1015, and the wafer is likely to cleave along the cleavage plane (for example, the inside of the peripheral circuit chip) in the stretching process during dicing, thereby affecting the chip yield and adversely affecting the chip throughput.

[0034] To overcome these and other problems, examples of the present disclosure provide an exemplary semiconductor structure. FIG. 2 is a schematic diagram of a semiconductor structure provided by an example of the present disclosure. FIG. 3 is a top schematic view of a first wafer 1001 provided by an example of the present disclosure. FIG. 5 is a top schematic view of a second wafer 1005 provided by an example of the present disclosure. As shown in FIGS. 2, 3, and 5, the semiconductor structure can include, for example, a first wafer 1001. The first wafer 1001 can include a plurality of first peripheral circuit chips 1002, a first dicing lane 1003 between the first peripheral circuit chips 1002, and a first mark 1004 at an edge of the first wafer 1001. The direction indicated by the first mark 1004 can be the same as the extending direction of the first dicing lane 1003. The cleavage plane of the first wafer 1001 can be parallel to the direction indicated by the first mark 1004. The direction indicated by the first mark 1004 can be the extending direction of the symmetry line of the first wafer 1001. The semiconductor structure shown in FIGS. 2, 3, and 5 can include a second wafer 1005. The second wafer 1005 and the first wafer 1001 can be stacked and arranged, and the second wafer 1005 can include a plurality of memory array chips 1007.

[0035] Here, the marks on the wafer generally include two types (notch marks and flat marks). FIG. 3 shows a schematic diagram marked by a notch mark, and FIG. 4 shows a schematic diagram marked by a flat mark. As shown in FIGS. 3 and 4, the extending direction of the first dicing lane 1003 can be, for example, the Y-axis direction as shown in FIGS. 3 and 4. The direction indicated by the first mark 1004 can be the extending direction of the symmetry line m of the first wafer 1001. The extending direction of the symmetry line m of the first wafer 1001 and the extending direction of the first dicing lane 1003 can be the same, both being the Y-axis direction. On the one hand, the cleavage plane of the first wafer 1001 can be parallel to the direction indicated by the first mark 1004. Therefore, the cleavage plane of the first wafer 1001 can be parallel to the extending direction of the first dicing lane 1003.

[0036] In an example of the present disclosure, the cleavage plane of the first wafer 1001 can be parallel to the extending direction of the first dicing lane 1003 of the first wafer 1001, and during subsequent dicing of the dicing lane of the semiconductor structure, dicing can be performed from the surface of the first wafer 1001 of the semiconductor structure. It can be understood that the first wafer 1001 may be more easily cleaved along the first dicing lane. This reduces or eliminates the problem that the chip yield is affected because the first peripheral circuit chip 1002 cleaves along the inside of the chip and the cleavage plane of the wafer passes through the first peripheral circuit chip 1002.

[0037] In some examples, the first wafer 1001, the second wafer 1005, and the third wafer in the following description can be, for example, wafers that have completed the process of a wafer stage (for example, a stage for forming a device structure and an interconnection structure of the device structure).

[0038] Here, the first wafer 1001 can include a plurality of first peripheral circuit chips 1002. Each of the first peripheral circuit chips 1002 can include a semiconductor substrate and a peripheral device structure on the semiconductor substrate. The peripheral device structure can include MOS devices or other semiconductor devices. The semiconductor substrate can include silicon (e.g., single crystal silicon (c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable material).

[0039] In some examples, the diameters of the first wafer 1001, the second wafer 1005, and the third wafer in the following description can be, for example, 150 mm, 200 mm, 300 mm, and 450 mm, etc., but the present disclosure is not limited thereto.

[0040] In some examples, the memory array chip 1007 can include a 3D NAND memory array chip, but the present disclosure is not limited thereto.

[0041] In some examples, the memory array chip 1007 can also include a 3D NOR memory array chip, a dynamic random access memory array chip, a ferroelectric memory array chip, a phase change memory array chip, etc., but the present disclosure is not limited thereto.

[0042] In some examples, the first wafer 1001 can be bonded to the second wafer 1005 through a bonding process, such that the first peripheral circuit chips 1002 in the first wafer 1001 are electrically connected to the memory array chips 1007 in the second wafer 1005.

[0043] In some examples, as shown in FIG. 5, it is possible for a third dicing lane 1006 to exist between a plurality of memory array chips 1007 of the second wafer 1005. Here, the extending direction of the third dicing lane 1006 and the extending direction of the first dicing lane 1003 can be the same, and both are in the Y-axis direction. In other words, the memory array chips 1007 and the first peripheral circuit chips 1002 can be separated along the same direction after dicing the semiconductor structure. The second wafer 1005 can further include a third mark 1008 at the edge of the second wafer 1005. The direction indicated by the third mark 1008 can be the same as the extending direction of the third dicing lane 1006, and there can be a specific included angle between the direction indicated by the third mark 1008 and the extending direction of the third dicing lane 1006.

[0044] In some examples, as shown in FIGS. 2 and 6, the semiconductor structure can further include a third wafer 1009. The third wafer 1009 can include a plurality of second peripheral circuit chips 1010, a second dicing lane 1011 between the second peripheral circuit chips 1010, and a second mark 1012 at the edge of the third wafer 1009. Here, the extending direction of the second dicing lane 1011 and the extending direction of the first dicing lane 1003 are the same, and both are in the Y-axis direction.

[0045] In some examples, as shown in FIG. 6, the included angle between the direction indicated by the second mark 1012 and the extending direction of the second dicing lane 1011 can be a, where a is in the range of 0° < a < 90°. The characteristic size of the devices in the second peripheral circuit chips 1010 can be smaller than the characteristic size of the devices in the first peripheral circuit chips 1002. The direction indicated by the second mark 1012 can be the extending direction of the symmetry line of the third wafer 1009.

[0046] Here, the characteristic size can refer to the minimum size of semiconductor devices in the field of integrated circuits. In a complementary metal-oxide-semiconductor process, a typical representative of the characteristic size is the width of the "gate" (for example, the channel length of a MOS device). Generally, when the characteristic size is smaller, it is possible for the integration level of the chip to be higher, the performance to be better, and the power consumption to be lower.

[0047] The included angle between the direction indicated by the second mark 1012 and the extending direction of the second dicing lane 1011 is a. Here, it can be understood that when a is in the range of 0° < a < 90°, the hole mobility of the devices formed on the third wafer 1009 can be higher. This may be more suitable for forming peripheral circuit devices with smaller characteristic sizes and higher performance.

[0048] In an example of the present disclosure, a semiconductor structure formed in a hybrid wafer stack for dicing is formed, and the peripheral circuit is formed in two wafers. A part of the device having a larger characteristic size can be formed in the first wafer 1001, and the first wafer 1001 can act as the wafer to be diced simultaneously. Another part of the device having a smaller characteristic size can be formed in the third wafer 1009. Therefore, the requirements for dicing can be met, the chip yield can be increased, high-performance peripheral circuit devices can be formed, thereby improving the performance of the chip.

[0049] In some examples, as shown in FIG. 7, the direction indicated by the second mark 1012 can be the same as the extending direction of the second dicing lane 1011, the cleavage plane of the third wafer 1009 can be parallel to the direction indicated by the second mark 1012, and the characteristic size of the devices in the first peripheral circuit chip 1002 can be the same as the characteristic size of the devices in the second peripheral circuit chip 1010. The direction indicated by the second mark 1012 can be the extending direction of the symmetry line of the third wafer 1009.

[0050] It can be understood that when the direction indicated by the second mark 1012 is the same as the extending direction of the second dicing lane 1011 and the cleavage plane of the third wafer 1009 is parallel to the direction indicated by the second mark 1012, the characteristic size in the formed second peripheral circuit chip 1010 can be the same as the characteristic size in the first peripheral circuit chip 1002. For example, devices having a large characteristic size can be formed in both the second peripheral circuit chip 1010 and the first peripheral circuit chip 1002.

[0051] In the examples of the present disclosure, there are some relative positional relationships among the first wafer 1001, the second wafer 1005, and the third wafer 1009.

[0052] In some examples, as shown in FIG. 8, the third wafer 1009 can be positioned between the first wafer 1001 and the second wafer 1005.

[0053] In some examples, as shown in FIG. 2, the second wafer 1005 can be positioned between the first wafer 1001 and the third wafer 1009.

[0054] When the direction indicated by the second mark 1012 is the same as the extending direction of the second dicing lane 1011, and the cleavage plane of the third wafer 1009 is parallel to the direction indicated by the second mark 1012, the cleavage plane of the third wafer 1009 can be parallel to the extending direction of the second dicing lane 1011 of the third wafer 1009, and it can be understood that the third wafer 1009 is also suitable for dicing. The second wafer 1005 can be positioned between the first wafer 1001 and the third wafer 1009, and the semiconductor structure can be diced simultaneously from the surfaces of the first wafer 1001 and the third wafer 1009. In this way, the process requirements for simultaneous double-sided dicing are satisfied, and it is possible to improve the subsequent dicing efficiency.

[0055] Examples of the present disclosure provide a semiconductor structure including a first wafer 1001 and a second wafer 1005. The first wafer 1001 can include a plurality of first peripheral circuit chips 1002, a first dicing lane 1003 between the first peripheral circuit chips 1002, and a first mark 1004 at the edge of the first wafer 1001. The direction indicated by the first mark 1004 can be the same as the extending direction of the first dicing lane 1003, the cleavage plane of the first wafer 1001 can be parallel to the direction indicated by the first mark 1004, and the direction indicated by the first mark 1004 can be the extending direction of the symmetry line of the first wafer 1001. The second wafer 1005 and the first wafer 1001 can be stacked and arranged, and the second wafer 1005 can include a plurality of memory array chips 1007.

[0056] In an example of the present disclosure, the direction indicated by the first mark 1004 can be the same as the extending direction of the first dicing lane 1003, the cleavage plane of the first wafer 1001 can be parallel to the direction indicated by the first mark 1004, and the cleavage plane of the first wafer 1001 is parallel to the extending direction of the first dicing lane 1003 of the first wafer 1001. Therefore, dicing can be performed from the surface of the first wafer 1001 of the semiconductor structure during subsequent dicing of the semiconductor structure, and the first wafer 1001 may be more easily cleaved along the direction of the first dicing lane. Thus, due to the fact that the cleavage plane of the wafer passes through the inside of the first peripheral circuit chip 1002 when there is a specific included angle between the cleavage plane of the wafer and the dicing lane, the problem that the first peripheral circuit chip 1002 cleaves along the inside of the chip is reduced, and the chip yield can be increased.

[0057] Based on the above semiconductor structure, an example of the present disclosure further provides a method for dicing a semiconductor structure. As shown in FIG. 9, the method can include operations S1001, S1002, and S1003.

[0058] For example, referring to FIG. 9, in S1001, the method can include providing a semiconductor structure to be diced. The semiconductor structure to be diced can include a first wafer 1001 and a second wafer 1005. The first wafer 1001 can include a plurality of first peripheral circuit chips, a first dicing lane between the first peripheral circuit chips, and a first mark at an edge of the first wafer 1001. The direction indicated by the first mark can be the same as the extending direction of the first dicing lane, and the cleavage plane of the first wafer 1001 can be parallel to the direction indicated by the first mark. The second wafer 1005 and the first wafer 1001 can be stacked and arranged, and the second wafer 1005 can include a plurality of memory array chips. The direction indicated by the first mark can be the extending direction of the symmetry line of the first wafer 1001.

[0059] In S1002, the method can include dicing the first dicing lane from a surface of the first wafer 1001 that is away from the second wafer 1005.

[0060] In S1003, the method can include stretching the semiconductor structure to be diced such that the cleavage plane of the first wafer 1001 extends to the second wafer 1005.

[0061] The dicing method of the semiconductor structure will be further introduced below in relation to FIGS. 10 to 13.

[0062] For example, in S1001, as shown in FIG. 10, a semiconductor structure to be diced is provided. The semiconductor structure to be diced has been introduced in detail in the above introduction of the semiconductor structure, and thus will not be repeated here. In some examples, providing the semiconductor structure to be diced can include providing a first wafer 1001 including a plurality of first peripheral circuit chips. In some examples, providing the semiconductor structure to be diced can include providing a second wafer 1005 including a plurality of memory array chips. In some examples, providing the semiconductor structure to be diced can include bonding the first wafer 1001 to the second wafer 1005 to form the semiconductor structure to be diced. In some examples, after providing the semiconductor structure to be diced, the method can further include providing a carrier wafer 1013 and disposing the semiconductor structure to be diced on the carrier wafer 1013 with the first wafer 1001 in the semiconductor structure to be diced facing away from the carrier wafer 1013.

[0063] Referring to FIG. 11, in S1002, the first dicing lane is diced. Here, the first dicing lane can be diced from the surface of the first wafer 1001 that is away from the second wafer 1005. As shown in FIG. 11, it can be understood that the first dicing lane of the first wafer 1001 is diced from the surface of the first wafer 1001. In the example of the present disclosure, the direction indicated by the first mark can be the same as the extending direction of the first dicing lane, the cleavage plane of the first wafer 1001 can be parallel to the direction indicated by the first mark, and it can be understood that the cleavage plane of the first wafer 1001 is parallel to the extending direction of the first dicing lane of the first wafer 1001. Therefore, dicing can be performed from the surface of the first wafer 1001 of the semiconductor structure to be diced during subsequent dicing of the semiconductor structure, and the first wafer 1001 is more easily cleaved along the direction of the first dicing lane. Thus, due to the fact that the cleavage plane of the wafer passes through the inside of the first peripheral circuit chip when there is a specific included angle between the cleavage plane of the wafer and the dicing lane, the problem that the first peripheral circuit chip cleaves along the inside of the chip can be reduced, thereby improving the chip yield. In some examples, dicing the first dicing lane of the first wafer 1001 from the surface of the first wafer 1001 that is away from the second wafer 1005 can include dicing the first dicing lane of the first wafer 1001 from the surface of the first wafer 1001 that is away from the second wafer 1005 by using a laser dicing process.

[0064] Referring to FIG. 12, in S1003, the semiconductor structure to be diced is stretched such that the cleavage plane of the first wafer 1001 extends up to the second wafer 1005. In some examples, there is a third dicing lane between a plurality of memory array chips of the second wafer 1005, and the extending direction of the third dicing lane is the same as the extending direction of the first dicing lane. After stretching the semiconductor structure to be diced, the cleavage plane of the first wafer 1001 can extend up to the second wafer 1005. The cleavage plane of the first wafer 1001 can be parallel to the extending direction of the first dicing lane, and the extending direction of the third dicing lane can be the same as the extending direction of the first dicing lane. Therefore, the cleavage plane extending up to the second wafer 1005 is parallel to the extending direction of the third dicing lane, and the second wafer 1005 is cleaved along the direction of the third dicing lane, thereby enabling an increase in the dicing yield of the chips.

[0065] In some examples, the semiconductor structure can further include a third wafer 1009. The third wafer 1009 can include a plurality of second peripheral circuit chips, a second dicing lane between the second peripheral circuit chips, and a second mark at the edge of the third wafer 1009, and the extending direction of the second dicing lane can be the same as the extending direction of the first dicing lane.

[0066] In some examples, the included angle between the direction indicated by the second mark and the extending direction of the second dicing lane can be a, where a is in the range of 0° < a < 90°. The characteristic size of the devices in the second peripheral circuit chip can be smaller than the characteristic size of the devices in the first peripheral circuit chip. The direction indicated by the second mark can be the extending direction of the symmetry line of the third wafer 1009. Stretching the semiconductor structure to be diced such that the cleavage plane of the first wafer 1001 extends to the second wafer 1005 can include stretching the semiconductor structure to be diced such that the cleavage plane of the first wafer 1001 extends to the second wafer 1005 and the third wafer 1009.

[0067] The first wafer 1001 is used as the wafer to be diced. On the other hand, the third wafer 1009 is mainly used to form high-performance peripheral circuit devices, and it can be understood that the yield problem during the dicing of the semiconductor structure can be improved and high-performance peripheral circuit devices can also be formed.

[0068] In some examples, the direction indicated by the second mark can be the same as the extending direction of the second dicing lane. The cleavage plane of the third wafer 1009 can be parallel to the direction indicated by the second mark. The characteristic size of the devices in the first peripheral circuit chip can be the same as the characteristic size of the devices in the second peripheral circuit chip. The direction indicated by the second mark can be the extending direction of the symmetry line of the third wafer 1009. The second wafer 1005 can be positioned between the first wafer 1001 and the third wafer 1009.

[0069] In some examples, the method can further include dicing a second dicing lane from a face of a third wafer 1009 that is remote from a second wafer 1005 while dicing a first dicing lane from a face of a first wafer 1001 that is remote from the second wafer 1005. In some examples, stretching the semiconductor structure to be diced such that the cleavage plane of the first wafer 1001 extends to the second wafer 1005 can include stretching the semiconductor structure to be diced such that the cleavage planes of the first wafer 1001 and the third wafer 1009 both extend to the second wafer 1005.

[0070] It can be understood that the direction indicated by the second mark is the same as the extending direction of the second dicing lane, the cleavage plane of the third wafer 1009 is parallel to the direction indicated by the second mark, and the cleavage plane of the third wafer 1009 is parallel to the extending direction of the second dicing lane of the third wafer 1009. Thus, the third wafer 1009 may also be suitable for dicing. The second wafer 1005 can be positioned between the first wafer 1001 and the third wafer 1009 such that the semiconductor structure can be diced simultaneously from the faces of the first wafer 1001 and the third wafer 1009. Then, the semiconductor structure to be diced can be stretched such that the cleavage planes of both the first wafer 1001 and the third wafer 1009 extend to the second wafer 1005, thereby separating the second wafer 1005 along a third dicing lane. Thus, the process requirements for simultaneous double-sided dicing can be satisfied, the dicing efficiency can be improved, and the yield of the diced chips can also be increased.

[0071] In some examples, the semiconductor structure to be diced can be diced using a wafer dicing device as follows. The wafer dicing device can include a carrier table, a first dicing sub-device, and a second dicing sub-device. The carrier table can be configured to carry the wafer to be diced. The first dicing sub-device can be configured to dice the wafer to be diced from a first surface. The second dicing sub-device can be configured to dice the wafer to be diced from a second surface. The first surface and the second surface can be two opposite surfaces of the carrier table along a first direction which is the thickness direction of the carrier table.

[0072] It can be understood that the wafer dicing device can include a first dicing sub-device and a second dicing sub-device, which are respectively configured to dice the semiconductor structure to be diced from both surfaces in the thickness direction of the carrier table. On the one hand, the front side and the back side dicing of the semiconductor structure to be diced can be realized simultaneously, which can improve the dicing efficiency. On the other hand, since the front side and the back side of the semiconductor structure to be diced can be diced simultaneously, the components of the first dicing sub-device and the second dicing sub-device can be arranged correspondingly. This can improve the problem that it is difficult to align the front side and the back side dicing positions in the process of dicing the front side and the back side of the semiconductor structure to be diced separately, which can further increase the yield of the diced chips.

[0073] In some examples, the semiconductor structure to be diced can be placed on a carrier table. The semiconductor structure to be diced can be diced from a first surface by using a first dicing sub-device, and the semiconductor structure to be diced can be diced from a second surface by using a second dicing sub-device. The first surface and the second surface are two opposite surfaces of the carrier table along a first direction which is the thickness direction of the carrier table.

[0074] In some examples, the direction indicated by the second mark can be the same as the extending direction of the second dicing lane, the cleavage plane of the third wafer 1009 can be parallel to the direction indicated by the second mark, and the characteristic size of the devices in the first peripheral circuit chip can be the same as the characteristic size of the devices in the second peripheral circuit chip. The direction indicated by the second mark can be the extending direction of the symmetry line of the third wafer 1009. The third wafer 1009 can be positioned between the first wafer 1001 and the second wafer 1005.

[0075] In some examples, dicing the first dicing lane from the surface of the first wafer 1001 away from the second wafer 1005 can include dicing the first dicing lane and the second dicing lane from the surface of the first wafer 1001 away from the second wafer 1005. Stretching the semiconductor structure to be diced such that the cleavage plane of the first wafer 1001 extends to the second wafer 1005 can include stretching the semiconductor structure to be diced such that the cleavage planes of the first wafer 1001 and the third wafer 1009 extend to the second wafer 1005.

[0076] The third wafer 1009 is positioned between the first wafer 1001 and the second wafer 1005. It can be understood that the cleavage plane of the first wafer 1001 is parallel to the extending direction of the first dicing lane, and the cleavage plane of the third wafer 1009 is parallel to the extending direction of the second dicing lane. Therefore, both the first wafer 1001 and the third wafer 1009 can be diced from the surface of the first wafer 1001 by using a laser dicing process. Then, the semiconductor structure to be diced is stretched such that the cleavage plane of the first wafer 1001 and the cleavage plane of the third wafer 1009 extend up to the second wafer 1005. In this way, the second wafer 1005 can be separated along the third dicing lane.

[0077] In some examples, stretching the semiconductor structure to be diced can include stretching the semiconductor structure to be diced along a direction perpendicular to the cleavage plane of the first wafer 1001.

[0078] In some examples, stretching can be along the X-axis direction as shown in FIG. 12, but the stretching direction of the semiconductor structure is not limited thereto.

[0079] The position of the wafer cleavage plane is a fragile position. When the semiconductor structure to be diced is stretched along a direction perpendicular to the cleavage plane of the first wafer 1001, it can be understood that the wafer is likely to cleave along the cleavage plane.

[0080] In some examples, as shown in FIG. 13, after the dicing operation is completed for the wafer to be diced, individual memories 1014 can be formed, and the separated memories 1014 can be removed from the carrier wafer 1013 by using a device equipped with a robot arm 1017.

[0081] Based on the above dicing method of the semiconductor structure, examples of the present disclosure further provide a memory, and the memory is obtained by dicing the semiconductor structure by using any one of the dicing methods of the above examples.

[0082] Throughout this specification, reference to "one example" or "an example" means that the particular feature, structure, or characteristic related to that example is included in at least one example of the present disclosure. Thus, references to "in one example" or "in an example" presented throughout this specification do not necessarily refer to the same example. Moreover, these particular features, structures, or characteristics can be incorporated into one or more examples in any suitable manner. In various examples of the present disclosure, the sequence numbers of the above processes do not refer to the execution sequence, and the execution sequence of the process is determined by its functionality and inherent logic and shall not constitute a limitation to the implementation process of the examples of the present disclosure. The above sequence numbers of the examples of the present disclosure are merely for illustration and do not represent the advantages or disadvantages of the examples.

[0083] The methods disclosed in some method examples as provided by the present disclosure can be freely combined to obtain new method examples if there is no contradiction.

[0084] The above description is merely specific implementations of the present disclosure, and the protection scope of the present disclosure is not limited thereto. Any modifications or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed by the present disclosure shall fall within the protection of the present disclosure. Therefore, the protection scope of the present disclosure shall be defined by the protection scope of the claims.

Description of Reference Numerals

[0085] 1001 First wafer 1002 First peripheral circuit chip 1003 First dicing lane 1004 First mark 1005 Second wafer 1006 Third dicing lane 1007 Memory array chip 1008 Third mark 1009 Third wafer 1010 Second peripheral circuit chip 1011 Second dicing lane 1012 Second mark 1013 Carrier wafer 1014 Memory 1015 Peripheral circuit chip 1016 Mark 1017 Robot arm m Symmetry line of the wafer

Claims

1. A first wafer, wherein the first wafer comprises: a plurality of first peripheral circuit chips, a first dicing lane between the first peripheral circuit chips, and a first mark at an edge of the first wafer . The direction indicated by the first mark is the same as the extending direction of the first dicing lane, the cleavage plane of the first wafer is parallel to the direction indicated by the first mark, and the direction indicated by the first mark is the extending direction of the symmetry line of the first wafer. The first wafer is A second wafer, wherein the second wafer and the first wafer are stacked and disposed, and the second wafer comprises a plurality of memory array chips. The second wafer . A semiconductor structure.

2. The semiconductor structure further comprises: a third wafer, wherein the third wafer comprises: a plurality of second peripheral circuit chips, a second dicing lane between the second peripheral circuit chips, and a second mark at an edge of the third wafer . The extending direction of the second dicing lane is the same as the extending direction of the first dicing lane. The semiconductor structure according to claim 1.

3. The included angle between the direction indicated by the second mark and the extending direction of the second dicing lane is a, where 0° < a < 90°. The characteristic size of the devices in the second peripheral circuit chips is smaller than the characteristic size of the devices in the first peripheral circuit chips. The direction indicated by the second mark is the extending direction of the symmetry line of the third wafer. The semiconductor structure according to claim 2.

4. The direction indicated by the second mark is the same as the extending direction of the second dicing lane. The cleavage plane of the third wafer is parallel to the direction indicated by the second mark. The characteristic size of the devices in the first peripheral circuit chips is the same as the characteristic size of the devices in the second peripheral circuit chips. The direction indicated by the second mark is the extending direction of the symmetry line of the third wafer. The semiconductor structure according to claim 2.

5. The third wafer is positioned between the first wafer and the second wafer. The semiconductor structure according to claim 2.

6. The semiconductor structure according to claim 2, wherein the second wafer is positioned between the first wafer and the third wafer.

7. The semiconductor structure according to claim 1, wherein the memory array chip includes a 3D NAND memory array chip.

8. A dicing method for a semiconductor structure, the dicing method comprising: providing a semiconductor structure to be diced, the semiconductor structure to be diced including a first wafer and a second wafer, the first wafer including a plurality of first peripheral circuit chips, a first dicing lane between the first peripheral circuit chips, and a first mark at an edge of the first wafer, a direction indicated by the first mark being the same as an extending direction of the first dicing lane, a cleavage plane of the first wafer being parallel to the direction indicated by the first mark, the second wafer and the first wafer being stacked and disposed, the second wafer including a plurality of memory array chips, the direction indicated by the first mark being an extending direction of a symmetry line of the first wafer; dicing the first dicing lane from a surface of the first wafer away from the second wafer; stretching the semiconductor structure to be diced such that the cleavage plane of the first wafer extends to the second wafer A dicing method including the above steps.

9. The step of dicing the first dicing lane of the first wafer from the surface of the first wafer away from the second wafer includes: dicing the first dicing lane of the first wafer from the surface of the first wafer away from the second wafer by using a laser dicing process The dicing method according to claim 8, including the above step.

10. The semiconductor structure is a third wafer, the third wafer including a plurality of second peripheral circuit chips, a second dicing lane between the second peripheral circuit chips, and a second mark at an edge of the third wafer, an extending direction of the second dicing lane being the same as the extending direction of the first dicing lane. The dicing method according to claim 8 further includes the third wafer.

11. The included angle between the direction indicated by the second mark and the extending direction of the second dicing lane is a, where 0° < a < 90°. The characteristic size of the devices in the second peripheral circuit chip is smaller than the characteristic size of the devices in the first peripheral circuit chip. The direction indicated by the second mark is the extending direction of the symmetry line of the third wafer. The step of stretching the semiconductor structure to be diced such that the cleavage plane of the first wafer extends to the second wafer. The step of stretching the semiconductor structure to be diced such that the cleavage plane of the first wafer extends to the second wafer and the third wafer. comprising The dicing method according to claim 10.

12. The direction indicated by the second mark is the same as the extending direction of the second dicing lane. The cleavage plane of the third wafer is parallel to the direction indicated by the second mark. The characteristic size of the devices in the first peripheral circuit chip is the same as the characteristic size of the devices in the second peripheral circuit chip. The direction indicated by the second mark is the extending direction of the symmetry line of the third wafer. The second wafer is positioned between the first wafer and the third wafer. The method comprises The step of dicing the second dicing lane from the surface of the third wafer away from the second wafer while dicing the first dicing lane from the surface of the first wafer away from the second wafer. further comprising The step of stretching the semiconductor structure to be diced such that the cleavage plane of the first wafer extends to the second wafer. The step of stretching the semiconductor structure to be diced such that the cleavage plane of the first wafer and the cleavage plane of the third wafer extend to the second wafer. comprising The dicing method according to claim 10.

13. The direction indicated by the second mark is the same as the extending direction of the second dicing lane, the cleavage plane of the third wafer is parallel to the direction indicated by the second mark, the characteristic size of the devices in the first peripheral circuit chip is the same as the characteristic size of the devices in the second peripheral circuit chip, the direction indicated by the second mark is the extending direction of the symmetry line of the third wafer, and the third wafer is positioned between the first wafer and the second wafer. The step of dicing the first dicing lane from the surface of the first wafer away from the second wafer is The step of dicing the first dicing lane and the second dicing lane from the surface of the first wafer away from the second wafer including The step of stretching the semiconductor structure to be diced such that the cleavage plane of the first wafer extends to the second wafer is The step of stretching the semiconductor structure to be diced such that the cleavage plane of the first wafer and the cleavage plane of the third wafer extend to the second wafer including The dicing method according to claim 10.

14. The step of stretching the semiconductor structure to be diced is The step of stretching the semiconductor structure to be diced along a direction perpendicular to the cleavage plane of the first wafer including, the dicing method according to claim 8.

15. The step of providing the semiconductor structure to be diced is The step of providing the first wafer including the plurality of first peripheral circuit chips, The step of providing the second wafer including the plurality of memory array chips, and the step of bonding the first wafer to the second wafer to form the semiconductor structure to be diced including, the dicing method according to claim 8.

16. A memory, wherein the memory is obtained by dicing a semiconductor structure by using the dicing method according to any one of claims 8 to 15.

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