Low-Temperature Etching of Doped Silicon Oxide

Abstract

Examples are disclosed related to etching features in a silicon oxide layer doped with an etch rate modifying dopant. One example provides a method of performing a memory device fabrication process. The method includes placing a substrate in a processing chamber of a processing tool, the substrate comprising a first structure having alternating layers within a mold stack for a 3D memory structure, and the substrate also comprising a second structure having a silicon oxide layer doped with an etch rate modifying dopant. The method further includes controlling the processing tool to perform an etching cycle that includes etching at least a portion of the channel holes in the first structure of the substrate and at least a portion of the holes in the second structure of the substrate.

Description

Background

[0001] The electronic device manufacturing process can involve many steps such as deposition, patterning, and removal of materials to form integrated circuits and / or memory structures on a substrate. Various methods can be used to deposit a film of material on a substrate. As an example, chemical vapor deposition (CVD) involves reacting precursors to form a film on a substrate. As another example, dry etching can be used to etch features into one or more material layers on a substrate. SUMMARY OF THE INVENTION

[0002] This summary of the invention is provided to introduce a selection of concepts in a simplified form that are further described in the following modes for carrying out the invention. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. Further, the claimed subject matter is not limited to embodiments that solve some or all of the disadvantages described in any part of this disclosure.

[0003] Examples are disclosed related to etching features into a layer of silicon oxide doped with an etching rate modifying dopant. One example provides a method of performing a memory device manufacturing process, the method including placing a substrate in a processing chamber of a processing tool. The substrate comprises a first structure having alternating layers within a mold stack for a 3D memory structure. The substrate also comprises a second structure having a silicon oxide layer doped with an etching rate modifying dopant. The method further includes controlling the processing tool to perform an etching cycle that includes etching at least a portion of the channel holes within the first structure of the substrate and at least a portion of the holes within the second structure.

[0004] In some such examples, the method further includes controlling the processing tool to cool the substrate to 0°C or below during the etching cycle.

[0005] Alternatively or additionally, in some such examples, controlling the processing tool to perform an etching cycle includes controlling the processing tool to introduce a fluorine-containing etchant into the processing chamber.

[0006] Alternatively or additionally, in some such examples, the holes in the second substrate structure comprise contact holes.

[0007] Alternatively or additionally, in some such examples, the method further includes reacting a silicon-containing precursor, an oxygen-containing precursor, and an etching rate modifying dopant precursor to deposit a second structure by forming silicon oxide doped with the etching rate modifying dopant.

[0008] Alternatively or additionally, in some such examples, the etching rate modifying dopant includes one or more of nitrogen, carbon, boron, arsenic, or phosphorus.

[0009] Alternatively or additionally, in some such examples, the second structure includes two or more etching rate modifying dopants.

[0010] Alternatively or additionally, in some such examples, the two or more etching rate modifying dopants include a first etching rate modifying dopant that includes nitrogen.

[0011] Alternatively or additionally, in some such examples, the second structure includes nitrogen at a concentration within the range of 5 to 10 atomic percent.

[0012] Alternatively or additionally, in some such examples, the etching rate modifying dopant precursor includes one or more of ammonia, di(isopropylamino)silane, or bis(t-butylamino)silane.

[0013] Alternatively or additionally, in some such examples, the etch rate modifying dopant comprises a second etch rate modifying dopant, and the second etch rate modifying dopant comprises phosphorus.

[0014] Alternatively or additionally, in some such examples, the silicon oxide layer comprises phosphorus at a concentration within the range of 0.1 to 1 atomic percent.

[0015] Alternatively or additionally, in some such examples, the etch rate modifying dopant precursor further comprises a second etch rate modifying dopant precursor, and the second etch rate modifying dopant precursor comprises one or more of phosphine or alkylphosphine.

[0016] Another example provides a method of etching a substrate. The method includes placing a substrate including a dielectric material in a processing chamber of a processing tool, the dielectric material including silicon oxide and an etch rate modifying dopant. The method further includes controlling the processing tool to cool the substrate to a substrate temperature of 0 °C or less. The method further includes controlling the processing tool to introduce an etchant into the processing chamber. The method further includes controlling the processing tool to form a plasma including an etchant for etching features having an aspect ratio of 10:1 or greater in the dielectric material.

[0017] In some such examples, the etch rate modifying dopant comprises one or more of nitrogen, carbon, boron, arsenic, or phosphorus.

[0018] Alternatively or additionally, in some such examples, the etch rate modifying dopant is a first etch rate modifying dopant, the dielectric material further comprises a second etch rate modifying dopant, the first etch rate modifying dopant comprises nitrogen, and the second etch rate modifying dopant comprises phosphorus.

[0019] Another example provides a 3D memory structure. The 3D memory structure includes channel holes extending through a first substrate structure having alternating material layers. The 3D memory structure further includes holes extending through a second substrate structure including a layer of silicon oxide doped with a first etch rate modifying dopant and a second etch rate modifying dopant.

[0020] In some such examples, the first etch rate modifying dopant includes nitrogen and the second etch rate modifying dopant includes phosphorus.

[0021] In some such examples, the layer of silicon oxide includes, additionally or alternatively, nitrogen at a concentration within the range of 5 to 10 atomic percent.

[0022] In some such examples, the layer of silicon dioxide includes, additionally or alternatively, phosphorus at a concentration within the range of 0.1 to 1.0 atomic percent.

[0023] In some such examples, the alternating material layers include, additionally or alternatively, a staircase structure, and the layer of silicon oxide doped with the first etch rate modifying dopant and the second etch rate modifying dopant is disposed on at least a portion of the staircase structure.

[0024] In some such examples, the holes extending through the second substrate structure include, additionally or alternatively, contact holes filled with a contact material.

Brief Description of the Drawings

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[0036] The term "aspect ratio" generally represents the ratio between the depth of a substrate feature such as a hole and the average width of the feature.

[0037] The term "channel hole" generally represents a hole etched into a stack of alternating material layers to form a channel that defines a memory cell in a 3D memory structure.

[0038] The term "contact hole" generally represents a hole in a dielectric material structure that can be filled with a conductive material to form a contact.

[0039] The term "etching" and variations thereof generally represent a process by which material is selectively removed from a substrate. Etching using a vapor phase etchant is called "dry etching". Etching using a liquid phase etchant is called "wet etching". Reactive ion etching (RIE) is a dry etching process that uses a plasma containing chemically reactive ions to etch material. In some etching processes, a mask is used to protect some regions of the substrate surface from being etched.

[0040] The term "etch rate modifying dopant" generally refers to a dopant in a silicon oxide film that enables the film to be etched at a different rate compared to an undoped film. Examples of etch rate modifying dopants for silicon oxide films include nitrogen, phosphorus, carbon, boron, arsenic, and combinations of two or more of these.

[0041] The term "etch rate modifying dopant precursor" generally refers to a material that includes an etch rate modifying dopant and can react with a silicon-containing precursor and an oxygen-containing gas to deposit a doped silicon oxide layer. Examples of etch rate modifying dopant precursors include nitrogen-containing precursors, phosphorus-containing precursors, carbon-containing precursors, boron-containing precursors, and arsenic-containing precursors.

[0042] Examples of nitrogen-containing precursors include ammonia (NH3) and aminosilanes. Examples of aminosilanes include bis(diethylamino)silane, di(isopropylamino)silane (DIPAS), bis(t-butylamino)silane (BTBAS), (di-sec-butylamino)silane, and tris(dimethylamino)silane (3DMAS).

[0043] Examples of phosphorus-containing precursors include phosphine (PH3), and alkylphosphines such as trimethylphosphine, triethylphosphine, and tributylphosphine.

[0044] An example of a suitable boron-containing precursor is diborane (B2H6).

[0045] Examples of carbon-containing precursors include carbon monoxide (CO), alkanes, alkenes, alkynes, cyclic hydrocarbons, aromatic compounds, alcohols, diols, aldehydes, esters, ethers, ketones, alkylamines, alkyldiamines, and organosilicon compounds. Examples of suitable alkanes (C n H 2n+2 , n = 1 - 10) can include methane, ethane, propane, and butane. Examples of suitable alkenes (C n H2n , for alkenes having a single carbon-carbon double bond where n = 2 to 10, examples can include ethene, propene, and butene. Suitable alkynes (C n H 2n-2 , for alkynes having a single carbon-carbon triple bond where n = 2 to 10, examples can include acetylene, propyne, and butyne. Examples of suitable cyclic hydrocarbons can include cyclobutane, cyclopentane, and cyclohexane. Examples of suitable aromatic compounds can include benzene, toluene, pyridine, and pyrimidine. Examples of suitable alcohols can include methanol, ethanol, and propanol. Examples of suitable diols can include ethylene glycol, propylene glycol, and hydroquinone. Examples of suitable aldehydes can include formaldehyde and acetaldehyde. Examples of suitable esters can include ethyl formate, methyl acetate, and ethyl acetate. Examples of suitable ethers can include diethyl ether, methyl phenyl ether, and aromatic ethers such as furan. Examples of suitable ketones can include acetone and methyl ethyl ketone. Examples of suitable alkyl halides can include ethyl fluoride, isopropyl bromide, and t-butyl chloride. Examples of suitable alkylamines can include methylamine, dimethylamine, trimethylamine, and piperidine. Examples of suitable alkyldiamines can include ethylenediamine and 1,3-diaminopropane. Examples of suitable organosilicon compounds can include siloxanes such as methylsilane, dimethylsilane, trimethylsilane, and dimethyldiethoxysilane.

[0046] An example of an arsenic-containing precursor is arsine (AsH3).

[0047] The term "etchant" generally refers to a chemical substance used in an etching process to chemically remove material from a substrate and / or to facilitate the chemical removal of material from the substrate. Exemplary etchants for plasma etching of silicon oxide include fluorine-containing etchants such as HF, NF3, CF4, and C2F6.

[0048] The term "feature" generally refers to a region of a substrate from which material has been removed (e.g., by etching) to form a recess in the substrate surface. Exemplary features that can be formed by etching include holes and gaps.

[0049] The term "film" generally refers to a layer of material deposited on a substrate.

[0050] The term "oxygen-containing gas" generally refers to a gas species containing oxygen that can be utilized to react with an oxide film precursor to form an oxide film. Examples of oxygen-containing gases include molecular oxygen (O2), ozone (O3), nitrous oxide (N2O), hydrogen peroxide (H2O2), and water vapor (H2O).

[0051] The term "processing chamber" generally refers to an enclosure in which chemical and / or physical processes are performed on a substrate. The pressure, temperature, and ambient composition within the processing chamber can be controllable to perform chemical and / or physical processes.

[0052] The term "processing tool" generally refers to a machine that includes a processing chamber and other hardware configured to enable a process to be performed within the processing chamber.

[0053] The term "radio frequency (RF) power source" generally refers to a component of a processing tool configured to apply power to a pair of electrodes within a processing chamber to form a plasma between the electrodes.

[0054] The term "silicon-containing precursor" generally refers to any material that can be introduced into a processing chamber in the gas phase to form a silicon oxide film on a substrate. Exemplary silicon-containing precursors for forming a silicon oxide film can include materials having the following general structure. [Chemical formula] R1, R2, and R3 can be the same or different substituents and can include silane, siloxy groups, amines, halides, hydrogen, or organic groups such as alkylamines, alkoxys, alkyls, alkenyls, alkynyls, and aromatic groups.

[0055] Exemplary silicon-containing precursors include polysilanes such as silane, disilane, trisilane, tetrasilane, and trisilylamine (H3Si-(SiH2) n -SiH3)(n≧1).

[0056] In some examples, the silicon-containing precursor is an alkoxysilane. Examples of alkoxysilanes that can be used include: H x -Si-(OR) y , where x = 1 to 3, x + y = 4, and each R is a substituted or unsubstituted alkyl, alkenyl, alkynyl, or aromatic group, H x (RO) y -Si-Si-(OR) y H x is a substituted or unsubstituted alkyl, alkenyl, alkynyl, or aromatic group.

[0057] Examples of silicon-containing precursors include tetraethyl orthosilicate (TEOS), tetramethoxysilane (TMOS), methylsilane, trimethylsilane (3MS), ethylsilane, butasilane, pentasilane, octasilane, heptasilane, hexasilane, cyclobutasilane, cycloheptasilane, cyclohexasilane, cyclooctasilane, cyclopentasilane, 1,4-dioxa-2,3,5,6-tetrasilacyclohexane, diethoxymethylsilane (DEMS), diethoxysilane (DES), dimethoxymethylsilane, dimethoxysilane (DMOS), methyldiethoxysilane (MDES), methyldimethoxysilane (MDMS), t-butoxydisilane, triethoxysilane (TES), and trimethoxysilane (TMS or TriMOS).

[0058] In some examples, the silicon-containing precursor can be a siloxane. Exemplary siloxanes include octamethylcyclotetrasiloxane (OMCTS), octamethoxydodecasiloxane (OMODDS), tetramethylcyclotetrasiloxane (TMCTS), triethoxysiloxane (TRIES), and tetraoxymethylcyclotetrasiloxane (TOMCTS).

[0059] As noted above, in some examples, the silicon-containing precursor can be an aminosilane, such as bis(diethylamino)silane, di(isopropylamino)silane (DIPAS), bis(t-butylamino)silane (BTBAS), (di-sec-butylamino)silane, and tris(dimethylamino)silane (3DMAS). The aminosilane precursor has the following formula: H x -Si-(NR) y , where x = 1 to 3, x + y = 4, and R is a substituted or unsubstituted alkyl, alkenyl, alkynyl, or aromatic group or a hydride group.

[0060] In some examples, the halogen-containing silane can be used such that the silane contains at least one hydrogen atom. Such silanes have the formula SiX a H yIt may have a chemical formula of (y≧1). For example, dichlorosilane (H2SiCl2) may be used in some examples.

[0061] The term "showerhead" generally refers to a process chemical outlet having a plurality of holes dispersed throughout the region.

[0062] The term "step structure" generally refers to a substrate structure having two or more stacked layers where each successive layer extends laterally a greater distance than the previous layer.

[0063] The term "substrate" generally refers to any object on which a film can be deposited.

[0064] The term "substrate support" generally refers to any structure for supporting a substrate in a processing chamber. Examples include chucks, pedestals, and showerhead pedestals used in backside deposition processes.

[0065] The term "3D memory structure" generally refers to a structure formed at any point in a fabrication process for forming a memory device having a stacked architecture in which memory cells are vertically layered. Examples of 3D memory structures include structures formed in 3D NAND memory and 3D NOR memory fabrication processes.

[0066] The term "3D NAND" is an acronym for three-dimensional NOT AND memory and represents a memory architecture based on NOT AND logic gates.

[0067] The term "3D NOR" is an acronym for three-dimensional NOT OR memory and represents a memory architecture based on NOT OR logic gates.

[0068] As described above, the fabrication of a memory structure can involve many steps such as material deposition, patterning, and removal. For example, 3D memory devices such as 3D NAND and 3D NOR semiconductor devices are built on pairs of stacked materials where an “active” device layer is one of the pair and the other is a dielectric for electrical insulation. By stacking pairs of these layers, a manufacturer can create more active layers and ultimately build what is called a “mold stack”. Patterning, etching, and metallization of the mold stack are performed to create a 3D NAND memory chip. During the integration flow of a 3D NAND device, large regions that are effectively empty space (aka gaps) are created within the device. These gaps are often filled with a dielectric material to provide material for further patterning steps. The material used to fill the gaps is referred to herein as a gap fill material.

[0069] Patterning and device integration often involve etching holes (e.g., cylindrical holes) through the gap fill material. The depth of the etching depends on the overall height of the mold stack. Considering the increasing feature height in 3D memory technologies, the amount of material that needs to be removed in the etching process continues to increase. The amount of time used to remove the material also increases as the etching depth increases. This can slow down the manufacturing line and potentially make the integration flow more complex.

[0070] Etching of features into the gap fill material can be performed using dry etching. Variables to consider in a dry etching environment include the gas mixture, process chamber pressure, and process temperature.

[0071] In some dry etching processes, the materials exposed to the dry etching environment are actively cooled. Such etching processes are called cryogenic etching. Since chemical and physical reactions occur between the deposited material and the etchant, cooling the exposed material removes heat from the substrate. By keeping the feature sidewalls at a low temperature during etching, ions during the etching process may be able to move deeper into the gap. The more reactants are at the bottom of the gap, the higher the etching rate can be increased. This can have a beneficial effect on relatively long and deep etching to keep the surrounding materials intact even as the etching progresses. Therefore, cryogenic etching tools can be used to etch features in 3D memory device technology. Although described below in relation to 3D NAND fabrication, the disclosed examples can also be used for the fabrication of other types of 3D devices such as 3D NOR memory devices.

[0072] Existing 3D NAND gap fill materials can include silicon, oxygen, carbon, and hydrogen, with silicon and oxygen being the majority elements. Referring to FIG. 1, as shown at 102, it can be seen that the etching rate of the silicon oxide dry etching process increases as the substrate temperature decreases. Therefore, it may be possible to achieve a faster etching rate of silicon oxide using cryogenic etching. Further, as shown at 104, it can be seen that silicon nitride has a higher etching rate than silicon oxide over a wide temperature range. Therefore, nitrogen can be doped into the silicon oxide film to increase the etching rate at a given temperature. It is also possible to modify the etching rate of silicon oxide using other etching rate modifying dopants. Examples of other etching rate modifying dopants can include one or more of carbon, boron, arsenic, or phosphorus.

[0073] By increasing the etching rate of the silicon oxide film by using cryogenic etching and doped silicon oxide films, the etching of features in gap fill materials such as 3D NAND or 3D NOR fabrication processes can be promoted. For example, as will be described in more detail below, when using dry etching to etch relatively deep and narrow features into a gap fill material, the etching rate can affect various dimensions of the feature. As a more specific example, if the dry etching rate is slow, warping (non-uniformity of the feature diameter as a function of the feature depth) can occur, and the rate of lateral growth (e.g., growth of the feature diameter) as a function of vertical growth (depth) can increase. Further, if the dry etching rate is slow, the process time can be long and the cost can increase. Cryogenic etching of doped silicon oxide gap fill materials can help mitigate such problems compared to cryogenic etching of undoped silicon oxide films. An exemplary etching process will be described in more detail below.

[0074] FIG. 2 schematically shows a schematic diagram of an exemplary processing tool 200 that can be used to deposit a silicon oxide gap fill material doped with an etching rate modifying dopant. The processing tool 200 is configured as a plasma enhanced chemical vapor deposition (PECVD) tool. In other examples, any other suitable deposition tool can be used to deposit a silicon oxide gap fill material doped with an etching rate modifying dopant. Examples can include atomic layer deposition (ALD) tools.

[0075] The processing tool 200 includes a processing chamber 202 and a substrate support 204 within the processing chamber. The substrate support 204 is configured to support a substrate 206 disposed within the processing chamber 202. In some examples, the processing tool 200 includes a substrate heater 208 disposed adjacent to the substrate 206. In other examples, the heater can be omitted or located at another location within the processing chamber 202. The substrate support 204 can comprise a pedestal, a chuck, and / or any other suitable structure.

[0076] The processing tool 200 further includes a showerhead 210, a gas inlet 212 connected to the showerhead 210, and flow control hardware 214. In other examples, the processing tool can include a nozzle or other device for introducing gas into the processing chamber 202, in contrast to or in addition to the showerhead. The flow control hardware 214 is connected to a silicon precursor gas source 216, a first etch rate modifying dopant gas source 217, an optional second etch rate modifying dopant gas source 218, an oxygen-containing gas source 219, and an inert gas source 220. The silicon precursor gas source 216 can include any suitable silicon-containing precursor that forms a silicon oxide film when reacted with an oxygen-containing gas. One exemplary silicon-containing precursor is silane. In some examples, one or more aminosilanes can be used. Suitable aminosilanes include di(isopropylamino)silane (DIPAS) and bis(t-butylamino)silane (BTBAS). Other exemplary silicon-containing precursors include those described above.

[0077] The oxygen-containing gas source 219 can include, for example, O2, O3, N2O, H2O2, water vapor, or a mixture of two or more thereof.

[0078] The first etching rate correction dopant gas source 217 can include any suitable gas for introducing the first etching rate correction dopant into the silicon oxide film. The optional second etching rate correction dopant gas source 218 can include a second etching rate correction dopant precursor different from the first etching rate correction dopant precursor. In some examples, the processing tool can include additional etching rate correction dopant gas sources.

[0079] Examples of suitable etching rate correction dopant precursors include nitrogen-containing precursors, phosphorus-containing precursors, carbon-containing precursors, boron-containing precursors, and arsenic-containing precursors. For a film using two additional etching rate correction dopants, any suitable combination of etching rate correction dopants can be used. In some examples, the first etching rate correction dopant gas source 217 includes a nitrogen-containing precursor. In some such examples, the second etching rate correction dopant gas source 218 includes a phosphorus-containing precursor. Examples of nitrogen-containing precursors include ammonia (NH3) and aminosilanes. For example, it is possible to use aminosilanes to provide both silicon and nitrogen and grow a nitrogen-doped silicon oxide film. Suitable aminosilanes include DIPAS and BTBAS. Examples of phosphorus-containing precursors include phosphine (PH3), and alkylphosphines such as trimethylphosphine, triethylphosphine, and tributylphosphine. An example of a boron-containing precursor is diborane (B2H6). Examples of carbon-containing precursors include carbon monoxide (CO), alkanes, alkenes, alkynes, cyclic hydrocarbons, aromatic compounds, alcohols, aldehydes, esters, ethers, ketones, alkylamines, alkyldiamines, and organosilicon precursors (e.g., methylsilane, dimethylsilane, trimethylsilane, and siloxane). An example of an arsenic-containing precursor is arsine (AsH3).

[0080] The inert gas source 220 can include any suitable inert gas such as one or more of helium, neon, argon, krypton, xenon, or nitrogen.

[0081] The flow control hardware 214 can be controlled to flow gas from various gas sources into the processing chamber 202 through the gas inlet 212. The flow control hardware 214 can include one or more valves that can be controlled to fluidly connect the selected gas source to the gas inlet 212.

[0082] The processing tool 200 further includes an exhaust system 224. The exhaust system 224 is configured to receive the gas flowing out of the processing chamber 202. In some examples, the exhaust system 224 is configured to actively remove gas from the processing chamber 202 and / or apply a partial vacuum. The exhaust system 224 can include any suitable hardware including one or more pumps.

[0083] The processing tool 200 further includes a high-frequency power supply 228 electrically connected to the substrate support 204. The high-frequency power supply 228 is configured to form a plasma containing an oxygen-containing gas. The processing tool 200 also includes a matching network 229 for impedance matching of the high-frequency power supply 228. The plasma can also include an inert dilution gas from the inert gas source 220. The high-frequency power supply 228 can be configured for any suitable frequency (e.g., 400 kHz or 13.56 MHz as an example) and power (e.g., 0 to 6500 watts). In some examples, the high-frequency power supply 228 is configured to operate at multiple different frequencies and / or powers.

[0084] Controller 230 is operably coupled to substrate heater 208, flow control hardware 214, exhaust system 224, and RF power supply 228. Controller 230 is configured to control various functions of processing tool 200, such as operating substrate heater 208 to heat to a desired temperature. Controller 230 is further configured to operate flow control hardware 214 to flow selected gases into process chamber 202. Controller 230 is further configured to operate exhaust system 224. Controller 230 is further configured to operate RF power supply 228 to form a plasma. Controller 230 can comprise any suitable computing system, examples of which are described below with reference to FIG. 11.

[0085] FIG. 3 schematically shows an exemplary etching tool 300 configured to perform an ultra-low temperature dry etching process, also referred to herein as a low temperature etching process. Etching tool 300 includes a process chamber 302 and a substrate support 304 within the process chamber. Substrate support 304 is configured to support a substrate 306 disposed within process chamber 302. Substrate support 304 can comprise a pedestal, a chuck, and / or any other suitable structure.

[0086] Etching tool 300 further includes a gas inlet 312 and flow control hardware 314. Flow control hardware 314 is connected to an etchant gas source 316 and an inert gas source 320. Etchant gas source 316 can contain any suitable etchant chemical. Examples include fluorine-containing etchants. Suitable fluorine-containing etchants include HF, NF3, CF4, and C2F6. Inert gas source 320 can contain any suitable inert gas, such as one or more of helium, neon, argon, krypton, xenon, or nitrogen.

[0087] The flow control hardware 314 is controllable to flow gas from the etchant gas source 316 and the inert gas source 320 into the processing chamber 302 via the gas inlet 312. The flow control hardware 314 includes one or more valves controllable to fluidly connect a selected gas source to the gas inlet 312.

[0088] The etching tool 300 further includes an exhaust system 324. The exhaust system 324 is configured to receive the gas flowing out of the processing chamber 302. In some examples, the exhaust system 324 is configured to actively remove the gas from the processing chamber 302 and / or apply a partial vacuum. The exhaust system 324 can include any suitable hardware including one or more pumps.

[0089] The etching tool 300 further includes a high-frequency power supply 328 electrically connected to the substrate support 304. Accordingly, the substrate support 304 forms the first electrode. The etching tool 300 further includes a second electrode 350. The high-frequency power supply 328 is configured to form a plasma including the etchant gas. The etching tool 300 can include a matching network 329 for impedance matching of the high-frequency power supply 328. The plasma can also include an inert dilution gas from the inert gas source 320. The high-frequency power supply 328 can be configured for any suitable frequency and power. In some examples, the high-frequency power supply 328 is configured to operate at multiple different frequencies and / or powers.

[0090] The etching tool 300 further includes a chiller 352 configured to circulate a coolant through the substrate support 304 to cool the substrate for a low-temperature etching process.

[0091] The controller 330 is operably coupled to the flow control hardware 314, the exhaust system 324, the high-frequency power supply 328, and the chiller 352. The controller 330 is configured to control various functions of the etching tool 300, such as operating the substrate chiller 352 to cool the substrate to a desired temperature. The controller 330 is further configured to operate the flow control hardware 314 to flow a selected gas into the processing chamber 302. The controller 330 is further configured to operate the exhaust system 324. The controller 330 is further configured to operate the high-frequency power supply 328 to form a plasma. The controller 330 can comprise any suitable computing system, examples of which are described below with reference to FIG. 11.

[0092] FIG. 4 shows a flowchart illustrating a method 400 for performing a low-temperature etching process. The etching tool 300 is an exemplary processing tool for performing the method 400. Method 400 includes, at 402, placing a substrate in the processing chamber of the processing tool, the substrate including a dielectric material including silicon oxide and an etch rate modifying dopant. In some examples, at 404, the etch rate modifying dopant includes one or more of nitrogen, carbon, boron, arsenic, or phosphorus.

[0093] Method 400 further includes, at 406, controlling the processing tool to cool the substrate to a substrate temperature of 0° C. or less. In some examples, the processing tool can cool the substrate to a substrate temperature within the range of -60° C. to -10° C. In other examples, substrate temperatures outside of this range can be used.

[0094] Subsequently, at 410, method 400 further includes controlling the processing tool to introduce an etchant into the processing chamber. In some examples, at 412, the etchant includes a fluorine-containing etchant. Suitable fluorine-containing etchants include HF, NF3, CF4, and C2F6.

[0095] Method 400 further includes controlling a processing tool to form a plasma including an etchant for etching a feature having an aspect ratio in the range of 10:1 to 100:1 in a dielectric material at 416. In some examples, at 418, the feature has an aspect ratio in the range of 30:1 to 70:1. All ranges described herein include the endpoints. In some examples, the feature can have an aspect ratio greater than 100:1. In some examples, the feature comprises a hole in a memory device structure. In some examples, at 420, the feature comprises a contact hole in a 3D NAND memory structure. In other examples, the feature comprises a contact hole in a 3D NOR memory structure. Further, in some examples, the substrate comprises a first substrate structure having alternating layers in a mold stack for a 3D NAND structure and a second substrate structure including a dielectric material. In such examples, the method further includes controlling the processing tool to simultaneously etch at least a portion of the holes in the second substrate structure and the channel holes in the first substrate structure, as shown at 422.

[0096] Figures 5A and 5B show diagrams comparing exemplary high aspect ratio features etched through a hard mask layer into a silicon oxide layer and exemplary high aspect ratio features etched through a hard mask layer into a nitrogen doped silicon oxide layer.

[0097] More specifically, FIG. 5A schematically shows a feature 500 etched into a gap-fill material 502 containing undoped silicon oxide using a low-temperature etching process. The feature is defined by a hard mask 504. As shown, in some examples, warping may occur because the dry etching rate of undoped silicon oxide is relatively slow. This is indicated by an increase and subsequent decrease in the width of feature 500 at the interface between gap-fill material 502 and hard mark 504. As a result, the width (e.g., diameter) dimension of feature 500 at this interface is larger than the width (e.g., diameter) of the corresponding opening in hard mask 504. Further, warping and the larger dimension can be apparent before etching feature 500 all the way to its depth.

[0098] FIG. 5B schematically shows a feature 550 etched into a gap-fill material 552 containing silicon oxide doped with an etch rate modifying dopant using a low-temperature etching process under etching conditions similar to those of feature 500. As described above, the use of an etch rate modifying dopant can provide a faster etch rate compared to etching undoped silicon oxide. Any suitable dopant concentration can be used. In some examples, an N-doped silicon oxide film containing a nitrogen concentration of 16-20 atomic percent can have an etch rate of about 180 nm / min. An undoped oxide film can have an etch rate of about 100 nm / min under similar etching conditions.

[0099] In contrast to feature 500, feature 550 has less warping and its width more closely matches the width of the corresponding opening in hard mask 554 as compared to feature 500 and hard mask 504. Feature 550 can have any suitable aspect ratio. In some examples, feature 550 can have an aspect ratio of 10:1 or greater. For example, feature 550 can have an aspect ratio in the range of 10:1 to 100:1. In some examples, feature 550 can have an aspect ratio in the range of 50:1 to 100:1.

[0100] Feature 550 can be any suitable structure within the integrated circuit. In some examples, feature 550 can comprise contact holes in a 3D NAND fabrication process or a 3D NOR fabrication process. Further, as described above, the etch rate modifying dopant can include any suitable material. Examples include one or more of nitrogen, carbon, boron, arsenic, or phosphorus.

[0101] The use of the etch rate modifying dopant can provide advantages other than those shown in FIGS. 5A and 5B. For example, a 3D NAND device can comprise high aspect ratio features formed through alternating layers of a mold stack (e.g., channel holes) and through a silicon oxide gap fill material. As a more specific example, high aspect ratio features can be formed through a silicon oxide gap fill material to make contacts to the NAND device. Such high aspect ratio features may also be referred to herein as contact holes. In a typical NAND fabrication process, channel holes and contact holes are etched in different processes. This is at least part of the alternating layers of the mold stack that are etched at a different rate than the silicon oxide gap fill using the same etch chemistry and etch conditions.

[0102] The use of one or more etching rate modifying dopants in a silicon oxide gap fill material can modify the etching rate of the gap fill material and can appropriately approximate the etching rate of the alternating layers of the mold stack. As one exemplary example, when the mold stack comprises alternating silicon oxide layers and silicon nitride layers, the etching rate modifying dopant can include nitrogen and / or one or more other suitable materials. Examples of using two or more co-dopants will be described in more detail below. The concentration of nitrogen and / or other dopants in the silicon oxide gap fill material is selected to modify the etching rate to match the average etching rate of the materials in the alternating layers of the mold stack. This can enable channel hole etching and gap fill etching to proceed at similar rates. Similarly, the concentration of the etching modifying dopant can also be selected to achieve control of the difference in etching rate, thereby enabling features of different depths to be etched in the same step. The amount of dopant incorporated into the gap fill material during deposition can be controlled by controlling the concentration of the dopant precursor gas used relative to the silicon-containing precursor gas.

[0103] FIG. 6 shows a flow diagram of an exemplary method for performing a memory device fabrication process that includes simultaneously etching at least a portion of a channel hole and a hole in a gap fill material. At 602, method 600 is to place a substrate in a processing chamber of a processing tool, the substrate comprising a first substrate structure having alternating layers in a mold stack for a 3D memory structure, the substrate also comprising a second substrate structure comprising a silicon oxide layer doped with one or more etching rate modifying dopants. In some examples, at 604, method 600 further includes depositing the second substrate structure by reacting a silicon-containing precursor, an oxygen-containing gas, and an etching rate modifying dopant precursor to form a silicon oxide layer doped with an etching rate modifying dopant. In some examples, at 606, the etching rate modifying dopant precursor includes one or more of a nitrogen-containing precursor, a phosphorus-containing precursor, a carbon-containing precursor, a boron-containing precursor, or an arsenic-containing precursor. Subsequently, at 610, method 600 further includes controlling the processing tool to perform an etching cycle that includes simultaneously etching at least a portion of a channel hole in the first substrate structure and at least a portion of a hole in the second substrate structure. In some examples, the holes in the second substrate structure comprise contact holes in the 3D memory structure.

[0104] In some examples, at 612, the method includes controlling a processing tool to cool the substrate to a substrate temperature of 0°C or less during an etching cycle. In some examples, at 614, the method includes introducing a fluorine-containing etchant into the processing chamber. Suitable fluorine-containing etchants include HF, NF3, CF4, and C2F6. In some examples, at 616, method 600 includes forming a plasma in the processing chamber. For example, the method can include controlling the processing tool to form a plasma that includes a fluorine-containing etchant. In some examples, at 618, the holes in the second substrate structure comprise contact holes. In some examples, at 620, controlling the processing tool to perform an etching cycle includes controlling the processing tool to etch the channel holes to an aspect ratio within a range of 50:1 to 100:1. In some examples, at 622, controlling the processing tool to perform an etching cycle includes controlling the processing tool to etch the holes in the second substrate structure to an aspect ratio within a range of 10:1 to 100:1. In some examples, the processing tool can be controlled to etch the holes in the second substrate structure to an aspect ratio greater than 100:1.

[0105] FIG. 7 schematically shows a starting structure and an ending structure before and after performing an exemplary gap-fill process in a 3D NAND fabrication process. First, a "staircase" structure is shown at 702. The staircase structure 702 is etched from a mold stack comprising alternating layers 704, 706. In some examples, the alternating layers 704, 706 can comprise silicon oxide layers and silicon nitride layers. In other examples, the alternating layers 704, 706 can comprise alternating silicon oxide layers and polysilicon layers. In other examples, the alternating layers 704, 706 can include any other suitable materials.

[0106] Next, a layer of gap-fill material 710 is deposited. The layer of gap-fill material 710 can be deposited in a series of steps not shown in FIG. 7. Such a process can include patterning, deposition, and etching steps in some examples.

[0107] The gap-fill material 710 includes silicon oxide and an etch rate modifying dopant. Exemplary dopants include one or more of nitrogen, carbon, boron, arsenic, or phosphorus. The dopant can have any suitable concentration to modify the etch rate.

[0108] The gap-fill material 710 can be deposited in any suitable manner. For example, a silicon-containing precursor (e.g., silane, etc.), an oxygen precursor (e.g., one or more of O2, O3, H2O, N2O, etc.), and an etch rate modifying dopant precursor (e.g., ammonia, aminosilane, etc.) can be introduced into a PECVD chamber under suitable conditions to form a film of the gap-fill material on the substrate. In other examples, the gap-fill material 710 can be deposited via an ALD process.

[0109] FIG. 8 schematically shows an exemplary 3D memory structure 800 including channel holes and a plurality of holes etched through the gap-fill material 710. The 3D memory structure 800 includes a first substrate structure 802 and a second substrate structure 804. The first substrate structure 802 includes alternating layers 704, 706. The first substrate structure 802 further includes channel holes 808 extending through the alternating layers 704, 706. Any suitable number of alternating layers can be used. Further, the channel holes 808 can extend through any suitable number of layers within the first substrate structure 802. The channel holes 808 can be filled with one or more materials to form a 3D NAND memory cell structure or a 3D NOR memory cell structure.

[0110] The second substrate structure 804 includes a gap-fill material 710. The gap-fill material 710 comprises a layer of silicon oxide doped with an etch rate modifying dopant. As described above, a suitable etch rate modifying dopant can include one or more of nitrogen, carbon, boron, arsenic, or phosphorus. The 3D memory structure 800 further comprises holes 814, 815, 816, 817 extending through the gap-fill material 710. Each of the holes 814, 815, 816, 817 extends to different layers within the staircase structure. Each of the holes 814, 815, 816, 817 can comprise a contact hole and can be filled with one or more materials to form an electrical contact. The 3D memory structure 800 can be formed, for example, using method 600 to simultaneously etch at least a portion of the channel hole 808 and at least a portion of one or more of the holes 814, 815, 816, or 817.

[0111] As described above, a doped silicon oxide film with a relatively high nitrogen concentration can have a relatively higher etch rate compared to a film with a relatively low nitrogen concentration. However, a relatively high concentration of dopant can potentially affect the dielectric properties of the film. For example, a silicon oxide film with a relatively high nitrogen concentration may have a lower breakdown voltage and / or a higher leakage current compared to a film with a relatively low nitrogen concentration.

[0112] Accordingly, examples are also disclosed for doping a silicon oxide film with two or more etching rate modifying dopants. The co-doped silicon oxide film can be useful in achieving the above-described etching rate advantages while using a relatively low dopant concentration as compared to examples using a single dopant. Thus, the co-doped silicon oxide film can have a lesser impact on the dielectric properties of the film than a silicon oxide film having a single dopant. For example, a silicon oxide film doped with nitrogen and phosphorus can be useful in achieving a similar or faster etching rate with a 50% reduction in dopant concentration as compared to a silicon oxide film doped with nitrogen only. In some examples, a co-doped silicon oxide film comprising a nitrogen concentration of 5 to 10 atomic percent and a phosphorus concentration of 0.1 to 1.0 atomic percent can have an etching rate of about 190 nm / min. As described above, an N-doped silicon oxide film comprising a nitrogen concentration of 16 to 20 atomic percent can have an etching rate of about 180 nm / min under similar etching conditions. Further, the co-doped silicon oxide film can be capable of having a relatively low hydrogen concentration as compared to a silicon oxide film doped with nitrogen only. In various examples, the doped silicon oxide film can comprise one, two, or more etching rate modifying dopants.

[0113] FIG. 9 shows a flow diagram illustrating an exemplary method 900 for performing low temperature etching of silicon oxide doped with two etching rate modifying dopants. In other examples, three or more etching rate modifying dopants can be used to perform low temperature etching.

[0114] Method 900 can be implemented, for example, with an etching tool 300. Method 900 includes, at 902, controlling the processing tool to cool a substrate to a substrate temperature of 0 °C or less within a processing chamber of the processing tool. The substrate includes a dielectric material including silicon oxide, a first etch rate modifying dopant, and a second etch rate modifying dopant. Any suitable combination of etch rate modifying dopants can be used. In some examples, at 904, the first etch rate modifying dopant includes nitrogen. In some such examples, at 906, the dielectric material includes silicon oxide including nitrogen at a concentration within the range of 5 to 10 atomic percent. Further, in some examples, at 908, the second etch rate modifying dopant includes phosphorus. In some such examples, at 910, the dielectric material includes silicon oxide including phosphorus at a concentration within the range of 0.1 to 1.0 atomic percent.

[0115] Subsequently, method 900 further includes, at 912, controlling the processing tool to introduce an etchant into the processing chamber. Any suitable etchant can be used. In some examples, at 914, the etchant includes a fluorine-containing etchant. Suitable fluorine-containing etchants include HF, NF3, CF4, and C2F6.

[0116] Method 900 further includes controlling a processing tool to form a plasma including an etchant for etching a feature having an aspect ratio within a range of 10:1 or greater in a dielectric material. In some examples, at 916, the feature includes an aspect ratio in the range of 10:1 to 100:1. In some examples, at 918, the feature includes an aspect ratio within the range of 30:1 to 70:1. In some examples, the feature comprises holes (e.g., holes 814, 815, 816, 817 of 3D memory structure 800) within a memory device structure. In some examples, at 920, the feature comprises contact holes within a 3D memory structure (e.g., 3D NAND or 3D NOR). In some examples, the substrate comprises a first substrate structure having alternating layers within a mold stack for a 3D memory structure and a second substrate structure including a dielectric material. In such examples, method 900 can further include controlling the processing tool to simultaneously etch at least a portion of the holes in the second substrate structure and channel holes in the first substrate structure, as shown at 922.

[0117] FIG. 10 shows a flowchart of another exemplary method 1000 for performing a memory device fabrication process using a processing tool. At 1002, method 1000 includes obtaining a substrate comprising a first substrate structure having alternating layers of a mold stack of a 3D memory structure. The substrate further comprises a second substrate structure comprising a silicon oxide layer doped with two or more etch rate modifying dopants. In some examples, at 1004, the two or more etch rate modifying dopants include a first etch rate modifying dopant including nitrogen. In some examples, at 1006, the silicon oxide layer includes nitrogen at a concentration within the range of 5 to 10 atomic percent. In some such examples, at 1008, the two or more etch rate modifying dopants further include a second etch rate modifying dopant including phosphorus. In some examples, at 1010, the silicon oxide layer includes phosphorus at a concentration within the range of 0.1 to 1 atomic percent.

[0118] In some examples, at 1012, obtaining a substrate with a second substrate structure involves depositing the second substrate structure by reacting a silicon-containing precursor, an oxygen-containing gas, a nitrogen-containing precursor, and a phosphorus-containing precursor within a CVD tool. Any suitable precursor can be used. In some examples, at 1014, the phosphorus-containing precursor includes one or more of phosphine or alkylphosphine. Further, in some examples, at 1016, the nitrogen-containing precursor includes one or more of ammonia, di(isopropylamino)silane, or bis(t-butylamino)silane. In some examples, the oxygen-containing gas includes one or more of O2, O3, nitrous oxide (N2O), or water vapor. Processing tool 200 is an exemplary tool for depositing the second substrate structure at 1012. Gap fill material 710 is an example of a second substrate structure that can be deposited at 1012. In other examples, a substrate with a pre-deposited second substrate structure can be obtained.

[0119] In some examples, the dopant concentration can be selected to achieve a desired etching rate for the holes. This can facilitate the simultaneous etching of the channel holes in the first substrate structure (e.g., channel holes 808 of the first substrate structure 802) and the holes in the second substrate structure (e.g., holes 814, 815, 816, 817 of the second substrate structure 804).

[0120] Method 1000 further includes, at 1020, placing a substrate on an etching tool and controlling the etching tool to execute an etching cycle. The etching cycle includes etching at least a portion of the channel holes in the first substrate structure and etching at least a portion of the holes in the second substrate structure. Channel hole 808 is an example of a channel hole in the first substrate structure that can be etched at 1020. Holes 814, 815, 816, 817 are examples of holes in the second substrate structure that can be etched at 1020. In some examples, at 1022, the holes in the second substrate structure include contact holes. In some examples, at 1024, the processing tool includes a processing chamber, and controlling the processing tool to execute an etching cycle includes controlling the processing tool to introduce a fluorine-containing etchant into the processing chamber. Suitable fluorine-containing etchants can include HF, NF3, CF4, and C2F6. When forming channel holes in the first substrate structure and holes in the second substrate structure, it is possible to use various patterning steps not described in detail herein. In some examples, at 1026, method 1000 further includes controlling the processing tool to cool the substrate to 0 °C or below during the etching cycle.

[0121] FIG. 11 schematically shows a block diagram of an exemplary computing system. Computing system 1100 is shown in a simplified form. Computing system 1100 can take the form of one or more personal computers, workstations, computers integrated with substrate processing tools, and / or network-accessible server computers.

[0122] Computing system 1100 includes a logic machine 1102 and a memory machine 1104. Computing system 1100 can optionally include a display subsystem 1106, an input subsystem 1108, a communication subsystem 1110, and / or other components not shown in FIG. 11. Controllers 230 and 330 are examples of computing system 1100.

[0123] Logic machine 1102 includes one or more physical devices configured to execute instructions. For example, the logic machine can be configured to execute instructions that are part of one or more applications, services, programs, routines, libraries, objects, components, data structures, or other logical structures. Such instructions can be implemented to perform a task, implement a data type, transform the state of one or more components, achieve a technical effect, or otherwise reach a desired result.

[0124] The logic machine can include one or more processors configured to execute software instructions. Additionally or alternatively, the logic machine can include one or more hardware or firmware logic machines configured to execute hardware or firmware instructions. The processors of the logic machine can be single-core or multi-core, and the instructions executed thereon can be configured for sequential, parallel, and / or distributed processing. The individual components of the logic machine can optionally be distributed across two or more separate devices, which can be remotely located and / or configured for coordinated processing. Aspects of the logic machine can be virtualized and executed by a remotely accessible network computing device configured in a cloud computing configuration.

[0125] The memory machine 1104 includes one or more physical devices configured to hold instructions 1112 executable by a logic machine to implement the methods and processes described herein. When such methods and processes are implemented, the state of the memory machine 1104 may be transformed, for example, to hold different data.

[0126] The memory machine 1104 may include removable devices and / or built-in devices. The memory machine 1104 may include, among other things, optical memories (e.g., CDs, DVDs, HD-DVDs, Blu-ray discs, etc.), semiconductor memories (e.g., RAM, EPROM, EEPROM, etc.), and / or magnetic memories (e.g., hard disk drives, floppy disk drives, tape drives, MRAM, etc.). The memory machine 1104 may include volatile, non-volatile, dynamic, static, read / write, read-only, random access, sequential access, location-addressable, file-addressable, and / or content-addressable devices.

[0127] It will be appreciated that the memory machine 1104 includes one or more physical devices. However, aspects of the instructions described herein may instead be propagated by a communication medium (e.g., electromagnetic signals, optical signals, etc.) that is not held by a physical device for a finite period of time.

[0128] Aspects of the logic machine 1102 and the memory machine 1104 may be integrated into one or more hardware logic components. Such hardware logic components may include, for example, field programmable gate arrays (FPGAs), program and application specific integrated circuits (PASIC / ASICs), program and application specific standard products (PSSP / ASSPs), system on chips (SOCs), and complex programmable logic devices (CPLDs).

[0129] When included, the display subsystem 1106 can be used to present a visual representation of data held by the memory machine 1104. This visual representation can take the form of a graphical user interface (GUI). When the methods and processes described herein change the data held by the memory machine, thereby transforming the state of the memory machine, the state of the display subsystem 1106 is similarly transformed and can visually represent the underlying data change. The display subsystem 1106 can include one or more display devices that utilize virtually any type of technology. Such display devices can be combined with the logic machine 1102 and / or the memory machine 1104 within a shared enclosure, or such display devices can be peripheral display devices.

[0130] When included, the input subsystem 1108 can comprise or interface with one or more user input devices such as a keyboard, mouse, or touch screen. In some examples, the input subsystem can comprise or interface with selected natural user input (NUI) component elements. Such component elements can be integrated or peripheralized, and the conversion and / or processing of input actions can be handled on-board or off-board. Exemplary NUI component elements can include a microphone for speech and / or voice recognition, and infrared, color, stereo, and / or depth cameras for machine vision and / or gesture recognition.

[0131] When included, the communication subsystem 1110 can be configured to communicatively couple the computing system 1100 to one or more other computing devices. The communication subsystem 1110 can include wired and / or wireless communication devices that are compatible with one or more different communication protocols. By way of non-limiting example, the communication subsystem can be configured to communicate via a wireless telephone network, or a wired or wireless local area network or wide area network. In some examples, the communication subsystem can enable the computing system 1100 to send and / or receive messages to and from other devices via a network such as the Internet.

[0132] It will be understood that the configurations and / or techniques described herein are exemplary in nature, and that numerous variations are possible, and thus these specific examples should not be considered in a limiting sense. The specific routines or methods described herein can represent one or more of any number of processing strategies. Accordingly, the various acts illustrated and / or described may be performed in other orders, in parallel, or omitted, in the order illustrated and / or described. Similarly, the order of the above-described processes may be changed.

[0133] The subject matter of the present disclosure includes all novel and non-obvious combinations and sub-combinations of the various processes, systems, and configurations, as well as other features, functions, acts, and / or properties disclosed herein, and any and all equivalents thereof.

Claims

1. A method for performing a memory device fabrication process, comprising: placing a substrate in a processing chamber of a processing tool, the substrate comprising a first structure having alternating layers within a mold stack for a 3D memory structure, the substrate also comprising a second structure comprising a silicon oxide layer doped with an etching rate modifying dopant; controlling the processing tool to perform an etching cycle that includes etching at least a portion of the channel holes in the first structure of the substrate and at least a portion of the holes in the second structure of the substrate. A method comprising the above.

2. The method according to claim 1, further comprising: controlling the processing tool to cool the substrate to a temperature of 0 °C or lower during the etching cycle.

3. The method according to claim 1, wherein: controlling the processing tool to perform the etching cycle includes controlling the processing tool to introduce a fluorine-based etchant into the processing chamber.

4. The method according to claim 1, wherein: the etching rate modifying dopant includes two or more etching rate modifying dopants.

5. The method according to claim 4, wherein: the two or more etching rate modifying dopants include two or more of nitrogen, carbon, boron, arsenic, or phosphorus.

6. The method according to claim 4, wherein: the second structure includes nitrogen at a concentration within the range of 5 to 10 atomic percent.

7. The method according to claim 6, wherein: the second structure includes phosphorus at a concentration within the range of 0.1 to 1 atomic percent.

8. The method according to claim 1, further comprising: reacting a silicon-containing precursor, an oxygen-containing precursor, and an etching rate modifying dopant precursor to deposit the second structure by forming silicon oxide doped with an etching rate modifying dopant.

9. The method according to claim 8, wherein: depositing the second structure further includes reacting two or more etching rate modifying dopant precursors, the silicon-containing precursor, and the oxygen-containing precursor.

10. The method according to claim 9, wherein: The method wherein the two or more etching rate modifying dopant precursors include ammonia, di(isopropylamino)silane, or bis(t-butylamino)silane.

11. The method according to claim 9, wherein the two or more etching rate modifying dopant precursors include one or more of phosphine or alkylphosphine.

12. A method of etching a substrate, comprising placing a substrate containing a dielectric material in a processing chamber of a processing tool, the dielectric material including silicon oxide and an etching rate modifying dopant, controlling the processing tool to cool the substrate to a substrate temperature of 0°C or less, controlling the processing tool to introduce an etchant into the processing chamber, controlling the processing tool to form a plasma including the etchant for etching features having an aspect ratio of 10:1 or greater in the dielectric material is provided.

13. The method according to claim 12, wherein the etching rate modifying dopant includes one or more of nitrogen, carbon, boron, arsenic, or phosphorus.

14. The method according to claim 12, wherein the etching rate modifying dopant is a first etching rate modifying dopant, and the dielectric material includes a second etching rate modifying dopant.

15. The method according to claim 14, wherein the first etching rate modifying dopant includes nitrogen and the second etching rate modifying dopant includes phosphorus.

16. A channel hole extending through a first substrate structure including alternating material layers, and a hole extending through a second substrate structure including a layer of silicon oxide doped with a first etching rate modifying dopant and a second etching rate modifying dopant is provided.

17. The 3D memory structure according to claim 16, wherein the first etching rate modifying dopant includes nitrogen and the second etching rate modifying dopant includes phosphorus.

18. The 3D memory structure according to claim 17, wherein the layer of silicon oxide includes nitrogen at a concentration within the range of 5 to 10 atomic percent and phosphorus at a concentration within the range of 0.1 to 1.0 atomic percent.

19. The 3D memory structure according to claim 16, The 3D memory structure, wherein the interlayer material layer has a staircase structure, and the silicon oxide layer doped with the first etching rate modifying dopant and the second etching rate modifying dopant is disposed on at least a part of the staircase structure.

20. A 3D memory structure according to claim 16, wherein the hole extending through the second substrate structure includes a contact hole filled with a contact material.

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