High aspect ratio etching using a mask containing a metal or a semimetal

Abstract

A method of etching a feature within a stack is provided. Above the stack, a metal or metalloid-containing mask is formed. The stack is etched through the metal or metalloid-containing mask such that the metal or metalloid within the metal or metalloid-containing mask is sputtered by the etching and the sputtered metal or metalloid physically redeposits as a sputtered metal or metalloid-containing passivation layer on sidewalls of the etched feature within the stack.

Description

Technical Field

[0001] <Cross - Reference to Related Applications> This application claims the benefit of priority of U.S. Patent Application No. 63 / 355,040, filed on June 23, 2022, which is hereby incorporated by reference in its entirety for all purposes.

Background Art

[0002] This disclosure relates to a method of forming semiconductor devices on a semiconductor wafer.

[0003] When forming a semiconductor device, an etching layer may be etched to form a memory hole or line, or other semiconductor features. Some semiconductor devices may be formed, for example, by etching a single stack of silicon dioxide, also known as silicon oxide (SiO2), to form the capacitor of a dynamic access random memory (DRAM). Other semiconductor devices may be formed by etching a stack of alternating double layers of silicon dioxide (oxide) and silicon nitride (nitride) (ONON), or a stack of alternating double layers of silicon dioxide and polysilicon (OPOP). Other stacks of alternating layers may be etched. Some of the stacks of alternating layers may have one layer that is an alternating layer of silicon oxide. Some of the alternating layers may be alternating triple layers. Such stacks may be used in memory applications and three-dimensional "NOT AND" gates (3D NAND). Such stacks tend to require relatively high aspect ratio (HAR) etching of dielectrics. In the case of high aspect ratio etching, examples of desired etching characteristics include high etching selectivity to a mask (such as an amorphous carbon mask), low sidewall etching with a straight profile, and high etching rate at the front of the etching. Some high aspect ratio etching results in a tapered feature where the top is much wider than the bottom. Such features can increase device failures or limit device density, device performance, and device depth.

[0004] In some etching processes of an OPOP stack using an amorphous carbon mask, a metal-containing passivation agent is used during the etching process. The metal-containing passivation agent may be supplied during the etching process so that passivation and etching are performed simultaneously, or there may be alternating steps of passivation and etching. When tungsten (W) passivation is used, it has been found that tungsten selectively deposits on polysilicon relative to silicon oxide. Therefore, the passivation on silicon oxide is less than the passivation on polysilicon. As a result of the reduced passivation of silicon oxide, there will be an increase in CD and an increase in defects such as notches. The ability of the passivation layer to protect the underlying material is determined by the weakest or thinnest deposit. For example, if a thinner deposit on the oxide deteriorates during further etching, the oxide may start to be etched even if Si still has tungsten passivation. Etching of the oxide not only increases the CD but also forms additional defects such as notches and keyholes. Non-uniform passivation may also cause profile twist, kink, and ion plane warp.

[0005] The description of the background art provided herein is intended to generally present the content of the present disclosure. Information described in this background art section, as well as aspects of the description that cannot be separately regarded as prior art as of the filing date, are not admitted as prior art against the present disclosure, whether explicitly or implicitly.

Summary of the Invention

[0006] To achieve the above and in accordance with the objectives of the present disclosure, a method of etching features in a stack is provided. A metal or metalloid-containing mask is formed over the stack. The stack is etched through the metal or metalloid-containing mask such that the metal or metalloid in the metal or metalloid-containing mask is sputtered during etching, and the sputtered metal or metalloid physically redeposits as a sputtered metal or metalloid-containing passivation layer on the sidewalls of the etched features in the stack.

[0007] In another embodiment, a method of forming a substrate support for use in a plasma processing chamber is provided. The baseplate includes a substrate support region and a shoulder surrounding the substrate support region. A thermal protection coating is sprayed on the surface of the baseplate, and the protection coating covers at least a portion of the shoulder. A layer of a silane coupling agent is deposited on the protection coating. These and other features of the present disclosure will be described in more detail below in conjunction with the detailed description and the following figures.

Brief Description of the Drawings

[0008] The present disclosure is shown by way of example and not for purposes of limitation. In the figures of the accompanying drawings, like reference numerals refer to like elements.

[0009]

Figure 1

[0010]

Figure 2A

Figure 2B

Figure 2C

Figure 2D

[0011]

Figure 3

[0012]

Figure 4

[0013] Next, the present disclosure will be described in detail with reference to some preferred embodiments thereof, as shown in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without some or all of these specific details. In other instances, well-known process steps and / or structures have not been described in detail in order not to unnecessarily obscure the present disclosure.

[0014] For dry development of high aspect ratio contacts, precise control of the sidewall taper angle is required. Various methods have been attempted to limit the difference in the lateral critical dimension (CD) between the top and bottom of the etched structure. With the recent development of 3D NAND memories having thicker structures with an increased number of ONON or OPOP bilayer, the need to precisely control the shape of the top and bottom has particularly increased. If the profile (the difference in CDs between the top and bottom) is large, risks occur in subsequent device manufacturing steps and it will affect device performance. In current technology, in reactive ion etching of high aspect ratio structures, sidewall deposition is relied upon to protect the lateral etching of the CD. Maintaining a delicate balance between etching and sidewall deposition is particularly difficult for high aspect ratio features. As a result, dry development of high aspect ratio is limited to thinner structures, and a very complex development is required to be able to etch thick stacks.

[0015] Embodiments described herein provide deeper high aspect ratio features etched within a stack, where the width of the feature near the top of the feature is substantially equal to the width of the feature near the bottom of the feature. For ease of understanding, FIG. 1 is a high-level flowchart that may be used in some embodiments. A metal or metal-containing mask is deposited over the stack (step 104). In some embodiments, plasma enhanced physical vapor deposition (PECVD) is used to deposit a metal-containing dielectric film that may be used as a mask. A method of depositing a tungsten carbide film using PECVD is described in U.S. Patent No. 9,875,890, titled "Deposition of Metal Dielectric Film for Hardmask," issued on January 23, 2018, which patent is incorporated by reference for all purposes and may be used in some embodiments. In some embodiments, the deposited tungsten carbide film is patterned to form a mask.

[0016] Figure 2A is a schematic cross-sectional view of stack 204 that can be etched in some embodiments. In some embodiments, stack 204 includes substrate 208 below a plurality of bilayer 212 disposed under patterned mask 216. In some embodiments, one or more layers may be disposed between substrate 208 and the plurality of bilayer 212 and / or between the plurality of bilayer 212 and patterned mask 216. Patterned mask 216 is a metal or semimetal-containing mask. In some embodiments, patterned mask 216 is a tungsten-doped amorphous carbon mask. In some embodiments, the pattern of the patterned mask provides mask feature 220 for high aspect ratio contacts. In some embodiments, mask feature 220 is formed before stack 204 is placed in the etching chamber. In other embodiments, mask feature 220 is formed while stack 204 is in the etching chamber. In some embodiments, each bilayer 212 includes a layer of silicon oxide 224 and a layer of silicon nitride 228.

[0017] Etch the stack and mask (step 108). In some embodiments, an etching gas is supplied. In some embodiments, the etching gas is a gas that does not contain metals and semimetals. In some embodiments, RF power is supplied to convert the etching gas into a plasma having etching ions. A voltage is applied to accelerate the etching ions from the plasma to the stack. In some embodiments, etching ions that do not contain metals and semimetals are supplied from an ion source and accelerated to the stack. The etching ions etch the stack and sputter metals and semimetals from the mask. The etching of the stack may include at least one of chemical etching and physical sputtering of the stack.

[0018] FIG. 2B is a schematic cross-sectional view of stack 204 during etching that forms partially etched feature 240 and deposits tungsten-containing passivation sputtered from mask 216. Etching ions 244 are accelerated toward stack 204. Etching ions 244 etch stack 204, form partially etched feature 240, and sputter a portion of mask 216. In some embodiments, etching ions 244 provide two separate processes for depositing a metal or semimetal passivation on the sidewalls of feature 240. In the first process, etching ions 244 sputter metal or semimetal atoms from mask 216 and generate metal or semimetal species in the plasma. The metal or semimetal species in the plasma are chemically deposited on the sidewalls of feature 240. In the second process, metal or semimetal is sputtered from mask 216 and redeposited on the sidewalls of partially etched feature 240. In some embodiments, sputtered metal or semimetal-containing passivation layer 248 is formed by both chemical deposition of metal or semimetal passivation and physical sputtering of metal or semimetal. This physical sputtering mechanism eliminates the reduction of metal or semimetal-containing deposits obtained particularly from chemical or ion-assisted deposition processes on silicon oxide, and a more uniform passivation layer can result.

[0019] In some embodiments, the etching of the stack continues until the etching of the stack is complete. FIG. 2C is a schematic cross-sectional view of stack 204 after the etching of stack 204 is complete. In some embodiments, feature 240 is etched throughout the depth of stack 204. Sputtered metal or semimetal-containing passivation layer 248 protects the sidewalls of feature 240, further results in an increase in the vertical etching rate, and thus can shorten the overall process time.

[0020] In some embodiments, the metal or metalloid-containing passivation layer 248 is removed (step 112). In some embodiments, a wet process is used to remove the sputtered metal or metalloid-containing passivation layer 248. In some embodiments, a dry process is used. FIG. 2D is a schematic cross-sectional view of the stack 204 after removing the sputtered metal or metalloid-containing passivation layer 248 shown in FIG. 2C. In some embodiments, the mask 216 shown in FIG. 2C is removed in the same process used to remove the sputtered metal or metalloid-containing passivation layer. In some embodiments, the mask is removed using a process different from the process used to remove the sputtered metal or metalloid-containing passivation layer.

[0021] One of the main problems during high aspect ratio (HAR) etching is CD scaling, and in particular, when scaling the desired feature in the vertical direction, it is required to keep the lateral feature size constant at the same time. In practice, it is very difficult to achieve this, and many of the current technologies have trade-offs. In some embodiments, a tungsten-doped carbon hard mask is used not only to protect the stack from unwanted etching, but also to provide a robust tungsten species that deposits on the sidewalls of the etched features and to protect from further lateral etching. This robust tungsten-containing passivation on the sidewalls of the features enables CD control and prevents the formation of other defects such as notches. Further, in some embodiments, both chemical deposition from tungsten species and direct physical sputtering of tungsten-doped carbon are possible, resulting in more uniform passivation at the top of the feature.

[0022] Some embodiments have been found to provide more uniform passivation by depositing more tungsten-containing species on SiO2, making it easier to prevent defect formation such as further lateral etching rates and notches. This is not limited to the deposition quality / thickness of tungsten on SiO2 provided by previously used processes. In some embodiments, improvements are provided in several ways because the tungsten required to produce the protective liner material is obtained from the mask material itself. The improvements provided in some embodiments are due to the liner deposition mechanism. By sputtering tungsten from the mask, not only are molecular tungsten species added as a reactive gas, but physical sputtering of the tungsten-doped carbon mask material also occurs and redeposits on the sidewalls. Thus, both a chemical assist deposition process (from tungsten byproduct formation) and a physical sputtering process (from tungsten-doped carbon) are performed, and their combination enables very uniform deposition across different materials within the etch feature. Overall, this enables significant protection of the top region within the feature from both lateral etching and defect formation (notches) on both bare Si and SiO2 materials.

[0023] Some embodiments may be used on an oxide / nitride (ONON) multilayer stack to form features such as contact holes or trenches when creating 3D NAND memory devices. Some embodiments may be used for dynamic random access memory (DRAM) capacitor etching. Some embodiments may be used to etch a silicon oxide and polysilicon bilayer (OPOP). Some embodiments provide an etch depth exceeding 1 micron. In some embodiments, the etch depth exceeds 10 microns.

[0024] The advantages of some embodiments are that device manufacturers can more precisely control the profile of high aspect ratio features. With various embodiments, the bottom CD of very high aspect ratio features can be increased. With various embodiments, next-generation devices that rely on deeper structures with higher aspect ratios are realized. With various embodiments, the manufacturing cost of the device is reduced by reducing the number of steps required for the development of high aspect ratio contacts. With various embodiments, the variation in the width of the feature along the depth of the feature is reduced, and as a result, the difference in width at any two points along the depth of feature 240 is reduced.

[0025] In some embodiments, the stack may be a single silicon-containing layer, such as a monolayer of silicon oxide, silicon nitride, or silicon. In some embodiments, the stack may be composed of a single layer or multiple layers of other silicon-containing materials.

[0026] In some embodiments, mask 216 is a single layer of mask material, and the metal or semimetal constitutes 1% to 50% by weight of the mask material.

[0027] In some embodiments, for etching a stack having a silicon layer, the mask may further contain oxygen. In some embodiments, for etching a silicon oxide stack, the mask may further contain silicon. Some embodiments may have other materials in addition to the metal or semimetal dopant. In some embodiments, the metal in the metal or semimetal-containing mask is at least one of tungsten, molybdenum, ruthenium, tantalum, titanium, platinum, and aluminum. In other embodiments, the semimetal is boron. In some embodiments, since the metal and semimetal species are provided by sputtering of the metal or semimetal-containing mask, the etching gas does not contain the metal and semimetal.

[0028] FIG. 3 is a schematic diagram of an etching reactor system 300 that may be used in some embodiments. In some embodiments, the etching reactor system 300 includes a gas distribution plate 306 that provides a gas inlet and an electrostatic chuck (ESC) 308 within an etching chamber 309 surrounded by a chamber wall 352. Within the etching chamber 309, a stack 304 is positioned above the ESC 308. The ESC 308 may be supplied with a bias from an ESC source 348. An etching gas source 310 is connected to the etching chamber 309 through the gas distribution plate 306. An ESC temperature controller 350 is connected to the ESC 308. A radio frequency (RF) source 330 supplies RF power to a lower electrode and / or an upper electrode, which in this embodiment are the ESC 308 and the gas distribution plate 306, respectively. In some embodiments, power supplies of 400 kilohertz (kHz), 60 megahertz (MHz), and optionally 2 MHz, 27 MHz, constitute the RF source 330 and the ESC source 348. In some embodiments, the upper electrode is grounded. In some embodiments, one generator is provided for each frequency. In some embodiments, the generator may be provided within a separate RF source, or separate RF generators may be connected to different electrodes. For example, the upper electrode may have an inner electrode and an outer electrode connected to different RF sources. In other embodiments, other configurations of the RF source and the electrodes may be used. A controller 335 is controllably connected to the RF source 330, the ESC source 348, an exhaust pump 320, and the etching gas source 310. An example of such an etching chamber is the Flex® etching system manufactured by Lam Research Corporation of Fremont, California. The process chamber may be a CCP (capacitively coupled plasma) reactor or an ICP (inductively coupled plasma) reactor.

[0029] FIG. 4 is a high-level block diagram showing a computer system 400 suitable for implementing the controller 335 used in the embodiment. The computer system 400 can have many physical forms, ranging from integrated circuits, printed circuit boards, and small portable devices to huge supercomputers. The computer system 400 includes one or more processors 402, an electronic display device 404 (for displaying graphics, text, and other data), a main memory 406 (e.g., random access memory (RAM)), a storage device 408 (e.g., hard disk drive), a removable storage device 410 (e.g., optical disk drive), a user interface device 412 (e.g., keyboard, touch screen, keypad, mouse, or other pointing device, etc.), and a communication interface 414 (e.g., wireless network interface). Through the communication interface 414, software and data can be transferred between the computer system 400 and external devices via a link. The system may also include a communication infrastructure 416 (e.g., communication bus, crossover bar, or network) to which the aforementioned devices / modules are connected.

[0030] The information transferred via the communication interface 414 may be in the form of electronic, electromagnetic, optical, or other signals receivable by the communication interface 414 via a communication link that transmits the signals, and may be implemented using wires or cables, optical fibers, telephone lines, cellular phone links, radio frequency links, and / or other communication channels. With such a communication interface 414, it is conceivable that, in the process of implementing the above-described method steps, one or more processors 402 receive information from a network or output information to a network. Further, embodiments of the method may be executed only by a processor, or may be executed on a network such as the Internet in cooperation with a remote processor that shares part of the processing.

[0031] The term "non-transitory computer-readable medium" generally refers to storage devices such as main memory, secondary memory, removable storage devices, and hard disks, flash memories, disk drive memories, CD-ROMs, and other persistent memories, and should not be construed to include transitory subjects such as carrier waves or signals. Examples of computer code include files containing machine code, such as that generated by a compiler, and higher-level code that is executed by a computer using an interpreter. A computer-readable medium may also be computer code embodied in a carrier wave and transmitted by a computer data signal representing a series of instructions executable by a processor.

[0032] Although the present disclosure has been described with respect to several preferred embodiments, within the scope of the present disclosure, there are changes, modifications, rearrangements, and various alternative equivalents. It should also be noted that there are many alternative means of implementing the methods and apparatuses of the present disclosure. Accordingly, the following appended claims are intended to be construed to include all such changes, modifications, rearrangements, and various alternative equivalents that are within the true spirit and scope of the present disclosure.

Claims

1. A method of etching a feature in a stack, comprising: a) forming a metal or metalloid-containing mask above the stack; b) etching the stack through the metal or metalloid-containing mask; wherein, during the etching, the metal or metalloid in the metal or metalloid-containing mask is sputtered, and the sputtered metal or metalloid physically redeposits on sidewalls of the etched feature in the stack as a sputtered metal or metalloid-containing passivation layer.

2. The method of claim 1, wherein the etching of the stack comprises: supplying etching ions that do not contain metal and metalloid; accelerating the etching ions towards the stack; wherein the etching ions etch a feature in the stack and sputter metal or metalloid from the metal or metalloid-containing mask.

3. The method of claim 2, wherein the metal or metalloid-containing passivation layer provides metal or metalloid species.

4. The method of claim 3, wherein in addition to the sputtered metal or metalloid physically redepositing on sidewalls of the feature, the metal or metalloid species chemically deposit on sidewalls of the feature.

5. The method of claim 1, wherein the metal or metalloid is at least one of tungsten, molybdenum, ruthenium, tantalum, titanium, platinum, aluminum, and boron.

6. The method of claim 1, wherein the stack is a silicon-containing stack.

7. The method of claim 1, wherein the stack is a silicon oxide-containing stack.

8. The method of claim 1, wherein the stack is a plurality of alternating layers, and at least one of the alternating layers is a silicon oxide-containing layer.

9. The method of claim 1, further comprising removing the sputtered metal or metalloid-containing passivation layer. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​

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