Semiconductor device having on-chip gate resistance

Abstract

The power semiconductor device comprises a gate pad, a gate bus, and a gate resistor electrically interposed between the gate pad and the gate bus and including a semiconductor material region of a wide bandgap.

Description

Technical Field

[0001] Cross - Reference to Related Applications This application claims the benefit of U.S. Patent Application No. 17 / 847,410, filed on June 23, 2022, the entire content of which is incorporated herein by reference.

[0002] The present invention relates to semiconductor devices, and more particularly, to power semiconductor devices having gate resistance.

Background Art

[0003] A wide variety of power semiconductor devices are known in the art, including, for example, junction field effect transistors (JFETs), metal - oxide - semiconductor field - effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), and various other devices. These power semiconductor devices are often fabricated from wide - bandgap semiconductor materials such as silicon carbide - based or gallium nitride - based materials. As used herein, the term "wide - bandgap semiconductor" encompasses any semiconductor having a bandgap of at least 1.4 eV. Power semiconductor devices are designed to selectively block or pass large voltages and / or currents. For example, in the blocking state, a power semiconductor device can be designed to withstand potentials of hundreds or thousands of volts.

[0004] Many power semiconductor devices have a gate structure. The gate structure can include, for example, a gate bond pad, a gate pad, a plurality of gate fingers in the active region of the device, and one or more gate buses extending between the gate pad and the gate fingers. The gate-controlled power semiconductor device can be turned on and off by applying various bias voltages to its gate structure. The gate structure has a distributed gate resistance that is a function of the electrical path length from the gate bond pad (or other gate terminal) of each individual unit cell to the gate fingers, the length of the gate fingers, and the sheet resistance of the material forming the gate structure. In many applications, it may be desirable to increase the magnitude of the gate resistance, for example, by adding one or more discrete gate resistors or "lumped" gate resistors into the gate structure.

[0005] A power JFET is typically a normally-on device, meaning that the JFET conducts current when a voltage of 0 volts is applied to the gate structure. To turn off the JFET (i.e., to stop conduction of the JFET), a non-zero voltage (above some threshold level) is applied to the gate structure. The power JFET can be used in combination with a normally-off MOSFET (e.g., a low-voltage silicon MOSFET) to form an integrated switch that is normally off. For example, the JFET and the MOSFET can be in a cascode configuration to form such a switch. When the power JFET is used within an integrated switch that is normally off, it may be desirable to increase the gate resistance, because the increased gate resistance can reduce voltage overshoot during switching transients by attenuating the gate-source loop of the JFET and can improve the behavior of the device in the avalanche breakdown state. When the power JFET is cascode-connected to a normally-off MOSFET for use as a circuit breaker, the device remains in the on state (conducting state) until a fault condition is sensed and is turned off when isolating the circuit. Thus, in this application, the importance of switching losses can be reduced because the device switches only under fault conditions and not during normal operation. However, reducing the turn-off time can be important because it can reduce the drain current and voltage overshoot during switching. SUMMARY OF THE INVENTION

[0006] According to some embodiments of the present invention, there is provided a semiconductor device comprising a gate pad, a gate bus, and a gate resistance electrically interposed between the gate pad and the gate bus and comprising a semiconductor material region of a wide-bandgap.

[0007] In some embodiments, the gate resistor has a first conductivity type and is a first portion of the semiconductor layer structure, the semiconductor layer structure further comprising a second portion having a second conductivity type, the gate pad comprising a metal gate pad, the gate bus comprising a metal gate bus, and the gate resistor electrically connecting the metal gate pad to the metal gate bus.

[0008] In some embodiments, the wide bandgap semiconductor material region further comprises a first portion having a first conductivity type between the metal gate pad and the second portion of the semiconductor layer structure, and a second portion having a first conductivity type between the metal gate bus and the second portion of the semiconductor layer structure.

[0009] In some embodiments, the metal gate pad comprises a first metal silicide region, the metal gate bus comprises a second metal silicide region, the first and second metal silicide regions are in contact with the first and second portions of the wide bandgap semiconductor material region respectively, the gate resistor comprises a third portion of the wide bandgap semiconductor material region between the first and second portions of the wide bandgap semiconductor material region, and the upper surface of the gate resistor is free of metal silicide.

[0010] In some embodiments, the first metal silicide region extends along the boundary of the lower surface of the metal gate pad, defines an outer portion of the lower surface of the metal gate pad, and further comprises an inner portion where the lower surface of the metal gate pad abuts against the first metal silicide region, and is free of metal silicide.

[0011] In some embodiments, the semiconductor device further comprises a gate pad insulating pattern between the inner portion of the metal gate pad and the semiconductor layer structure.

[0012] In some embodiments, each of the first and second metal silicide regions contains nickel silicide.

[0013] In some embodiments, the wide bandgap semiconductor material region contains silicon carbide.

[0014] In some embodiments, a wide-bandgap semiconductor material region is part of a semiconductor layer structure, and the semiconductor layer structure further includes an active area including a plurality of junction field effect transistors (JFETs).

[0015] In some embodiments, a semiconductor device is cascode-connected to a metal oxide semiconductor field effect transistor (MOSFET) to form a circuit breaker.

[0016] In some embodiments, an upper portion of the active area of the semiconductor layer structure includes a plurality of gate trenches, and a plurality of JFETs each include a plurality of metal gate contacts within the plurality of gate trenches.

[0017] In some embodiments, the wide-bandgap semiconductor material region is a first wide-bandgap semiconductor material region having a first conductivity type, the semiconductor layer structure further includes a plurality of second wide-bandgap semiconductor material regions having the first conductivity type, the plurality of JFETs further include a plurality of gate electrodes, each of the plurality of gate electrodes includes one of the plurality of second wide-bandgap semiconductor material regions, and contacts a lower surface of one of the plurality of metal gate contacts.

[0018] In some embodiments, the semiconductor device further includes a source contact on the semiconductor layer structure and a plurality of gate insulating patterns, and each of the plurality of gate insulating patterns separates one of the plurality of metal gate contacts from the source contact.

[0019] In some embodiments, the wide-bandgap semiconductor material region has a sheet resistance in the range of about 14000 ohm / sq to about 22000 ohm / sq. For example, the wide-bandgap semiconductor material region has a sheet resistance of about 18000 ohm / sq.

[0020] In some embodiments, the gate resistance has a gate resistance in the range of from about 5 ohms to about 50 ohms. For example, the gate resistance has a gate resistance of about 18 ohms.

[0021] According to some embodiments of the present invention, there is provided a semiconductor device including a semiconductor layer structure including an active area including a plurality of junction field effect transistors (JFETs), a metal gate pad on the semiconductor layer structure, and a metal gate bus on the semiconductor layer structure and electrically connected to the plurality of JFETs. The semiconductor layer structure further includes a gate resistance electrically inserted between the metal gate pad and the metal gate bus.

[0022] In some embodiments, the gate resistance includes a semiconductor material region of a wide bandgap.

[0023] In some embodiments, the semiconductor material region of the wide bandgap is a first semiconductor material region of a wide bandgap having a first conductivity type, the semiconductor layer structure further includes a plurality of second semiconductor material regions of a wide bandgap having the first conductivity type, the plurality of JFETs each include a plurality of metal gate contacts and a plurality of gate electrodes, each of the plurality of gate electrodes includes one of the plurality of second semiconductor material regions of a wide bandgap, and contacts a lower surface of one of the plurality of metal gate contacts.

[0024] In some embodiments, the plurality of JFETs each include a plurality of metal gate contacts. The semiconductor device further includes a source contact on the semiconductor layer structure and a plurality of gate insulating patterns, each of the plurality of gate insulating patterns separating one of the plurality of metal gate contacts from the source contact.

[0025] In some embodiments, a semiconductor device is cascode-connected to a metal-oxide-semiconductor field-effect transistor (MOSFET) to form a circuit breaker.

[0026] In some embodiments, it has a gate resistance within a range from about 5 ohms to about 50 ohms. For example, it has a gate resistance of about 18 ohms.

[0027] In some embodiments, the gate resistance includes a wide-bandgap semiconductor material region having a first conductivity type and being a first part of a semiconductor layer structure, the semiconductor layer structure further includes a second part having a second conductivity type, and the wide-bandgap semiconductor material region further includes a first part between a metal gate pad and the second part of the semiconductor layer structure and a second part between a metal gate bus and the second part of the semiconductor layer structure.

[0028] In some embodiments, the metal gate pad includes a first metal silicide region, the metal gate bus includes a second metal silicide region, the first and second metal silicide regions respectively contact the first and second parts of the wide-bandgap semiconductor material region, the gate resistance includes a third part of the wide-bandgap semiconductor material region between the first and second parts of the wide-bandgap semiconductor material region, and an upper surface of the third part of the wide-bandgap semiconductor material region lacks a metal silicide.

[0029] In some embodiments, the first metal silicide region extends along a boundary of a lower surface of the metal gate pad, defines an outer part of the lower surface of the metal gate pad, and the lower surface of the metal gate pad further includes an inner part that abuts against the first metal silicide region and lacks a metal silicide.

[0030] In some embodiments, the semiconductor device further includes a gate pad insulating pattern between an inner part of the lower surface of the metal gate pad and the semiconductor layer structure.

[0031] In some embodiments, each of the first and second metal silicide regions includes nickel silicide.

[0032] In some embodiments, the gate resistance includes silicon carbide.

[0033] In some embodiments, the gate resistance comprises a wide-bandgap semiconductor region having a sheet resistance in the range of from about 14,000 ohms / sq to about 22,000 ohms / sq. For example, the gate resistance comprises a wide-bandgap semiconductor region having a sheet resistance of about 18,000 ohms / sq.

[0034] According to an additional embodiment of the present invention, a method of forming a semiconductor device is provided. The method includes providing a temporary semiconductor layer structure comprising a wide-bandgap semiconductor material, the temporary semiconductor layer structure comprising a source region, a drift region, and a channel region within an upper portion of the semiconductor layer structure, the source region, the drift region, and the channel region; forming trenches within the source region and the channel region; forming a wide-bandgap semiconductor material region having a first conductivity type within the channel region, the wide-bandgap semiconductor material region defining a lower surface of the trench, the first conductivity type being different from a second conductivity type of the channel region; forming a metal gate pad and a metal gate bus within the trench, the metal gate pad and the metal gate bus being spaced apart from each other and contacting a first portion and a second portion of the wide-bandgap semiconductor material region, respectively; and forming an insulating pattern contacting a third portion of the wide-bandgap semiconductor material region, the third portion of the wide-bandgap semiconductor material region being between the first portion and the second portion of the wide-bandgap semiconductor material region.

[0035] In some embodiments, forming the metal gate pad and the metal gate bus comprises forming a metal contact layer over a wide bandgap semiconductor material region and removing a portion of the metal contact layer for the purpose of exposing a third portion of the wide bandgap semiconductor material region, thereby removing a portion of the metal contact layer that forms the metal gate pad and the metal gate bus.

[0036] In some embodiments, the method further comprises performing an annealing process after removing a portion of the metal contact layer, thereby forming a first silicide region of the metal gate pad and a second metal silicide region of the metal gate bus.

[0037] In some embodiments, the metal gate pad is the lower portion of the metal gate pad, and the method further comprises forming an upper portion of the metal gate pad over the lower portion of the metal gate pad.

[0038] In some embodiments, forming the metal gate pad and the metal gate bus comprises forming a gate pad insulating pattern in an inner portion of the upper surface of a wide bandgap semiconductor material region, forming a metal contact layer over the wide bandgap semiconductor material region and over the gate pad insulating pattern, wherein the metal contact layer contacts an outer portion of the upper surface of the wide bandgap semiconductor material region, and removing a portion of the metal contact layer until the wide bandgap semiconductor material region is exposed, thereby removing a portion of the metal contact layer that forms the metal gate pad and the metal gate bus. The gate pad insulating pattern is provided within the metal gate pad.

[0039] In some embodiments, the method further comprises performing an annealing process after removing a portion of the metal contact layer, thereby forming a first silicide region of the metal gate pad and a second metal silicide region of the metal gate bus.

[0040] In some embodiments, the trench is a first trench, the wide-bandgap semiconductor material region is a first wide-bandgap semiconductor material region, and the method includes forming a plurality of gate trenches in the source region and the channel region while forming the first trench, and forming a plurality of second wide-bandgap semiconductor material regions having a first conductivity type in the channel region while forming the first wide-bandgap semiconductor material region, wherein each of the plurality of second wide-bandgap semiconductor material regions defines a lower surface of one of the plurality of gate trenches, forming the plurality of second wide-bandgap semiconductor material regions, and forming a plurality of metal gate contacts in the plurality of gate trenches, respectively. Each of the plurality of second wide-bandgap semiconductor material regions contacts one of the plurality of metal gate contacts.

[0041] In some embodiments, the method further includes forming a plurality of gate insulation patterns on the plurality of gate metal contacts, respectively, and forming a source contact on the plurality of gate insulation patterns.

[0042] According to some embodiments of the present invention, a semiconductor device is provided that includes a semiconductor layer structure having an active area including a plurality of junction field effect transistors (JFETs), and a metal gate pad on the semiconductor layer structure. The metal gate pad has a lower surface facing the semiconductor layer structure, and the metal gate pad includes a metal silicide region that extends at least partially along a boundary of the lower surface of the metal gate pad to define an outer portion of the lower surface of the metal gate pad, and the lower surface of the metal gate pad further includes an inner portion that abuts the metal silicide region and lacks metal silicide.

[0043] In some embodiments, the semiconductor device further includes a gate pad insulation pattern between the inner portion of the lower surface of the metal gate pad and the semiconductor layer structure.

[0044] In some embodiments, the gate pad insulating pattern contacts the semiconductor layer structure.

[0045] In some embodiments, the metal gate pad extends on the sidewall of the gate pad insulating pattern.

[0046] In some embodiments, the metal silicide region contacts the semiconductor layer structure.

[0047] In some embodiments, the semiconductor device further includes a metal gate bus on the semiconductor layer structure and electrically connected to a plurality of JFETs. The semiconductor layer structure further includes a gate resistor electrically interposed between the metal gate pad and the metal gate bus.

[0048] In some embodiments, the gate resistor includes a wide bandgap semiconductor material region.

[0049] According to some embodiments of the present invention, there is provided a semiconductor device including a semiconductor layer structure having an active area including a plurality of junction field effect transistors (JFETs), a metal gate pad on the semiconductor layer structure, and a gate pad insulating pattern within the metal gate pad.

[0050] In some embodiments, the gate pad insulating pattern contacts the semiconductor layer structure.

[0051] In some embodiments, the gate pad insulating pattern contacts an inner portion of the upper surface of the semiconductor layer structure, and the metal gate pad contacts an outer portion of the upper surface of the semiconductor layer structure.

[0052] In some embodiments, the metal gate pad extends on the sidewall of the gate pad insulating pattern.

[0053] In some embodiments, the semiconductor device further comprises a metal gate bus on the semiconductor layer structure and electrically connected to a plurality of JFETs. The semiconductor layer structure further comprises a gate resistor electrically inserted between the metal gate pad and the metal gate bus.

[0054] In some embodiments, the gate resistor comprises a wide-bandgap semiconductor material region.

[0055] According to some embodiments of the present invention, there is provided a semiconductor device comprising a semiconductor layer structure comprising a wide-bandgap semiconductor material region, a metal gate bus on the semiconductor layer structure, a field-effect transistor comprising a metal gate contact on the semiconductor layer structure, and an inter-gate resistor electrically inserted between the metal gate bus and the metal gate contact and including a portion of the wide-bandgap semiconductor material region.

[0056] In some embodiments, the wide-bandgap semiconductor material region has a first conductivity type and is a first portion of the semiconductor layer structure, the semiconductor layer structure further comprising a second portion having a second conductivity type, and the wide-bandgap semiconductor material region further comprising a gate bus portion between the metal gate bus and the second portion of the semiconductor layer structure and a gate contact portion between the metal gate contact and the second portion of the semiconductor layer structure.

[0057] In some embodiments, the metal gate bus comprises a first metal silicide region, the metal gate contact comprises a second metal silicide region, the first and second metal silicide regions contact the gate bus portion and the gate contact portion of the wide-bandgap semiconductor material region, respectively, a portion of the wide-bandgap semiconductor material region is between the gate bus portion and the gate contact portion of the wide-bandgap semiconductor material region, and the upper surface of the portion of the wide-bandgap semiconductor material region is free of metal silicide.

[0058] In some embodiments, each of the first and second metal silicide regions includes nickel silicide.

[0059] In some embodiments, the wide-bandgap semiconductor material region includes silicon carbide.

[0060] In some embodiments, the field effect transistor is a junction field effect transistor.

[0061] In some embodiments, the semiconductor device further includes a source contact on the semiconductor layer structure, and a gate insulating pattern separates the metal gate contact from the source contact.

[0062] In some embodiments, the semiconductor device further includes a metal gate pad on the semiconductor layer structure, and a gate resistor electrically inserted between the metal gate pad and the metal gate bus.

[0063] In some embodiments, the inter-gate resistor includes a first portion of the wide-bandgap semiconductor material region, and the gate resistor includes a second portion of the wide-bandgap semiconductor material region.

[0064] In some embodiments, the wide-bandgap semiconductor material region has a sheet resistance in the range of about 14,000 ohms / sq to about 22,000 ohms / sq. For example, the wide-bandgap semiconductor material region has a sheet resistance of about 18,000 ohms / sq.

[0065] In some embodiments, the wide-bandgap semiconductor material region is one of a plurality of wide-bandgap semiconductor material regions, the field-effect transistor is one of a plurality of field-effect transistors each having a plurality of metal gate contacts, the plurality of metal gate contacts are respectively on the plurality of wide-bandgap semiconductor material regions, the inter-gate resistance is one of a plurality of inter-gate resistances, each of the plurality of inter-gate resistances is a part of one of the plurality of wide-bandgap semiconductor material regions, and is electrically inserted between the metal gate bus and one of the plurality of metal gate contacts.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0067] As described above, many power semiconductor devices, such as JFETs, can include one or more lumped gate resistors designed to increase the gate resistance to a desired value. These lumped gate resistors can also improve the electromagnetic interference (EMI) performance of the device. Conventionally, lumped gate resistors are implemented by routing the current path for the gate signal through a higher resistance material such as a semiconductor layer (the reason being that semiconductor materials have a higher sheet resistance compared to the metals used to form the metal gate and potentially other parts of the gate structure such as metal gate buses). Lumped gate resistors are often implemented on the customer motherboard along the gate signal transmission path to a separate semiconductor chip installed on the customer motherboard. However, for the reason of reducing the number of components, it may be desirable to incorporate the lumped gate resistor into the semiconductor chip. Further, if this on-chip gate resistance is lumped and "seen" equally across the chip, it may not cause an imbalance among the various components of the chip.

[0068] According to some embodiments of the present invention, a semiconductor device (e.g., a power JFET device) can include an "on-chip" lumped gate resistor. Specifically, the lumped gate resistor can be provided between the gate pad and the gate bus of the device. Further, according to some embodiments of the present invention, the lumped gate resistor can be formed using the sheet resistor of an implantation region (e.g., P++ region) already included in a conventional power JFET device. Thus, the lumped gate resistor according to some embodiments of the present invention can add a marginal overhead area to the chip and can be formed by a process already existing for a conventional power JFET device.

[0069] FIG. 1 is a schematic plan view of a power semiconductor device 1000 from which a plurality of its elements (e.g., source contacts 50 and gate insulation patterns 39B and 39C of FIGS. 2A and 2B) are excluded. FIGS. 2A and 2B are schematic cross-sectional views along lines A-A and B-B of FIG. 1, respectively.

[0070] Referring to FIGS. 1-2B, the power semiconductor device 1000 includes a semiconductor layer structure 5 (FIG. 2B), a metal gate pad 38P, a metal gate bus 38B, and a metal gate contact 38C, and the metal gate pad 38P, the metal gate bus 38B, and the metal gate contact 38C are provided on the semiconductor layer structure 5. The metal gate pad 38P and the metal gate bus 38B can be spaced apart from each other, and the power semiconductor device 1000 can further include a concentrated gate resistor 32R electrically inserted between the metal gate pad 38P and the metal gate bus 38B. The gate resistor 32R can have a gate resistance in the range of about 5 ohms to about 50 ohms (e.g., from about 15.5 ohms to about 20.5 ohms) in the exemplary embodiment. For example, the gate resistor 32R can have a gate resistance of about 18 ohms. However, it will be appreciated that the gate resistance value can be adjusted based on the application.

[0071] The semiconductor layer structure 5 can include a substrate 10, a drift region 20, a channel region 30, a source region 40, a wide-bandgap semiconductor material region 32, and gate electrode regions 36B and 36E. The substrate 10 can be formed of a wide-bandgap semiconductor material (e.g., can be a silicon carbide substrate) and can be highly doped with an n-type (n+) dopant in the exemplary embodiment. The drift region 20 can be provided on the upper surface of the substrate 10. The drift region 20 can be formed of a wide-bandgap semiconductor material (e.g., can be an epitaxially grown silicon carbide layer) and can be an n-type (n-) region doped at a low concentration. For example, the drift region 20 can be a low-concentration n-type (n-) silicon carbide drift region. The drift region 20 is, for example, 1×10 14 to 5×1016 Dopants / cm 3 can have a doping concentration of. The drift region 20 can be a thick region having a vertical height above the substrate 10 that is, for example, 3 to 100 microns. Although not shown in FIGS. 2A and 2B, in some embodiments, the upper portion of the drift region 20 may be doped at a higher concentration compared to its lower portion in order to provide a current spreading layer within the upper portion of the drift region 20 (e.g., 1×10 16 to 1×10 17 Dopants / cm 3 doping concentration).

[0072] The channel region 30 can be provided on the upper surface of the drift region 20. The channel region 30 can be formed of a wide-bandgap semiconductor material (e.g., silicon carbide) and can be an n-type (n) region. For example, the channel region 30 can be an n-type silicon carbide channel region. The channel region 30 can have a higher doping concentration than the drift region 20, for example, 1×10 16 to 1×10 17 Dopants / cm 3 doping concentration.

[0073] The source region 40 can be provided on the upper surface of the channel region 30. The source region 40 can be formed of a wide-bandgap semiconductor material (e.g., silicon carbide) and can be a highly doped n-type (n+) region. For example, the source region 40 can be a highly doped n-type (n+) silicon carbide source region 40. The source region 40 can have a higher doping concentration than the channel region 30, for example, 1×10 19 to 5×10 20 Dopants / cm 3 doping concentration.

[0074] The wide-bandgap semiconductor material region 32 can be provided within the channel region 30. The wide-bandgap semiconductor material region 32 can be formed of a wide-bandgap semiconductor material (e.g., silicon carbide) and can be a highly doped p-type (p++) region. For example, the wide-bandgap semiconductor material region 32 can be a wide-bandgap semiconductor material region 32 of highly doped p-type (p++) silicon carbide. The wide-bandgap semiconductor material region 32 can have a doping concentration of, for example, 1×10 19 to 5×10 20 dopants / cm 3 .

[0075] The gate electrode regions 36E and 36B can be provided within the channel region 30 and can contact the wide-bandgap semiconductor material region 32. The gate electrode regions 36E and 36B can be formed of a wide-bandgap semiconductor material (e.g., silicon carbide) and can be a highly doped p-type (p+) region. For example, the gate electrode regions 36E and 36B can be highly doped p-type (p+) silicon carbide gate electrode regions 36E and 36B. The gate electrode regions 36E and 36B can have a doping concentration lower than that of the wide-bandgap semiconductor material region 32, and can have a doping concentration of, for example, 1×10 17 to 5×10 20 dopants / cm 3 .

[0076] In some embodiments, the drift region 20, the channel region 30, the source region 40, the wide-bandgap semiconductor material region 32, and the gate electrode region 36 can be formed by, for example, performing an epitaxial growth process using the substrate 10 as a seed layer and further performing an ion implantation process.

[0077] In an exemplary embodiment, the wide bandgap semiconductor material region 32 can have a sheet resistance in the range of from about 14,000 ohms / sq to about 22,000 ohms / sq. A single wide bandgap semiconductor material region 32 can include a gate pad portion 32P, a gate bus portion 32B, a gate contact portion 32C, and a gate resistor 32R, as shown in FIG. 2A.

[0078] The gate pad portion 32P can be present between the channel region 30 and the metal gate pad 38P and can contact both the channel region 30 and the metal gate pad 38P. The gate bus portion 32B can be present between the channel region 30 and the metal gate bus 38B and can contact both the channel region 30 and the metal gate bus 38B. The gate contact portion 32C can be present between the channel region 30 and the metal gate contact 38C and can contact both the channel region 30 and the metal gate contact 38C.

[0079] The metal gate pad 38P and the gate pad portion 32P can together form a gate pad, and the metal gate bus 38B and the gate bus portion 32B can together form a gate bus. The metal gate contact 38C, the gate contact portion 32C, and the electrode region 36E can together form the gate of the unit cell JFET. Because the drift region 20, the channel region 30, and the source region 40 have the same conductivity type (e.g., n-type), the JFET is normally on and is turned off when a sufficient negative gate bias is applied to its gate.

[0080] The power semiconductor device 1000 can include a plurality of unit cell JFETs provided in the active area of the semiconductor layer structure 5. The upper portion of the semiconductor layer structure 5 can include a first trench 31F and a second trench 31S. A metal gate pad 38P and a metal gate bus 38B can be provided in the first trench 31F, respectively, and a metal gate contact 38C can be provided in the second trench 31S.

[0081] The metal gate pad 38P can include a first metal silicide region 35P and a metal pad region 37P sequentially stacked on the gate pad portion 32P. The metal gate bus 38B can include a second metal silicide region 35B and a metal bus region 37B sequentially stacked on the gate bus portion 32B. The upper surface of the gate pad portion 32P can contact the first metal silicide region 35P, and the upper surface of the gate bus portion 32B can contact the second metal silicide region 35B. The metal gate contact 38C can include a third metal silicide region 35C and a metal contact region 37C sequentially stacked on the gate contact portion 32C. The upper surface of the gate contact portion 32C can contact the third metal silicide region 35C.

[0082] The gate pad portion 32P and the first metal silicide region 35P, the gate bus portion 32B and the second metal silicide region 35B, and the gate contact portion 32C and the third metal silicide region 35C can form low-resistance resistive contacts having a sheet resistance between 2 ohm / sq and 5 ohm / sq.

[0083] The first silicide region 35P, the second silicide region 35B, and the third silicide region 35C can be formed of a metal silicide (e.g., silicon carbide, tungsten silicide, titanium silicide, or molybdenum silicide). In some embodiments, the first silicide region 35P, the second silicide region 35B, and the third silicide region 35C can be formed of nickel silicide. The metal pad region 37P, the metal bus region 37B, and the metal contact region 37C can be formed of a metal (e.g., aluminum, tungsten, nickel, titanium, ruthenium, and / or an alloy thereof).

[0084] The gate resistor 32R can be electrically inserted between a gate pad and a gate bus (e.g., between the metal gate pad 38P and the metal gate bus 38B), and current flowing between the gate pad and the gate bus can flow through the gate resistor 32R. The upper surface of the gate resistor 32R can be free of a silicide region.

[0085] The power semiconductor device 1000 can further include gate insulating patterns 39B and 39C. The gate insulating patterns 39B and 39C can be provided on the metal gate bus 38B and the metal gate contact 38C, respectively. Each of the gate insulating patterns 39B and 39C can include one or more dielectric materials such as, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0086] The source contact 50 can be provided on the source region 40 and the gate insulating patterns 39B and 39C. The source contact 50 can include one or more layers such as, for example, a diffusion barrier layer and a bulk metal layer. The gate insulating patterns 39B and 39C can isolate the metal gate bus 39B and the metal gate contact 38C from the source contact 50.

[0087] The insulating pattern 42 can be provided between the metal gate pad 38P and the source contact 50 on the gate resistor 32R. In some embodiments, the insulating pattern 42 can contact the upper surface of the gate resistor 32R. The insulating pattern 42 can include a plurality of layers stacked in sequence on the gate resistor 32R. In some embodiments, the insulating pattern 42 can include a dielectric layer (e.g., a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer, a magnesium oxide layer, and / or a silicon oxynitride layer) and a protective layer (e.g., a polyimide layer).

[0088] The drain pad 60 can be provided on the bottom side of the power semiconductor device 1000. The drain pad 60 can be connected to a lower submount such as a lead frame, a heat sink, or a power substrate through soldering, brazing, or direct compression, etc.

[0089] FIG. 3 is a schematic plan view of a power semiconductor device 2000 from which a plurality of elements (e.g., the source contact 50 and the gate insulating patterns 39B and 39C in FIGS. 4A and 4B) are excluded. FIGS. 4A and 4B are schematic cross-sectional views taken along lines C-C and D-D of FIG. 3, respectively.

[0090] As can be seen, the power semiconductor device 2000 can be very similar to the power semiconductor device 1000, with the main difference being that the gate pad insulating pattern 41 can be provided within the metal gate pad 38P. The gate pad insulating pattern 41 can be provided between an inner portion of the lower surface of the metal gate pad 38P and an inner portion of the upper surface of the gate pad portion 32P of the wide bandgap semiconductor material region 32. The gate pad insulating pattern 41 can contact the inner portion of the lower surface of the metal gate pad 38P and the inner portion of the upper surface of the gate pad 32P. The metal gate pad 38P can extend over the sidewalls of the gate pad insulating pattern 41. In some embodiments, the metal gate pad 38P can surround the sidewalls of the gate pad insulating pattern 41 and can contact the sidewalls of the gate pad insulating pattern 41.

[0091] The first metal silicide region 35P can extend along the boundary of the lower surface of the metal gate pad 38P and can define the outer portion of the lower surface of the metal gate pad 38P. The inner portion of the lower surface of the metal gate pad 38P can be free of metal silicide. The first metal silicide region 35P can contact the outer portion of the upper surface of the gate pad portion 32P.

[0092] FIG. 5 is a flow chart showing a method of fabricating a power semiconductor device 2000 according to some embodiments of the present invention. FIGS. 6A, 7A, 8A, 9A, 10A, 11A, and 12A are cross-sectional views taken along line C-C of FIG. 3, and FIGS. 6B, 7B, 8B, 9B, 10B, 11B, and 12B are cross-sectional views taken along line D-D of FIG. 3 showing a method of fabricating a power semiconductor device 2000 according to some embodiments of the present invention.

[0093] Referring to FIGS. 5, 6A, and 6B, the method can include providing a temporary semiconductor layer structure 5p (block 110). The temporary semiconductor layer structure 5p can include a substrate 10, a drift region 20, a channel region 30, and a source region 40. The drift region 20, the channel region 30, and the source region 40 can be formed, for example, by performing an epitaxial growth process using the substrate 10 as a seed layer and further performing an ion implantation process.

[0094] Referring to FIGS. 5, 7A, and 7B, the method can further include forming a first trench 31F and a second trench 31S in the temporary semiconductor layer structure 5p (block 120). The first trench 31F and the second trench 31S can be formed by etching the temporary semiconductor layer 5p. The first trench 31F and the second trench 31S can extend through the source region 40 and can be formed within the channel region 30. The channel region 30 can define the lower surfaces of the first trench 31F and the second trench 31S.

[0095] Referring to FIGS. 5, 8A, and 8B, a wide-bandgap semiconductor region 32 and gate electrode regions 36B and 36E can be formed within the channel region 30 (block 130). In some embodiments, the wide-bandgap semiconductor region 32 can be formed by implanting impurities into the channel region 30 through the bottom surfaces of the first trench 31F and the second trench 31S, and the gate electrode regions 36B and 36E can be formed by implanting impurities into the channel region 30 through the side surfaces of the first trench 31F and the second trench 31S.

[0096] After the wide-bandgap semiconductor region 32 and the gate electrode regions 36B and 36E are formed, a gate pad insulating pattern 41 can be formed over the wide-bandgap semiconductor region 32 (block 140). The gate pad insulating pattern 41 can be formed over an inner portion of the upper surface of the gate pad portion 32P of the wide-bandgap semiconductor region 32 and may not cover an outer portion of the upper surface of the gate pad portion 32P. The gate pad insulating pattern 41 can contact the inner portion of the upper surface of the gate pad portion 32P.

[0097] Referring to FIG. 5, lower portions of a metal gate pad 38P, a metal gate bus 38B, and a metal gate contact 38C can be formed over the wide-bandgap semiconductor region 32 (block 150). In some embodiments, the lower portions of the metal gate pad 38P, the metal gate bus 38B, and the metal gate contact 38C can be formed by the processes shown in FIGS. 9A, 9B, 10A, and 10B.

[0098] Referring to FIGS. 9A and 9B, forming the lower portions of the metal gate pad 38P, the metal gate bus 38B, and the metal gate contact 38C can include forming a metal contact layer and a metal layer on the wide-bandgap semiconductor region 32 and on the gate pad insulating pattern 41, and then removing a portion of the metal contact layer to form the metal contact patterns 33P, 33B, and 33C, and removing a portion of the metal layer to form the metal regions 37L, 37B, and 37C. The metal contact layer can be a metal layer (e.g., a nickel layer, a tungsten layer, a titanium layer, or a molybdenum layer). The metal region 37L can be the lower portion of the metal pad region (e.g., the metal pad region 37P in FIG. 4A).

[0099] A portion of the metal contact layer and a portion of the metal layer formed on the upper surface of the resistor 32R can be removed, thereby exposing the upper surface of the resistor 32R. Thus, there may be no metal silicide formed on the upper surface of the resistor R through the subsequent annealing process, and the upper surface of the resistor 32R can be free of metal silicide.

[0100] Referring to FIGS. 10A and 10B, an annealing process can be performed to convert the metal contact patterns 33P, 33B, and 33C into a first metal silicide region 35P, a second metal silicide region 35B, and a third metal silicide region 35C.

[0101] In some embodiments, the gate pad insulating pattern 41 can be excluded, and as shown in FIGS. 2A and 2B, the first metal silicide region 35P can be formed over the entire lower surface of the metal pad region 37P and can contact the entire upper surface of the gate pad portion 32P.

[0102] Referring to FIGS. 5, 11A, and 11B, gate insulation patterns 39B and 39C can be respectively formed on metal gate buses 38B and metal gate contacts 38C (block 160). Each of the gate insulation patterns 39B can be formed in a first trench 31F, and the gate insulation pattern 39C can be formed in a second trench 31S. In some embodiments, a portion of the metal contact pattern 33P and a portion of the metal region 37L formed on the gate pad insulation pattern 41 can be removed, thereby exposing the upper surface of the gate pad insulation pattern 41.

[0103] Referring to FIGS. 5, 12A, and 12B, a source contact 50 and an insulation pattern 42 can be formed (block 170). The source contact 50 can be formed on the gate insulation patterns 39B and 39C. In some embodiments, during the formation of the source contact 50, an upper portion 37U of the metal pad region 37P can be formed on the gate pad insulation pattern 41. The insulation pattern 42 can be formed between the metal pad region 37P and the source contact 50.

[0104] FIG. 13 is a schematic cross-sectional view of a portion of a power semiconductor device 3000 along the gate length direction according to some embodiments of the present invention. Referring to FIG. 13, the power semiconductor device 3000 can include an inter-gate resistor 32IR electrically inserted between a gate path and a gate (for example, between a metal gate bus 38B and a metal gate contact 38C). The upper surface of the inter-gate resistor 32IR can be free of a silicide region. The metal gate bus 38B and the metal gate contact 38C, which have a lower resistance than the resistance of the wide-bandgap semiconductor material region 32, are spaced apart from each other, so that the current flowing between the gate bus and the gate can be forced to flow through the inter-gate resistor 32IR.

[0105] The power semiconductor device 3000 includes a plurality of metal gate contacts 38C and a plurality of inter-gate resistors 32IR. Each of the inter-gate resistors 32IR is electrically inserted between a gate bus and one of the metal gate contacts 38C of the plurality of metal gate contacts 38C. In some embodiments, all of the metal gate contacts 38C of the device are electrically connected to the metal gate bus 38B through respective inter-gate resistors 32IR. In other embodiments, a group of the metal gate contacts 38C contacts the metal gate bus 38B and is electrically connected to the metal gate bus 38B without using an inter-gate resistor therebetween.

[0106] The inter-gate resistor 32IR can be formed by a process similar to the process described with reference to FIGS. 9A through 10B. A metal contact layer and a metal layer can be formed over the gate contact portion 32C, the gate bus portion 32B, and the inter-gate resistor 32IR, and then a portion of the metal contact layer and a portion of the metal layer formed over the inter-gate resistor 32IR can be removed, thereby exposing the upper surface of the inter-gate resistor 32IR. Thereafter, an annealing process can be performed to convert a portion of the metal contact layer into a second metal silicide region 35B and a third metal silicide region 35C spaced apart from each other. Because a portion of the metal contact layer formed over the inter-gate resistor 32IR is removed before performing the annealing process, metal silicide may not be formed over the inter-gate resistor 32IR during the annealing process, and the upper surface of the inter-gate resistor 32IR can be free of metal silicide.

[0107] FIG. 14 is a circuit diagram of a circuit breaker including a power JFET cascode-connected to a MOSFET. The MOSFET can be a normally-off MOSFET. It may be desirable to increase the gate resistance of the power JFET to reduce and mitigate the effects of high voltage spikes, including electromagnetic interference (EMI), crosstalk, and potential device damage. The gate resistance (gate resistance 32R in FIG. 2) according to some embodiments of the present invention can increase the gate resistance of the power JFET.

[0108] As discussed above, the gate resistance according to some embodiments of the present invention can be integrated around the gate pad, so that the avalanche current can bypass the gate resistance and can flow only under the gate pad in an avalanche condition. Thus, the avalanche current may not bias the gate voltage as much as in the case of an external gate resistance, thereby reducing the tendency for the channel to turn on.

[0109] In some embodiments, the gate pad can include a narrow silicide region along the outer portion of the gate pad. As a result, the inner portion of the gate pad corresponding to most of the gate pad area can be free of the silicide region, as discussed with reference to FIGS. 3, 4A, and 4B. In these embodiments, the avalanche current spanning most of the gate pad area can flow through a non-silicided wide-bandgap semiconductor material region (e.g., gate pad region 32P in FIG. 4A) having the same sheet resistance as the gate resistance before reaching the metal gate pad, thus reducing the degree of shunting of the avalanche current from the active area to the gate pad. Thus, the avalanche capability can be improved.

[0110] The semiconductor device discussed above is an n-type device, but it should be recognized that in a p-type device these positions are reversed. Further, although the power semiconductor device described above and the other devices described herein are shown as silicon carbide-based semiconductor devices, it should be recognized that embodiments of the present invention are not limited thereto. Rather, the semiconductor device can include any wide-bandgap semiconductor suitable for use in a power semiconductor device, including, for example, gallium nitride-based semiconductor devices, gallium nitride-based semiconductor devices, and II-VI compound semiconductors.

[0111] The present invention has been described above with reference to the accompanying drawings that illustrate embodiments of the invention. However, the invention can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. When an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, the element or layer can be directly on, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, no intervening elements or layers are present. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Unless otherwise specified, like reference numerals throughout indicate like elements.

[0112] In this specification, the terms "first" and "second" are used to describe various regions, layers, and / or elements, but it should be understood that these regions, layers, and / or elements should not be limited by these terms. These terms are merely used to distinguish one region, layer, or element from another region, layer, or element. Thus, without departing from the scope of the present invention, the first region, layer, or element discussed later may also be referred to as the second region, layer, or element, and similarly, the second region, layer, or element may also be referred to as the first region, layer, or element.

[0113] Relative terms such as "lower" or "bottom" and "upper" or "top" may be used in this specification to describe the relationship of one element to another as shown in the drawings. It should be understood that the relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the drawings. For example, if the device in the drawing is inverted, an element described as being on the "lower" side of another element will be oriented on the "upper" side of the other element. Thus, the exemplary term "lower side" can encompass both "lower side" and "upper side" orientations depending on the specific orientation of the figure. Similarly, if the device in one of these figures is inverted, an element described as being "below" or "under" another element will be oriented "above" the other element. Thus, the exemplary terms "below" or "under" can encompass both upward and downward orientations.

[0114] The technical terms used in this specification are for the sole purpose of describing specific embodiments and are not intended to limit the present invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. As used herein, the terms "comprising", "having", "including", and / or "containing" indicate the presence of the recited features, elements, and / or components, but do not preclude the presence or addition of one or more other features, elements, components, and / or groups thereof.

[0115] In this specification, embodiments of the present invention are described with reference to cross-sectional views which are schematic illustrations. Accordingly, for example, variations in the form of the shape from the illustrations as a result of manufacturing techniques and / or tolerances are also to be expected. Accordingly, embodiments of the present invention should not be construed as being limited only to the specific shapes of the regions shown herein, but also include, for example, variations in shape resulting from manufacturing. For example, an implantation region shown as rectangular will typically have a circular or curvilinear nature and / or will have a gradient of implantation concentration at its edges rather than a binary change from an implanted region to a non-implanted region. Accordingly, the regions shown in the figures are essentially schematic and their shapes are not intended to represent the actual shape of the regions of the device and are not intended to limit the scope of the present invention.

[0116] It will be understood that the embodiments disclosed herein may be combined. Accordingly, features depicted and / or described in connection with a first embodiment may equally be included in a second embodiment and vice versa.

[0117] The above embodiments have been described with reference to specific figures, but it will be understood that some embodiments of the present invention may also include additional and / or intervening layers, structures, or elements and / or that specific layers, structures, or elements may be deleted. Although some exemplary embodiments of the present invention have been described, those skilled in the art will readily recognize that many modifications are possible in the exemplary embodiments without substantially departing from the novel teachings and advantages of the present invention. Accordingly, all such modifications are intended to be included within the scope of the present invention as defined by the claims. Accordingly, the foregoing is illustrative of the present invention and should not be construed as being limited only to the specific embodiments disclosed, and further, modifications to the disclosed embodiments as well as other embodiments are intended to be included within the scope of the appended claims. The present invention is defined by the following claims and equivalents of the claims are also included in the present invention.

Claims

1. A gate pad, a gate bus, a gate resistor electrically inserted between the gate pad and the gate bus and comprising a semiconductor material region of a wide bandgap, and a semiconductor device comprising the same.

2. The gate resistor has a first conductivity type and is a first part of a semiconductor layer structure, and the semiconductor layer structure further comprises a second part having a second conductivity type, the gate pad comprises a metal gate pad, the gate bus comprises a metal gate bus, the gate resistor electrically connects the metal gate pad to the metal gate bus, The semiconductor device according to claim 1.

3. The semiconductor material region of the wide bandgap further comprises a first part having the first conductivity type between the metal gate pad and the second part of the semiconductor layer structure, and a second part having the first conductivity type between the metal gate bus and the second part of the semiconductor layer structure. The semiconductor device according to claim 2.

4. The metal gate pad comprises a first metal silicide region, the metal gate bus comprises a second metal silicide region, and the first and second metal silicide regions are in contact with the first and second parts of the semiconductor material region of the wide bandgap respectively, the gate resistor comprises a third part of the semiconductor material region of the wide bandgap between the first and second parts of the semiconductor material region of the wide bandgap, and an upper surface of the gate resistor lacks a metal silicide. The semiconductor device according to claim 3.

5. The first metal silicide region extends along a boundary of a lower surface of the metal gate pad and defines an outer part of the lower surface of the metal gate pad, The semiconductor device according to claim 4, further comprising an inner part of the lower surface of the metal gate pad that abuts against the first metal silicide region and lacks a metal silicide.

6. The semiconductor device according to claim 5, further comprising a gate pad insulating pattern between the inner part of the metal gate pad and the semiconductor layer structure.

7. The semiconductor device according to claim 4, wherein each of the first and second metal silicide regions contains nickel silicide.

8. The semiconductor device according to any one of claims 1 to 7, wherein the wide bandgap semiconductor material region contains silicon carbide.

9. The wide bandgap semiconductor material region is part of a semiconductor layer structure, The semiconductor device according to any one of claims 1 to 8, wherein the semiconductor layer structure further includes an active area including a plurality of junction field effect transistors (JFETs).

10. The semiconductor device according to claim 9, wherein the semiconductor device is cascode-connected to a metal-oxide-semiconductor field-effect transistor (MOSFET) to form a circuit breaker.

11. The semiconductor device according to claim 9, wherein an upper portion of the active area of the semiconductor layer structure includes a plurality of gate trenches, and the plurality of junction field effect transistors (JFETs) each include a plurality of metal gate contacts in the plurality of gate trenches.

12. The wide bandgap semiconductor material region is a first wide bandgap semiconductor material region having a first conductivity type, and the semiconductor layer structure further includes a plurality of second wide bandgap semiconductor material regions having the first conductivity type, The semiconductor device according to claim 11, wherein the plurality of junction field effect transistors (JFETs) further include a plurality of gate electrodes, each of the plurality of gate electrodes includes one of the plurality of second wide bandgap semiconductor material regions, and contacts a lower surface of one of the plurality of metal gate contacts.

13. A source contact on the semiconductor layer structure, A plurality of gate insulating patterns, each of the plurality of gate insulating patterns separating one of the plurality of metal gate contacts from the source contact, The semiconductor device according to claim 11, further comprising.

14. The semiconductor device according to any one of claims 1 to 13, wherein the wide bandgap semiconductor material region has a sheet resistance in the range of about 14,000 ohms / sq to about 22,000 ohms / Sq.

15. The semiconductor device according to any one of claims 1 to 14, wherein the wide bandgap semiconductor material region has a sheet resistance of about 18,000 ohms / sq.

16. The semiconductor device according to any one of claims 1 to 15, having a gate resistance in the range of about 5 ohms to about 50 ohms.

17. The semiconductor device according to any one of claims 1 to 16, having a gate resistance of about 18 ohms.

18. A semiconductor layer structure comprising an active area having a plurality of junction field effect transistors (JFETs), a metal gate pad on the semiconductor layer structure, a metal gate bus on the semiconductor layer structure and electrically connected to the plurality of junction field effect transistors (JFETs), comprising, the semiconductor layer structure further comprising a gate resistance electrically inserted between the metal gate pad and the metal gate bus. Semiconductor device.

19. The semiconductor device according to claim 18, wherein the gate resistance comprises a wide bandgap semiconductor material region.

20. The wide bandgap semiconductor material region is a first wide bandgap semiconductor material region having a first conductivity type, and the semiconductor layer structure further comprises a plurality of second wide bandgap semiconductor material regions having the first conductivity type, each of the plurality of junction field effect transistors (JFETs) comprises a plurality of metal gate contacts and a plurality of gate electrodes, and each of the plurality of gate electrodes comprises one of the plurality of second wide bandgap semiconductor material regions, and contacts the lower surface of one of the plurality of metal gate contacts. The semiconductor device according to claim 19.

21. Each of the plurality of junction field effect transistors (JFETs) comprises a plurality of metal gate contacts, The semiconductor device is, a source contact on the semiconductor layer structure, A plurality of gate insulation patterns, each of the plurality of gate insulation patterns separating one of the plurality of metal gate contacts from the source contact, the plurality of gate insulation patterns; further comprising; The semiconductor device according to any one of claims 18 to 20.

22. The semiconductor device according to any one of claims 18 to 21, wherein the semiconductor device is cascode-connected to a metal-oxide-semiconductor field-effect transistor (MOSFET) to form a circuit breaker.

23. The semiconductor device according to any one of claims 18 to 22, having a gate resistance within a range of about 5 ohms to about 50 ohms.

24. The semiconductor device according to any one of claims 18 to 23, having a gate resistance of about 18 ohms.

25. The gate resistance includes a wide-bandgap semiconductor material region having a first conductivity type, which is a first portion of the semiconductor layer structure, and the semiconductor layer structure further includes a second portion having a second conductivity type, The wide-bandgap semiconductor material region further includes a first portion between the metal gate pad and the second portion of the semiconductor layer structure, and a second portion between the metal gate bus and the second portion of the semiconductor layer structure. The semiconductor device according to claim 18.

26. The metal gate pad includes a first metal silicide region, the metal gate bus includes a second metal silicide region, and the first metal silicide region and the second metal silicide region are respectively in contact with the first and second portions of the wide-bandgap semiconductor material region, The gate resistance includes a third portion of the wide-bandgap semiconductor material region between the first portion and the second portion of the wide-bandgap semiconductor material region, and an upper surface of the third portion of the wide-bandgap semiconductor material region is free of metal silicide. The semiconductor device according to claim 25.

27. The first metal silicide region extends along a boundary of a lower surface of the metal gate pad and defines an outer portion of the lower surface of the metal gate pad, The semiconductor device according to claim 26, further comprising an inner portion of the lower surface of the metal gate pad that abuts the first metal silicide region, and lacking a metal silicide.

28. The semiconductor device according to claim 27, further comprising a gate pad insulating pattern between the inner portion of the lower surface of the metal gate pad and the semiconductor layer structure.

29. The semiconductor device according to any one of claims 26 to 28, wherein each of the first metal silicide region and the second metal silicide region contains nickel silicide.

30. The semiconductor device according to any one of claims 18 to 29, wherein the gate resistance contains silicon carbide.

31. The semiconductor device according to any one of claims 18 to 30, wherein the gate resistance comprises a wide bandgap semiconductor region having a sheet resistance within a range of about 14000 ohms / sq to about 22000 ohms / Sq.

32. The semiconductor device according to any one of claims 18 to 31, wherein the gate resistance comprises a wide bandgap semiconductor region having a sheet resistance of about 18000 ohms / sq.

33. A method of forming a semiconductor device, the method comprising: providing a temporary semiconductor layer structure comprising a wide bandgap semiconductor material, the temporary semiconductor layer structure comprising a source region, a drift region within an upper portion of the temporary semiconductor layer structure, and a channel region between the source region and the drift region; forming trenches in the source region and the channel region; forming a wide bandgap semiconductor material region having a first conductivity type within the channel region, the wide bandgap semiconductor material region defining a lower surface of the trench, the first conductivity type being different from a second conductivity type of the channel region. Forming a metal gate pad and a metal gate bus in the trench, wherein the metal gate pad and the metal gate bus are spaced apart from each other and contact a first portion and a second portion of the wide bandgap semiconductor material region, respectively, the step of forming a metal gate pad and a metal gate bus; Forming an insulating pattern contacting a third portion of the wide bandgap semiconductor material region, wherein the third portion of the wide bandgap semiconductor material region is between the first portion and the second portion of the wide bandgap semiconductor material region, the step of forming an insulating pattern, a method comprising.

34. The step of forming the metal gate pad and the metal gate bus is Forming a metal contact layer on the wide bandgap semiconductor material region; Removing a portion of the metal contact layer to expose the third portion of the wide bandgap semiconductor material region, thereby forming the metal gate pad and the metal gate bus, the step of removing a portion of the metal contact layer, the method according to claim 33.

35. Further comprising performing an annealing process after the step of removing the portion of the metal contact layer, thereby forming a first silicide region of the metal gate pad and a second metal silicide region of the metal gate bus, the method according to claim 34.

36. The method according to claim 35, wherein each of the first silicide region and the second silicide region contains nickel silicide.

37. The step of forming the metal gate pad and the metal gate bus is Forming a gate pad insulating pattern on an inner portion of an upper surface of the wide bandgap semiconductor material region; Forming a metal contact layer on the wide bandgap semiconductor material region and on the gate pad insulating pattern, wherein the metal contact layer contacts an outer portion of the upper surface of the wide bandgap semiconductor material region, the step of forming a metal contact layer; Removing a portion of the metal contact layer until the semiconductor material region of the wide bandgap is exposed, thereby forming the metal gate pad and the metal gate bus, removing a portion of the metal contact layer; comprising; The method according to any one of claims 33 to 36, wherein the gate pad insulating pattern is provided in the metal gate pad.

38. Further comprising performing an annealing process after the step of removing the portion of the metal contact layer, thereby forming a first silicide region of the metal gate pad and a second metal silicide region of the metal gate bus, the method according to claim 37.

39. The trench is a first trench, and the semiconductor material region of the wide bandgap is a first semiconductor material region of the wide bandgap, The method is, While forming the first trench, forming a plurality of gate trenches in the source region and the channel region; While forming a first semiconductor material region of the wide bandgap, forming a plurality of second semiconductor material regions of the wide bandgap having the first conductivity type in the channel region, each of the plurality of second semiconductor material regions of the wide bandgap defining a lower surface of one of the plurality of gate trenches, forming a plurality of second semiconductor material regions of the wide bandgap; Respectively forming a plurality of metal gate contacts in the plurality of gate trenches; comprising; The method according to any one of claims 33 to 38, wherein each of the plurality of second semiconductor material regions of the wide bandgap contacts one of the plurality of metal gate contacts.

40. Respectively forming a plurality of gate insulating patterns on the plurality of gate metal contacts; Forming a source contact on the plurality of gate insulating patterns; The method according to claim 39, further comprising.

41. A semiconductor layer structure comprising an active area including a plurality of junction field effect transistors (JFETs); A metal gate pad on the semiconductor layer structure; comprising; The metal gate pad has a lower surface facing the semiconductor layer structure. A semiconductor device, wherein the metal gate pad includes a metal silicide region that extends at least partially along a boundary of the lower surface of the metal gate pad to define an outer portion of the lower surface of the metal gate pad, the lower surface of the metal gate pad further includes an inner portion that abuts the metal silicide region, and lacks a metal silicide.

42. The semiconductor device according to claim 41, further comprising a gate pad insulating pattern between the inner portion of the lower surface of the metal gate pad and the semiconductor layer structure.

43. The semiconductor device according to claim 42, wherein the gate pad insulating pattern contacts the semiconductor layer structure.

44. The semiconductor device according to claim 42, wherein the metal gate pad extends on sidewalls of the gate pad insulating pattern.

45. The semiconductor device according to any one of claims 41 to 44, wherein the metal silicide region contacts the semiconductor layer structure.

46. Further comprising a metal gate bus on the semiconductor layer structure and electrically connected to the plurality of junction field effect transistors (JFETs), The semiconductor device according to any one of claims 41 to 45, wherein the semiconductor layer structure further comprises a gate resistor electrically inserted between the metal gate pad and the metal gate bus.

47. The semiconductor device according to claim 46, wherein the gate resistor comprises a wide bandgap semiconductor material region.

48. A semiconductor layer structure comprising an active area with a plurality of junction field effect transistors (JFETs), A metal gate pad on the semiconductor layer structure, A gate pad insulating pattern within the metal gate pad, A semiconductor device comprising the above.

49. The semiconductor device according to claim 48, wherein the gate pad insulating pattern contacts the semiconductor layer structure.

50. The semiconductor device according to claim 48 or 49, wherein the gate pad insulating pattern contacts an inner portion of the upper surface of the semiconductor layer structure, and the metal gate pad contacts an outer portion of the upper surface of the semiconductor layer structure.

51. The semiconductor device according to any one of claims 48 to 50, wherein the metal gate pad extends on sidewalls of the gate pad insulating pattern.

52. Further comprising a metal gate bus disposed on the semiconductor layer structure and electrically connected to the plurality of junction field effect transistors (JFETs). The semiconductor device according to any one of claims 48 to 51, wherein the semiconductor layer structure further comprises a gate resistor electrically inserted between the metal gate pad and the metal gate bus. **Claim 53** The semiconductor device according to claim 52, wherein the gate resistor comprises a wide bandgap semiconductor material region. **Claim 54** A semiconductor layer structure comprising a wide bandgap semiconductor material region; A metal gate bus disposed on the semiconductor layer structure; A field effect transistor comprising a metal gate contact disposed on the semiconductor layer structure; An intergate resistor including a portion of the wide bandgap semiconductor material region and electrically inserted between the metal gate bus and the metal gate contact; A semiconductor device comprising the above. **Claim 55** The wide bandgap semiconductor material region has a first conductivity type and is a first portion of the semiconductor layer structure, and the semiconductor layer structure further comprises a second portion having a second conductivity type. The semiconductor device according to claim 54, wherein the wide bandgap semiconductor material region further comprises a gate bus portion between the metal gate bus and the second portion of the semiconductor layer structure, and a gate contact portion between the metal gate contact and the second portion of the semiconductor layer structure. **Claim 56** The metal gate bus comprises a first metal silicide region, the metal gate contact comprises a second metal silicide region, and the first metal silicide region and the second metal silicide region are in contact with the gate bus portion and the gate contact portion of the wide bandgap semiconductor material region, respectively. The portion of the wide bandgap semiconductor material region is between the gate bus portion and the gate contact portion of the wide bandgap semiconductor material region, and the upper surface of the portion of the wide bandgap semiconductor material region is free of metal silicide. The semiconductor device according to claim 55. **Claim 57** The semiconductor device according to claim 56, wherein each of the first metal silicide region and the second metal silicide region contains nickel silicide. **Claim 58** The semiconductor device according to any one of claims 54 to 57, wherein the wide bandgap semiconductor material region contains silicon carbide.

59. The semiconductor device according to any one of claims 54 to 58, wherein the field effect transistor is a junction field effect transistor.

60. A source contact on the semiconductor layer structure, A gate insulating pattern that separates the metal gate contact from the source contact, The semiconductor device according to any one of claims 54 to 59, further comprising.

61. A metal gate pad on the semiconductor layer structure, A gate resistor electrically inserted between the metal gate pad and the metal gate bus, The semiconductor device according to any one of claims 54 to 60, further comprising.

62. The intergate resistance includes a first portion of the wide bandgap semiconductor material region, The semiconductor device according to claim 61, wherein the gate resistor includes a second portion of the wide bandgap semiconductor material region.

63. The semiconductor device according to any one of claims 54 to 62, wherein the wide bandgap semiconductor material region has a sheet resistance in the range of about 14000 ohms / sq to about 22000 ohms / Sq.

64. The semiconductor device according to any one of claims 54 to 63, wherein the wide bandgap semiconductor material region has a sheet resistance of about 18000 ohms / sq.

65. The wide bandgap semiconductor material region is one of a plurality of wide bandgap semiconductor material regions, The field effect transistor is one of a plurality of field effect transistors each having a plurality of metal gate contacts, and the plurality of metal gate contacts are respectively on the plurality of wide bandgap semiconductor material regions. The inter-gate resistor is one of a plurality of inter-gate resistors, each of the plurality of inter-gate resistors being a part of one of the plurality of wide-bandgap semiconductor material regions, and being electrically inserted between the metal gate bus and one of the plurality of metal gate contacts, the semiconductor device according to any one of claims 54 to 64.

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