Power semiconductor device and method for manufacturing a power semiconductor device

Abstract

The power semiconductor device (100) includes a semiconductor body (1) having an upper surface (10), a main electrode (2) on the upper surface, and a gate electrode (3) on the upper surface and disposed adjacent to the main electrode in a first lateral direction (L1). The semiconductor body includes a drift layer (11) of a first conductivity type, a base region (12) of a second conductivity type disposed between the drift layer and the upper surface in the longitudinal direction, and a contact region (13) of the first conductivity type disposed between the drift layer and the upper surface in the longitudinal direction. The contact region is adjacent to the base region and the upper surface. Further, the semiconductor body includes a drift region (14) of the first conductivity type disposed adjacent to the base region in the first lateral direction and adjacent to the base region. The main electrode is in electrical contact with the contact region. In a plan view of the upper surface, the gate electrode at least partially covers a channel portion (12a) of the base region located between the contact region and the drift region in the first lateral direction. On the upper surface, at least one of the contact region and the drift region protrudes beyond the base region in the longitudinal direction.

Description

Technical Field

[0001] The present disclosure relates to a power semiconductor device and a method for manufacturing a power semiconductor device.

Background Art

[0002] For example, there is a need for improved power semiconductor devices having good contact resistance and / or reduced parasitic capacitance. Further, there is a need for improved methods for manufacturing such power semiconductor devices.

Summary of the Invention

Means for Solving the Problems

[0003] Embodiments of the present disclosure relate to improved power semiconductor devices. Other embodiments relate to improved methods for manufacturing power semiconductor devices.

[0004] First, the power semiconductor device will be specified. The power semiconductor device is configured to process, for example, a current of at least 1 A and / or a voltage of at least 100 V. The power semiconductor device is, for example, a so-called vertical power semiconductor device.

[0005] According to one embodiment, a power semiconductor device includes a semiconductor body having an upper surface, a main electrode on the upper surface, and a gate electrode on the upper surface and disposed adjacent to the main electrode in a first lateral direction. The semiconductor body includes a drift layer of a first conductivity type, a base region of a second conductivity type disposed between the drift layer and the upper surface in a vertical direction, and a contact region of the first conductivity type disposed between the drift layer and the upper surface in a vertical direction. The contact region is adjacent to the base region and the upper surface. Further, the semiconductor body includes a drift region of the first conductivity type disposed adjacent to the base region in the first lateral direction and adjacent to the base region. The main electrode is in electrical contact with the contact region. In a plan view of the upper surface, the gate electrode at least partially covers a channel portion of the base region located between the contact region and the drift region in the first lateral direction. On the upper surface, at least one of the contact region and the drift region protrudes beyond the base region in a vertical direction.

[0006] Today, most commercially available power semiconductor devices are based on a cell design having a planar channel aligned with the upper surface of the semiconductor body. However, boosting the current density in such devices is hampered by the parasitic junction FET (parasitic JFET) under the gate electrode and the increasing contact resistance associated with downscaling. Further, the parasitic gate / drain capacitance Cgd, which is strongly related to the parasitic JFET, increases significantly with the reduction of the pitch dimension. Although the trench design originally promised to reduce or even eliminate the parasitic JFET, current trench power semiconductor devices still actually rely on the parasitic JFET.

[0007] The device concept proposed herein is based, among other things, on the idea of using a raised source and / or drift region. This can significantly reduce the contact resistance and eliminate the parasitic gate / drain capacitance Cgd. As a result, this brings about unparalleled switching performance and enables a significant reduction in chip size.

[0008] The semiconductor body is based on, for example, Si, SiC or GaN. The main electrode on the upper surface is, for example, a metal electrode. The gate electrode may be made of metal or may be made of highly doped polysilicon. The gate electrode is electrically insulated from the semiconductor body by an electrical insulating material such as, for example, SiO2. Thus, the power semiconductor device may be an insulated gate device. In particular, the gate electrode and the main electrode are electrically insulated from each other and can be set to different potentials for operation.

[0009] The gate electrode is arranged next to or adjacent to the main electrode in a first lateral direction. In this specification, the lateral direction is, for example, a direction parallel to the main extension plane of the semiconductor body. Thus, the longitudinal direction is defined as the direction perpendicular to the main extension plane of the semiconductor body.

[0010] The drift layer is of a first conductivity type. The first conductivity type can be either electron conduction or hole conduction. The second conductivity type is different from the first conductivity type, that is, either hole conduction or electron conduction. The electron-conductive region or layer is n-doped, and the hole-conductive region or layer is p-doped. For example, the doping concentration of the first drift layer is at least 10 8 cm -3 and at most 10 15 cm -3 is.

[0011] The base region is arranged in the longitudinal direction between the drift layer and the upper surface, that is, in the longitudinal direction between the upper surface and the drift layer. For example, the base region is adjacent to the drift layer and / or the upper surface. For example, the doping concentration in the base region is greater than the doping concentration in the drift layer, for example, at least 10 times or at least 100 times greater. For example, the doping concentration in the base region is at least 10 15 cm -3 and / or at most 10 18 cm -3 is.

[0012] In this specification, when comparing the doping concentrations of layers or regions, the average doping concentration or the maximum doping concentration of these layers or regions is compared. When defining the upper and lower limits of the doping concentration within a layer or region, this means that the maximum doping concentration within each layer / region does not exceed the upper limit and the minimum doping concentration within each layer / region does not fall below the lower limit. The regions referred to in this specification are, for example, each continuous region without holes or interruptions in particular.

[0013] The contact region has the same conductivity type as the drift region. For example, the doping concentration of the contact region is greater than the doping concentration of the drift layer and / or the base region, for example at least 10 times or at least 100 times greater. By way of example, the doping concentration within the contact region is at least 10 17 cm -3 or at least 10 18 cm -3 or at least 10 19 cm -3 .

[0014] The contact region is adjacent to the base region and the upper surface, i.e., forms part of the upper surface. The contact region may be adjacent to the base region in the longitudinal direction and / or the transverse direction, in particular the first transverse direction. For example, the contact region is partially or completely surrounded laterally by the base region. The contact region may be embedded in the base region.

[0015] The drift region has the same conductivity type as the contact region and the drift layer. For example, the doping concentration in the drift region is smaller than the doping concentration in the contact region, for example, at most one tenth or at most one hundredth. However, the doping concentration in the drift region may be greater than the doping concentration in the drift layer, for example, at least 10 times or at least 100 times greater. For example, the doping concentration within the drift region is at least 10 15 cm -3 and / or at most 10 18cm -3 It is. The drift region is also known as the JFET region.

[0016] The drift region is arranged adjacent to the base region in a first lateral direction and is adjacent to the base region in the first lateral direction. The drift region is separated from the contact region by a portion of the base region in the first lateral direction, and this portion is referred to herein as the "channel portion". The drift region and / or the channel portion may be adjacent to the upper surface of the semiconductor body, i.e., may form a part of the upper surface.

[0017] The main electrode is in electrical contact with the contact region, i.e., directly in electrical contact. The main electrode may be adjacent to the contact region on the upper surface. In this specification, electrical contact means, for example, an ohmic electrical contact.

[0018] The gate electrode is arranged adjacent to the lateral side of the main electrode and is aligned with the channel portion of the base region in a first lateral direction. Therefore, in a plan view of the upper surface, the gate electrode partially or completely covers each of the channel portions or overlaps the channel portions. The gate electrode may also overlap a part of the contact region and / or the drift region in this plan view. However, the gate electrode may be electrically insulated from the channel portion, the contact region, and the base region by an electrically insulating material.

[0019] The semiconductor body may include several drift regions, base regions, and corresponding contact regions. All features disclosed in relation to one drift region, one base region, and one contact region are also disclosed for all other drift regions, base regions, and contact regions. For example, in a first lateral direction, a drift region is arranged between each pair of base regions. Further, for each channel portion of the base region, a gate electrode overlapping the channel portion may be assigned in a plan view of the upper surface.

[0020] The channel portion is the portion where charge carriers flow from the contact region to the drift region during operation. For example, a power semiconductor device is configured to deplete the channel portion on the side facing the gate electrode with the help of the gate electrode, thereby enabling current to flow from the main electrode through the contact region, through the depleted channel portion, and into the drift region.

[0021] On the upper surface, at least one of the contact region and the drift region protrudes beyond the base region in the vertical direction. For example, the contact region and / or the drift region protrudes at least 50 nm or at least 100 nm beyond the base region, and / or up to 1 μm or up to 5 μm. In other words, the contact region and / or the drift region terminate such that their height with respect to the drift layer is greater than that of the base region. For example, both the contact region and the drift region protrude beyond the base region in the vertical direction on the upper surface. The protruding contact region and / or drift region may taper in the vertical direction away from the drift layer.

[0022] By raising the contact region, the contact resistance can be reduced. The raised drift region, for example, enables the reduction of Cgd.

[0023] According to a further embodiment, at least one of the contact region and the drift region is epitaxially grown. For example, both the contact region and the drift region are epitaxially grown. The contact region and / or the drift region may be grown on a base semiconductor body including a drift layer. The drift layer and / or the base region may be formed by doping implantation.

[0024] According to at least one embodiment, at least one epitaxially grown region, i.e., the contact region and / or the drift region, has, for example, an inverted doping profile over its entire volume, and the doping concentration decreases in the direction (along) from the inside of the semiconductor body towards the upper surface. Additionally or alternatively, at least one of the epitaxially grown regions has, for example, a uniform doping profile over its entire volume. It is possible for both regions to have an inverted doping profile or a uniform doping profile. It is also possible for the epitaxially grown contact region to have a uniform doping profile and the epitaxially grown drift region to have an inverted doping profile, or vice versa.

[0025] An epitaxially grown region having an inverted doping profile has, for example, a minimum doping concentration that is at least one order or at least two orders lower than the maximum doping concentration within said region. An epitaxially grown region having a uniform doping profile has, for example, a maximum deviation from the average doping concentration of up to 20% or up to 10%.

[0026] It is also possible for at least one of the epitaxially grown regions to have a doping profile in which the doping concentration decreases in the direction (along) from the upper surface of the semiconductor body towards the inside. The difference between the maximum doping concentration and the minimum doping concentration may be the same as in the case of the inverted doping profile.

[0027] By epitaxially growing the contact region and / or the drift region, not only can these regions be formed to protrude beyond the base region, but it is also possible to individually and independently set the doping concentration of these regions. Furthermore, the doping concentration of these regions can be set higher, for example, than when these regions are formed by implantation. Moreover, the doping concentration of these regions can be made very uniform over the entire volume of the region or have a special doping profile such as an inverted doping profile.

[0028] According to a further embodiment, on the upper surface, the drift region protrudes beyond the base region in the vertical direction. In a plan view of the upper surface, the gate electrode covers most of the drift region. For example, in a plan view of the upper surface, the gate electrode covers up to 50% or up to 25% of the drift region at most. As an example, the gate electrode does not cover the drift region at all and is, for example, separated from the drift region in a first lateral direction or terminates coplanar with the drift region in the first lateral direction.

[0029] The raised / protruding drift region enables the gate electrode to be formed such that it does not completely overlap the drift region. In this way, Cgc can be significantly reduced.

[0030] According to a further embodiment, the contact region and the channel portion are at least partially aligned in the vertical direction. For example, when viewed along a first lateral direction, the contact region and the channel portion at least partially overlap each other. For example, in this figure, the contact region and the channel portion completely overlap each other. The vertical alignment enables efficient injection of charge carriers from the contact region into the channel portion.

[0031] Starting from the top, the contact region may protrude deeper into the semiconductor body than the base region, or the base region may protrude deeper into the semiconductor body than the contact region. In the second case, a part of the base region may be arranged vertically between the contact region and the drift layer. In other words, the distance between the contact part and the back surface of the semiconductor body may be larger or smaller than the distance between the base region and the back surface. The back surface is the surface of the semiconductor body on the side opposite to the top surface.

[0032] According to a further embodiment, the doping concentration in the drift region is higher than the doping concentration in the drift layer, for example, at least 10 times or at least 100 times higher.

[0033] According to a further embodiment, in a plan view of the top surface, the gate electrode partially covers the contact region and / or the drift region. The gate electrode may have a first section that tapers towards the top surface, that is, a first lateral extension in the first lateral direction decreases in the direction towards the top surface. This first section may overlap the contact region and / or the drift region in the plan view. The tapering is, for example, a result of the manufacturing process.

[0034] The gate electrode may also have a second section that tapers away from the top surface. The first section may be arranged vertically between the top surface and the second section.

[0035] According to a further embodiment, the power semiconductor device is a MOSFET or an IGBT or a JFET or a MISFET or a thyristor.

[0036] According to a further embodiment, the semiconductor body is based on a wide-bandgap semiconductor such as SiC or GaN.

[0037] According to a further embodiment, the gate electrode is at least partially vertically aligned with at least one of the contact region and the drift region that protrudes beyond the base region. For example, when viewed along a first lateral direction, the gate electrode and the protruding contact region and / or the protruding drift region at least partially overlap each other.

[0038] Next, a method for manufacturing a power semiconductor device will be specified. This method may in particular be used to manufacture a power semiconductor device according to any of the embodiments described herein. Accordingly, all features disclosed for the power semiconductor device are also disclosed for the method, and vice versa.

[0039] According to one embodiment, the method comprises manufacturing a semiconductor body having an upper surface, the semiconductor body having a drift layer of a first conductivity type, a base region of a second conductivity type disposed vertically between the drift layer and the upper surface, a contact region of the first conductivity type disposed vertically between the drift layer and the upper surface and adjacent to the base region and the upper surface, and a drift region of the first conductivity type disposed adjacent to the base region in a first lateral direction and adjacent to the base region. In a further step, a main electrode is applied to the upper surface and an electrical contact is established between the main electrode and the contact region. In a further step, a gate electrode is manufactured such that at an end, the gate electrode is disposed on the upper surface and adjacent to the main electrode in a first lateral direction, and in a plan view of the upper surface, the gate electrode at least partially overlaps a channel portion of the base region that is between the contact region and the drift region in the first lateral direction. The semiconductor body is manufactured such that at least one of the contact region and the drift region protrudes beyond the base region in the vertical direction at the upper surface.

[0040] The gate electrode may be manufactured before or after applying the main electrode. Further, the gate electrode may be manufactured before or after forming the raised, i.e., protruding, contact region and / or drift region.

[0041] According to a further embodiment, manufacturing the semiconductor body includes providing a base semiconductor body having a drift layer and a base region. Prior thereto, the base region and / or the drift layer may be formed within the base semiconductor body by doping implantation. The base semiconductor body may be based on a wide bandgap semiconductor such as SiC or GaN.

[0042] According to a further embodiment, manufacturing the semiconductor body includes epitaxially growing at least one of a contact region and a drift region on the base semiconductor body.

[0043] According to at least one embodiment, the epitaxial growth is performed by chemical vapor deposition (CVD).

[0044] According to at least one embodiment, at least one of the following precursors is used for the epitaxial growth: monosilane, disilane, trisilane, chlorinated precursors such as DCS (Dichlorsilane), carbon precursors such as methane.

[0045] According to at least one embodiment, at least one of the following doping precursors is used for doping during the epitaxial growth: diborane or phosphine.

[0046] According to at least one embodiment, the doping profile of the epitaxially grown region is set by adjusting the mass flow rate of the doping precursor. For example, an inverted doping profile is created by reducing the mass flow rate of the doping precursor during the epitaxial growth.

[0047] According to a further embodiment, prior to growing the contact region, a portion of the base semiconductor is removed in the area where the contact region is to be formed. Then, the contact region is grown in that area.

[0048] For example, to define an area for the growth of the contact region, a hole is etched in the base semiconductor body. The depth of the hole, measured in the vertical direction, is, for example, at least 1 μm or at least 2 μm. For example, the hole is etched so as to completely penetrate the base region in the vertical direction. Alternatively, the hole may be etched to a depth that opens into the base region.

[0049] According to a further embodiment, before growing the drift region, a part of the base semiconductor body in the area where the drift region is to be formed is removed. Then, the drift region is grown in that area.

[0050] For example, to define an area for the growth of the drift region, a hole is etched in the base semiconductor body. The depth of the hole, measured in the vertical direction, is, for example, at least 1 μm or at least 2 μm.

[0051] According to a further embodiment, the gate electrode is formed on the base semiconductor body. For example, this is done after the formation of the base region and / or the drift layer. The gate electrode may be formed before at least one of the drift region and the contact region is manufactured, for example, by epitaxial growth.

[0052] To form the gate electrode, first, a gate electrode layer may be applied to the upper surface of the base semiconductor body. Thereby, the gate electrode layer may be electrically insulated from the upper surface by a layer of an electrically insulating material disposed between the gate electrode layer and the upper surface.

[0053] In a further step, the gate electrode layer and the underlying electrical insulation layer may be structured to form the gate electrode. Thereby, a part of the gate electrode layer and the underlying insulation layer may be removed, for example, by etching. A mask may be used for structuring the gate electrode layer and the electrical insulation layer.

[0054] According to a further embodiment, an electrical insulating material is applied at least to the side surfaces of the gate electrode. The side surfaces are the surfaces that define the gate electrode in the lateral direction, in particular in a first lateral direction. The side surfaces extend obliquely or perpendicularly to the main extension plane of the (base) semiconductor body.

[0055] The electrical insulating material may be deposited on the gate electrode by a non-directional or conformal deposition method, respectively.

[0056] According to a further embodiment, at least one of the contact region and the drift region is selectively grown adjacent to the gate electrode on which the insulating material is applied. That is, the gate electrode on which the insulating material is applied is used as a mask for the selective growth process. For example, the contact region is grown on one side of the gate electrode and the drift region is grown on the other side of the gate electrode, where "side" and "the other side" are meant with respect to the first lateral direction.

[0057] For example, when growing the contact region and / or the drift region, each region is grown adjacent to the electrical insulating material in the first lateral direction.

[0058] Hereinafter, with reference to the drawings, a power semiconductor device and a method for manufacturing a power semiconductor will be described in more detail based on exemplary embodiments. The accompanying drawings are included to provide a further understanding. In the drawings, elements having the same structure and / or function may sometimes be referred to with the same reference numerals. It should be understood that the embodiments shown in the drawings are exemplary representations and are not necessarily drawn to scale. The description of each of the following figures will not be repeated as long as the elements or components correspond to each other with respect to their functions in different figures. For clarity, elements may not be denoted with corresponding reference numerals in all figures.

Brief Description of the Drawings

[0059]

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DETAILED DESCRIPTION OF THE INVENTION

[0060] A first exemplary embodiment of the power semiconductor device 100 according to FIG. 1 includes a semiconductor body 1 based on a wide bandgap material such as, for example, 6H-SiC or 3C-SiC. The main electrodes 2 and the two gate electrodes 3 are disposed on the upper surface 10 of the semiconductor body 1.

[0061] The semiconductor body 1 includes a drift layer 11 of a first conductivity type. Hereinafter, the first conductivity type is respectively electron conduction or n-conduction. Therefore, the drift layer 11 is n-doped. The second conductivity type is respectively hole conduction or p-conduction, and therefore, the corresponding doping is p-type doping. However, the overall concept also functions when different regions or layers have opposite types of doping. For example, the doping concentration of the drift layer 11 is 10 8 cm -3 ~10 15 cm -3 in the range of.

[0062] On the bottom surface of the drift layer 11, a substrate 15 adjacent to the drift layer 11, that is, a SiC substrate 15, is disposed. The substrate 15 is also of the first conductivity type, that is, in this case, it is n-doped. For example, the doping concentration is in the same range as that of the drift layer 11. In the vertical direction V perpendicular to the main extension plane of the semiconductor body 1, the substrate 15 is disposed between the further main electrode 6 and the drift layer 11. The further main electrode 6 is adjacent to the substrate 15 and is in electrical contact with the substrate 15. For example, the further main electrode is made of metal.

[0063] The semiconductor body 1 includes two base regions 12 spaced apart from each other in a first lateral direction L1, and the first lateral direction L1 is parallel to the main extension plane of the semiconductor body 1. The semiconductor body 1 further includes a drift region 14 disposed between the two base regions 12 in the first lateral direction L1. The base regions 12 are of the second conductivity type, that is, p-doped, and the drift region 14 is of the first conductivity type, that is, n-doped. The base regions 12 are adjacent to the drift region 14 in the first lateral direction L1. The base regions 12 and the drift region 14 are disposed between the drift layer 11 and the upper surface 10 of the semiconductor body 1 in the vertical direction V. Thereby, the drift region 14 and the base regions 12 are adjacent to the drift layer 11 and the upper surface 10 in the vertical direction V.

[0064] As an example, each of the base regions 12 is 10 15 cm-3 ~10 18 cm -3 has a doping concentration within the range of.

[0065] The doping concentration of the drift region 14 may be greater than the doping concentration of the drift layer 11, for example, 10 15 cm -3 ~10 18 cm -3 and may be within the range of.

[0066] The semiconductor body 1 further includes two contact regions 13, and each contact region 13 is assigned to the base region 12. The contact regions 13 are of the first conductivity type and are adjacent to the base region 12 to which each is assigned and the upper surface 10 of the semiconductor body 1. In the exemplary embodiment of FIG. 1, the contact regions 13 are adjacent to the base region 12 assigned in the longitudinal direction V and the first lateral direction L1. The doping concentration of the first contact region 13 is, for example, at least 10 19 cm -3 in each case.

[0067] In the exemplary embodiment of FIG. 1, the contact regions 13 and the drift region 14 protrude beyond the base region 12 in the longitudinal direction V, for example, at least 1 μm in each case. Accordingly, the upper surface 10 is not flat but has a raised section due to the protruding regions. The contact regions 13 are in electrical contact with a main electrode 2 made of, for example, metal. The gate electrode 3 is disposed between the contact region 13 and the drift region 14 in the first lateral direction L1 in each case and is made of, for example, highly doped polysilicon. Each gate electrode 3 is assigned to the base region 12 and covers the channel portion 12a of each base region 12 in a plan view of the upper surface 10. However, in this plan view, the gate electrode 3 does not overlap with the drift region 14 protruding in the first lateral direction L1, that is, is not aligned with the drift region.

[0068] The gate electrode 3 is electrically insulated from the semiconductor body 1 by an electrically insulating material 5 which is, for example, SiO2. The electrically insulating material 5 covers the gate electrode 3 on the side facing the semiconductor body 1, on the side remote from the semiconductor body 1, and on the side faces extending obliquely with respect to the main extension plane of the semiconductor body 1. In a first lateral direction L1, the contact region 13 and the drift region 14 are adjacent to the insulating material 5 covering the side face of the gate electrode 3. This is possible because the raised contact region 13 and the raised drift region 14 are partially aligned with the gate electrode 3 in the longitudinal direction V.

[0069] As can be further seen in FIG. 1, the contact region 13 projects into the assigned base region 12 such that the channel portion 12a of the base region 12 is partially aligned with the contact region 13 in the longitudinal direction V. The drift region 14 projects deeper into the semiconductor body 1 than the base region 12, i.e., closer to the further main electrode 6 in the longitudinal direction V.

[0070] The power semiconductor device 100 of FIG. 1 is a vertical MOSFET. The path of the electrons during operation is indicated by the arrows. During operation and in the on state of the MOSFET, the channel portion 12a of the base region 12 is partially depleted with the aid of the gate electrode 3. Thereby, current, i.e., electrons, can flow from the main electrode 2 through the contact region 13 and the depleted portion of the channel portion 12a to the drift region 14 and from there through the drift layer 11 to the further main electrode 6. By the contact region 13 protruding beyond the base region 12, the contact resistance can be reduced. Since the protruding drift region 14 and the gate electrode 3 are not aligned laterally, the capacitance between the gate electrode 3 and the further main electrode 6 is kept small. Since the contact region 13 projects into the base region 12, electrons can be efficiently injected from the contact region 13 into the depleted portion of the channel portion 12a.

[0071] FIG. 2 shows a second exemplary embodiment of a power semiconductor device 100, which is also a vertical power MOSFET. In this case, only one base region 12, one contact region 13 and one gate electrode 3 are shown. However, also in this case, there may be several gate electrodes 3, as well as several base regions 12 and assigned contact regions 13.

[0072] As can be inferred from FIG. 2, the gate electrode 3 covers or overlaps the contact region 13 and the drift region 14, respectively, in the plan view of the upper surface 10. Further, the first section of the gate electrode 3 tapers in the direction towards the upper surface 10, and the second section tapers in the direction away from the upper surface 10. Therefore, in the cross-sectional view of FIG. 2, the gate electrode 3 is diamond-shaped. Such a structure can occur when the gate electrode 3 is formed after the contact region 13 and / or after the drift region 14.

[0073] FIG. 3 shows a third exemplary embodiment of the power semiconductor device 100, in which only the contact region 13 protrudes beyond the base region 12 on the upper surface 10. The gate electrode 3 completely overlaps the drift region 14 in the plan view of the upper surface 10.

[0074] FIG. 4 shows a fourth exemplary embodiment of the power semiconductor device 100. In contrast to the previous exemplary embodiments, the contact region 13 protrudes completely through the base region 12 and protrudes deeper into the semiconductor body 1 than the base region 12.

[0075] In all the exemplary embodiments of the power semiconductor device 100 shown so far, the contact region 13 and / or the drift region 14 protruding beyond the base region 12 may be epitaxially grown.

[0076] FIG. 5 shows a flowchart of an exemplary embodiment of a method for manufacturing a power semiconductor device. In step S1, a semiconductor body having an upper surface is manufactured, the semiconductor body including a drift layer of a first conductivity type, a base region of a second conductivity type that is vertically between the drift layer and the upper surface, a contact region of the first conductivity type that is vertically between the drift layer and the upper surface and is adjacent to the base region and the upper surface, and a drift region of the first conductivity type that is adjacent to the base region and is adjacent to the base region in a first lateral direction. In a further step S2, a main electrode is applied to the upper surface, and an electrical contact is established between the main electrode and the contact region. In a further step S3, the gate electrode is manufactured such that, at an end, the gate electrode is on the upper surface and adjacent to the main electrode in a first lateral direction, and in a plan view of the upper surface, the gate electrode at least partially overlaps a channel portion of the base region that is between the contact region and the drift region in the first lateral direction. In step S1, the semiconductor body is manufactured such that, on the upper surface, at least one of the contact region and the drift region projects vertically beyond the base region.

[0077] FIG. 6 shows a position in an exemplary embodiment of a method for manufacturing a power semiconductor device, for example, the power semiconductor device 100 of FIG. 1. At this position, a base semiconductor body 1' based on, for example, the same material system as the semiconductor body of FIG. 1 is provided. The base semiconductor body 1' includes a substrate 15, an n-doped drift layer 11, and a p-doped base region 12 adjacent to the upper surface of the base semiconductor body 1'. The drift layer 11 and / or the base region 12 may be formed by doping implantation. A mask may be used during implantation to manufacture the laterally spaced base regions 12.

[0078] At the next position shown in FIG. 7, a gate electrode layer 30 is applied to the upper surface of the base semiconductor body 1'. A layer of the electrical insulating material 5 is disposed between the base semiconductor body 1' and the gate electrode layer 30.

[0079] At the position of FIG. 8, the gate electrode layer 30 is structured such that individual gate electrodes 3 spaced apart from each other in the first lateral direction L1 are fabricated. The gate electrodes 3 are electrically insulated from the base semiconductor body 1' by an electrically insulating material 5 structured together with the gate electrode layer 30. For the structuring of the gate electrode layer 30 and the underlying electrically insulating material 5, an etching process using a mask may be used.

[0080] At the position of FIG. 9, the electrically insulating material 5 is applied onto the side surfaces of the gate electrodes 3, and these side surfaces extend obliquely with respect to the main extension plane of the base semiconductor body 1'. For depositing the electrically insulating material 5, a conformal or non - directed deposition method may be used. The electrically insulating material that may have been deposited on the upper surface of the semiconductor substrate 1' has been removed.

[0081] At the position of FIG. 10, holes are etched in the base semiconductor body 1', i.e., in the areas where the contact region and the drift region are to be fabricated. In the area where the contact region is to be fabricated, the etched holes do not completely protrude from the base region 12 but open into the base region 12. However, alternatively, the holes in these areas may be etched completely through the base region 12. In the area where the drift region is to be fabricated, the etched holes are deeper.

[0082] Figure 11 shows the positions where the contact region 13 and the drift region 14 are selectively epitaxially grown within a previously etched area. The growth is carried out such that the contact region 13 and the drift region 14 finally protrude beyond the base region 12 of the upper surface 10 in the vertical direction V. To grow the contact region 13 and the drift region 14, a gate electrode 3 having an electrically insulating material 5 on each side surface may be used as a mask for the selective growth process. The growth of the contact region 13 and the drift region 14 has the advantage that the doping concentrations of these regions can be adjusted independently and, for example, can be set to be higher than in an implantation process. Figure 11 shows the final positions in the manufacture of the semiconductor body 1.

[0083] Figure 12 shows the position where, for example, a main electrode 2 of metal is applied on the upper surface 10 of the semiconductor body 1 and an electrical connection of the main electrode 2 to the contact region 13 is established.

[0084] To complete the power semiconductor device, a further main electrode may be applied to the back surface of the semiconductor body 1 (see Figure 1).

[0085] The embodiments shown in the figures as described above represent exemplary embodiments of an improved power semiconductor device and an improved method for manufacturing a power semiconductor device, and thus they do not constitute a complete list of all embodiments by the improved power semiconductor device and method. The actual power semiconductor device and method may be different from the embodiments shown, for example, with respect to the arrangement, elements, and the order of method steps.

Description of Reference Signs

[0086] Reference Sign 1 Semiconductor body 1’ Base semiconductor body 2 Main electrode 3 Gate electrode 5 Electrically insulating material 6 Further main electrode 10 Upper surface 11 Drift layer 12 Base region 12a Channel portion 13 Contact region 14 Drift region 15 Substrate 30 Gate electrode layer 100 Power semiconductor device L1 First lateral direction V Vertical direction Si Method step.

Claims

1. A semiconductor body (1) having an upper surface (10), a main electrode (2) on the upper surface (10), a gate electrode (3) on the upper surface (10) and arranged adjacent to the main electrode (2) in a first lateral direction (L1), A power semiconductor device (100) comprising: wherein the semiconductor body (1) is - a drift layer (11) of a first conductivity type, - a base region (12) of a second conductivity type arranged between the drift layer (11) and the upper surface (10) in the longitudinal direction, - a contact region (13) of the first conductivity type arranged between the drift layer (11) and the upper surface (10) in the longitudinal direction and adjacent to the base region (12) and the upper surface (10), - a drift region (14) of the first conductivity type arranged adjacent to the base region (12) in the first lateral direction (L1) and adjacent to the base region (12), comprising, the main electrode (2) being in electrical contact with the contact region (13), in a plan view of the upper surface (10), the gate electrode (3) at least partially covering a channel portion (12a) of the base region (12) between the contact region (13) and the drift region (14) in the first lateral direction (L1), On the upper surface (10), at least one of the contact region (13) and the drift region (14) projects beyond the base region (12) in the longitudinal direction (V), a power semiconductor device (100).

2. At least one of the contact region (13) and the drift region (14) is epitaxially grown, The power semiconductor device (100) according to claim 1.

3. At least one of the epitaxially grown regions (13, 14) has a reverse doping profile in which the doping concentration decreases in a direction from the inside of the semiconductor body (1) towards the upper surface (10), or a uniform doping profile The power semiconductor device (100) according to claim 2.

4. On the upper surface (10), the drift region (14) projects beyond the base region (12) in the longitudinal direction (V), in a plan view of the upper surface (10), the gate electrode (3) covering at most a part of the drift region (14), The power semiconductor device (100) according to any one of the preceding claims.

5. The contact region (13) and the channel portion (12a) are at least partially aligned in the longitudinal direction (V). The power semiconductor device (100) according to any one of the preceding claims.

6. The drift region (14) has a higher doping concentration than the drift layer (11). The power semiconductor device (100) according to any one of the preceding claims.

7. In a plan view of the upper surface (10), the gate electrode (3) partially covers the contact region (13). The power semiconductor device (100) according to any one of the preceding claims.

8. It is a MOSFET or an IGBT or a MISFET. The power semiconductor device (100) according to any one of the preceding claims.

9. The semiconductor body (1) is based on a wide bandgap semiconductor. The power semiconductor device (100) according to any one of the preceding claims.

10. At least one of the contact region (13) and the drift region (14) that protrudes beyond the base region (12) and the gate electrode (3) are at least partially aligned in the longitudinal direction (V). The power semiconductor device (100) according to any one of the preceding claims.

11. Manufacturing a semiconductor body (1) having an upper surface (10), the semiconductor body (1) being - a drift layer (11) of a first conductivity type; - a base region (12) of a second conductivity type disposed between the drift layer (11) and the upper surface (10) in the longitudinal direction; - a contact region (13) of the first conductivity type disposed between the drift layer (11) and the upper surface (10) in the longitudinal direction and adjacent to the base region (12) and the upper surface (10); - a drift region (14) of the first conductivity type disposed adjacent to the base region (12) in a first lateral direction (L1) and adjacent to the base region (12); having; Applying the main electrode (2) onto the upper surface (10) and establishing electrical contact between the main electrode (2) and the contact region (13). At an end portion, the gate electrode (3) is arranged on the upper surface (10) in the first lateral direction (L1) and adjacent to the main electrode (2), and in a plan view of the upper surface (10), the gate electrode (3) overlaps at least a channel portion (12a) of the base region (12) between the contact region (13) and the drift region (14) in the first lateral direction (L1), manufacturing the gate electrode (3) Including, the semiconductor body (1) is manufactured on the upper surface (10) such that at least one of the contact region (13) and the drift region (14) protrudes beyond the base region (12) in the longitudinal direction (V), a method for manufacturing a power semiconductor device (100).

12. The manufacturing of the semiconductor body (1) Providing a base semiconductor body (1') having the drift layer (11) and the base region (12); Epitaxially growing at least one of the contact region (13) and the drift region (14) on the base semiconductor body (1'); The method according to claim 11, including.

13. The method according to claim 12, wherein the inverted doping profile of the epitaxially grown region (13, 14) is created by reducing the mass flow rate of the doping precursor during epitaxial growth.

14. Before growing the contact region (13), a part of the base semiconductor body (1') in the area where the contact region (13) is to be formed is removed, The contact region (13) is grown within that area, The method according to claim 12 or 13.

15. Before growing the drift region (14), a part of the base semiconductor body (1') in the area where the drift region (14) is to be formed is removed, The drift region (14) is grown within that area, The method according to any one of claims 12 to 14.

16. The gate electrode (3) is formed on the base semiconductor body (1'), An electrically insulating material (5) is applied at least to the side surface of the gate electrode (3), At least one of the contact region (13) and the drift region (14) is selectively grown adjacent to the gate electrode (3) to which the insulating material (5) is applied. The method according to any one of claims 12 to 15.

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