Resistance change type random access memory (RRAM) element that does not require a forming process

Abstract

The present disclosure relates to a method of manufacturing a resistive change type random access memory (RRAM) device that does not require a forming process. The method includes a step of manufacturing an RRAM cell and a step of annealing the RRAM cell. The RRAM cell includes a bottom electrode, an oxide switching layer including at least one transition metal oxide, an upper electrode, and an interface layer between the oxide switching layer and the upper electrode. In some embodiments, the at least one transition metal oxide includes at least one of HfO x and TaO y where x ≦ 2.0 and y ≦ 2.5. The interface layer includes at least one layer of Al2O3, MgO, Y2O3, and La2O3. The RRAM device that does not require a forming process can be switched to a plurality of resistance levels without a forming process. 【Representative drawing】FIG. 1A

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to resistive random access memory (RRAM) devices, and more specifically, to RRAM devices that do not require a forming process, and methods of manufacturing and operating the same.

Background Art

[0002] A resistive random access memory (RRAM) device is a two-terminal passive device having an adjustable and non-volatile resistance. The resistance of the RRAM device can be electrically switched between a high resistance state (HRS) and a low resistance state (LRS) by applying an appropriate programming signal to the RRAM device. The RRAM device can be used to form a crossbar array used to implement in-memory computing applications, non-volatile solid-state memories, image processing applications, neural networks, and the like.

Summary of the Invention

[0003] A simplified summary of one or more aspects of the present disclosure is presented below. This summary is not an extensive overview of the present disclosure. Nor is it intended to identify key features or essential elements of the present disclosure or to delineate the scope of particular embodiments of the present disclosure or the claims. Its purpose is to present some concepts of the present disclosure in a simplified form as a prelude to the more detailed description that follows.

[0004] According to one or more aspects of the present disclosure, a method of manufacturing a resistive random access memory (RRAM) device that does not require a forming process is provided. The method includes manufacturing an RRAM cell having a designed interface layer and annealing the RRAM cell.

[0005] In some embodiments, the manufacturing of the RRAM cell includes manufacturing an oxide switching layer containing at least one transition metal oxide on a bottom electrode, manufacturing an interface layer containing a material chemically more stable than at least one transition metal oxide on the oxide switching layer, and manufacturing a top electrode on the interface layer.

[0006] In some embodiments, the RRAM cell is annealed in a forming gas environment containing N2 and H2.

[0007] In some embodiments, the RRAM cell is annealed at an annealing temperature between about 350°C and 450°C.

[0008] In some embodiments, the method further includes manufacturing one or more interconnect layers on the RRAM cell, and the RRAM cell is annealed together with the one or more interconnect layers.

[0009] In some embodiments, the manufacturing of one or more interconnect layers includes manufacturing metal pads or metal vias of the one or more interconnect layers on the top electrode of the RRAM cell.

[0010] In some embodiments, the RRAM and one or more interconnect layers are annealed by multiple annealing processes. The RRAM cell and the one or more interconnect layers are annealed in forming gas at a temperature between about 350°C and 450°C in each of the multiple annealing processes.

[0011] In some embodiments, the thickness of the interface layer is determined based on the device size of the RRAM cell and the thermal budget related to annealing. The interface layer is configured to reduce diffusion and reaction between the top electrode and the oxide switching layer.

[0012] According to one or more aspects of the present disclosure, a resistive change random access memory (RRAM) device that does not require a forming process is provided. The RRAM device that does not require a forming process includes a bottom electrode, an oxide switching layer including at least one transition metal oxide, a top electrode, and an interface layer fabricated between the top electrode and the oxide switching layer. The interface layer includes a material that is more chemically stable than at least one transition metal oxide. The RRAM device that does not require a forming process is configured to be able to switch between multiple resistances without performing a forming process for generating a conductive filament in the oxide switching layer.

[0013] In some embodiments, the at least one transition metal oxide includes at least one of HfO x and TaO y where x ≦ 2.0 and y ≦ 2.5.

[0014] In some embodiments, the interface layer includes at least one layer of Al2O3, MgO, Y2O3, and La2O3.

[0015] In some embodiments, the thickness of the interface layer is between 0.2 nm and 1 nm.

[0016] In some embodiments, the thickness of the interface layer is greater than 1 nm.

[0017] In some embodiments, the initial resistance of the RRAM device that does not require a forming process is between 1 kΩ and 1 MΩ.

[0018] According to one or more aspects of the present disclosure, a method for operating a RRAM device that does not require a forming process is provided. This method includes performing a first read operation on a first RRAM device that is in an initial state and does not require a forming process to determine a first initial resistance of the first RRAM device, and performing a first reset operation on the first RRAM device that does not require a forming process to switch the first RRAM device from the first initial resistance to a first target resistance. The first target resistance is greater than the first initial resistance. The first read operation and the first reset operation are performed without pre-forming a conductive filament in the first RRAM device that does not require a forming process in the forming process.

[0019] In some embodiments, a first reset current passing through the first RRAM device that does not require a forming process during the first reset operation is not greater than 500 μA.

[0020] In some embodiments, the method for operating a RRAM device that does not require a forming process further includes performing a first set operation on the first RRAM device that does not require a forming process to switch the first RRAM device from the first target resistance to a second target resistance. In some embodiments, performing the first set operation includes applying a first set voltage to the first RRAM device that does not require a forming process, and the first set voltage is not greater than 1.0 V.

[0021] In some embodiments, performing the first reset operation on the first RRAM device that does not require a forming process includes applying a first reset voltage to the first RRAM device that does not require a forming process, and the first set voltage and the first reset voltage have opposite polarities.

[0022] In some embodiments, a method of operating a RRAM device that does not require a forming process further includes performing a second read operation on a second RRAM device that does not require a forming process to determine an initial resistance of the second RRAM device that does not require a forming process, and performing a second set operation on the second RRAM device that does not require a forming process to switch the second RRAM device that does not require a forming process from the second initial resistance to a third target resistance, where the third target resistance is smaller than the second initial resistance. The second read operation and the second set operation are performed without pre-forming a conductive filament in the second RRAM device that does not require a forming process in the forming process.

[0023] In some embodiments, a method of operating a RRAM device that does not require a forming process further includes applying a second reset voltage to a second RRAM device that does not require a forming process to switch the second RRAM device that does not require a forming process from the third target resistance to a fourth target resistance. In some embodiments, performing the second set operation on the second RRAM device that does not require a forming process includes applying a second set voltage to the second RRAM device that does not require a forming process, where the second reset voltage and the second set voltage have opposite polarities.

[0024] In some embodiments, a second reset current passing through a second RRAM device that does not require a forming process in response to the second reset voltage is not greater than 500 μA. The second reset voltage is not greater than 1.0 V.

Brief Description of the Drawings

[0025] The present disclosure will be more fully understood from the following detailed description of various embodiments of the present disclosure. However, the drawings are not intended to limit the present disclosure to specific embodiments, but are for explanation and understanding.

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[0026] Aspects of the present disclosure provide a resistive random access memory (RRAM) device that does not require a formation process, and a method for manufacturing and operating the RRAM device that does not require a formation process.

[0027] The RRAM device is a two-terminal passive device having a programmable resistance. The RRAM device may include a bottom electrode, a top electrode, and an oxide switching layer disposed between the bottom electrode and the top electrode. The bottom electrode may include a non-reactive metal such as platinum (Pt) or palladium (Pd). The top electrode may include a reactive metal such as tantalum (Ta) or titanium (Ti). The oxide switching layer is hafnium oxide (HfO x ) or tantalum oxide (TaOx It may contain transition metal oxides such as

[0028] Conventional RRAM devices act as insulators in their initial state (i.e., before receiving appropriate stimuli after fabrication). Conventional RRAM devices can transition to a conductive state through a forming process in which a high forming voltage (e.g., a voltage of 1.7 V) is applied to the conventional RRAM device. During the forming process, a conductive filament is formed in the conventional RRAM device. Thereafter, the RRAM device can switch between two resistance states, namely a high resistance state (HRS) and a low resistance state (LRS), in response to an appropriate programming signal (e.g., a voltage signal or a current signal). The switching event for programming the RRAM device from the HRS is called a set process. The switching event for programming the RRAM device from the LRS is called a reset process. In a crossbar array circuit including an RRAM array, the programming signal can be supplied to a specified RRAM device via a selector such as a transistor.

[0029] The forming process involves the initial decomposition of the metal oxide in the oxide switching layer. Thus, the formation of the initial conductive filament in the forming process is a rapid process and requires a high forming voltage (e.g., a voltage of 1.7 V). In some embodiments, to form an RRAM device with a thicker oxide switching layer, the forming voltage may be higher than 2V - 3V. Since it is difficult to control the dimensions of the filaments formed in the forming process, the forming process usually does not result in a desirable device resistance. Conventional RRAM devices may need to be adjusted in a subsequent reset process (also referred to as an "initial reset process") to achieve a desirable device resistance. A high reset current is required to break the conductive filament in the initial reset process. As a result, conventional RRAM devices operate at a high current (e.g., a current exceeding 1 mA), leading to high power consumption and requiring a relatively large transistor capable of supplying such a high operating current. The forming process is also time-consuming. For example, it may take several minutes to form a 256×256 RRAM array, making it a time-consuming process for forming a crossbar circuit including multiple 256×256 RRAM arrays. Furthermore, the formation of the initial filaments in the forming process and the breaking of the initial filaments in the initial reset process are rapid and can cause performance variations between devices.

[0030] Accordingly, the present disclosure provides RRAMs that do not require a forming process and methods of marking and operating them. Unlike conventional RRAMs that require a forming process to operate, the RRAM devices described herein are conductive in their initial state and do not require the formation of filaments to operate. The RRAM devices that do not require a forming process have a moderate to low resistance in their initial state that can be read to determine appropriate programming parameters for subsequent operations (e.g., set operation, reset operation, etc.).

[0031] In some embodiments, the RRAM device that does not require a forming process may include an RRAM cell including a bottom electrode, a top electrode, an oxide switching layer formed between the bottom electrode and the top electrode, and an interface layer formed between the oxide switching layer and the top electrode. The oxide switching layer may include one or more transition metal oxides such as hafnium oxide and tantalum oxide. The interface layer may include one or more layers of a metal oxide that is more chemically stable than a transition metal oxide such as aluminum oxide. The metal oxide of the interface layer does not react with the top electrode or the oxide switching layer. Thus, the interface layer may control the reaction and diffusion between the top electrode and the oxide switching layer. The interface layer may include one or more continuous or discontinuous layers of aluminum oxide.

[0032] The RRAM cell may be annealed to achieve an operation that does not require a forming process. For example, the RRAM cell may be annealed by one or more annealing processes, and each annealing process includes annealing the RRAM cell in a forming gas environment (e.g., a mixture of N2 and H2) at an annealing temperature of 350 to 450 °C for an appropriate time (e.g., 15 to 30 minutes). Annealing may promote the diffusion and reaction between the top electrode and the oxide switching layer, while the interface layer may reduce the diffusion and reaction between the top electrode and the oxide switching layer. The interface layer and the annealing conditions (e.g., temperature, annealing time, etc.) may be optimized in view of the device size (e.g., critical dimension) of the RRAM device to achieve a desired initial resistance of the RRAM device.

[0033] The resistance of a RRAM device that does not require a forming process may be programmed to multiple levels without a forming process. For example, in order to program a RRAM device that does not require a forming process to a target resistance, a read operation may be performed on the RRAM device that does not require a forming process to determine the initial resistance of the RRAM device that does not require a forming process. In some embodiments where the initial resistance is greater than the target resistance, the RRAM device that does not require a forming process may be programmed to the target resistance by applying a set voltage (e.g., a voltage of 0.6V) to the RRAM device that does not require a forming process without performing a forming process in advance. In some embodiments where the target resistance is greater than the initial resistance of the RRAM device that does not require a forming process, the RRAM device that does not require a forming process may be programmed to the target resistance by applying a reset voltage to the RRAM device that does not require a forming process. The reset current passing through the RRAM device may be lower than 200 μA. Reset is performed without performing either a forming process or an initial set process on the RRAM device in advance. The set voltage and the reset voltage may have opposite polarities (e.g., positive polarity and negative polarity). The RRAM device that does not require a forming process may be switched between a high resistance state and a low resistance state in response to an ultra-low set voltage (e.g., a voltage lower than 1V) and a reset current (e.g., a reset peak current lower than 200 μA).

[0034] Accordingly, the present disclosure provides a mechanism for manufacturing and operating a RRAM device that does not require a forming process. By balancing material factors (e.g., the thickness of the interface layer) and annealing factors (e.g., annealing conditions), the mechanism described herein provides a RRAM device that does not require a forming process with desirable characteristics such as low energy switching, low inter-device performance variation, ultra-low operating current and voltage, and a large I on / I off ratio, bipolar switching, multi-level analog resistance switching, etc. The RRAM device that does not require a forming process disclosed herein may enhance the scalability of the crossbar array of RRAM devices and enable high-density memory and / or computing applications with low power consumption.

[0035] FIG. 1A is a schematic diagram of an example 100 of a crossbar circuit according to some embodiments of the present disclosure. As shown, the crossbar circuit 100 may include a plurality of interconnected electrically conductive wires such as one or more row wires 111a, 111b, ..., 111i, ..., 111n and column wires 113a, 113b, ..., 113j, ..., 113m for an n-row m-column crossbar array. The crossbar circuit 100 may further include cross-point elements 120a, 120b, ..., 120z, etc. Each cross-point element may connect a row wire and a column wire. For example, the cross-point element 120ij may connect the row wire 111i and the column wire 113j. In some embodiments, the crossbar circuit 100 may further include a digital-to-analog converter (DAC, not shown), an analog-to-digital converter (ADC, not shown), a switch (not shown), and / or other suitable circuit components for implementing a crossbar-based device. The number of column wires 113a-m and row wires 111a-n may be the same or different.

[0036] The row wires 111 may include a first row wire 111a, a second row wire 111b, ..., 111i, ..., an nth row wire 111n. Each of the row wires 111a, ..., 111n may be and / or include a suitable electrically conductive material. In some embodiments, each of the row wires 111a-n may be a metal wire.

[0037] The column wires 113 may include a first column wire 113a, a second column wire 113b, ..., an mth column wire 113m. Each of the column wires 113a-m may be and / or include a suitable electrically conductive material. In some embodiments, each of the column wires 113a-m may be a metal wire.

[0038] Each cross-point element 120 may be, and / or may include, any suitable element having an adjustable resistance, such as a memristor, a phase change memory (PCM) element, a floating gate, a spintronics element, a resistive random access memory (RRAM), a static random access memory (SRAM), etc. In some embodiments, one or more cross-point elements 120 may include RRAM elements as described in connection with FIGS. 3-11.

[0039] The crossbar circuit 100 may perform parallel weighted voltage multiplication and current addition. For example, an input voltage signal may be applied to one or more rows (e.g., one or more selected rows) of the crossbar circuit 100. The input signal can flow through the cross-point elements of the rows of the crossbar circuit 100. The conductance of the cross-point element can be adjusted to a specific value (also referred to as "weight"). According to Ohm's law, the input voltage multiplies the cross-point conductance to generate a current from the cross-point element. According to Kirchhoff's law, the sum of the currents passing through the elements of each column generates a current as the output signal (e.g., the output of an ADC) that can be read from the column. According to Ohm's law and Kirchhoff's current law, the input-output relationship of the crossbar array can be expressed as I = VG. Here, I represents the output signal matrix as current, V represents the input signal matrix as voltage, and G represents the conductance matrix of the cross-point elements. Thus, the input signal is weighted by its conductance at each cross-point element according to Ohm's law. The weighted currents are output via each column wire and can be accumulated according to Kirchhoff's current law. This enables in-memory computing (IMC) by parallel multiplication and addition performed in the crossbar array.

[0040] Figure 1B is a schematic diagram of Example 1200 of a cross-point element according to some embodiments of the present disclosure. As shown, the cross-point element 1200 may connect bit lines (BL) 1211, selection lines (SEL) 1213, and word lines (WL) 1215. The bit lines 1211 and the word lines 1215 may be the column wires and row wires described in connection with Figure 1A, respectively.

[0041] The cross-point element 1200 may include an RRAM element 1201 and a transistor 1203. The transistor is a three-terminal element and may be labeled as a gate (G), a source (S), and a drain (D), respectively. The transistor 1203 may be connected in series to the RRAM element 1201. As shown in Figure 1B, the bottom electrode of the RRAM element 1201 may be connected to the drain of the transistor 1203. The top electrode of the RRAM element 1201 may be connected to the bit line 1211. The source of the transistor 1203 may be connected to the word line 1215. The gate of the transistor 1203 may be connected to the selection line 1213. The RRAM element 1201 may include one or more RRAM elements described in connection with Figures 2A - 5D below. The cross-point element 1200 may also be referred to as a 1-transistor 1-resistor (1T1R) configuration. The transistor 1203 functions as a selector and can function as a current controller that sets current compliance for the RRAM element 1201 during programming. The gate voltage of the transistor 1203 can set current compliance for the cross-point element 1200 during programming, thereby controlling the conductance and analog operation of the cross-point element 1200. For example, when the cross-point element 1200 is set from a high-resistance state to a low-resistance state, a set signal (e.g., a voltage signal, a current signal) may be supplied via the bit line (BL) 1211. While the word line (WL) 1215 is grounded, another voltage, also referred to as a selection voltage or a gate voltage, may be applied to the transistor gate via the selection line (SEL) to open the gate and set the current compliance. When the cross-point element 1200 is reset from the low-resistance state to the high-resistance state, a gate voltage can be applied to the gate of the transistor 1203 via the selection line 1213 to open the transistor gate. On the other hand, while the bit line 1211 is grounded, a reset signal can be sent to the RRAM element 1201 via the word line 1215.

[0042] FIGS. 2A, 2B, and 2C are schematic views showing cross-sectional views of conventional RRAM elements that require a forming process to operate. The RRAM elements 200a, 200b, and 200c may correspond to RRAM elements in an initial state, a low-resistance state, and a high-resistance state, respectively.

[0043] As shown in FIG. 2A, the RRAM element 200a may include a bottom electrode 210, an oxide switching layer 220, and a top electrode 230. The bottom electrode 210 may include a suitable material that is electrically conductive and non-reactive to oxide switching, such as Pt, Pd, etc. The oxide switching layer 220 may include one or more transition metal oxides of binary oxides, ternary oxides, and higher-order oxides such as TaO x , HfO x , TiO x , NbOx, ZrOx. In some embodiments, the chemical stability of the non-reactive material of the bottom electrode 210 may be higher than that of the transition metal oxide of the oxide switching layer 220. The top electrode 230 may include any suitable metal material that is electrically conductive and reactive to oxide switching. For example, the metal material of the top electrode 230 may include Ta, Hf, Ti, etc.

[0044] The RRAM device 200a has a high initial resistance (e.g., several gigaohms) and can be regarded as an insulator in its initial state. The initial resistance of the RRAM device 200a can be changed through a forming process, and the RRAM device 200a can be switched to a low-resistance state. For example, a forming voltage can be applied to the RRAM device 200a. Applying a voltage to the RRAM device 200a can cause the metal material of the upper electrode to absorb oxygen from the oxide switching layer 220 and generate oxygen vacancies in the oxide switching layer 220. As a result, a conductive path (e.g., a filament) rich in oxygen vacancies can be formed in the oxide switching layer 220. For example, as shown in FIG. 2B, a conductive filament 225a can be formed in the oxide switching layer 220. As shown in the figure, the conductive filament 225a can be formed from the upper electrode 230 to the bottom electrode 210 through the oxide switching layer 220. The RRAM device 200b can be reset to a high-resistance state. For example, a reset signal (e.g., a voltage signal or a current signal) can be applied to the RRAM device 200b during the reset process. In some embodiments, the set signal and the reset signal may have opposite polarities, that is, they may be a positive signal and a negative signal, respectively. Applying the reset signal can cause oxygen to flow back into the oxide switching layer 220 and recombine with one or more oxygen vacancies. For example, as shown in FIG. 2C, a broken conductive filament 225b can be formed in the oxide switching layer 220 during the reset process. As shown in the figure, the conductive filament can be interrupted with an oxide gap between the broken conductive filament 225b and the bottom electrode 210. The lateral dimension of the conductive filament 225b may be smaller than that of the conductive filament 225a. The conductive filament 225b does not continuously connect the bottom electrode 210 and the upper electrode 230. The RRAM devices 200b-c can be electrically switched between a high-resistance state and a low-resistance state by applying an appropriate programming signal (e.g., a voltage signal, a current signal, etc.) to the RRAM device.

[0045] Figures 2D, 2E, and 2F are graphs 200d, 200e, and 200f showing the current-voltage (I-V) characteristics of a conventional RRAM device described in connection with FIGS. 2A-2C. FIG. 2D is the I-V curve 200d of a conventional RRAM device in an initial state. As shown, the initial resistance of the conventional device is approximately 1.3 GΩ at 0.2V. Thus, the conventional RRAM device can be regarded as an insulator in its initial state. As shown in FIG. 2E, a forming process may be performed by applying a forming voltage V form to the RRAM device. The forming voltage may be approximately 1.7V. After the forming process, the RRAM device can be reset to a high resistance state by applying a reset voltage within voltage range 261 in a reset process (also referred to as an “initial reset process”). The reset peak current through the RRAM device in the initial reset process is approximately 1 mA. As shown in FIG. 2F, the RRAM device can be switched between a high resistance state and a low resistance state by applying an appropriate set voltage within voltage range 263 and a reset voltage within voltage range 261, respectively. The set voltage may be approximately 0.7V. The reset peak current may be approximately 100 μA. Thus, a high forming voltage needs to be applied for forming a conventional RRAM device. The reset peak current in the initial reset process is high. Conventional RRAM devices operate with a high operating current. The resistance of a conventional RRAM device cannot be switched without a forming process.

[0046] FIG. 3 is a schematic diagram showing a cross-sectional view of an example of an RRAM cell 300 that does not require a forming process according to some embodiments of the present disclosure. The RRAM cell 300 is also referred to as an RRAM device herein.

[0047] As shown, the RRAM cell 300 may include a substrate 310, a bottom electrode 320, an oxide switching layer 330, an interface layer 340, and a top electrode 350. The interface layer 340 is fabricated between the top electrode 350 and the oxide switching layer 330.

[0048] The substrate 310 may include one or more layers of a suitable material that can function as a substrate for an RRAM device, such as silicon (Si), silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), aluminum nitride (AlN), etc. In some embodiments, the substrate 310 may include a diode, a transistor, an interconnection, an integrated circuit, etc. In some embodiments, the substrate may include a drive circuit that includes one or more individually controllable electrical circuits (e.g., an array of electrical circuits). In some embodiments, the drive circuit may include one or more complementary metal oxide semiconductor (CMOS) drivers.

[0049] The bottom electrode 320 may be and / or include any suitable material that is electrically conductive and non-reactive to oxide switching, such as platinum (Pt), palladium (Pd), iridium (Ir), titanium nitride (TiN), tantalum nitride (TaN), etc.

[0050] The oxide switching layer 330 may include one or more transition metal oxides of binary oxides, ternary oxides, and higher-order oxides such as TaO x , HfO x , TiO x , NbO x , ZrO x . Here, x can be used to indicate an oxide in which oxygen is deficient compared to the complete oxide in its stoichiometry, and the value of x can be varied from the atomic ratio of oxygen to metal in the complete oxide. For example, in HfO x (when HfO2 is the complete oxide), x ≤ 2.0, and in TaO x (when Ta2O5 is the complete oxide), x ≤ 2.5. As an example, the oxide switching layer 330 may include Ta2O5 and / or HfO2.

[0051] The upper electrode 350 may include any suitable metallic material that is electrically conductive and reactive to oxide switching. For example, the metallic material of the upper electrode 350 may include Ta, Hf, Ti, TiN, TaN, etc. The upper electrode 350 may be reactive to oxide switching and may have an oxygen solubility suitable for absorbing oxygen from the oxide switching layer 330 and creating oxygen vacancies in the oxide switching layer 330. That is, the reactive metallic material of the upper electrode 350 may have suitable oxygen solubility and / or oxygen mobility. In some embodiments, the upper electrode 350 can not only create oxygen vacancies in the oxide switching layer 330 (e.g., by collecting oxygen), but can also function as an oxygen reservoir or source to the oxide switching layer 330 during cell programming.

[0052] In some embodiments, the upper electrode 350 may include one or more alloys. Each alloy may include two or more metallic elements. Each alloy may include a binary alloy (e.g., an alloy including two metallic elements), a ternary alloy (e.g., an alloy including three metallic elements), a quaternary alloy (e.g., an alloy including four metallic elements), a quinary alloy (e.g., an alloy including five metallic elements), a senary alloy (e.g., an alloy including six metallic elements), and / or a higher-order alloy (e.g., an alloy including more than six metallic elements). In some embodiments, the upper electrode 350 may include one or more alloys including a first metallic element and one or more second metallic elements. Each second metallic element may be less or more reactive to the transition metal oxide in the oxide switching layer than the first metallic element. In some embodiments, the first metallic element may be Ta. The second metallic element may include one or more of W, Hf, Mo, Nb, Zr, etc.

[0053] The interface layer 340 is in thermochemical equilibrium with the upper electrode 350 and the oxide switching layer 330 and does not react with either the upper electrode 350 or the oxide switching layer 330. Thus, the interface layer 340 may reduce diffusion and reaction between the upper electrode 350 and the oxide switching layer 330. The interface layer 340 may be and / or include a film of a material that is more chemically stable than the transition metal oxide of the oxide switching layer 330. As a result, the material may not react with the transition metal oxide of the oxide switching layer 330. As an example, the transition metal oxide of the oxide switching layer is HfO x and / or TaO y where x≦2.0, y≦2.5, and the interface layer 340 may include one or more layers such as Al2O3, MgO, Y2O3, La2O3. In some embodiments, the interface layer 340 may include a continuous film (e.g., a film with a thickness of 1 nm or more) of a material that is more chemically stable than the transition metal oxide. In some embodiments, the interface layer 340 may be discontinuous (e.g., a film with a thickness of 0.2 nm to 0.6 nm).

[0054] The RRAM cell 300 may be annealed with one or more annealing processes to achieve the desired operation without a forming process. Each annealing process may include annealing the RRAM element in a forming gas atmosphere at an appropriate period (e.g., 15 to 30 minutes) and an appropriate temperature (e.g., 350 to 450 °C). The forming gas may include a mixture of nitrogen (N2) and hydrogen (H2) in an appropriate ratio (e.g., 95:5, 90:10, etc.). The thickness of the interface layer 340 may be determined based on the device size (critical size, device area, etc.) of the RRAM cell 300 and the annealing conditions. A smaller device size may require a longer annealing time and / or a thinner interface layer 340 to reduce the initial resistance of the RRAM without a forming process.

[0055] Annealing may reduce the diffusion and reaction between the interface layer 340 and the upper electrode 350 and the oxide switching layer 330, while it may also promote the diffusion and reaction between the upper electrode 350 and the oxide switching layer 330. In view of the device size of the RRAM cell 300, balancing and / or optimizing the interface layer 340 and the thermal budget related to annealing (e.g., annealing temperature, annealing time, etc.) can control the initial resistance of the RRAM cell 300 within a desired target range and achieve desirable device operations such as no need for a forming process, low-energy switching, and low inter-device performance variation. As will be described in more detail in connection with FIGS. 9A-9J, the thickness of the interface layer 340 may be determined based on the device size and the thermal budget of the RRAM cell 300. In some embodiments, the initial resistance of the RRAM cell 300 that does not require a forming process may be between about 1 kΩ and about 1 MΩ. In some embodiments, the initial resistance of the RRAM cell 300 may be from several hundred ohms to several kiloohms (e.g., 500 Ω to 5 kΩ).

[0056] In some embodiments, the RRAM cell 300 may be manufactured during a CMOS process. The thermal budget for annealing the RRAM cell 300 may be determined based on the annealing conditions related to the CMOS process. For example, as shown in FIG. 4, the semiconductor device 400 may include a transistor 403 manufactured on a substrate 401. The transistor 403 may include a source region 403a, a gate 403b, and a drain region 403c. The interconnect layer 410 may be manufactured on the transistor 403 and the substrate 401.

[0057] Each interconnect layer 410 may provide electrical connections between the transistor 403 and / or one or more other elements (e.g., one or more other transistors, RRAM cells 300, one or more other RRAM elements, etc.). The interconnect layer 410 may include, for example, via layers 411, 412, 413, 414, and 415 and metal layers (or pad layers) 421, 423, 424, and 425. Each via layer may include one or more metal vias. Each metal via may include a suitable metal material such as Al, Cu, W, etc. Each metal layer may include one or more metal pads and / or one or more metal wires. Each metal pad may include a suitable metal material such as Al, Cu, W, etc. For example, the via layer 411 may include metal vias 411a, 411b, and 411c that may be connected to the source region 403a, gate 403b, and drain region 403c of the transistor 403, respectively. In some embodiments, the via layer 411 may include tungsten (W) vias and doped polycrystalline silicon (poly-Si) terminals, and the poly-Si terminals may be in direct contact with the gate 403b, source region 403a, and drain region 403c of the transistor 403. The tungsten vias may be in direct contact with the poli-Si terminals. Other via layers and metal layers above the via layer 411 may be fabricated from Cu, W, Al, etc. The metal layer 421 may include metal pads 421a, 421b, and 421c. The metal pads 421a, 421b, and 421c may be connected to the metal vias 411a, 411b, and 411c, respectively. The metal layer 422 may include metal pads 422a, 422b, and 422c. The metal pads 422a, 422b, and 422c may be connected to the metal vias 412a, 412b, and 412c, respectively. As shown, pairs of adjacent metal layers may be connected via via layers fabricated between the adjacent metal layers.

[0058] Manufacturing the interconnect layer 410 may include manufacturing a layer of dielectric material using a suitable deposition technique such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), sputtering, etc. The dielectric layer may be patterned to form one or more vias. One or more suitable metal materials may be deposited within the vias and patterned to form one or more metal vias and / or metal pads. The metal vias and / or metal pads may then be annealed in a forming gas environment. In some embodiments, the via layer and the metal layer may be manufactured in a dual damascene manufacturing process where the metal vias and metal pads are manufactured during the same metal deposition and patterning process and annealed together.

[0059] As an example, to manufacture the first via layer 411, a dielectric layer 451 may be manufactured over the substrate 401 and the transistor 403. The dielectric layer 451 may include any suitable dielectric material such as silicon nitride (Si3N4), silicon dioxide (SiO2), etc. The dielectric layer 451 may be processed using any suitable deposition technique. For example, the dielectric layer 451 may be patterned and filled by metal deposition to manufacture metal vias 411a, 411b, and 411c within the dielectric layer 451.

[0060] The RRAM cell 300 may be manufactured during the manufacture of the interconnect layer 410 and may thus be referred to as a CMOS-compatible RRAM device. For example, the RRAM cell 300 may be manufactured over a metal pad or a metal via of the topmost interconnect layer of the first interconnect layer 410a. Thereafter, one or more second interconnect layers 410b may be manufactured over the RRAM cell 300 and the first interconnect layer 410a. More specifically, for example, a metal pad or a metal via of the bottommost interconnect layer of the second interconnect layer 410b may be manufactured over the RRAM cell 300 and may be in direct contact with the RRAM cell 300.

[0061] Manufacturing each second interconnect layer 410b may include annealing the second interconnect layer in relation to the RRAM cell 300. In some embodiments, the via layer and the metal layer may be manufactured in a dual damascene manufacturing process where the metal vias and metal pads are manufactured during the same metal deposition and patterning process and annealed together. The interface layer 340 may have an appropriate thickness to achieve a desired forming gas annealing (FGA) tolerance. For example, a relatively thick interface layer may have higher FGA tolerance than a relatively thin interface layer. Thus, the thermal budget for annealing the RRAM cell 300 may be determined based on the location of the RRAM cell 300, the number of second interconnect layers manufactured on the RRAM cell 300, and / or the annealing conditions utilized to anneal the second interconnect layer. Thereafter, the thickness of the interface layer 340 may be optimized based on the annealing conditions and the device size of the RRAM cell 300.

[0062] The specific interconnect layers (e.g., metal layer and via layer) shown in FIG. 4 are merely illustrative. The first interconnect layer 410a and the second interconnect layer 410b may include any suitable number of interconnect layers. For example, in some embodiments, the RRAM cell 300 may be manufactured on the metal layer 413. In some embodiments, the semiconductor device 400 and / or the interconnect layer 410 may be manufactured using the techniques described in U.S. Patent Application No. 17 / 848,238, filed June 23, 2022, the entire disclosure of which is incorporated herein by reference.

[0063] FIGS. 5A-5D are diagrams showing the I-V curves 500A, 500B, 500C, and 500D of a first exemplary RRAM that does not require a forming process according to some embodiments of the present disclosure.

[0064] FIG. 5A shows the I-V curve 500A of the RRAM in the initial state. The horizontal axis of the I-V curve 500A represents the read voltage applied to the RRAM element in the initial state. The vertical axis of the I-V curve 500A represents the current passing through the RRAM element during the application of the read voltage. As shown, the initial resistance of the RRAM element is approximately 4.5 kΩ at 0.2V.

[0065] As shown in FIG. 5B, in order to switch the RRAM element from the initial resistance to a target resistance greater than the initial resistance (also referred to as the "first target resistance"), a reset voltage within the voltage range 511 may be applied to the RRAM element. The initial resistance of the RRAM element is reset without previously performing a forming process or an initial set process on the RRAM element. As an example, the resistance of the RRAM element may be reset to approximately 127 kΩ. As shown in FIG. 5B, the reset peak current passing through the RRAM element is lower than 200 μA and significantly lower than the reset current required to reset a conventional RRAM element after formation.

[0066] After the reset process, the resistance of the RRAM element may be set to a second target resistance greater than the first target resistance. For example, as shown in FIG. 5C, a set voltage within the voltage range 513 may be applied to the RRAM element during the set process. In some embodiments, the set voltage is approximately 0.6V. The set voltage and the reset voltage have opposite polarities. In some embodiments, the resistance of the RRAM element after the set process is approximately 5.2 kΩ at 0.2V.

[0067] As shown in FIG. 5D, the resistance of the RRAM element can be switched between the high resistance state 521 and the low resistance state 523 under the set voltage within the voltage range 513 or the reset voltage within the voltage range 511. The set voltage may be approximately 0.6V. The reset peak current is not greater than approximately 200 μA or more. In some embodiments, the reset peak current is not greater than about 500 μA. As shown in FIGS. 5A-5D, the RRAM device can be reset to a desired target resistance with a low initial reset peak current without a preliminary forming process and an initial reset process. The RRAM device switches at a large I on / I off ratio at a low voltage and operates at an ultra-low current.

[0068] FIGS. 6A-6D are diagrams showing current-voltage curves (I-V curves) 600A, 600B, 600C, and 600D of a second exemplary RRAM that does not require a forming process according to some embodiments of the present disclosure.

[0069] FIG. 6A shows the I-V curve 600A of the RRAM in the initial state. The horizontal axis of the I-V curve 600A represents the read voltage applied to the RRAM device in the initial state. The vertical axis of the I-V curve 600A represents the current passing through the RRAM device during the application of the read voltage. The initial resistance of the RRAM device is approximately 19 kΩ at 0.2V.

[0070] As shown in FIG. 6B, the RRAM device can be switched from the initial state 621 to the low resistance state 623 by applying a set voltage within the voltage range 611. As an example, the set voltage may be about 0.6V, which is much lower than the forming voltage required to electrically form a conventional RRAM device. After the setting process, the resistance of the RRAM device is approximately 8 kΩ at 0.2V.

[0071] After the setting process, the RRAM device can be reset to a higher resistance by applying a reset voltage within the voltage range 613 to the RRAM device. The reset peak current may be lower than 200 μA, which is significantly lower than the reset peak current required to reset a conventional device after formation. The resistance of the RRAM device after reset may be approximately 100 kΩ.

[0072] As shown in FIGS. 6C and 6D, the RRAM device can be repeatedly switched on and off under a set voltage within voltage range 611 or a reset voltage within voltage range 613. As an example, the resistance of the RRAM device can be set to about 5 kΩ by applying a set voltage of 0.7 V to the RRAM device. In some embodiments, the set voltage may be about 1 V or lower. As another example, the resistance of the RRAM device can be reset to about 100 kΩ under a reset peak current of about 200 μA or lower. As shown in FIGS. 6A - 6D, the RRAM device can be reset to a desired target resistance at a set voltage significantly lower than the forming voltage required in the forming process, and operate at low voltage and low current in subsequent switching events.

[0073] FIG. 7A is a flowchart showing an exemplary process 700a for operating a forming - process - free RRAM device according to some embodiments of the present disclosure. The resistance of the forming - process - free RRAM device can be switched to one of a plurality of resistance levels without a forming process.

[0074] At 710, a read operation for determining the initial resistance of the RRAM device may be performed. For example, to determine the initial resistance of the RRAM device, one or more read voltages may be applied to the RRAM device in the initial state. The read voltage may be, for example, a voltage between 0.05 and 0.5 V. Note that a read operation cannot be performed on a conventional RRAM without performing a forming process in advance because a conventional RRAM is non - conductive in its initial state.

[0075] At 720, the initial resistance is compared with the target resistance, and it may be determined whether the target resistance is greater than the initial resistance. The target resistance may be a desired resistance or the weight at which the RRAM device is programmed.

[0076] In some embodiments, the target resistance may be greater than the initial resistance of the RRAM device. In such embodiments, process 700a may proceed to 730 and a reset operation may be performed to program the RRAM device to the target resistance. For example, a reset voltage may be applied to the RRAM device. The reset current may be several hundred microamperes (μA). Different from the conventional RRAM devices described in connection with FIGS. 2A-2F, the RRAM device that does not require a forming process can be programmed to the target resistance without the forming process and the subsequent initial reset process.

[0077] In some embodiments, the initial resistance of the RRAM device may be greater than the target resistance. In such embodiments, process 700a may proceed to 735 and a set operation may be performed on the RRAM device to program the RRAM device to the target resistance. For example, a set voltage may be applied to the RRAM device. The set voltage may be about 0.3-0.7V in some embodiments. In some embodiments, the set voltage may be about 0.5-1V. Therefore, the RRAM device that does not require a forming process can be set to the target resistance without a forming process for generating a conductive filament in the RRAM device.

[0078] FIG. 7B is a flowchart showing an exemplary process 700b for operating a RRAM device that does not require a forming process (also referred to as a "first RRAM device that does not require a forming process") according to some embodiments of the present disclosure.

[0079] At 740, a first read operation may be performed on the first RRAM device that does not require a forming process in the initial state, and the first initial resistance of the first RRAM device that does not require a forming process may be determined. The first initial resistance represents the resistance of the first RRAM device that does not require a forming process in the initial state without going through a forming process. Performing the first read operation on the first RRAM device that does not require a forming process in the initial state includes applying one or more read voltages (e.g., a voltage of about 0.2V) to the first RRAM device that does not require a forming process.

[0080] At 750, a first reset operation for programming a RRAM element that does not require a first formation step to a first target resistance greater than the first initial resistance may be performed. Performing the first reset operation may include applying a reset signal (e.g., a voltage signal, a current signal, etc.) to the RRAM element that does not require the first formation step. The reset peak current (also referred to as the "first reset current") passing through the RRAM element that does not require the first formation step during the first reset operation may be about 200 μA or less. In some embodiments, the first reset current may be about 500 μA or less. The reset operation is performed without previously forming the RRAM element that does not require the first formation step in a formation step.

[0081] At 760, a first set operation may be performed on the RRAM element that does not require the first formation step, and the RRAM element that does not require the first formation step may be switched from the first target resistance to a second target resistance. The first target resistance is greater than the second target resistance. Performing the first set operation may include applying a first set voltage to the RRAM element that does not require the first formation step. In some embodiments, the first set voltage is not greater than 0.7V. In some embodiments, the first set voltage is not greater than 1V.

[0082] Referring to FIG. 7C, a flowchart showing an exemplary process 700c for operating a RRAM element that does not require a formation step and has a medium resistance (the "second RRAM element that does not require a formation step") according to some embodiments of the present disclosure is shown.

[0083] At 770, a second read operation may be performed on the second RRAM element in the initial state, and the initial resistance (the "second initial resistance") of the second RRAM element that does not require the formation step may be determined. The second initial resistance represents the resistance of the second RRAM element in the initial state without going through a formation step. Performing the second read operation on the second RRAM element that does not require the formation step includes applying one or more read voltages to the second RRAM element in the initial state.

[0084] At 780, a second set operation for switching the second RRAM element from a second initial resistance to a third target resistance may be performed. The second initial resistance is greater than the third target resistance. The second set operation is performed without previously performing a formation process on the second formation-process-omissible RRAM element. Performing the second set operation may include applying a second set voltage to the second formation-process-omissible RRAM element. In some embodiments, the second set voltage is not greater than 0.7V. In some embodiments, the second set voltage is not greater than 1V.

[0085] At 790, a second reset operation for switching the second formation-process-omissible RRAM element from a third resistance to a fourth target resistance may be performed. The fourth target resistance may be less than the third target resistance. The reset operation is performed without previously performing a formation process on the second formation-process-omissible RRAM element.

[0086] FIG. 8 is a flowchart showing an exemplary process 800 for manufacturing a formation-process-omissible RRAM element according to some embodiments of the present disclosure.

[0087] In block 810, RRAM cells may be fabricated. The RRAM cells may include a bottom electrode, an oxide switching layer, a top electrode, and an interface layer fabricated between the oxide switching layer and the top electrode. The RRAM cells may be the RRAM cells 300 of FIG. 3. In particular, the bottom electrode may be fabricated on the substrate at 811. The fabrication of the bottom electrode may include depositing one or more layers of one or more inert metals such as Pt, Pd, Ir, etc. using physical vapor deposition (PVD) technology, chemical vapor deposition (CVD) technology, sputter deposition technology, atomic layer deposition (ALD) technology, and / or any other suitable deposition technology. In some embodiments, the fabrication of the bottom electrode may include depositing one or more layers of a metal nitride such as TiN or TaN. The bottom electrode may be and / or may include the bottom electrode 320 described in connection with FIG. 3 above.

[0088] In block 813, the oxide switching layer may be fabricated on the bottom electrode. The oxide switching layer may include one or more transition metal oxides. The transition metal oxides may include, for example, TaO x , HfO x , TiO x , NbO x , ZrO x , etc. The oxide switching layer may be deposited using PVD, CVD, ALD, and / or any other suitable deposition technology.

[0089] In block 815, an interface layer may be fabricated on the oxide switching layer. Fabrication of the interface layer may include depositing a material that is more chemically stable than the transition metal oxide of the oxide switching layer, such as Al2O3, MgO, Y2O3, La2O3. In certain embodiments, fabrication of the interface layer may include depositing a continuous layer, such as Al2O3, MgO, Y2O3, La2O3. In another embodiment, fabrication of the interface layer may include depositing a layer of material having an appropriate thickness (e.g., a thickness from about 0.2 nm to about 0.6 nm) to form a discontinuous film, such as Al2O3, MgO, Y2O3, La2O3. The interface layer may be deposited using PVD, CVD, ALD, and / or any other suitable deposition technique.

[0090] In block 817, a top electrode may be fabricated on the interface layer. Fabrication of the top electrode may include depositing one or more suitable metal materials that are electrically conductive and reactive with respect to the oxide switching of the oxide switching layer, such as Ta, Hf, Ti, TiN, TaN. The top electrode may include one or more alloys. The top electrode may be fabricated using PVD, CVD, ALD, and / or any other suitable deposition technique.

[0091] In block 830, the RRAM cell may be annealed. For example, the RRAM cell may be annealed in one or more annealing processes, and each annealing process may include annealing the RRAM cell in a forming gas environment (e.g., a mixture of N2 and H2) at an appropriate annealing temperature (e.g., 350 - 450 °C) for an appropriate time (e.g., 15 - 30 minutes) for each annealing process.

[0092] In some embodiments, process 800 may further include block 820, where one or more interconnect layers are fabricated on the top electrode. In such embodiments, the RRAM cells may be annealed together with the interconnect layers at block 830. Fabrication of each interconnect layer may include fabricating a layer of a dielectric material, such as Si3N4, SiO2, etc., using a suitable deposition technique such as chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), sputtering, etc. The dielectric layer may be patterned to form one or more vias. One or more suitable metal materials may be deposited within the vias and patterned to fabricate one or more metal vias and / or metal pads.

[0093] FIGS. 9A - 9E are diagrams showing I - V characteristics of exemplary RRAM devices having different device sizes and fabricated under the same annealing conditions.

[0094] I - V curves 911, 913, and 915 show the I - V characteristics of RRAM devices with a critical dimension of 0.18 μm. I - V curves 921, 923, and 925 show the I - V characteristics of RRAM devices with a critical dimension of 0.24 μm. I - V curves 931, 933, and 935 show the I - V characteristics of RRAM devices with a critical dimension of 0.28 μm. The RRAM devices corresponding to I - V curves 911, 921, and 931 do not include an interface layer. Each RRAM device corresponding to I - V curves 913, 923, and 933 includes a thin interface layer (e.g., a layer of 0.2 nm to 0.6 nm). In some embodiments, the thin interface layer may be a discontinuous layer and / or may include such a layer. Each RRAM device corresponding to I - V curves 915, 925, and 935 includes a thick interface layer (e.g., a layer of about 1 nm or greater). The RRAM devices exhibit various resistances as shown in FIG. 9A. The RRAM devices corresponding to I - V curves 921, 931, 913, 923, and 933 are RRAM devices without a forming process having initial resistances of about 549 Ω, 543 Ω, 7.5 kΩ, 465 Ω, and 460 Ω, respectively.

[0095] Figures 9F - 9J are diagrams showing the I - V characteristics of exemplary RRAM devices fabricated under various annealing conditions with the same device size (e.g., critical dimension 0.24 μm).

[0096] The RRAM devices corresponding to the I - V curves 941, 943, and 945 are fabricated without annealing. The RRAM devices corresponding to the I - V curves 951, 953, and 955 are fabricated under short - time annealing. The RRAM devices corresponding to the I - V curves 961, 963, and 965 are fabricated under long - time annealing. Each RRAM device corresponding to the I - V curves 941, 951, and 961 does not include an interface layer. Each RRAM device corresponding to the I - V curves 943, 953, and 963 includes a thin interface layer (e.g., a layer of 0.2 nm to 0.6 nm). In some embodiments, the thin interface layer may be a discontinuous layer and / or may include it. Each RRAM device corresponding to the I - V curves 945, 955, and 965 includes a thick interface layer (e.g., a layer of about 1 nm or greater). The RRAM devices corresponding to the I - V curves 951, 953, 961, and 963 are RRAM devices that do not require the forming process described herein and have initial resistances of about 549 Ω, 460 Ω, 389 Ω, and 239 Ω, respectively. According to FIGS. 9A - 9B, the annealing conditions and the thickness of the interface layer may be optimized in view of the device size to achieve a desired initial resistance.

[0097] FIG. 10 is a diagram showing an I - V curve 1000 showing the analog operation of an exemplary forming - process - free RRAM device according to some embodiments of the present disclosure. As shown, the forming - process - free RRAM device can adjust the device resistance to multiple levels (or analog operation) without a forming process by controlling current compliance, and shows a desirable analog operation in which the current is linearly proportional to the voltage (or linear operation) at each resistance state.

[0098] FIG. 11 is a graph 1100 showing the element read current characteristics of an exemplary formation process-free RRAM element according to some embodiments of the present disclosure with respect to time. Graph 1100 shows the element read current characteristics of an exemplary RRAM element at 135°C. Graph 1100 may represent the results of an element retention test regarding the ability of a formation process-free RRAM element to retain a resistance level over time. Graph 1100 may also represent the results of a read stability test since the RRAM element is under a constant read (at a read voltage of 0.2V) regarding its ability to retain a resistance level over time.

[0099] For simplicity of explanation, the methods of the present disclosure are depicted and described as a series of acts. However, the acts of the present disclosure may occur in various orders and / or simultaneously, as well as with other acts not presented and described herein. Further, not all acts illustrated are required to implement the methods of the present disclosure. Additionally, as would be understood and recognized by those skilled in the art, the methods may alternatively be represented as a series of interrelated states via a state diagram or events.

[0100] As used herein, "about," "approximately," and "substantially" may mean within ±20% of a target dimension in some embodiments, within ±10% of a target dimension in some embodiments, within ±5% of a target dimension in some embodiments, within ±2% of a target dimension in some embodiments, within ±1% of a target dimension in some embodiments, and within ±0.1% of a target dimension in some further embodiments, etc., within the normal tolerances in the art, e.g., within 2 standard deviations of the mean. "About" and "approximately" may include the target dimension. Unless otherwise specified or clear from the context, all numerical values described herein are modified by "about."

[0101] Ranges used herein include all values within that range. For example, a range from 1 to 10 may include any number, any combination of numbers, any sub-range, and fractions thereof from the numbers 1, 2, 3, 4, 5, 6, 7, 8, 9, and 10.

[0102] In the foregoing description, numerous details are set forth. It is, however, apparent that the present disclosure may be practiced without these specific details. In some instances, well-known structures and elements are shown in block diagram form in order to avoid obscuring the present disclosure.

[0103] As used herein, terms such as "first", "second", "third", "fourth", etc. are meant as labels to distinguish different elements and do not necessarily have the meaning of ordinal numbers according to their numerical designations.

[0104] As used herein, the words "example" or "exemplary" are used to mean serving as an example, instance, or illustration. Any aspect or design described herein as "example" or "exemplary" should not be construed as necessarily being more preferred or advantageous than other aspects or designs. Rather, the use of the words "example" or "exemplary" is intended to present concepts in a concrete form. As used in this application, "or" is intended to mean an inclusive "or" unless specifically stated otherwise or otherwise apparent from the context. That is, unless specifically stated otherwise or otherwise apparent from the context, "X includes A or B" is intended to be satisfied under any of the following instances: X includes A, X includes B, or X includes both A and B. Additionally, the articles "a" and "an" used in this application and the appended claims should generally be construed to mean "one or more" unless specifically stated otherwise or otherwise apparent from the context that they refer to the singular form. References throughout this specification to "an embodiment" or "one embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases "an embodiment" or "one embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment.

[0105] As used herein, when an element or layer is referred to as being "on" another element or layer, that element or layer may be directly on the other element or layer or intervening elements or layers may be present. In contrast, when an element or layer is referred to as being "directly on" another element or layer, no intervening elements or layers are present.

[0106] Many variations and modifications of the present disclosure will be apparent to those skilled in the art after reading the foregoing description. These are illustrated and described by way of specific embodiments, but are in no way intended to be construed as limiting any particular embodiment. Accordingly, references to details of various embodiments are not intended to limit the claims to only those features.

[0107] [Cross - Reference to Related Applications] This application claims the benefit of U.S. Patent Application No. 17 / 812,866, filed July 15, 2022, entitled "FORMING - FREE RANDOM - ACCESS MEMORY (RRAM) DEVICES," which is hereby incorporated by reference in its entirety.

Claims

1. A method for manufacturing a resistive change type random access memory (RRAM) element that does not require a forming process, A process for manufacturing an RRAM cell, comprising: manufacturing an oxide switching layer containing at least one transition metal oxide on a bottom electrode; manufacturing an interface layer containing a material that is chemically more stable than the at least one transition metal oxide on the oxide switching layer; and manufacturing a top electrode on the interface layer, A step of annealing the RRAM cell, A method comprising the above.

2. The RRAM cell is annealed in a forming gas environment containing N ２ and H ２ The method according to claim 1, wherein the method is annealed in a forming gas environment containing

3. The method according to claim 1, wherein the RRAM cell is annealed at an annealing temperature between about 350 °C and 450 °C.

4. The method according to claim 1, further comprising a step of manufacturing one or more interconnect layers on the RRAM cell, The method according to claim 1, wherein the RRAM cell is annealed together with the one or more interconnect layers.

5. The method according to claim 4, wherein the step of manufacturing the one or more interconnect layers includes a step of manufacturing a metal pad or a metal via of the one or more interconnect layers on the top electrode of the RRAM cell.

6. The RRAM and the one or more interconnect layers are annealed by a plurality of annealing processes, The method according to claim 4, wherein the RRAM cell and the one or more interconnect layers are annealed in forming gas at a temperature between about 350 °C and 450 °C in each of the plurality of annealing processes.

7. The thickness of the interface layer is determined based on the device size of the RRAM cell and the thermal budget related to the annealing process of the annealing step, The method according to claim 1, wherein the interface layer is configured to reduce diffusion and reaction between the top electrode and the oxide switching layer.

8. A resistive change type random access memory (RRAM) element that does not require a forming process, A bottom electrode, An oxide switching layer containing at least one transition metal oxide, A top electrode, An interface layer manufactured between the top electrode and the oxide switching layer, Comprising, The interface layer contains a material that is chemically more stable than the at least one transition metal oxide, The RRAM element that does not require the forming process is configured to be switched to a plurality of resistances without performing a forming process for generating a conductive filament in the oxide switching layer, and is an RRAM element that does not require the forming process.

9. The at least one transition metal oxide is HfO ｘ and TaO ｙ The RRAM element that does not require a forming process according to claim 8, comprising at least one of them, where x ≤ 2.0 and y ≤ 2.

5.

10. The interface layer is Al ２ O ３ , MgO, Y ２ O ３ , and La ２ O ３ The RRAM element that does not require a forming process according to claim 9, comprising at least one layer of

11. The thickness of the interface layer is between 0.2 nm and 1 nm, and the RRAM element that does not require the forming process according to claim 10.

12. The thickness of the interface layer is greater than 1 nm, and the RRAM element that does not require the forming process according to claim 10.

13. The initial resistance of the RRAM element is between 1 kΩ and 1 MΩ, and the RRAM element that does not require the forming process according to claim 8.

14. A method for operating an RRAM element that does not require a forming process, performing a first read operation on a first RRAM element that does not require the forming process in an initial state, and determining a first initial resistance of the first RRAM element that does not require the forming process; performing a first reset operation on the first RRAM element that does not require the forming process, and switching the first RRAM element that does not require the forming process from the first initial resistance to a first target resistance; including, the first target resistance is greater than the first initial resistance, the first read operation and the first reset operation are performed without previously forming a conductive filament in the first RRAM element that does not require the forming process in the forming process.

15. The first reset current passing through the first RRAM element that does not require the forming process during the first reset operation is not greater than 500 μA, and the method according to claim 14.

16. further including performing a first set operation on the first RRAM element that does not require the forming process, and switching the first RRAM element that does not require the forming process from the first target resistance to a second target resistance; the step of performing the first set operation includes applying a first set voltage to the first RRAM element that does not require the forming process, and the first set voltage is not greater than 1.0 V, and the method according to claim 14.

17. The step of performing the first reset operation on the first RRAM element that does not require the forming process includes applying a first reset voltage to the first RRAM element that does not require the forming process, and the first set voltage and the first reset voltage have opposite polarities, and the method according to claim 16.

18. Performing a second read operation on the RRAM device that does not require the second formation step, and determining a second initial resistance of the RRAM device that does not require the second formation step; Further including performing a second set operation on the RRAM device that does not require the second formation step, and switching the RRAM device that does not require the second formation step from the second initial resistance to a third target resistance; The third target resistance is smaller than the second initial resistance; The method according to claim 14, wherein the second read operation and the second set operation are performed without previously forming a conductive filament in the RRAM device that does not require the second formation step in a formation step.

19. Further including applying a second reset voltage to the RRAM device that does not require the second formation step, and switching the RRAM device that does not require the second formation step from the third target resistance to a fourth target resistance; The step of performing the second set operation on the RRAM device that does not require the second formation step includes applying a second set voltage to the RRAM device that does not require the second formation step, and the second reset voltage and the second set voltage have opposite polarities. The method according to claim 18.

20. The second reset current passing through the RRAM device that does not require the second formation step in response to the second reset voltage is not greater than 500 μA, and the second reset voltage is not greater than 1.0 V. The method according to claim 19.

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