Ruthenium Carbide for DRAM Capacitor Mold Patterning

Abstract

A method of forming an electronic device and a film stack including depositing a ruthenium carbide hard mask on a capacitor mold formed on a substrate. A hard mask oxide and a patterned photoresist are formed, and the pattern of the patterned photoresist is transferred to the ruthenium carbide hard mask. A film stack including the ruthenium carbide hard mask on the capacitor mold is also described.

Description

Technical Field

[0001]

[0001] Embodiments of the present disclosure generally relate to the manufacture of integrated circuits. In particular, embodiments of the present disclosure relate to a film stack for an electronic device using a ruthenium carbide hard mask and a method of forming the film stack.

Background Art

[0002]

[0002] Reliably manufacturing sub-micron and smaller features is one of the important requirements for very large scale integration (VLSI) and ultra very large scale integration (ULSI) of semiconductor devices. However, with the continuous miniaturization of circuit technology, the sizes and pitch dimensions of circuit features such as interconnects impose further requirements on processing capabilities. Various semiconductor components (interconnects, vias, capacitors, transistors, etc.) need to accurately place high aspect ratio features. Reliably forming these components is essential for further improving device and integration density.

[0003]

[0003] Furthermore, the electronics and semiconductor industries continue to strive for higher production yields while improving the uniformity of the layers deposited on substrates with increasingly large surface areas. By combining these same factors with new materials, high circuit integration per unit area on the substrate can also be achieved.

[0004]

[0004] During the formation of many electronic devices, a hard mask is used to protect a portion of the substrate from being removed. Hard masks are generally used in the patterning process. Once patterning is complete, the hard mask is often removed leaving the protected portions of the substrate. Removal of the hard mask material can be done separately from other etching processes or together with other etching steps. The ability to remove the hard mask material without affecting other surface features (also called etching selectivity) is a useful function.

[0005]

[0005] The development of hard mask materials with high etching selectivity is important for patterning the new generation of NAND and DRAM devices. For devices at each technology node, it is necessary to improve the selectivity of the capacitor mold hard mask by 30% compared to the conventional nodes. Currently, boron-doped silicon is used for patterning the DRAM capacitor mold at N to N+2 nodes.

[0006]

[0006] As the N+2 node is proposed, the dopant concentration is dominated by boron. Therefore, it is considered that even if the dopant concentration of boron is increased, the selectivity of the hard mask cannot be continuously improved sufficiently.

[0007]

[0007] Therefore, there is a continuous need in the art for capacitor mold hard masks with improved selectivity.

Summary of the Invention

[0008]

[0008] One or more embodiments of the present disclosure are directed to a method including depositing a ruthenium carbide hard mask on a capacitor mold formed on a substrate. A hard mask oxide is formed on the ruthenium carbide layer. A patterned photoresist is formed on the hard mask oxide. The pattern of the patterned photoresist is transferred to the ruthenium carbide hard mask to form a patterned ruthenium carbide hard mask.

[0009]

[0009] A further embodiment of the present disclosure is directed to a method that includes forming a capacitor mold on a substrate. The capacitor mold includes a silicon oxide (SiO) layer and a silicon carbonitride (SiCN) layer or a silicon nitride (SiN) layer on the silicon oxide layer. The silicon oxide (SiO) layer has a thickness in the range of 1 μm to 3 μm, and the SiCN layer or the SiN layer has a thickness of up to 1000 Å. Optionally, one or more amorphous silicon films or carbon films are directly deposited on the capacitor mold. A ruthenium carbide hard mask is deposited on the capacitor mold and, if present, on the optional amorphous silicon film or carbon film. The ruthenium carbide hard mask contains ruthenium in the range of 20 atomic % to 45 atomic % and hydrogen in the range of 5 atomic % to 15 atomic %. The total thickness of the optional amorphous silicon film or carbon film and the ruthenium carbide hard mask is in the range of 2500 Å to 3500 Å. A hard mask oxide is formed on the ruthenium carbide layer. An anti-reflective coating including one or more of a dielectric anti-reflective coating (DARC) or a bottom anti-reflective coating (BARC) is formed on the hard mask oxide. A photoresist having a pattern is formed on the anti-reflective coating. The pattern of the photoresist is transferred to the anti-reflective coating, the hard mask oxide, and the ruthenium carbide hard mask by exposing the substrate to an etchant plasma including oxygen, chlorine, and carbonyl sulfide to form a patterned hard mask oxide and a patterned ruthenium carbide hard mask and to remove the anti-reflective coating. The chlorine content is in the range of 5% to 15% of the oxygen content on a molar basis, and the carbonyl sulfide content is in the range of 5% to 10% of the oxygen content on a molar basis. The remaining photoresist and the anti-reflective coating are removed to leave the patterned hard mask oxide and the patterned ruthenium carbide hard mask. Optionally, the pattern of the patterned hard mask oxide and the patterned ruthenium carbide hard mask is transferred to the optional amorphous silicon film or carbon film.

[0010]

[0010] Further embodiments of the present disclosure are directed to a film stack comprising a capacitor mold, a ruthenium carbide hard mask on the capacitor mold, a hard mask oxide on the ruthenium carbide hard mask, and a patterned photoresist on the hard mask oxide.

[0011]

[0011] To enable a more detailed understanding of the features of the present disclosure described above, the present disclosure summarized above will be described more specifically with reference to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings only show typical embodiments of the present disclosure and should not be regarded as limiting the scope of the present disclosure, as the present disclosure may admit other equally valid embodiments.

Brief Description of the Drawings

[0012]

Figure 1

Figure 2

Modes for Carrying Out the Invention

[0013]

[0014] For ease of understanding, wherever possible, the same reference numbers are used to denote the same elements common to the drawings. It is assumed that the elements and features of one embodiment can be beneficially incorporated into other embodiments without further elaboration.

[0014]

[0015] Before describing some exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of the structures or process steps shown in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0015]

[0016] As used in this specification and the appended claims, the term "substrate" refers to the surface, or a portion of the surface, on which a process acts. Further, unless the context clearly indicates otherwise, it will be understood by those skilled in the art that a reference to a substrate may refer to only a portion of the substrate. Additionally, a reference to deposition on a substrate may mean either a bare substrate or a substrate on which one or more films or features have been deposited or formed thereon.

[0016]

[0017] As used herein, "substrate" refers to any substrate or the surface of a material formed on a substrate on which film processing is performed during a manufacturing process. For example, the substrate surface on which processing can be performed includes materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, etc., depending on the application, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. The substrate can be exposed to a pretreatment process for polishing, etching, reducing, oxidizing, hydroxiding, annealing, and / or firing the substrate surface. In addition to performing film processing directly on the surface of the substrate itself, in the present disclosure, any of the disclosed film processing steps may be performed on an underlying layer formed on the substrate, as will be disclosed in more detail below, and the term "substrate surface" is intended to include such underlying layers as the context indicates.

[0017]

[0018] The term "on" indicates direct contact between elements. The term "directly on" indicates direct contact between elements with no intervening elements.

[0018]

[0019] As used in this specification and the appended claims, the terms "precursor", "reactant", "reactive gas", etc. are used interchangeably to refer to any gas species that can react with the substrate surface.

[0019]

[0020] Some embodiments of the present disclosure advantageously provide a new hard mask material with improved selectivity to boron-doped silicon. In some embodiments, a ruthenium carbide film is used as a hard mask that has selectivity to adjacent hard mask oxides and / or capacitor mold parts. Some embodiments provide a ruthenium carbide hard mask that can be ashed or etched from a substrate surface.

[0020]

[0021] FIG. 1 is a schematic diagram of an exemplary substrate processing system 132 that can be used for the deposition of ruthenium carbide, or other processes, in accordance with embodiments described herein. Examples of suitable processing chambers and tools include, but are not limited to, the CENTURA® system, PRECISION5000® system, PRODUCER(™) systems such as the PRODUCER SE(™) process chamber and the PRODUCER GT(™) process chamber, all commercially available from Applied Materials, Inc. of Santa Clara, Calif., DxZ(™) process chambers can be used. The processes described herein can also be performed in other substrate processing systems, including those from other manufacturers.

[0021]

[0022] The substrate processing system 132 shown in FIG. 1 includes a process chamber 100 coupled to a gas panel 130 and a controller 110. The process chamber 100 generally includes an upper portion 124, sidewalls 101, and a bottom wall 122 that define an internal processing region 126. A support pedestal 150 is provided in the internal processing region 126 of the chamber 100. The pedestal 150 is supported by a stem 160 or a pedestal support and can typically be made of aluminum, ceramic, and other suitable materials. The pedestal 150 can be moved vertically within the chamber 100 using a displacement mechanism (not shown) or rotated about the central axis of the stem 160 using a suitable rotation mechanism (not shown).

[0022]

[0023] The illustrated pedestal 150 includes an embedded heating element 170 suitable for controlling the temperature of a substrate 190 supported on the surface 192 of the pedestal 150. The pedestal 150 can be resistively heated by applying a current from a power source 106 to the heater element 170. The heater element 170 may be made of nickel-chromium wire encapsulated in a nickel-iron-chromium alloy (e.g., INCOLOY®) sheath tube. The current supplied from the power source 106 is adjusted by a controller 110 to control the heat generated by the heater element 170, thereby maintaining the substrate 190 and the pedestal 150 during film deposition at a substantially constant temperature. The supplied current can be adjusted to selectively control the temperature of the pedestal 150 between about 100°C and about 700°C.

[0023]

[0024] To monitor the temperature of the pedestal 150 in a conventional manner, a temperature sensor 172, such as a thermocouple, may be embedded in the support pedestal 150. The measured temperature is used by the controller 110 to control the power supplied to the heating element 170 to maintain the substrate at a desired temperature.

[0024]

[0025] A vacuum pump 102 is coupled to a port formed in the bottom of the chamber 100. The vacuum pump 102 is used to maintain a desired gas pressure within the process chamber 100. The vacuum pump 102 also evacuates post-process gases and by-products from the chamber 100.

[0025]

[0026] The processing system 132 may further include additional equipment for controlling the chamber pressure, such as valves (e.g., throttle valves and isolation valves) positioned between the process chamber 100 and the vacuum pump 102 for controlling the chamber pressure.

[0026]

[0027] A showerhead 120 having a plurality of apertures 128 is disposed above a substrate support pedestal 150 at the top of a process chamber 100. Process gas is introduced into the chamber 100 using the apertures 128 of the showerhead 120. The apertures 128 may have different sizes, numbers, distributions, shapes, designs, and diameters to facilitate the flow of various process gases under different process requirements. The showerhead 120 is connected to a gas panel 130 that can supply various gases to an internal processing region 126 during the process. Plasma is formed from the mixed process gas exiting the showerhead 120, promoting the thermal decomposition of the process gas, and as a result, material is deposited on the surface 191 of the substrate 190.

[0027]

[0028] The gas panel 130 may also be used to control and supply various vaporized liquid precursors. Although not shown, the liquid precursor from a liquid precursor supply may be vaporized, for example, by a liquid injection vaporizer and delivered to the process chamber 100 in the presence of a carrier gas. The carrier gas is typically an inert gas such as nitrogen, or a noble gas such as argon or helium. Alternatively, the liquid precursor may be vaporized from an ampule by a thermal and / or vacuum vaporization process.

[0028]

[0029] The showerhead 120 and the substrate support pedestal 150 can form a pair of electrodes spaced apart within the internal processing region 126. One or more RF power supplies 140 supply a bias potential to the showerhead 120 through a matching network 138 to facilitate the generation of plasma between the showerhead 120 and the pedestal 150. Alternatively, the RF power supply 140 and the matching network 138 may be coupled to the showerhead 120, may be coupled to the substrate pedestal 150, or may be coupled to an antenna (not shown) disposed outside the chamber 100. In one embodiment, the RF power supply 140 can supply from about 50 watts to about 10,000 watts at a frequency from about 50 kHz to about 100 MHz. In another embodiment, the RF power supply 140 can supply from about 500 watts to about 1,800 watts at a frequency from about 50 kHz to about 13.6 MHz.

[0029]

[0030] The controller 110 includes a central processing unit (CPU) 112, a memory 116, and support circuits 114 that are used to control the process sequence and regulate the gas flow from the gas panel 130. The CPU 112 can be any form of general-purpose computer processor that can be used in an industrial environment. Software routines may be stored in the memory 116 such as random access memory, read-only memory, floppy disks, or hard disk drives, or other forms of digital storage. The support circuits 114 are conventionally coupled to the CPU 112 and may include caches, clock circuits, input / output systems, power supplies, and the like. Bidirectional communication between the controller 110 and the various components of the processing system 132 is processed through a number of signal cables collectively referred to as a signal bus 118, such as that shown in FIG. 1.

[0030]

[0031] Refer to FIGS. 2A - 2D, which illustrate an exemplary process for forming an electronic device using schematic cross-sectional views of the electronic device. The shading shown in the figures is used to illustrate different components and should not be construed as representing any particular structural material unless otherwise specified.

[0031]

[0032] FIG. 2A is a diagram showing an electronic device 200 having a capacitor mold 210 formed on a substrate 205. The capacitor mold 210 in some embodiments includes one or more of silicon oxide (SiO), silicon carbide (SiC), or silicon carbonitride (SiCN). As used herein and in the appended claims, unless otherwise specified, chemical formulas merely represent the elemental identity of the film and are not intended to be stoichiometric. For example, an SiO film contains silicon atoms and oxygen atoms. A typical silicon oxide film mainly contains silicon dioxide (SiO2), which implies a specific stoichiometric relationship. In some embodiments, the elemental formula of a layer means that the layer contains about 95% or more, 98% or more, 99% or more, or 99.5% or more of the described elements on an atomic basis. One of ordinary skill in the art will recognize that interatomic diffusion can occur unintentionally and affect the overall composition of the described layer. Thus, for example, in a silicon oxide (SiO) layer, the total of silicon atoms and oxygen atoms occupies 95% or more, 98% or more, 99% or more, or 99.5% or more of all the atoms in the layer, allowing for a small amount of contaminant atoms and interdiffused atoms. Stated another way, the layer is "essentially composed of" the described elements. "Essentially composed of" means that the described elements occupy 95% or more, 98% or more, 99% or more, or 99.5% or more on an atomic basis. The term "essentially composed of" can be applied to any of the individual layers described herein and is not limited to the example of silicon oxide.

[0032]

[0033] The capacitor mold 210 in some embodiments includes a silicon oxide (SiO) layer 212 and a second layer 214 including one or more of a silicon carbonitride (SiCN) layer or a silicon nitride (SiN) layer. The silicon oxide layer 212 in some embodiments has a thickness in the range of 0.5 μm to 5 μm, or in the range of 1 μm to 3 μm. In some embodiments, the silicon oxide layer 212 has a maximum thickness of 3.5 μm.

[0033]

[0034] The second layer 214 of some embodiments includes a silicon carbonitride (SiCN) layer. In some embodiments, the second layer 214 includes a silicon nitride (SiN) layer. The second layer 214, or the SiCN layer, or the SiN layer has a thickness of up to 10000 Å, or 5000 Å, or 1000 Å. In some embodiments, the second layer 214 has a thickness in the range of 100 Å to 1000 Å, or in the range of 500 Å to 900 Å.

[0034]

[0035] The silicon oxide layer 212 and the second layer 214 can be formed by any suitable technique known to those skilled in the art. For example, the layers can be formed by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma atomic layer deposition (PEALD), physical vapor deposition (PVD).

[0035]

[0036] The substrate 205 and / or the capacitor mold 210 of some embodiments have a substantially planar surface. Alternatively, the substrate 205 and / or the capacitor mold 210 of some embodiments have a surface in which patterned structures, trenches, holes, or vias are formed. Although the substrate 205 is shown alone, those skilled in the art will understand that the substrate can include one or more material layers used in forming semiconductor devices such as metal contacts, trench isolation, gates, bit lines, or any other interconnect features. The substrate 205 may comprise one or more metal layers, one or more dielectric materials, semiconductor materials, and combinations thereof used to fabricate semiconductor devices. For example, the substrate 205 can include oxide materials, nitride materials, polysilicon materials, etc., depending on the application. In one embodiment where memory applications are desired, the substrate 205 can include silicon substrate material, oxide material, and nitride material, with or without polysilicon sandwiched therebetween.

[0036]

[0037] In some embodiments, substrate 205 includes a plurality of alternating oxide and nitride materials (i.e., oxide-nitride-oxide (ONO)) deposited on the surface of a substrate (not shown). In various embodiments, substrate 205 may include a plurality of alternating oxide and nitride materials, one or more oxide or nitride materials, a polysilicon or amorphous silicon material, an amorphous silicon alternating with an oxide, a polysilicon alternating with an oxide, an undoped silicon alternating with a doped silicon, an undoped polysilicon alternating with a doped polysilicon, or an undoped amorphous silicon alternating with a doped amorphous silicon. Substrate 205 may be any substrate or material surface on which a film process is performed. For example, substrate 205 may be a material such as crystalline silicon, silicon oxide, silicon oxynitride, silicon nitride, strained silicon, silicon germanium, tungsten, titanium nitride, doped or undoped polysilicon, doped or undoped silicon wafers, and patterned or unpatterned wafers, silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, low dielectric constant dielectrics, and combinations thereof.

[0037]

[0038] FIG. 2B is a diagram showing an electronic device 220 after forming an optional hard mask lower layer 222 on a capacitor mold 210. The hard mask lower layer 222 of some embodiments includes one or more of an amorphous silicon (a-Si) film or a carbon (C) film. In some embodiments, the hard mask lower layer 222 includes an amorphous silicon film. In some embodiments, the hard mask lower layer 222 includes a carbon film. The hard mask lower layer 222 of some embodiments is formed directly on the capacitor mold 210 without an intervening layer.

[0038]

[0039] An optional seed layer 224 formed on the hard mask lower layer 222 is shown. In some embodiments, the optional seed layer 224 is formed directly on the hard mask lower layer 222. In some embodiments, the optional seed layer 224 is formed directly on the capacitor mold 210 and the hard mask lower layer 222 is omitted. In one or more embodiments, the optional seed layer 224 contains boron. In some embodiments, the optional seed layer 224 has a thickness in the range of up to 100 Å, or from 10 Å to 100 Å, or from 20 Å to 60 Å.

[0039]

[0040] A ruthenium carbide hard mask 226 is formed on the capacitor mold 210. In the illustrated embodiment, the ruthenium carbide hard mask 226 is formed directly on the optional seed layer 224 on the hard mask lower layer 222. In some embodiments, the optional hard mask lower layer 222 and the optional seed layer 224 are omitted and the ruthenium carbide hard mask 226 is formed directly on the capacitor mold 210. In some embodiments, the hard mask lower layer 222 is omitted and the ruthenium carbide hard mask 226 is formed directly on the optional seed layer 224 formed on the capacitor mold 210.

[0040]

[0041] The ruthenium carbide hard mask 226 may be an amorphous material, a semi-crystalline material or a crystalline material. The hard mask may also be referred to as a carbon film doped with ruthenium. However, those skilled in the art will recognize that the term carbon film doped with ruthenium is interchangeable with a ruthenium carbide film and may depend on the level of crystallinity of the material.

[0041]

[0042] The ruthenium carbide hard mask 226 of some embodiments has a ruthenium composition of ruthenium in the range of 20 atomic % to 45 atomic %. In some embodiments, the composition of the ruthenium carbide hard mask 226 includes ruthenium in the range of greater than 0 atomic % to 50 atomic %, ruthenium in the range of 5 atomic % to 50 atomic %, ruthenium in the range of 10 atomic % to 45 atomic %, ruthenium in the range of 20 atomic % to 45 atomic %, or ruthenium in the range of 25 atomic % to 40 atomic %, or ruthenium in the range of 30 atomic % to 35 atomic %.

[0042]

[0043] The ruthenium carbide hard mask 226 of some embodiments has a hydrogen composition of hydrogen in the range of 2 atomic % to 20 atomic %. In some embodiments, the composition of the ruthenium carbide hard mask 226 includes hydrogen in the range of 5 atomic % to 15 atomic %, or hydrogen in the range of 8 atomic % to 12 atomic %. In some embodiments, the composition of the ruthenium carbide hard mask 226 includes hydrogen of 15 atomic % or less, hydrogen of 10 atomic % or less, or hydrogen of 5 atomic % or less.

[0043]

[0044] In some embodiments, the ruthenium carbide hard mask 226 includes ruthenium in the range of greater than 0 atomic % to 50 atomic % and hydrogen of 15 atomic % or less, with the balance being carbon. In some embodiments, the ruthenium carbide hard mask 226 includes ruthenium in the range of 10 atomic % to 45 atomic % and hydrogen of 10 atomic % or less, with the balance being carbon. In some embodiments, the ruthenium carbide hard mask 226 includes ruthenium in the range of 20 atomic % to 45 atomic % and hydrogen in the range of 5 atomic % to 15 atomic %, with the balance being carbon. In some embodiments, the ruthenium carbide hard mask 226 includes ruthenium in the range of 20 atomic % to 45 atomic %, and hydrogen of 15 atomic % or less, 10 atomic % or less, or 5 atomic % or less, with the balance being carbon.

[0044]

[0045] The ruthenium carbide hard mask 226 of some embodiments has a thickness in the range of 500 Å to 4000 Å, or in the range of 1000 Å to 4000 Å, or in the range of 1500 Å to 3500 Å. In some embodiments, the thickness of the ruthenium carbide hard mask 226 is in the range of 2500 Å to 3500 Å. In some embodiments, the optional hard mask underlayer 222 has a thickness in the range of 100 Å to 500 Å, and the ruthenium carbide hard mask 226 has a thickness in the range of 2500 Å to 3400 Å. In some embodiments, the combination of the optional hard mask underlayer 222 and the ruthenium carbide hard mask 226 has a thickness in the range of 2500 Å to 3500 Å. In some embodiments, the thickness of the combination of the optional hard mask underlayer 222, the optional seed layer 224, and the ruthenium carbide hard mask 226 is in the range of 500 Å to 4000 Å.

[0045]

[0046] In the illustrated embodiment, a hard mask oxide 228 is formed on the ruthenium carbide hard mask 226. The hard mask oxide 228 may be any suitable material known to those skilled in the art that has an etching selectivity with respect to the ruthenium carbide hard mask 226. The hard mask oxide 228 of some embodiments has a thickness in the range of 500 Å to 1500 Å.

[0046]

[0047] In the illustrated embodiment, an advanced patterning film (APF) 230 is formed on the hard mask oxide 228. The advanced patterning film 230 of some embodiments includes a carbon film or a diamond-like carbon film. In some embodiments, the advanced patterning film 230 has a thickness in the range of 500 Å to 1500 Å. In some embodiments, the advanced patterning film 230 has a thickness greater than 0 Å and less than or equal to 1500 Å, or a thickness of 1000 Å.

[0047]

[0048] A dielectric anti-reflection coating (DARC) 232 is formed on the advanced patterning film 230. The DARC 232 can be formed by any suitable technique known to those skilled in the art. The dielectric anti-reflection coating 232 of some embodiments includes silicon oxynitride (SiON). In some embodiments, the DARC 232 has a thickness in the range of 250 Å to 500 Å. In some embodiments, the DARC 232 has a thickness greater than 0 Å and less than or equal to 500 Å.

[0048]

[0049] A bottom anti-reflection coating (BARC) 234 is formed on the DARC 232. The BARC 234 can be formed by any suitable technique known to those skilled in the art. In some embodiments, the BARC 234 has a thickness in the range of 100 Å to 500 Å.

[0049]

[0050] A photoresist 236 is formed on the BARC 234. The photoresist 236 can be deposited by any suitable technique known to those skilled in the art. The photoresist 236 is patterned by any suitable technique (e.g., lithography) to form a patterned photoresist, exposing the upper surface 235 of the BARC 234. In some embodiments, the photoresist 236 is an energy-sensitive resist material, and the energy-sensitive resist material is exposed to UV radiation through a patterning device such as a mask (not shown), and then the energy-sensitive resist material is developed with a suitable developer to be patterned. After the energy-sensitive resist material is developed, a defined pattern of through openings 237 is present in the photoresist 236.

[0050]

[0051] FIG. 2C is a diagram showing the electronic device 220 after the pattern of the photoresist 236 has been transferred to the antireflection coatings 232, 234, the advanced patterning film 230, the hard mask oxide 228, and the ruthenium carbide hard mask 226. In some embodiments, by transferring the pattern of the photoresist 236, the photoresist 236, the BARC 234, the DARC 232, and the advanced patterning film 230 are removed, leaving the patterned hard mask oxide 248 and the patterned ruthenium carbide hard mask 246. In the illustrated embodiment, pattern transfer also forms the patterned hard mask lower layer 242 and the patterned seed layer 244. In some embodiments, an optional hard mask lower layer 222 and an optional seed layer 224 are present and are not patterned by the ruthenium carbide hard mask 226.

[0051]

[0052] Pattern transfer in some embodiments is performed by exposing the substrate to an etchant plasma using the photoresist 236 as a mask. The etchant plasma of some embodiments includes an oxygen (O2) content and a chlorine (Cl2) content. The chlorine content of the etchant plasma of some embodiments ranges from 5% to 15% of the oxygen content on a molar basis. In some embodiments, the chlorine content of the etchant plasma is 15% or less, 10% or less, or 5% or less of the oxygen content on a molar basis.

[0052]

[0053] In some embodiments, the etchant plasma includes carbonyl sulfide (COS). The COS content of some embodiments ranges from 1% to 10% of the oxygen content on a molar basis.

[0053]

[0054] In some embodiments, the etchant plasma includes oxygen, chlorine, and carbonyl sulfide. The composition of the etchant plasma of some embodiments is 1% to 10% COS and 5% to 15% Cl2 on a molar basis based on the amount of O2.

[0054]

[0055] In some embodiments, the photoresist 236, the antireflective coatings 232, 234, and the advanced patterning film 230 are removed simultaneously with the pattern transfer. In some embodiments, one or more of the photoresist 236, the antireflective coatings 232, 234, or the advanced patterning film 230 remain after the pattern transfer and are removed in a separate process.

[0055]

[0056] FIG. 2D is a diagram showing an embodiment of the electronic device 240 after transferring a pattern to the capacitor mold 210 to form an electronic device 260 having a patterned capacitor mold 262. The patterned capacitor mold 262 in the illustrated embodiment includes a patterned silicon oxide layer 264 and a patterned second layer 266.

[0056]

[0057] FIG. 2D is a diagram showing the electronic device 240 after removing the patterned hard mask oxide 248, the patterned ruthenium carbide hard mask 246, the patterned optional seed layer 244, and the patterned optional hard mask underlayer 242. The patterned hard mask oxide 248, the patterned ruthenium carbide hard mask 246, the patterned optional seed layer 244, and the patterned optional hard mask underlayer 242 can be removed simultaneously with the pattern transfer to the capacitor mold 210 or in one or more separate processes. In some embodiments, a plasma containing oxygen and chlorine is used to remove the patterned ruthenium carbide hard mask 246, the patterned optional seed layer 244, and the patterned optional hard mask underlayer 242.

[0057]

[0058] As used throughout this specification, the terms "one embodiment", "a particular embodiment", "one or more embodiments", or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one or more embodiments", "in a particular embodiment", "in one embodiment", or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment of the present disclosure. Further, in one or more embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner.

[0058]

[0059] Although the disclosure of this specification has been described with reference to particular embodiments, those skilled in the art will understand that the described embodiments are merely examples of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and changes can be made to the methods and apparatuses of the present disclosure without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure may include modifications and changes that fall within the scope of the appended claims and their equivalents.

Claims

1. Depositing a ruthenium carbide hard mask on a capacitor mold formed on a substrate; Forming a hard mask oxide on the ruthenium carbide layer; Forming a patterned photoresist on the hard mask oxide; Transferring the pattern of the patterned photoresist to the ruthenium carbide hard mask to form a patterned ruthenium carbide hard mask; A method comprising the above steps.

2. The method according to claim 1, wherein the ruthenium carbide hard mask contains ruthenium in the range of 20 atomic % to 45 atomic %.

3. The method according to claim 2, wherein the ruthenium carbide hard mask contains 15 atomic % or less of hydrogen.

4. The method according to claim 1, further comprising transferring the pattern of the patterned ruthenium carbide hard mask to the capacitor mold.

5. The method according to claim 4, further comprising etching the patterned ruthenium carbide hard mask from the capacitor mold.

6. The method according to claim 1, wherein transferring the pattern of the patterned photoresist to the ruthenium carbide hard mask includes exposing the substrate to an etchant plasma containing oxygen and chlorine.

7. The method according to claim 6, wherein the chlorine content is 15% or less of the oxygen content on a molar basis.

8. The method according to claim 7, wherein the etchant plasma further contains carbonyl sulfide.

9. The method according to claim 8, wherein the carbonyl sulfide content is 10% or less of the oxygen content on a molar basis.

10. The method according to claim 1, wherein the ruthenium carbide hard mask has a thickness in the range of 500 Å to 4000 Å.

11. The method according to claim 1, further comprising forming one or more of a carbon film or an amorphous silicon film between the capacitor mold and the ruthenium carbide hard mask on the capacitor mold.

12. The method according to claim 11, wherein the combination of the carbon film, the amorphous silicon film and the ruthenium carbide hard mask has a thickness in the range of 500 Å to 4000 Å.

13. The method according to claim 1, wherein the capacitor mold includes a silicon oxide (SiO) layer.

14. The method according to claim 13, wherein the capacitor mold further includes a silicon carbonitride (SiCN) layer or a silicon nitride (SiN) layer on the silicon oxide (SiO) layer.

15. The method according to claim 14, wherein the silicon oxide (SiO) layer has a maximum thickness of 3 μm and the SiCN layer has a maximum thickness of 1000 Å.

16. Forming a capacitor mold on a substrate, the capacitor mold including a silicon oxide (SiO) layer and a silicon carbonitride (SiCN) layer or a silicon nitride (SiN) layer on the silicon oxide (SiO) layer, the silicon oxide (SiO) layer having a thickness in the range of 1 μm to 3 μm, and the SiCN layer or the SiN layer having a maximum thickness of 1000 Å; Optionally, depositing one or more of an amorphous silicon film or a carbon film directly on the capacitor mold; Depositing a ruthenium carbide hard mask on the capacitor mold and, if present, on the optional amorphous silicon film or carbon film, the ruthenium carbide hard mask containing ruthenium in the range of 20 atomic % to 45 atomic % and hydrogen in the range of 5 atomic % to 15 atomic %, and the total thickness of the optional amorphous silicon film or carbon film and the ruthenium carbide hard mask being in the range of 2500 Å to 3500 Å; Forming a hard mask oxide on the ruthenium carbide layer; Forming an anti-reflection coating including one or more of a dielectric anti-reflection coating (DARC) or a bottom anti-reflection coating (BARC) on the hard mask oxide; Forming a photoresist having a pattern on the anti-reflection coating; To form a patterned hard mask oxide and a patterned ruthenium carbide hard mask and to remove the antireflection coating, the pattern of the photoresist is transferred to the antireflection coating, the hard mask oxide, and the ruthenium carbide hard mask by exposing the substrate to an etchant plasma containing oxygen, chlorine, and carbonyl sulfide, wherein the chlorine content ranges from 5% to 15% of the oxygen content on a molar basis, and the carbonyl sulfide content ranges from 5% to 10% of the oxygen content on a molar basis, and transferring the pattern of the photoresist, Removing the residual photoresist and the antireflection coating to leave the patterned hard mask oxide and the patterned ruthenium carbide hard mask, Optionally, transferring the pattern of the patterned hard mask oxide and the patterned ruthenium carbide hard mask to the optional amorphous silicon film or carbon film A method comprising.

17. A capacitor mold, A ruthenium carbide hard mask on the capacitor mold, A hard mask oxide on the ruthenium carbide hard mask, And a patterned photoresist on the hard mask oxide A film stack comprising.

18. The film stack according to claim 17, wherein the ruthenium carbide hard mask contains ruthenium in the range of 20 atomic % to 45 atomic % and hydrogen of 15 atomic % or less, and the balance is carbon.

19. The film stack according to claim 17, wherein the ruthenium carbide hard mask has a thickness in the range of 500 Å to 4000 Å.

20. The film stack according to claim 17, further comprising one or more of a carbon film or an amorphous silicon film between the capacitor mold and the ruthenium carbide hard mask on the capacitor mold, and the combination of the carbon film, the amorphous silicon film, and the ruthenium carbide hard mask has a thickness in the range of 500 Å to 4000 Å.

Images