Method for depositing a silicon-based dielectric film

Abstract

A method for forming a high aspect ratio structure within a 3D NAND structure is provided. The method includes supplying a precursor to a high aspect ratio opening disposed within a multilayer stack having two or more alternating layers. The precursor is selected from the group consisting of diamino silanes, amino silanes, and combinations thereof. The method includes supplying an oxygen-containing compound to the high aspect ratio opening. The precursor and the oxygen-containing compound are periodically and alternately arranged to fill the high aspect ratio opening.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to chemistries and methods for forming high aspect ratio features that are substantially void and seam free.

Background Art

[0002] Memory devices achieve increased capacity through density scaling that involves vertically stacking memory cells in layers. These high aspect ratio structures pose various processing challenges, particularly in large area gap filling. Currently, large area gap filling is performed using a plasma enhanced chemical vapor deposition process that deposits a silicon-containing film. Conventional PECVD processes tend to have issues with seams and voids in addition to conformality issues. Subsequently, the silicon-containing film is etched to form memory openings, filled with a conductive metal, and connections are formed. When forming the connections, cracks and other defects that can cause problems in downstream processes may occur.

[0003] Accordingly, there is a need for a process and chemistry for large area gap filling that enables high throughput and high quality devices with structures that are substantially void and seam free.

Summary of the Invention

[0004] In some embodiments, a method for forming a high aspect ratio structure within a 3D NAND structure is provided. The method includes supplying a precursor to a high aspect ratio opening disposed within a multilayer stack having two or more alternating layers. The precursor is selected from the group consisting of diamino silanes, amino silanes, and combinations thereof. The method includes supplying an oxygen-containing compound to the high aspect ratio opening. The precursor and the oxygen-containing compound are periodically and alternately arranged to fill the high aspect ratio opening.

[0005] In some embodiments, a method of forming a 3D NAND structure is provided. The method includes supplying a precursor into high aspect ratio openings disposed within a multilayer stack having two or more alternating layers. The precursor is selected from the group consisting of diamino silanes, amino silanes, and combinations thereof. The method includes supplying an oxygen-containing plasma into the high aspect ratio openings. The precursor and the oxygen-containing plasma are periodically and alternately arranged to fill the high aspect ratio openings with a silicon-containing material. The method includes etching the openings within the silicon-containing material.

[0006] In some embodiments, a method of forming a 3D NAND structure on a substrate is provided. The method includes a step of supplying a precursor into high aspect ratio openings disposed within a multilayer stack having two or more alternating layers, wherein the precursor includes diamino silane. The method includes supplying an oxygen-containing plasma into the high aspect ratio openings. The precursor and the oxygen-containing plasma are periodically and alternately arranged to fill the high aspect ratio openings with a silicon-containing material. The high aspect ratio openings include an aspect ratio of about 10:1 or greater.

[0007] To better understand the above features of the present disclosure, a more specific description of the present disclosure briefly summarized above can be obtained by referring to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only exemplary embodiments and should not be considered as limiting the scope thereof, and other equally effective embodiments may be permitted.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

[0009] For ease of understanding, wherever possible, the same reference numbers are used to denote the same elements common to the figures. It is contemplated that the elements and features of one embodiment can be beneficially incorporated into other embodiments without further recitation.

[0010] In recent years, high-density storage devices including three-dimensional (3D) stacked memory structures have been developed. For example, a 3D NAND stacked memory device can be formed from an array of alternating vertical stacks of dielectric materials and conductive layers (e.g., tungsten-containing layers). A staircase structure can be formed in the alternating vertical stacks of dielectric materials using an etching process. During the etching process used to form the staircase structure, large-area high aspect ratio openings are formed. In some embodiments, the large-area high aspect ratio openings have a depth of from about 10 μm to about 15 μm and a width of from about 1 μm to about 2 μm. In some embodiments, the aspect ratio of the openings is from about 5:1 to about 50:1, such as from about 10:1 to about 20:1. The high aspect ratio openings are filled with a dielectric material such as a silicon-containing material.

[0011] A memory opening is formed that extends vertically through silicon-containing materials and dielectric material-containing layers in an alternating stack, exposing a portion of the conductive layer. The memory openings have various depths within the alternating stack structure. The memory openings are ultimately filled with a conductive material to form connections with the exposed portions of each conductive layer of each layer of the alternating stack. The conductive layers within the alternating stack can function as word lines of a 3D NAND stacked memory device, and bit lines over an array of the memory stack structure can be connected to the drain-side end of the semiconductor channel. During etching and filling of the memory openings with the conductive material, cracks and defects may occur along the connections, particularly at the bottom and top of the connections. Without being bound by theory, it is believed that cracks and defects may occur when the silicon-containing material has tensile stress. It has been discovered that depositing the silicon-containing material using the processes described herein provides large-area gap filling with compressive stress. The compressibility of the silicon-containing material enables the formation of the memory openings and connections without cracks.

[0012] Furthermore, filling large areas (e.g., large area gap filling) with silicon-containing materials can form voids and seams, which may cause quality problems such as cracks and shrinkage in the memory device during downstream processing. The processes described herein optimize large area gap filling while reducing the potential for shrinkage and stress and improving the quality of the film. The methods described herein use a diamino silane precursor, an amino silane precursor, or a combination thereof in an atomic layer deposition process to deposit a silicon-containing material such as a silicon-based dielectric film. In particular, a 3D NAND structure can be formed by stacking alternating films and forming channels through the stack of alternating films. Conventional methods for filling high aspect ratio openings with silicon-containing materials include using a plasma enhanced chemical vapor deposition (PECVD) process. Films deposited by conventional methods typically have tensile properties and cause cracks in the device after subsequent processing such as during etching and formation of metal connections. It has been discovered that the chemistry and use of atomic layer deposition (ALD) described herein enables the deposition of films that have compressibility and are less prone to cracking. The resulting devices maintain structural integrity even after further processing.

[0013] FIG. 1 shows a process flow diagram of an exemplary method 100 according to some embodiments. Method 100 includes, at operation 102, supplying a precursor to a high aspect ratio opening. The precursor includes a diaminosilane, an aminosilane, or a combination thereof. The precursor is pulsed for between about 200 milliseconds (ms) and about 1200 ms, such as between about 400 ms and about 1000 ms. In some embodiments, the precursor is flowed at a rate of between about 350 mg / m and about 1400 mg / m, such as between about 400 mg / m and about 1200 mg / m, such as between about 500 mg / m and about 1000 mg / m, such as between about 600 mg / m and about 800 mg / m. In some embodiments, the precursor is supplied as a mixture with a carrier gas such as argon gas. The total flow rate of the mixture is between about 1500 sccm and about 2500 sccm, such as between about 1700 sccm and about 2300 sccm. The temperature of the substrate is maintained between about 350° C. and about 650° C., such as between about 450° C. and about 550° C. The pressure is between about 2 torr and about 10 torr, such as between about 4 torr and about 8 torr. As used herein, all flow rates and process conditions provided are for a chamber that processes a substrate having a substrate diameter of about 300 nm. Other process condition ranges are contemplated and can be adjusted for other process chamber sizes.

[0014] In operation 106, the method includes supplying an oxygen-containing compound to a high aspect ratio opening. In some embodiments, the oxygen-containing compound is an oxygen-containing plasma supplied from a remote plasma source. Oxygen (O2) gas is provided to the remote plasma source at a flow rate of about 1000 sccm to about 3000 sccm, such as about 1500 sccm to about 2500 sccm, such as about 2000 sccm to about 2250 sccm. In some embodiments, the carrier gas is supplied to the high aspect ratio opening at a rate of about 0 sccm to about 3000 sccm, such as about 100 sccm to about 2000 sccm, such as about 500 sccm to about 1000 sccm. It has been found that supplying the oxygen-containing compound from a remote plasma source improves film quality and reduces seams within the filled openings. The oxygen-containing compound may include O3 (e.g., ozone), H2O2 (e.g., hydrogen peroxide), oxygen plasma, or combinations thereof.

[0015] In some embodiments, the oxygen-containing compound is pulsed for about 2 seconds to about 10 seconds, such as about 2 seconds to about 8 seconds, such as about 4 seconds to about 6 seconds. In some embodiments, the time pulse ratio of the precursor to the oxygen-containing plasma is about 1:100 to about 1:2, such as about 1:20 to about 1:5, such as about 1:12 to about 1:8, such as about 1:10 to about 1:7. The power source coupled to the remote plasma source excites the gas supplied to the remote plasma source with a power of about 100 W to about 300 W, such as about 200 W to about 250 W, and a frequency of about 2 MHz to about 60 MHz, such as about 13 MHz to about 60 MHz, such as 13.56 MHz, or about 27 MHz, or about 40 MHz, or about 60 MHz. It has been discovered that adjusting the power and frequency applied to the plasma, such as using increased power and frequency during processing and oxidation, can fill high aspect ratio openings with a gap filler that is substantially void-free and substantially seam-free. Without being bound by theory, increasing the power and frequency is thought to generate more radicals required for the reaction to deposit the film and increase the growth per cycle of the deposit, such as when the growth per cycle begins to decrease.

[0016] Operations 102 and 106 are periodically and alternately arranged, for example, in an atomic layer deposition process, to fill high aspect ratio openings. Method 100 can be combined with a PECVD process to increase the gap filling rate of the openings. In some embodiments, about 10% to about 50% of the total thickness of the gap filling of the opening is deposited using PECVD. For example, about 20% to about 30% is then deposited using ALD deposition for the remaining thickness. Method 100 can be used for any high aspect ratio opening of various semiconductor devices. In some embodiments, at any operation 104, any operation 108, a purge gas is supplied to the opening between each pulse. The purge gas can be a non-reactive gas such as a nitrogen-containing gas (e.g., diatomic nitrogen), an argon-containing gas (e.g., argon), or a combination thereof. As used herein, a process cycle includes operation 102, operation 106, and any operation 104, any operation 108 between each operation 102 and 106. The processes described herein provide film deposition growth of about 1.5 Å per cycle to about 3 Å per cycle, for example, about 1.75 Å per cycle to about 2.25 Å per cycle. In some embodiments, the substrate is maintained at a temperature of about 100 °C to about 450 °C, for example, about 150 °C to about 350 °C, for example, about 200 °C to about 325 °C during one or more of operations 102, 104, 106, 108. In some embodiments, the chamber is maintained at a pressure of about 2 torr to about 10 torr, for example, about 4 torr to about 8 torr. Without being bound by theory, an increase in the temperature of the substrate is thought to increase the compressive strength of the deposited silicon-containing gap filling material.

[0017] In some embodiments, the deposited film (e.g., the gap-fill material) has a film conformality of about 98% to about 100%. In some embodiments, the deposited film has a shrinkage of less than 15%, such as about 0.1% to about 5%, such as about 1% to about 3%, or about 7% to about 10%, etc. As used herein, "shrinkage" refers to the percent reduction in dimensions such as the width or thickness of the deposited film after annealing at a temperature of about 850 °C for about 1 hour. Shrinkage can be measured in the horizontal and / or vertical directions.

[0018] Figure 2 shows a memory device 200 having a staircase structure 200 before depositing a gap-fill material (e.g., a silicon-containing material) according to some embodiments described herein. In some embodiments, the substrate 225 includes a multilayer stack 201 that includes a plurality of conductive layers 220 and a plurality of intervening dielectric material layers disposed therebetween. In some embodiments, the multilayer stack 201 includes more than about 100 layers, such as more than about 150 layers, in the case of a 3D NAND structure. The large-area high aspect ratio opening 203 is disposed adjacent to and above a portion of the multilayer stack 201.

[0019] In some embodiments, the conductive layers 220 disposed within the dielectric material 210 of the multilayer stack 201 can consist of tungsten, platinum, titanium, ruthenium, silicon, molybdenum, cobalt, and hafnium. Each of the memory openings 215 can be filled using any method known in the art, such as PECVD or ALD.

[0020] Figure 3 shows a first view (e.g., in the X-Y plane) of a memory device 300 having a staircase structure after a gap-fill material 315 has been deposited in a high aspect ratio opening according to some embodiments described herein.

[0021] FIG. 4 shows a second view (e.g., on the Y-Z plane) of the memory device 300 after the gap filling material 315 has been deposited in the high aspect ratio opening 203. As used herein, the term "high aspect ratio opening" refers to an opening having a ratio of maximum depth 404 to minimum width 402 of about 2:1 or greater, e.g., about 10:1 or greater, e.g., about 20:1 or greater, e.g., about 30:1 to about 1000:1, e.g., about 200:1 to about 500:1. In some embodiments, the high aspect ratio opening has a width of about 1 μm to about 2 μm and a depth of about 10 μm to about 12 μm.

[0022] In some embodiments, the gap filling material 315 comprises one or more of silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), and silicon oxycarbide (SiOC). The gap filling material 315 is substantially void and seam free. The silicon-containing gap filling material 315 can have good compressibility, high conformality, and low shrinkage. The stress can be about 200 MPa to about 350 MPa, e.g., about 225 MPa to about 325 MPa.

[0023] In some embodiments, the silicon-containing gap filling process 100 described herein enables the deposition of the silicon-containing gap filling material 315 to a thickness of about 800 nm using about 3000 cycles to about 4000 cycles. As used herein, growth per cycle refers to the thickness deposited per cycle of operation 102, any of operations 104, 106, and any of operation 108. In some embodiments, the growth per cycle at the first duration is greater than the growth per cycle at the second duration after the first duration. In some embodiments, the precursor rate, gas ratio, or a combination thereof is adjusted to adjust the growth per cycle.

[0024] FIG. 5 shows a memory device 500 having a staircase structure, a gap fill material 315, and a memory opening 215, according to some embodiments described herein. The mask layer 205 includes a pre-etching pattern formed based on a predetermined specification using a lithography and mask etching process. The patterned mask layer 205 guides the formation of features such as the memory opening 215 through the gap fill material 315. The multilayer stack 201 includes a plurality of conductive layers 220, which form an alternating arrangement such that each of the memory openings 215 reaches a respective one of the conductive layers 220 located at different depths (Z direction shown in FIG. 4) within the multilayer stack 205. Each of the memory openings 215 is formed using a plasma etching process according to the pattern formed in the mask layer 205, has different depths, and contacts different conductive layers 220. Each of the memory openings 215 formed during the plasma etching process also does not extend through the corresponding conductive layer 220. In some embodiments, the memory opening 215 is formed using a fluorocarbon radical plasma etching process. Although not shown in the figure, the memory opening 215 can be filled with a conductive material such as copper, tungsten, or a combination thereof to form a connection. The connection is substantially free of cracks and defects.

[0025] In some embodiments, the diaminosilane and / or the aminosilane precursor is supplied to the high aspect ratio opening 203. The diaminosilane and / or the aminosilane precursor can be co-reacted with an oxygen-containing gas such as ozone, peroxide, oxygen-containing plasma, or a combination thereof. In some embodiments, the precursor comprises a component having the formula R2-Si-Si-R2, wherein each R is independently a group comprising a carbon-containing group, a hydrogen-containing group, an oxygen-containing group, a nitrogen-containing group, a silicon-containing group, or a combination thereof. In some embodiments, one or more Rs independently comprise an isopropyl group, a butyl group, an amine group, or a combination thereof. In some embodiments, the precursor comprises silane, disilane, trisilane, tetrasilane, and combinations thereof. In some embodiments, one or more Rs independently comprise an isopropylamine group and a silane group having a structure represented by Formula I.

[0026]

Chemical formula

[0027] In some embodiments, one or more R groups independently comprise a diisopropylamino group such as 1,2-bis(diisopropylamino)disilane (e.g., BDIPADS).

[0028]

Chemical formula

[0029] Without being bound by theory, additional silicon atoms in the precursor, such as two, three, or four silicon atoms, are thought to enable enhanced growth per cycle by increasing the reactivity of the precursor. A further molar concentration of silicon in the molecule of the precursor allows for a decreased amount of the precursor to be used to deposit the film.

[0030] In some embodiments, the precursor comprises a compound having the formula (R3Si)3N, wherein each R is independently a group comprising a carbon-containing group, a hydrogen-containing group, an oxygen-containing group, a nitrogen-containing group, a silicon-containing group, or a combination thereof. In some embodiments, each R independently comprises a propyl group, an isopropyl group, a butyl group, an amine group, or a combination thereof. In some embodiments, the precursor comprises a tris(trialkylsilyl)amine, such as tris(trimethylsilyl)amine, trisylylamine, or a combination thereof.

[0031] In some embodiments, the precursor comprises a component having the formula SiR4, wherein each R is independently a group comprising a carbon-containing group, a hydrogen-containing group, an oxygen-containing group, a nitrogen-containing group, a silicon-containing group, or a combination thereof. In some embodiments, each R independently comprises hydrogen, a propyl group, an isopropyl group, a butyl group, an amine group, or a combination thereof. In some embodiments, the precursor comprises tetraethyl orthosilicate (TEOS) (e.g., tetraethyl silicate), silane, disilane, trisilane, tetrasilane, or a combination thereof.

[0032] In some embodiments, the precursor includes a component having the formula R2Si-NR2, such as a silylamine, where each R is independently a group containing a carbon-containing group, such as a branched or linear group, a hydrogen-containing group, an oxygen-containing group, a nitrogen-containing group, a silicon-containing group, or a combination thereof. In some embodiments, one or more Rs independently include hydrogen, a propyl group, an isopropyl group, a butyl group, an amine group, or a combination thereof. In some embodiments, the precursor is one or more of the following compounds: N-isopropyltrisilane-1-amine, N-isopropyl-N’,N’-disilylsilanediamine, 1,1-dimethoxy-N,N,N’,N’-tetramethylsilanediamine, 1,1-diethoxy-N,N,N’,N’-tetramethylsilanediamine, N,N-dimethylsilanamine, N,N-diethylsilanamine, N,N-dipropylsilanamine, N,N-diisopropylsilanamine, N,N-dibutylsilanamine, N,N-di-tert-butylsilanamine, tetramethylsilanediamine, N,N,N’,N’-tetraethylsilanediamine, N,N,N’,N’-tetraisopropylsilanediamine, N,N,N’,N’-tetrapropylsilanediamine, N,N,N’,N’-tetrabutylsilanediamine, N,N,N’,N’-tetra-tert-butylsilanediamine.In some embodiments, the precursor includes N,N-di-sec-butylsilanamine, N,N'-dimethylsilanediamine, N,N'-diethylsilanediamine, N,N'-dibutylsilanediamine, N,N'-dipropylsilanediamine, N,N'-diisopropylsilanediamine, N,N'-di-tert-butylsilanediamine, N,N,N',N',N",N"-hexaethylsilanetriamine, N,N,N',N',N",N"-hexaisopropylsilanetriamine, N,N,N',N',N",N"-hexapropylsilanetriamine, N,N,N',N',N",N"-hexamethylsilanetriamine, N,N,N',N',N",N"-hexabutylsilanetriamine, N,N,N',N',N",N"-hexa-tert-butylsilanetriamine, N,N',N"-tripropylsilanetriamine, N,N',N"-tributylsilanetriamine, N,N',N"-triethylsilanetriamine, N,N',N"-triisopropylsilanetriamine, N,N',N"-tri-tert-butylsilanetriamine, N,N',N"-trimethylsilanetriamine, N,N,N',N',N",N",N''',N'''-octamethylsilanetetraamine, N,N,N',N',N",N",N''',N'''-octaisopropylsilanetetraamine, N,N,N',N',N",N",N''',N'''-octa-tert-butylsilanetetraamine, N,N,N',N',N",N",N''',N'''-octapropylsilanetetraamine, N,N',N",N'''-tetraethylsilanetetraamine, N,N,N',N',N",N",N''',N'''-octabutylsilanetetraamine, N,N',N",N'''-tetra-tert-butylsilanetetraamine, N,N,N',N',N",N",N''',N'''-octaethylsilanetetraamine, N,N',N",N'''-tetramethylsilanetetraamine, N,N',N",N'''-tetraisopropylsilanetetraamine, N,N',N",N'''-tetrapropylsilanetetraamine, and N,N',N",N'''-tetrabutylsilanetetraamine. In some embodiments, the precursor includes the compound N,N-di-sec-butylsilanamine having a structure represented by Formula III.

[0033]

Chem.

[0034] The methods and precursor chemistries described herein enable large area gap fill of 3D NAND devices. The deposited large area gap fill material comprises a compressible silicon-containing film that is substantially void and seam free. The compressible film can be etched to form openings, which can then be filled with a conductive material to form connections. The connections are formed without cracking within the silicon-containing film and are substantially defect free. The methods also reduce the amount of precursor required to fill large area gaps as compared to conventional methods.

[0035] The above is directed to embodiments of the present disclosure, but other and further embodiments of the present disclosure can be devised without departing from the basic scope thereof, which is determined by the claims that follow.

Claims

1. A method for forming a high aspect ratio structure within a 3D NAND structure, comprising: supplying a precursor to a high aspect ratio opening disposed within a multilayer stack having two or more alternating layers, the precursor being selected from the group consisting of diamino silanes, amino silanes, and combinations thereof; supplying an oxygen-containing compound to the high aspect ratio opening, the precursor and the oxygen-containing compound being periodically and alternately arranged to fill the high aspect ratio opening; A method comprising the above steps.

2. The method of claim 1, wherein the multilayer stack comprises a plurality of conductive layers alternately arranged with a plurality of dielectric layers.

3. The method of claim 1, wherein the precursor comprises a compound having a structure. 【Chemical 1】

4. The method of claim 1, wherein the precursor comprises a compound having a structure. 【Chemical 2】

5. wherein the precursor further contains a component having the formula R 2 -Si-Si-R 2 The method according to claim 1. (wherein each R is independently a group containing a carbon-containing group, a hydrogen-containing group, an oxygen-containing group, a nitrogen-containing group, a silicon-containing group, or a combination thereof)

6. wherein the precursor further contains a component having the formula R 2 -Si-Si-R 2 The method according to claim 1. (wherein one or more Rs independently comprise an isopropyl group, a butyl group, an amine group, or a combination thereof)

7. The method of claim 1, wherein the precursor further comprises silane, disilane, trisilane, tetrasilane, and combinations thereof.

8. The method of claim 1, wherein the ratio of the high aspect ratio opening is about 10:1 or more.

9. The method of claim 1, wherein filling the high aspect ratio opening further comprises forming a silicon-containing material selected from the group consisting of silicon germanium (SiGe), silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC), and combinations thereof.

10. wherein the oxygen-containing compound is O 3 (for example, ozone), H 2 O 2 (for example, hydrogen peroxide), oxygen plasma, and combinations thereof, the method according to claim 1.

11. A method for forming a 3D NAND structure, comprising: supplying a precursor to a high aspect ratio opening disposed within a multilayer stack having two or more alternating layers, the precursor being selected from the group consisting of diamino silanes, amino silanes, and combinations thereof; supplying an oxygen-containing plasma to the high aspect ratio opening, the precursor and the oxygen-containing plasma being periodically and alternately arranged to fill the high aspect ratio opening with a silicon-containing material; etching an opening within the silicon-containing material. A method comprising...

12. The method according to claim 11, wherein the oxygen-containing plasma is pulsed for about 2 seconds to about 10 seconds.

13. The method according to claim 11, wherein the time pulse ratio of the precursor to the oxygen-containing plasma is from about 1:20 to about 1:

5.

14. The method according to claim 11, wherein the oxygen-containing plasma is provided from a remote plasma source coupled to a power supply, and the gas supplied to the remote plasma source is excited with a power of about 100 W to about 300 W and a frequency of about 13 MHz to about 60 MHz.

15. The method according to claim 11, wherein etching the opening in the silicon-containing material comprises a fluorocarbon radical plasma etching process.

16. A method of forming a 3D NAND structure on a substrate, comprising: supplying a precursor to a high aspect ratio opening disposed within a multilayer stack having two or more alternating layers, the precursor comprising diaminosilane; supplying an oxygen-containing plasma to the high aspect ratio opening, the precursor and the oxygen-containing plasma being periodically and alternately arranged to fill the high aspect ratio opening with a silicon-containing material, the high aspect ratio opening having an aspect ratio of about 10:1 or more; A method comprising...

17. The method according to claim 16, further comprising maintaining a substrate temperature of about 100 °C to about 450 °C.

18. The method according to claim 16, wherein supplying the precursor and the oxygen-containing plasma is an atomic layer deposition process with a growth per cycle of about 1.5 Å to about 3 Å per cycle.

19. wherein the precursor contains a component having the formula R 2 Si—NR 2 The method according to claim 16, wherein the method comprises a component having the formula R (wherein each R is independently selected from the group consisting of carbon-containing groups such as branched or linear groups, hydrogen-containing groups, oxygen-containing groups, nitrogen-containing groups, silicon-containing groups, and groups comprising combinations thereof)

20. A multilayer stack comprising a plurality of conductive layers alternately arranged with a plurality of dielectric layers; a gap filling material disposed across and at least partially adjacent to the multilayer stack, having a stress of about 200 MPa to about 350 MPa; a conformality of about 98% to about 99%; a shrinkage of about 0.01% to about 10%, a gap filling material having one or more of...; a plurality of conductive connections disposed within the gap filling material; A memory device comprising...

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