Silicon-on-insulator semiconductor components and process platforms, and methods of manufacturing

Abstract

The present application relates to a silicon-on-insulator semiconductor component including a substrate, a buried dielectric layer, a first electrode, a second electrode, and a drift region, the buried dielectric layer being disposed on the substrate, the drift region being disposed on the buried dielectric layer, a stepped structure formed on an upper surface of the drift region, the stepped structure including a first side proximate to the first electrode, a second side proximate to the second electrode, and a transition region between the first and second sides, the upper surface of the second side being higher than the lower surface of the first side, such that a thickness of the drift region on the second side is greater than a thickness of the drift region on the first side, and the first and second electrodes being configured such that when a reverse bias voltage is applied to the component, a voltage applied to the second electrode is greater than a voltage applied to the first electrode.

Description

[Technical Field]

[0001] TECHNICAL FIELD This application relates to the field of semiconductor manufacturing, and more particularly to silicon-on-insulator semiconductor components, and further to silicon-on-insulator semiconductor process platforms and methods for manufacturing silicon-on-insulator semiconductor components. [Background technology]

[0002] This application claims priority to a Chinese patent application filed on June 15, 2023, application number 2023107131192, entitled "Silicon-on-insulator semiconductor component and process platform, and manufacturing method," the entire contents of which are incorporated herein by reference.

[0003] With the widespread application of ultra-large-scale integrated circuits (ULCs) in various fields, the development requirements for high-voltage, high-power semiconductor components in systems are becoming increasingly demanding. Integrated high-voltage components (e.g., LDMOS, LIGBT, and high-voltage diodes) using silicon-on-insulator (SOI) technology have been widely researched and applied due to the advantages of both SOI technology and the components themselves, including fast operating speed, low parasitic effects, high breakdown voltage, simple manufacturing process, and convenient integration. However, conventional silicon-on-insulator integrated high-voltage components have difficulty achieving breakdown voltages of 1200V and above. While the thickness of the buried oxide layer is related to breakdown voltage, a thick buried oxide layer reduces the thermal conductivity of the component. Furthermore, if the buried oxide layer is too thick, it does not contribute to breakdown voltage and increases costs. Therefore, once breakdown voltage reaches a certain value, it is not practical to continue increasing the buried oxide layer thickness to improve breakdown voltage. Summary of the Invention [Means for solving the problem]

[0004] A first aspect provides a silicon-on-insulator semiconductor component including a substrate, a buried dielectric layer, a first electrode, a second electrode, and a drift region, the buried dielectric layer being disposed on the substrate, the drift region being disposed on the buried dielectric layer, a stepped structure formed on an upper surface of the drift region, the stepped structure including a first side proximate to the first electrode, a second side proximate to the second electrode, and a transition region between the first and second sides, the upper surface of the second side being higher than the lower surface of the first side, such that a thickness of the drift region at the second side is greater than a thickness of the drift region at the first side, and the first and second electrodes being configured such that when a reverse bias voltage is applied to the component, a voltage applied to the second electrode is greater than a voltage applied to the first electrode.

[0005] In one embodiment, the component is a lateral double-diffused metal-oxide-semiconductor field effect transistor, the first electrode is a source, the second electrode is a drain, and the lateral double-diffused metal-oxide-semiconductor field effect transistor further includes a gate.

[0006] In one embodiment, the component is a lateral insulated gate bipolar transistor, the first electrode is an emitter, the second electrode is a collector, and the lateral insulated gate bipolar transistor further includes a gate.

[0007] In one embodiment, the component is a diode, the first electrode is an anode, and the second electrode is a cathode.

[0008] In one embodiment, the drop structure is a step structure and includes a first base surface located on the first side, a second base surface located on the second side, and a step wall located in the transition region, and the height difference between the second base surface and the first base surface is 3 to 10 microns.

[0009] In one embodiment, the inclination angle of the step wall is between 20 degrees and 90 degrees.

[0010] In one embodiment, the drift region has a first conductivity type, and the component further includes a protective layer of a second conductivity type, the protective layer of the second conductivity type being located in the drift region and surrounding a corner formed by the first plateau and the step wall and a corner formed by the second plateau and the step wall, and the first conductivity type and the second conductivity type being opposite conductivity types.

[0011] In one embodiment, the component further includes a first electrode lead region and a second electrode lead region, the first electrode lead region and the second electrode lead region being provided in the buried dielectric layer.

[0012] In one embodiment, the component further includes a field oxide layer extending from a second side of the top surface of the drift region adjacent to the second electrode to a first side adjacent to the first electrode.

[0013] In one embodiment, the component further includes an interlayer dielectric layer, the interlayer dielectric layer covering at least the field oxide layer, the first electrode lead-out region, and the second electrode lead-out region.

[0014] A second aspect provides a silicon-on-insulator semiconductor process platform including a silicon-on-insulator semiconductor component according to any of the above embodiments, and further including at least one of a complementary metal-oxide-semiconductor field effect transistor and a well resistor.

[0015] A third aspect provides a method for manufacturing a silicon-on-insulator semiconductor component, the method comprising: obtaining a wafer including a substrate, a buried dielectric layer on the substrate, and a drift region on the buried dielectric layer; forming by photolithography and etching a stepped structure on a top surface of the drift region, the stepped structure including a first side, a second side, and a transition region between the first and second sides, the top surface of the second side being higher than the bottom surface of the first side, such that a thickness of the drift region on the second side is greater than a thickness of the drift region on the first side; and forming a first electrode and a second electrode, the first side being one side adjacent to the first electrode and the second side being one side adjacent to the second electrode, the first electrode and the second electrode being configured such that when a reverse bias voltage is applied to the component, a voltage applied to the second electrode is greater than a voltage applied to the first electrode.

[0016] In one embodiment, the drop structure is a step structure and includes a first platform surface located on the first side, a second platform surface located on the second side, and a step wall located in the transition region, and before forming the first electrode and the second electrode, the method further includes forming a protective layer in a drift region of the step structure by ion implantation, and the protective layer surrounding a corner formed by the first platform surface and the step wall and a corner formed by the second platform surface and the step wall.

[0017] In one embodiment, the etching is a reactive ion etching process.

[0018] A fourth aspect provides a method for manufacturing another silicon-on-insulator semiconductor component, the method including the steps of: obtaining a wafer including a substrate, a buried dielectric layer on the substrate, and a first epitaxial layer on the buried dielectric layer; forming a second epitaxial layer on a portion of the first epitaxial layer and forming a step structure at a boundary between the first epitaxial layer and the second epitaxial layer, the step structure including a first side adjacent to the second epitaxial layer, a second side adjacent to the first epitaxial layer, and a transition region between the first side and the second side; and forming a first electrode and a second electrode, the first side being one side adjacent to the first electrode and the second side being one side adjacent to the second electrode, the first electrode and the second electrode being configured such that when a reverse bias voltage is applied to the component, a voltage applied to the second electrode is greater than a voltage applied to the first electrode.

[0019] The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the application will become apparent from the description, drawings, and claims. [Brief explanation of the drawings]

[0020] To better describe and illustrate the embodiments and / or examples of the invention disclosed herein, reference may be made to one or more drawings. Any additional details or examples used to illustrate the drawings should not be deemed to limit the scope of the disclosed invention, either of the presently described embodiments and / or examples, or of the best mode of such invention as currently understood. [Figure 1] 1 is a cross-sectional schematic view of a silicon-on-insulator semiconductor component in one embodiment where the component is an LDMOS. [Figure 2a] 1 is a cross-sectional schematic diagram of an SOI LDMOS with an integral protective layer formed in one embodiment. [Figure 2b] 1 is a cross-sectional schematic diagram of an SOI LDMOS having protective layers formed around two corners in one embodiment. FIG. [Figure 2c] FIG. 1 is a cross-sectional schematic diagram of an SOI LDMOS formed using a secondary epitaxial method in one embodiment. [Figure 3] 1 is a cross-sectional schematic view of a silicon-on-insulator semiconductor component in one embodiment where the component is a LIGBT. [Figure 4] 1 is a cross-sectional schematic diagram of a LIGBT formed using a secondary epitaxial method in one embodiment. [Figure 5] 2 is a cross-sectional schematic diagram of a diode in an embodiment in which the silicon-on-insulator semiconductor component is a diode. [Figure 6] FIG. 2 is a cross-sectional schematic diagram of a diode formed using a secondary epitaxial method in one embodiment. [Figure 7] 1 is a cross-sectional schematic view of a silicon-on-insulator semiconductor processing platform in accordance with one embodiment of the present application. [Figure 8] 1 is a flowchart of a method for manufacturing a silicon-on-insulator semiconductor component in one embodiment of the present application. [Figure 9] 1 is a flowchart of a method for manufacturing a silicon-on-insulator semiconductor component in accordance with another embodiment of the present application. [Figure 10] 10 is a flowchart of the steps between steps S420 and S430 in an embodiment in which the component being fabricated is an SOI LDMOS. [Figure 11a] 11A-11C are cross-sectional schematic diagrams of components during the manufacturing process of an SOI LDMOS according to the method shown in FIG. 10. [Figure 11b] 11A-11C are cross-sectional schematic diagrams of components during the manufacturing process of an SOI LDMOS according to the method shown in FIG. 10. [Figure 11c] 11A-11C are cross-sectional schematic diagrams of components during the manufacturing process of an SOI LDMOS according to the method shown in FIG. 10. [Figure 11d] 11A-11C are cross-sectional schematic diagrams of components during the manufacturing process of an SOI LDMOS according to the method shown in FIG. 10. [Figure 11e]11A-11C are cross-sectional schematic diagrams of components during the manufacturing process of an SOI LDMOS according to the method shown in FIG. 10. [Figure 12] 4 is a flow chart of the steps between steps S420 and S430 in an embodiment in which the component being manufactured is an SOI LIGBT. [Figure 13a] 13A-13C are cross-sectional schematic diagrams of components in the process of manufacturing an SOI LIGBT based on the method shown in FIG. 12. [Figure 13b] 13A-13C are cross-sectional schematic diagrams of components in the process of manufacturing an SOI LIGBT based on the method shown in FIG. 12. [Figure 13c] 13A-13C are cross-sectional schematic diagrams of components in the process of manufacturing an SOI LIGBT based on the method shown in FIG. 12. [Figure 13d] 13A-13C are cross-sectional schematic diagrams of components in the process of manufacturing an SOI LIGBT based on the method shown in FIG. 12. [Figure 13e] 13A-13C are cross-sectional schematic diagrams of components in the process of manufacturing an SOI LIGBT based on the method shown in FIG. 12. [Figure 14] 10 is a flow chart of the steps between steps S420 and S430 in an embodiment in which the component being fabricated is an SOI diode. [Figure 15a] 15A-15C are cross-sectional schematic diagrams of components during the manufacturing of an SOI diode according to the method shown in FIG. 14. [Figure 15b] 15A-15C are cross-sectional schematic diagrams of components during the manufacturing of an SOI diode according to the method shown in FIG. 14. [Figure 15c] 15A-15C are cross-sectional schematic diagrams of components during the manufacturing of an SOI diode according to the method shown in FIG. 14. [Figure 15d] 15A-15C are cross-sectional schematic diagrams of components during the manufacturing of an SOI diode according to the method shown in FIG. 14. [Figure 16] FIG. 1 is a cross-sectional schematic diagram of a silicon-on-insulator semiconductor processing platform in one embodiment using reactive ion etching to form a step structure in the drift region. [Figure 17]1 is a cross-sectional schematic diagram of a silicon-on-insulator semiconductor processing platform in one embodiment using secondary epitaxial growth to form a step structure in the drift region. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0021] To facilitate an understanding of the present invention, the present invention will now be described more fully hereinafter with reference to the associated drawings. Preferred embodiments of the present invention are illustrated in the drawings. However, the present invention may be embodied in many different forms and is not limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more complete disclosure of the present invention.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. The terms used herein are for the purpose of describing particular examples only and are not intended to limit the invention. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0023] When an element or layer is referred to as being "located on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly located on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. When an element or layer is referred to as being "directly located on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. In this specification, "connection" should be understood as "electrical connection," "communication connection," etc., when it involves the transmission of electrical signals or data between connected circuits, modules, units, etc. Note that terms such as first, second, and third may be used to describe various elements, components, regions, layers, and / or sections, but these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, component, region, layer or section described below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

[0024] Spatially relative terms such as "below," "below," "below," "beneath," "above," and the like may be used herein to readily describe the relationship of one element or feature to another element or feature shown in a figure. Note that spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if a device in a figure were inverted, an element or feature described as "below" or "beneath" or "beneath" another element or feature would be oriented as "above" the other element or feature. Thus, the exemplary terms "below" and "below" can include both an orientation of above and below. A device may be oriented differently (rotated 90 degrees or at another orientation), and the spatial terms used herein may be interpreted accordingly.

[0025] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present invention. As used herein, the singular forms "a," "one," and "said" are intended to include the plural forms unless the context clearly dictates otherwise. "At least one" can be understood to mean one or more, and "plurality" to mean two or more. "At least some of the elements" means some or all of the elements. It will be further understood that the terms "consisting of" and / or "including," as used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0026] Embodiments of the present invention are described herein with reference to cross sections that are schematic illustrations of idealized embodiments of the present invention (and intervening structures). As such, variations from the shapes depicted due, for example, to manufacturing techniques and / or tolerances are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of regions illustrated herein but should include deviations in shape that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle typically has rounded or curved features at its edges and / or an implant concentration gradient, rather than a binary transition from implanted to non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface where the implantation occurs. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to represent the actual shape of the region of a part, nor are they intended to limit the scope of the present invention.

[0027] The terms in the semiconductor field used in this specification are technical terms commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type indicates a P-type with a high doping concentration, P-type indicates a P-type with a medium doping concentration, P-type indicates a P-type with a low doping concentration, N+ type indicates an N-type with a high doping concentration, N-type indicates an N-type with a medium doping concentration, and N-type indicates an N-type with a low doping concentration.

[0028] In a typical SOI semiconductor process platform, integrated high-voltage components typically only achieve breakdown voltages of around 600V, with difficulty reaching breakdown voltages above 1200V. Furthermore, increasing the thickness of the top silicon layer does not improve the withstand voltage of integrated high-voltage components above 1200V. This is because simply increasing the thickness of the top silicon layer does not solve the problem of premature vertical breakdown. An exemplary SOI semiconductor process platform uses a thick buried oxide and thin top silicon structure to enable integrated high-voltage components to achieve breakdown voltages of 1200V. This is because the breakdown voltage of a component increases with increasing buried oxide thickness within a certain range, and the thin top silicon layer limits the energy gained by carriers due to the vertical electric field, making the component less susceptible to breakdown. However, this technology has obvious drawbacks. The buried oxide layer of the SOI structure blocks the transfer of heat to the substrate, which reduces the heat dissipation of the component and increases the temperature of the local crystal lattice of the component, causing deterioration of the component's electrical parameters. These degradation phenomena reduce the reliability of the component, and this problem is more pronounced for components with a thick buried oxide layer.

[0029] The present application proposes a silicon-on-insulator semiconductor component, the silicon-on-insulator semiconductor component including a substrate, a buried dielectric layer, a first electrode, a second electrode, and a drift region; the buried dielectric layer is disposed on the substrate; the drift region is provided on the buried dielectric layer, and a step structure is formed on an upper surface of the drift region, the step structure including a first side adjacent to the first electrode, a second side adjacent to the second electrode, and a transition region between the first side and the second side, and an upper surface of the second side is higher than a lower surface of the first side, such that a thickness of the drift region on the second side is greater than a thickness of the drift region on the first side; The first electrode and the second electrode are configured such that when a reverse bias voltage is applied to the component, the voltage applied to the second electrode is greater than the voltage applied to the first electrode.

[0030] The silicon-on-insulator semiconductor component employs a structure in which the thickness of the drift region at the low-voltage end of the component is smaller than the thickness of the drift region at the high-voltage end when a reverse bias voltage is applied, thereby controlling the breakdown point of the component below the high-voltage end and completely depleting the drift region, thereby improving the breakdown voltage of the component without increasing the thickness of the buried oxide layer.

[0031] In one embodiment of the present application, the silicon-on-insulator semiconductor component further includes a first electrode lead-out region and a second electrode lead-out region, the first electrode lead-out region and the second electrode lead-out region being disposed in the buried dielectric layer and having P-type doping or N-type doping, a first electrode located in the first electrode lead-out region and electrically connected to the first electrode lead-out region, and a second electrode located in the second electrode lead-out region and electrically connected to the second electrode lead-out region.

[0032] In one embodiment of the present application, the drift region has a first conductivity type, and the component further includes a protection layer of a second conductivity type, the protection layer of the second conductivity type being located in the drift region and surrounding a corner formed by the first plateau and the step wall and a corner formed by the second plateau and the step wall, and the first conductivity type and the second conductivity type are opposite conductivity types.

[0033] 1 is a cross-sectional schematic diagram of an embodiment of a silicon-on-insulator semiconductor component that is a lateral double-diffused metal-oxide-semiconductor field effect transistor (LDMOS). The LDMOS includes a substrate 110, a buried dielectric layer 120, a drift region 130, a first electrode 162, a second electrode 164, and a gate 166. The first electrode 162 is the source, and the second electrode 164 is the drain. One side of the top surface of the drift region 130 that is closest to the drain (hereinafter referred to as the drift region high side) is higher than the other side that is closest to the source (hereinafter referred to as the drift region low side), thereby forming a drop structure 131.

[0034] The LDMOS further includes a first electrode lead region (i.e., source region) 142 located on the lower side of the drift region and a second electrode lead region (i.e., drain region) 144 located on the higher side of the drift region. A first electrode 162 (i.e., source) is located in the first electrode lead region 142 and is electrically connected to the first electrode lead region 142. A second electrode 164 (i.e., drain) is located in the second electrode lead region 144 and is electrically connected to the second electrode lead region 144. In the embodiment shown in FIG. 1 , a gate 166 extends from the lower side of the drift region to an edge of the first electrode lead region 142 and can have a certain area overlap with the first electrode lead region 142.

[0035] 1, the LDMOS further includes a field oxide layer 147 that extends from the high drift region side to the low drift region side. A portion of the gate 166 extends over the field oxide layer 147.

[0036] 1, the LDMOS is an N-type LDMOS, the drift region 130 is an N-type drift region, and the LDMOS further includes a P-type body region 132 located on the lower side of the drift region and an N-well 134 located on the upper side of the drift region. The first electrode extension region 142 is an N+ region and is located in the P-type body region 132. The second electrode extension region 144 is an N+ region and is located in the N-well 134.

[0037] 1, the LDMOS further includes a body lead region 146 located in the P-type body region 132. The body lead region 146 is a P+ region. A first electrode 162 is electrically connected to the body lead region 146.

[0038] In one embodiment of the present application, the LDMOS further includes an interlayer dielectric (ILD) layer 150. The ILD layer 150 covers structures such as the gate 166, the field oxide layer 147, the first electrode lead region 142, the second electrode lead region 144, and the body lead region 146.

[0039] In one embodiment of the present application, the buried dielectric layer 120 is a buried oxide layer, which may be made of silicon dioxide.

[0040] In one embodiment of the present application, the stepped structure includes a first base surface located on the first side, a second base surface located on the second side, and a step wall located in the transition region. The height difference between the second base surface and the first base surface (corresponding to H1 in FIG. 1) is 3 to 10 microns. The appropriate height difference can ensure that the drift region is fully depleted. The inclination angle of the step wall (corresponding to θ1 in FIG. 1) is 20 to 90 degrees. The appropriate θ1 can ensure that the component does not break down prematurely at this angle.

[0041] When a reverse bias voltage is applied to the LDMOS, a positive voltage is applied to the drain, and the gate 166, source, and substrate are grounded. The PN junction formed by the P-type body region 132 and the N-type drift region 130 is reverse biased, and as the applied bias voltage continues to increase, the space charge region in the lightly doped drift region 130 expands toward the drain edge. The depletion region in the drift region 130 can extend at most to the top surface of the buried oxide layer, and the electric field of the depletion region is barely affected by the substrate 110. The presence of the buried oxide layer improves the vertical breakdown voltage of the component and prevents premature vertical breakdown when the depletion region expands toward the drain edge. At the same time, the thickness of the drift region at the source end is smaller than that at the drain end, so that when the device operates in a reverse breakdown state, the depletion region tends to extend further toward the drain end, and the depletion is likely to occur from the source end to the drain end. The drift region 130 can be fully depleted before vertical breakdown, and the breakdown point is controlled to the boundary between the drift region at the drain end and the buried oxide layer. In this way, the breakdown voltage of the device can still be improved without increasing the thickness of the buried oxide layer, and the breakdown voltage of the device can reach 1200 V or more.

[0042] Referring to FIG. 2a, in one embodiment of the present application, the LDMOS further includes a protective layer 136. The protective layer 136 is located in the drift region 130, has a conductivity type opposite to that of the drift region 130, and surrounds the corner formed by the first plateau and the step wall and the corner formed by the second plateau and the step wall. The protective layer 136 may have an integral structure as shown in FIG. 2a, or may have a structure surrounding two corners, respectively, as shown in FIG. 2b. By forming a protective layer having a conductivity type opposite to that of the drift region 130 at the step corner, early breakdown of the component caused by the concentration of electric field lines at the step corner can be avoided.

[0043] In some embodiments of the present application, the step structure of the drift region of a silicon-on-insulator semiconductor component can be formed using reactive ion etching (RIE) or a secondary epitaxy method. Referring to FIG. 2c, secondary epitaxy can achieve a more "vertical" drift region step. FIG. 2c may also show an LDMOS formed using a secondary epitaxy method, which differs from the structure shown in FIG. 1 primarily in that the step structure is steeper, and its specific structure will not be described in detail here. The structure shown in FIG. 1 can be formed using a reactive ion etching method. By implementing the proposed drift region step structure using primary epitaxy and reactive ion etching or secondary epitaxy, a 1200V silicon-on-insulator semiconductor process platform can be realized. Using a typical primary epitaxy method, a 600V silicon-on-insulator semiconductor process platform can be realized. Therefore, the 1200V process platform proposed in this application is compatible with the 600V process platform and has good compatibility.

[0044] 3 is a cross-sectional schematic diagram of an embodiment in which the silicon-on-insulator semiconductor component is a lateral insulated gate bipolar transistor (LIGBT). The LIGBT includes a substrate 210, a buried dielectric layer 220, a drift region 230, a first electrode 262, a second electrode 264, and a gate 266. The first electrode 262 is the emitter, and the second electrode 264 is the collector. One side of the top surface of drift region 230 closest to the collector (hereinafter referred to as the drift region high side) is higher than the other side closest to the emitter (hereinafter referred to as the drift region low side), thereby forming a drop structure 231.

[0045] In the embodiment shown in FIG. 3 , the LIGBT is an N-type LIGBT, and the drift region 230 is an N-type drift region. The LIGBT further includes a P-type first body region 234 and a second body region 236, as well as an N-well 232. The N-well 232 and the second body region 236 are located on the high side of the drift region, and the first body region 234 is located on the low side of the drift region. A first N+ region 242 and a first P+ region 246 are provided in the first body region 234, and an emitter 262 is electrically connected to the first N+ region 242 and the first P+ region 246. A second P+ region 248 is provided in the N-well 232, a second N+ region 244 is provided in the second body region 236, and a collector 264 is electrically connected to the second N+ region 244, the second P+ region 248, and the second body region 236. 3, the gate 266 extends from the lower side of the drift region to the edge of the first N+ region 242 and can have a certain area overlap with the first N+ region 242. When a reverse bias voltage is applied to the LIGBT, the collector is connected to a high voltage and the emitter is connected to a low voltage or grounded.

[0046] 3, the LIGBT further includes a field oxide layer 247 that extends from the high drift region side to the low drift region side. A portion of the gate 266 extends over the field oxide layer 247.

[0047] In one embodiment of the present application, the LIGBT further includes an interlayer dielectric layer 250. The interlayer dielectric layer 250 covers structures such as the gate 266, the field oxide layer 247, the first N+ region 242, the first P+ region 246, the second N+ region 244, the second P+ region 248, and the second body region 236.

[0048] The step structure of the drift region of the LIGBT can also be formed using reactive ion etching or secondary epitaxial growth. Referring to FIG. 4, secondary epitaxial growth can achieve a more "vertical" drift region step. The main difference between FIG. 4 and FIG. 3 is that the step structure is steeper, and its specific structure will not be described in detail. The structure shown in FIG. 3 was formed using reactive ion etching, and the height difference H2 between the second base surface and the first base surface is 3 to 10 microns, and the inclination angle θ2 of the step wall is 20 to 90 degrees.

[0049] In one embodiment of the present application, the LIGBT further includes a protective layer. The protective layer is located in the drift region, has a conductivity type opposite to that of the drift region, and surrounds a corner formed by the first plateau and the step wall and a corner formed by the second plateau and the step wall. The protective layer may have an integral structure or a structure surrounding two corners, respectively.

[0050] 5 is a cross-sectional schematic diagram of an embodiment in which the silicon-on-insulator semiconductor component is a diode. The diode includes a substrate 310, a buried dielectric layer 320, a drift region 330, a first electrode 362, and a second electrode 364. The first electrode 362 is an anode, and the second electrode 364 is a cathode. One side of the top surface of the drift region 330 closest to the cathode (hereinafter referred to as the drift region high side) is higher than the other side closest to the anode (hereinafter referred to as the drift region low side), thereby forming a drop structure 331.

[0051] The diode further includes a first electrode lead region (i.e., anode region) 342 located on the lower side of the drift region and a second electrode lead region (i.e., cathode region) 344 located on the higher side of the drift region. A first electrode 362 (i.e., anode) is located in the first electrode lead region 342 and is electrically connected to the first electrode lead region 342. A second electrode 364 (i.e., cathode) is located in the second electrode lead region 344 and is electrically connected to the second electrode lead region 344. When a reverse bias voltage is applied to the diode, the cathode is connected to a high voltage and the anode is connected to a low voltage or grounded.

[0052] 5, the drift region 330 is an N-type drift region, and the diode further includes an N-well 334 located on the high side of the drift region. The second electrode extension region 344 is an N+ region and located in the N-well 334. The first electrode extension region 342 is a P+ region and located on the low side of the drift region.

[0053] In the embodiment shown in FIG. 5, the diode further includes a field oxide layer 347 that extends from the high drift region side to the low drift region side.

[0054] In one embodiment of the present application, the diode further includes an interlayer dielectric layer 350. The interlayer dielectric layer 350 covers structures such as the field oxide layer 347, the first electrode lead region 342, and the second electrode lead region 344.

[0055] The step structure of the diode drift region can also be formed using reactive ion etching or secondary epitaxy. Referring to FIG. 6, secondary epitaxy can achieve a more "vertical" drift region step. The main difference between FIG. 6 and FIG. 5 is that the step structure is steeper, and its specific structure will not be described in detail. The structure shown in FIG. 5 can be formed using reactive ion etching, with a height difference H3 between the second base and the first base being 3 to 10 microns, and a slope angle θ3 of the step wall being 20 to 90 degrees.

[0056] In one embodiment of the present application, the diode further includes a protective layer. The protective layer is located in the drift region, has a conductivity type opposite to that of the drift region, and surrounds a corner formed by the first plateau and the step wall and a corner formed by the second plateau and the step wall. The protective layer may have an integral structure or a structure surrounding two corners, respectively.

[0057] The present application further provides a silicon-on-insulator semiconductor process platform, which includes the silicon-on-insulator semiconductor component described in any of the above embodiments, and further includes low-voltage components and / or passive components. In one embodiment of the present application, the low-voltage component may be a complementary metal-oxide-semiconductor field-effect transistor (CMOS), and the passive component may be a well resistor. FIG. 7 is a cross-sectional schematic diagram of a silicon-on-insulator semiconductor process platform in one embodiment of the present application. In the embodiment shown in FIG. 7, the silicon-on-insulator semiconductor process platform includes an LDMOS, a LIGBT, a diode, a CMOS, and a well resistor. The structures of the LDMOS, LIGBT, and diode have been described above, so they will not be repeated here. Different components are isolated from each other by isolation structures. The height of the top surface of the drift region of the CMOS and well resistor structures is the same as the height of the upper side of the drift region.

[0058] The present application correspondingly provides a method for manufacturing a silicon-on-insulator semiconductor component, which can be used to manufacture the silicon-on-insulator semiconductor component described in any of the above embodiments. Figure 8 is a flowchart of a method for manufacturing a silicon-on-insulator semiconductor component in one embodiment of the present application, in which the step structure of the drift region is formed by etching, and the manufacturing method includes the following steps:

[0059] In step S410, a wafer is obtained. The wafer includes a substrate, a buried dielectric layer on the substrate, and a drift region on the buried dielectric layer, which may be epitaxially formed in the buried oxide layer.

[0060] In step S420, a drop structure is formed on the top surface of the drift region by photolithography and etching.

[0061] The drift region (epitaxial layer) is etched to a certain thickness in the area where the photoresist is exposed, thereby making the thickness of the epitaxial layer in the etched area smaller than that of the epitaxial layer in other parts. That is, the drop structure includes a first side, a second side, and a transition region between the first and second sides. The upper surface of the second side is higher than the lower surface of the first side, so that the thickness of the drift region on the second side is greater than the thickness on the first side.

[0062] In one embodiment of the present application, the etching is specifically performed using a reactive ion etching process, which has good anisotropy, a sharp transition region, a fast etching rate, and the etching depth can be precisely controlled.

[0063] In step S430, the first electrode and the second electrode are formed.

[0064] The first side is one side adjacent to the first electrode, and the second side is one side adjacent to the second electrode.

[0065] The component formed by the above-described method for manufacturing a silicon-on-insulator semiconductor component has a structure in which the thickness of the drift region at the low-voltage end of the component is smaller than the thickness of the drift region at the high-voltage end (when a reverse bias voltage is applied). In this way, the breakdown point of the component can be controlled below the high-voltage end, and the drift region can be fully depleted, thereby improving the breakdown voltage of the component without increasing the thickness of the buried oxide layer.

[0066] In one embodiment of the present application, after step S420 and before step S430, the method may further include forming a protective layer in the step structure drift region by ion implantation. The protective layer surrounds the corner formed by the first plateau and the step wall and the corner formed by the second plateau and the step wall. The conductivity type of the protective layer is opposite to that of the drift region. The protective layer may be a monolithic structure or may have a structure surrounding two corners. In an embodiment in which the protective layer has a monolithic structure, the length of the implantation window of the protective layer (the length direction is the length direction of the conductive channel) is 110% to 120% of the length of the transition region (the length direction is the length direction of the conductive channel). FIG. 16 is a schematic cross-sectional view of a silicon-on-insulator semiconductor process platform in an embodiment in which the step structure of the drift region is formed using reactive ion etching. In this embodiment, the protective layer has a monolithic structure. In an embodiment where the protective layer has a structure surrounding two corners, the length of each injection window in the protective layer is 5% to 10% of the length of the transition region.

[0067] FIG. 9 is a flowchart of a method for manufacturing a silicon-on-insulator semiconductor component in another embodiment of the present application, in which the step structure of the drift region is formed using a secondary epitaxial method, and includes the following steps:

[0068] In step S510, a wafer is obtained.

[0069] The wafer includes a substrate, a buried dielectric layer on the substrate, and a first epitaxial layer on the buried dielectric layer.

[0070] In step S520, a second epitaxial layer is formed on a partial region on the first epitaxial layer.

[0071] A portion of the surface of the first epitaxial layer is exposed by photolithography, and then epitaxial growth is performed to form a second epitaxial layer in the exposed region. In this manner, a stepped structure is formed at the boundary between the first epitaxial layer and the second epitaxial layer, and the stepped structure includes a first side on the second epitaxial layer side, a second side on the first epitaxial layer side, and a transition region between the first side and the second side.

[0072] In step S530, the first electrode and the second electrode are formed.

[0073] In one embodiment of the present application, the drop structure is a step structure, including a first base surface located on the first side, a second base surface located on the second side, and a step wall located in the transition region, the height difference between the second base surface and the first base surface is 3 to 10 microns, and the inclination angle of the step wall is 20 degrees to 90 degrees.

[0074] In one embodiment of the present application, after step S520 and before step S530, the method may further include a step of forming a protective layer in the drift region of the stepped structure by ion implantation. The protective layer surrounds a corner formed by the first plateau and the step wall and a corner formed by the second plateau and the step wall. The conductivity type of the protective layer is opposite to that of the drift region. The protective layer may have an integral structure or a structure surrounding two corners, respectively. In an embodiment in which the protective layer has an integral structure, the length of the implantation window of the protective layer (the length direction is the length direction of the conductive channel) is 110% to 120% of the length of the transition region (the length direction is the length direction of the conductive channel). In an embodiment in which the protective layer has a structure surrounding two corners, the length of each implantation window of the protective layer is 5% to 10% of the length of the transition region. FIG. 17 is a cross-sectional schematic diagram of a silicon-on-insulator semiconductor process platform in one embodiment using secondary epitaxial growth to form a step structure in the drift region, where the protective layer surrounds each of the two corners.

[0075] Taking fabricating an SOI LDMOS as an example, the structure after completing step S420 is as shown in Figure 11a. Referring to Figure 10, the fabrication method for an SOI LDMOS further includes the following steps after step S420:

[0076] In step S421, a P-type body region and an N-well are formed.

[0077] 11b, photolithography and ion implantation can be used to form P-type body regions 132 and N-wells 134. P-type body regions 132 are formed on a first side of the stepped structure, and N-wells 134 are formed on a second side of the stepped structure.

[0078] In step S422, a field oxide layer is formed.

[0079] 11c, a field oxide layer 147 is formed on the surface of the drift region 130, between the P-type body region 132 and the N-well 134. The field oxide layer 147 can be formed by deposition or thermal oxidation.

[0080] In step S423, a gate is formed.

[0081] 11d, gate 166 extends from above P-type body region 132 to above field oxide layer 147. Gate 166 may be made of polycrystalline silicon. Gate 166 may be formed by deposition, photolithography, and etching methods.

[0082] In step S424, a source region, a drain region, and a body extension region are formed.

[0083] Referring to FIG. 11e, an N+ source region (i.e., first electrode lead region 142) is formed in the P-type body region 132, an N+ drain region (i.e., second electrode lead region 144) is formed in the N-well 134, and a P+ body lead region 146 is formed in the P-type body region 132.

[0084] In step S425, an interlayer dielectric layer and contact holes are formed.

[0085] After depositing interlayer dielectric layer 150, interlayer dielectric layer 150 is etched to form contact holes. Then, step S430 is performed to form first electrode 162 and second electrode 164, resulting in the structure shown in FIG. 1. First electrode 162 is electrically connected to the N+ source region, and second electrode 164 is electrically connected to the N+ drain region. In addition to being applied to an embodiment in which the step structure of the drift region is formed by reactive ion etching, steps S421 to S425 are also applied to an embodiment in which the step structure of the drift region is formed by secondary epitaxial growth, where the step structure formed by secondary epitaxial growth is steeper.

[0086] Taking manufacturing an SOI LIGBT as an example, the structure after completing step S420 is as shown in Figure 13a. Referring to Figure 12, the manufacturing method of an SOI LIGBT further includes the following steps after step S420:

[0087] In step S621, a first body region and an N-well are formed.

[0088] 13b, photolithography and ion implantation can be used to form a first body region 234 and an N-well 232. The first body region 234 is formed on a first side of the stepped structure, and the N-well 232 is formed on a second side of the stepped structure.

[0089] In step S622, a field oxide layer is formed.

[0090] 13c, a field oxide layer 247 is formed on the surface of the drift region 130 between the first body region 234 and the N-well 232. The field oxide layer 247 can be formed by deposition or thermal oxidation.

[0091] In step S623, a gate is formed.

[0092] 13d, the gate 266 extends from above the first body region 234 to above the field oxide layer 247. The material of the gate 266 may be polycrystalline silicon. The gate 266 may be formed by deposition, photolithography, and etching methods.

[0093] In step S624, a first N+ region, a second N+ region, a first P+ region, a second P+ region, and a second body region are formed.

[0094] 13e, a first N+ region 242 and a first P+ region 246 are formed in the first body region 234. A second P+ region 248 is formed in the N-well 232, and a second N+ region 244 is formed in the second body region 236.

[0095] In step S625, an interlayer dielectric layer and contact holes are formed.

[0096] After depositing interlayer dielectric layer 250, interlayer dielectric layer 250 is etched to form contact holes. Then, step S430 is performed to form first electrode 262 and second electrode 264, resulting in the structure shown in FIG. 3. First electrode 262 is electrically connected to first N+ region 242 and first P+ region 246, and second electrode 264 is electrically connected to second P+ region 248, second N+ region 244, and second body region 236. The above steps S621 to S625 are applicable not only to an embodiment in which the step structure of the drift region is formed by reactive ion etching, but also to an embodiment in which the step structure of the drift region is formed by secondary epitaxial growth, where the step structure formed by secondary epitaxial growth is steeper.

[0097] Taking manufacturing an SOI diode as an example, the structure after completing step S420 is as shown in Figure 15a. Referring to Figure 14, the manufacturing method of an SOI diode further includes the following steps after step S420:

[0098] In step S721, an N-well is formed.

[0099] 15b, photolithography and ion implantation can be used to form an N-well 334. The N-well 334 is formed on the second side of the stepped structure.

[0100] In step S722, a field oxide layer is formed.

[0101] 15c, a field oxide layer 347 is formed on the surface of the drift region 330. The field oxide layer 347 can be formed by deposition or thermal oxidation.

[0102] In step S723, the anode and cathode regions are formed.

[0103] Referring to FIG. 15d, an N+ cathode region (ie, second electrode lead region 344) is located in the N-well 334, and a P+ anode region (ie, first electrode lead region 342) is formed on the first side of the drop structure.

[0104] In step S724, an interlayer dielectric layer and contact holes are formed.

[0105] After depositing interlayer dielectric layer 350, interlayer dielectric layer 350 is etched to form contact holes. Then, step S430 is performed to form first electrode 362 and second electrode 364, resulting in the structure shown in FIG. 5. First electrode 362 is electrically connected to the P+ anode region, and second electrode 364 is electrically connected to the N+ cathode region. In addition to being applied to an embodiment in which the step structure of the drift region is formed by reactive ion etching, steps S721 to S724 are also applied to an embodiment in which the step structure of the drift region is formed by secondary epitaxial growth, where the step structure formed by secondary epitaxial growth is steeper.

[0106] Note that, although the steps in the flowcharts of the present application are displayed in the order indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated otherwise in this specification, the execution of these steps is not limited to a strict order, and these steps may be executed in other orders. Furthermore, at least some of the steps in the flowcharts of the present application may include multiple steps or multiple stages, and these steps or stages may not necessarily be executed and completed at the same time but may be executed at different times. The execution of these steps or stages may not necessarily be executed sequentially, but may be executed in order or alternately with other steps or at least some of the steps or stages in other steps.

[0107] In the description herein, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" mean that the specific features, structures, materials, or characteristics described with reference to the embodiments or examples are included in at least one embodiment or example of the present application. In the description herein, exemplary references to the above terms do not necessarily refer to the same embodiment or example.

[0108] The technical features of the above embodiments can be combined in any way, and for the sake of brevity, not all possible combinations of the technical features in the above embodiments are described, but as long as there is no contradiction in the combination of these technical features, they should be considered within the scope described in this specification.

[0109] The above examples merely illustrate some embodiments of the present application, and although the description is specific and detailed, it should not be understood as limiting the scope of the patent application. It should be noted that a person skilled in the art can make multiple modifications and improvements without departing from the concept of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the patent application should be determined based on the appended claims.

Claims

1. 1. A silicon-on-insulator semiconductor component comprising: a substrate, a buried dielectric layer, a first electrode, a second electrode, and a drift region; the buried dielectric layer is disposed on the substrate; the drift region is provided on the buried dielectric layer, and a stepped structure is formed on an upper surface of the drift region, the stepped structure including a first side adjacent to the first electrode, a second side adjacent to the second electrode, and a transition region between the first side and the second side, and an upper surface of the second side is higher than a lower surface of the first side, such that a thickness of the drift region on the second side is greater than a thickness of the drift region on the first side; the first electrode and the second electrode are configured such that when a reverse bias voltage is applied to the component, a voltage applied to the second electrode is greater than a voltage applied to the first electrode.

2. 10. The silicon-on-insulator semiconductor component of claim 1, wherein the component is a lateral double-diffused metal-oxide-semiconductor field effect transistor, the first electrode being a source, the second electrode being a drain, and the lateral double-diffused metal-oxide-semiconductor field effect transistor further comprising a gate.

3. 2. The silicon-on-insulator semiconductor component of claim 1, wherein the component is a lateral insulated gate bipolar transistor, the first electrode being an emitter, the second electrode being a collector, and the lateral insulated gate bipolar transistor further comprising a gate.

4. 2. The silicon-on-insulator semiconductor component of claim 1, wherein the component is a diode, the first electrode is an anode, and the second electrode is a cathode.

5. 5. The silicon-on-insulator semiconductor component according to claim 1, wherein the step structure is a step structure and includes a first base surface located on the first side, a second base surface located on the second side, and a step wall located in the transition region, and a height difference between the second base surface and the first base surface is 3 to 10 microns.

6. 6. The silicon-on-insulator semiconductor component according to claim 5, wherein the inclination angle of the step wall is between 20 degrees and 90 degrees.

7. 6. The silicon-on-insulator semiconductor component of claim 5, wherein the drift region has a first conductivity type, the component further includes a protective layer of a second conductivity type, the protective layer of the second conductivity type is located in the drift region and surrounds a corner formed by the first plateau and the step wall and a corner formed by the second plateau and the step wall, and the first conductivity type and the second conductivity type are opposite conductivity types.

8. 6. The silicon-on-insulator semiconductor component of claim 5, further comprising a first electrode lead-out region and a second electrode lead-out region, the first electrode lead-out region and the second electrode lead-out region being provided in the buried dielectric layer.

9. 9. The silicon-on-insulator semiconductor component of claim 8, further comprising a field oxide layer, the field oxide layer extending from a second side of the top surface of the drift region adjacent to the second electrode to a first side adjacent to the first electrode.

10. 10. The silicon-on-insulator semiconductor component of claim 9, further comprising an interlayer dielectric layer, said interlayer dielectric layer covering at least said field oxide layer, said first electrode lead-out region and said second electrode lead-out region.

11. 11. A silicon-on-insulator semiconductor process platform comprising the silicon-on-insulator semiconductor component of any one of claims 1 to 10, further comprising at least one of a complementary metal-oxide-semiconductor field effect transistor and a well resistor.

12. 1. A method for manufacturing a silicon-on-insulator semiconductor component, comprising: obtaining a wafer including a substrate, a buried dielectric layer on the substrate, and a drift region on the buried dielectric layer; forming a drop structure on an upper surface of the drift region by photolithography and etching, the drop structure including a first side, a second side, and a transition region between the first and second sides, the upper surface of the second side being higher than the lower surface of the first side, such that a thickness of the drift region on the second side is greater than a thickness of the drift region on the first side; forming a first electrode and a second electrode, the first side being one side adjacent to the first electrode and the second side being one side adjacent to the second electrode; wherein the first and second electrodes are configured such that when a reverse bias voltage is applied to the component, a voltage applied to the second electrode is greater than a voltage applied to the first electrode.

13. The drop structure is a step structure and includes a first base surface located on the first side, a second base surface located on the second side, and a step wall located in the transition region, and before forming the first electrode and the second electrode, the method further includes:

13. The method for manufacturing a silicon-on-insulator semiconductor component according to claim 12, further comprising forming a protective layer in a drift region of the step structure by ion implantation, the protective layer surrounding a corner formed by the first plateau and the step wall and a corner formed by the second plateau and the step wall.

14. 13. The method of claim 12, wherein said etching is a reactive ion etching process.

15. 1. A method for manufacturing a silicon-on-insulator semiconductor component, comprising: obtaining a wafer including a substrate, a buried dielectric layer on the substrate, and a first epitaxial layer on the buried dielectric layer; forming a second epitaxial layer in a partial region on the first epitaxial layer, and forming a stepped structure at a boundary between the first epitaxial layer and the second epitaxial layer, the stepped structure including a first side on the second epitaxial layer side, a second side on the first epitaxial layer side, and a transition region between the first side and the second side; forming a first electrode and a second electrode, the first side being one side adjacent to the first electrode and the second side being one side adjacent to the second electrode; wherein the first and second electrodes are configured such that when a reverse bias voltage is applied to the component, a voltage applied to the second electrode is greater than a voltage applied to the first electrode.

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