Wordline sidewall contacts in 3D NAND structures

Abstract

A three-dimensional (3D) NAND memory structure may include material layers arranged in a vertical stack including alternating horizontal insulating layers and word line layers. The material layers may be etched to form landing pads. Vertical word lines may extend through one or more of the horizontal word line layers underlying the landing pads. The vertical word lines may be conductively connected to the top horizontal word line. The vertical word lines may also be insulated from any horizontal word lines that they pass under. A liner may also be formed on the top horizontal word line at the landing pad.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 396,214, filed August 8, 2022, entitled "WORDLINE SIDEWALL CONTACTS IN 3D NAND STRUCTURES," the entire disclosure of which is incorporated herein by reference for all purposes as if fully set forth herein.

[0002]

[0002] This disclosure generally describes methods and structures for 3D NAND flash memory devices. More specifically, this disclosure describes techniques for fabricating word lines of 3D NAND memory structures. [Background technology]

[0003]

[0003] The memory design known as NAND memory is a non-volatile flash memory storage architecture that does not require power to maintain stored data. NAND flash memory is used in many products, including solid-state devices and portable electronics. To increase the density and reduce the size of NAND memory, traditional two-dimensional (2D) NAND architectures are transitioning to three-dimensional (3D) NAND stacks. Unlike 2D planar NAND technology, in which individual memory cells are stacked on separate horizontal substrates, 3D NAND is stacked vertically using multiple layers of alternating conductive and dielectric materials, intersecting vertical channels. Summary of the Invention

[0004] In some embodiments, a 3D NAND memory structure may include multiple material layers arranged in a vertical stack, which may include alternating horizontal insulating layers and horizontal word line layers. The multiple material layers may be etched to form landing pads. The structure may also include vertical word lines that may extend through one or more of the horizontal word line layers underlying the landing pads. The vertical word lines may be conductively connected to a top horizontal word line in the multiple alternating material layers. The vertical word lines may also be insulated from one or more horizontal word lines that they pass below.

[0005] In some embodiments, a method for fabricating a 3D NAND memory structure may include forming multiple material layers arranged in a vertical stack, which may include alternating horizontal insulating layers and horizontal word line layers. The multiple material layers may be etched to form landing pads. The method may also include etching holes for vertical word lines that extend through one or more of the horizontal word line layers underlying the landing pads.

[0006] In some embodiments, a 3D NAND memory structure may include multiple material layers arranged in a vertical stack, which may include alternating horizontal insulating layers and horizontal word line layers. The multiple material layers may be etched to form landing pads. The structure may include a liner formed on the top horizontal word line at the landing pad. The liner may define a gap between the liner and a vertical sidewall adjacent to the landing pad.

[0007] In any embodiment, any and / or all of the following features may be realized in any combination, without limitation. The structure may also include an oxide barrier layer insulating one or more horizontal word lines from the vertical word lines. The barrier layer may be disposed between the vertical word lines at the landing pad and the top horizontal word line. The structure may also further include a conductive liner on the top horizontal word line at the landing pad that conductively contacts the top horizontal word line and the vertical word lines. The vertical word lines may extend down to a substrate underlying the multiple material layers. The vertical word lines may extend down to a substrate underlying the multiple material layers. The vertical word lines may contact the horizontal insulating layer. The method may also include filling holes for the vertical word lines with a fill material and exhuming sacrificial material from the horizontal word line layer. The method may also include forming a barrier layer in voids left after removing sacrificial material from the horizontal word lines. A barrier layer may be formed on vertical sidewalls of the fill material exposed in voids left after removing the sacrificial material. Forming the barrier layer may include forming an oxide layer on the vertical sidewalls of the fill material using an ALD process. The barrier layer may have a thickness between 100 Å and 150 Å. The method may also include filling voids left after removing the sacrificial material from the horizontal word lines with a first conductive material, removing the fill material from holes for the vertical word lines, and / or filling the holes for the vertical word lines with a second conductive material, where the barrier layer may insulate the second conductive material from the first conductive material for the one or more horizontal word lines underlying the landing pad. The liner may include an insulating liner formed of a material different from the sacrificial material forming the horizontal word line layer. The liner may include a conductive liner including a first conductive material in conductive contact with a second conductive material forming the top horizontal word line at the landing pad. The structure may also include a barrier layer between the horizontal word line layer and the vertical word lines that insulates the horizontal word line layer from the vertical word lines.The liner can expose vertical sidewalls of the multiple material layers adjacent to the landing pad. The gap can be between about 50 nm and about 100 nm wide. The gap can expose a portion of the top horizontal word line at the landing pad.

[0008] A further understanding of the nature and advantages of various embodiments may be realized by reference to the remaining portions of the specification and the drawings. In the drawings, like reference numerals are used throughout the several views to refer to like components. In some instances, a sub-label is associated with the reference numeral to indicate one of multiple similar components. When referring to a reference numeral without specifying an existing sub-label, it is intended to refer to all such multiple similar components. [Brief explanation of the drawings]

[0009] [Figure 1]

[0009] FIG. 1 shows a top view of one embodiment of a processing system with a deposition chamber, an etch chamber, a bake chamber, and a cure chamber, according to some embodiments. [Figure 2]

[0010] 1A and 1B illustrate a 3D NAND structure formed to expose landing pads for horizontal word lines, according to some embodiments. [Figure 3]

[0011] 1 illustrates a method for fabricating a 3D NAND memory structure, according to some embodiments. [Figure 4A]

[0012] 1 illustrates steps in a process for forming a 3D NAND structure, according to some embodiments. [Figure 4B] 1 illustrates steps in a process for forming a 3D NAND structure, according to some embodiments. [Figure 4C] 1 illustrates steps in a process for forming a 3D NAND structure, according to some embodiments. [Figure 4D]1 illustrates steps in a process for forming a 3D NAND structure, according to some embodiments. [Figure 4E] 1 illustrates steps in a process for forming a 3D NAND structure, according to some embodiments. [Figure 4F] 1 illustrates steps in a process for forming a 3D NAND structure, according to some embodiments. [Figure 4G] 1 illustrates steps in a process for forming a 3D NAND structure, according to some embodiments. [Figure 4H] 1 illustrates steps in a process for forming a 3D NAND structure, according to some embodiments. [Figure 4I] 1 illustrates steps in a process for forming a 3D NAND structure, according to some embodiments. [Figure 4J] 1 illustrates steps in a process for forming a 3D NAND structure, according to some embodiments. [Figure 4K] 1 illustrates steps in a process for forming a 3D NAND structure, according to some embodiments. [Figure 4L] 1 illustrates steps in a process for forming a 3D NAND structure, according to some embodiments. [Figure 5]

[0013] 1 illustrates a 3D NAND structure, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0010]

[0014] FIG. 1 illustrates a top view of one embodiment of a deposition, etch, bake, and cure chamber processing system 100, according to some embodiments. In this illustration, a pair of front-opening unified pods 102 supply substrates of various sizes. These substrates are received by a robotic arm 104 and placed in a low-pressure holding area 106, which is then placed into one of the substrate processing chambers 108a-f located in tandem sections 109a-c. A second robotic arm 110 may be used to transfer substrate wafers from the holding area 106 to and from the substrate processing chambers 108a-f. Each substrate processing chamber 108a-f can be equipped to perform multiple substrate processing steps, including cyclical layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, annealing, plasma treatment, degassing, orientation, and other substrate processes, as well as the dry etching processes described herein.

[0011]

[0015] The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing, and / or etching a material film on a substrate or wafer. In one configuration, two pairs of processing chambers, e.g., 108c-d and 108e-f, may be used to deposit material on a substrate, and a third pair of processing chambers, e.g., 108a-b, may be used to cure, anneal, or process the deposited film. In another configuration, all three pairs of chambers, e.g., 108a-f, may be configured to deposit and cure a film on a substrate. Any one or more of the described processes may be performed in additional chambers separate from the fabrication system shown in different embodiments. It will be understood that the processing system 100 contemplates additional configurations of deposition chambers, etch chambers, annealing chambers, and curing chambers for material films. Additionally, any number of other processing systems may be utilized with the present technology, and these processing systems may incorporate chambers for performing any of the specific steps. In some embodiments, a chamber system may provide access to multiple processing chambers while maintaining a vacuum environment in various sections, such as the holding area and transfer area described above, allowing operations to be performed in multiple chambers while maintaining a particular vacuum environment between individual processes.

[0012]

[0016] The processing system 100, and more particularly the chambers incorporated into the processing system 100 or other processing systems, may be used to fabricate structures according to some embodiments of the present technique. For example, the processing system 100 may be used to fabricate memory arrays by performing processes such as deposition, etching, sputtering, polishing, cleaning, etc. in the various substrate processing chambers 108.

[0013]

[0017] A 3D NAND memory structure may include multiple alternating metal and oxide layer pairs stacked vertically on top of each other. Each horizontal metal layer may represent a word line associated with a vertical channel to form a memory element. To connect these horizontal word lines, landing pads may be created on each metal and oxide layer pair for connection to the vertical word lines.

[0014]

[0018] FIG. 2A illustrates a 3D NAND structure 200 formed using a step etch to expose landing pads 216 of each of the horizontal word lines, according to some embodiments. The step formation of this 3D NAND structure 200 may be formed by forming a lithographic photoresist mask on the top of the structure, then repeatedly removing edge portions of the mask and performing a downward directional etch to remove individual layer pairs 210. Each of the layer pairs 210 may include a metal layer 212 and an oxide layer 214. As described below, each of the metal layers 212 may be formed by filling voids left after removing a sacrificial nitride material. The landing pads 216 may expose the individual metal layers 212 in each layer pair 210. Vertical word lines 218 may then be formed such that each vertical word line 218 only contacts its corresponding horizontal word line. Typically, care is taken to avoid etching through the metal layers 212 so that the vertical word lines 218 do not contact multiple metal layers 212.

[0015]

[0019] FIG. 2B illustrates an alternative 3D NAND structure 202 according to some embodiments. Instead of forming a pure staircase structure as shown in FIG. 2A, other embodiments may use a different shape to expose the landing pads of each vertical word line. This particular type of structure 202 may be formed using what is called a chop etch. It should be understood that any geometry or 3D NAND structure may be used in combination with the techniques described below and / or disclosed methods to form contacts between horizontal metal layers and vertical word lines. Thus, as used herein, a landing pad or contact pad may be defined as a surface etched into the 3D NAND structure as part of a staircase or chop etch that forms a surface for contacting the vertical word lines.

[0016]

[0020] It should also be understood that these 3D NAND structures 200, 202 may actually be very large structures, including hundreds of alternating oxide and nitride layers. The metal layer 212 may be formed from any conductive or metallic material. The vertical word lines 218 may also be formed from any conductive or metallic material, including tungsten, molybdenum, or other similar materials. These figures are not drawn to scale, and the vertical word lines 218 may be much wider than the thickness of the metal layer 212 and / or the oxide layer 214. For example, the exposed surface of the landing pad 216 may be between about 600 nm and about 900 nm, and the width of the vertical word lines 218 may be between about 100 nm and about 300 nm, e.g., about 200 nm.

[0017]

[0021] Each of the vertical word lines 218 may be formed together in a single etching process. Thus, the etching process may typically have a very high selectivity to the tungsten of the metal layer 212 of the landing pads 216 to avoid etching through the metal layer 212 when forming vertical holes for the vertical word lines 218. Therefore, a technical challenge exists when fabricating 3D NAND structures: very high precision is required when etching holes for the vertical word lines 218. Because the etch must be very selective to the material of the metal layer 212, it limits the type of etch that can be used and creates the risk of unintentionally punching through the metal layer 212 and connecting multiple metal layers 212 in the structure.

[0018]

[0022] The embodiments described herein solve these and other technical problems by forming horizontal contact layers over the landing pads and vertically isolating the vertical word lines from underlying metal layers in the stack. Instead of carefully etching down to the contact pads, holes can be etched through the contact pads and through the underlying oxide-oxide layer pairs. These holes can then be filled with silicon and subjected to an oxidation process after the sacrificial nitride layer is removed. Then, when filling the voids left from the sacrificial nitride layer with a metal layer, the silicon oxide layer can insulate the horizontal metal word line layer from the vertical holes formed for the vertical metal word lines. The metal layer can fill the voids in the layers from each landing pad to contact the vertical word lines in the top layer, while the underlying layers are insulated by the silicon oxide insulating layer.

[0019]

[0023] FIG. 3 illustrates a method 300 for fabricating a 3D NAND memory structure according to some embodiments. FIGS. 4A-4L illustrate incremental structural steps in a process for forming a 3D NAND structure. The structural diagrams are provided by way of example only and are not intended to be limiting. Each method step may be more extensive than the specific example shown in FIGS. 4A-4L.

[0020]

[0024] Method 300 may include forming 302 multiple material layers arranged in a vertical stack including alternating horizontal insulating layers and horizontal word line layers. FIG. 4A shows a 3D NAND structure 400 after performing a step etch or other process to expose multiple landing pads, according to some embodiments. The 3D NAND structure 400 may be formed on a substrate and may have multiple stacked layers on the substrate. The substrate may include silicon, silicon germanium, or other substrate material. The layers may include an IPD layer of ONO layers including a dielectric material, which may be silicon oxide, in alternating layers. For example, structure 400 may include multiple alternating layers of horizontal insulating layers 414, such as oxide layers or silicon oxide layers. Structure 400 may also include a layer of placeholder or sacrificial material. This layer may be silicon nitride or polysilicon and may be referred to as a horizontal sacrificial layer 416. The sacrificial layer 416 may be or include a material that will be removed in a subsequent process to create individual memory cells. Therefore, the sacrificial layers 414 may also be referred to as horizontal word line layers, since these layers will later be used as word lines. As used herein, the term word line may refer to these layers filled with a sacrificial material or a conductive or metallic material.

[0021]

[0025] Although shown with only a limited number of material layers, the exemplary structure may include any number of layers, including hundreds of material layers. It should also be understood that the figures are merely schematic diagrams for illustrating aspects of the present technology. For example, semiconductor structure 400 may include 10 or more layer pairs, 20 or more layer pairs, 50 or more layer pairs, 100 or more layer pairs, etc. For example, the height of structure 400 may be 10 μm or more, 20 μm or more, etc.

[0022]

[0026] In this example, etching is used to expose wordline contact pads or landing pads 422. The landing pads 422 may expose the sacrificial layer 416 at each alternating oxide / nitride layer. The landing pads 422 may be defined as flat areas of the sacrificial layer exposed between different etch levels in the structure 400. For example, FIG. 4A shows three different landing pads 421, 422, and 423. The etch that creates the landing pads 421, 422, and 423 may include a step etch, as illustrated in FIG. 2A, and / or a chop etch, as illustrated in FIG. 2B. The following discussion will focus on the landing pads 422, but is equally applicable to other etch types.

[0023]

[0027] After exposing the landing pads 422, a liner 420 may be deposited on the structure 400. The liner 420 may include a doped silicon oxide layer. For example, the silicon oxide of the liner 420 may be doped with boron, phosphorus, both boron and phosphorus, or other similar materials. The liner 420 may be deposited using any deposition technique. For example, the liner 420 may be deposited using an atomic layer deposition (ALD) process so that it is formed on the exposed sacrificial layer 416 at the top of the landing pads 422. The liner 420 may also be formed perpendicular to the exposed alternating layers of the sacrificial layer 416 and the insulating layer 414. Other techniques for deposition may include chemical vapor deposition (CVD) and other similar processes.

[0024]

[0028] 4B illustrates removing a portion of the liner, according to some embodiments. For example, the sidewalls 429 of the liner 420 can be removed from the exposed edges of the alternating insulating layers 414 and sacrificial layers 416. The sidewalls 429 of the liner 420 can be removed using a dry etching process, such as a directional etch. For example, a carbon layer can be deposited on top of the liner 420, and the sidewalls 429 can be exposed to an argon process so that only the surface area of the sidewalls 429 is exposed to the argon process, after which the vertical sidewalls 429 can be removed.

[0025]

[0029] Removing the sidewalls 429 may define a gap 428 exposing the sacrificial layer 416. For example, the gap 428 may be defined by the edge of the liner 420 and the vertical sidewalls of the multiple material layers adjacent to the landing pad, as shown in FIG. 4B . The gap 428 may be about 50 nm to about 100 nm wide. In various implementations, the gap 428 may be less than about 25 nm, less than about 50 nm, less than about 75 nm, less than about 100 nm, less than about 125 nm, less than about 150 nm, etc. The gap 428 may be sized based on the thickness of the vertical sidewalls 429 exposed by the carbon layer when the vertical sidewalls 429 are removed. In comparison, the length of the landing pad 422 may be about 600 nm to about 1000 nm wide. After removing the sidewalls 429 of the liner 420 and exposing the gaps 428 above the landing pads 422, large area gap filling can be performed using a gap filler 430. For example, in the areas above the landing pads 421, 422, 423 of the staircase structure 400, silicon oxide can serve as the gap filler 430.

[0026]

[0030] 4C shows that a hard mask 432 is deposited on top of the gap fill material 430, according to some embodiments. FIG. 4D shows how the hard mask 432 can be opened with a pattern 434 above each of the landing pads, according to some embodiments. These steps can be performed using conventional techniques. This process can create holes in the hard mask 432 for a subsequent etching process to form contact holes in which vertical word lines can be formed.

[0027]

[0031] Method 300 may also include etching holes (304) for vertical word lines that extend through one or more of the horizontal word line layers below the landing pads. FIG. 4E illustrates a contact etch that may be performed to form holes for the vertical word lines according to some embodiments. Etching may be performed through a hard mask 432 to etch holes through the gap fill material 430 and the liner 420. This may contrast with conventional methods for forming vertical word lines. Prior to the present disclosure, this etch was performed after the sacrificial layer 416 was removed and the voids were filled with a metal layer. The etch then had to be performed so that only the top metal layer of each landing pad was exposed. Therefore, the etch had to be highly selective to the metal layer (e.g., tungsten) so as not to punch through the top metal layer and short out the memory elements in structure 400.

[0028]

[0032] In contrast to conventional methods, some embodiments may instead etch contact holes 436 that penetrate not only the gap fill material but also the liner 420 and the underlying multiple sacrificial layers 416 and / or insulating layers 414. For example, some embodiments may etch the holes 436 down to the substrate 438. The substrate 438 may comprise a silicon substrate or an oxide layer that is thicker than the other insulating layers 414. Some embodiments may etch the holes 436 through all of the sacrificial layers 416 and / or insulating layers 414. Some embodiments may etch the holes 436 such that the holes 436 penetrate one or more, but not all, of the sacrificial layers 416 below the landing pads 422. Some embodiments may etch the holes 436 so that the holes 436 penetrate below the surface level of the substrate 438. Some embodiments may etch each hole 436 to the same depth. On the other hand, other embodiments may adjust the depth of each hole to penetrate below the top sacrificial layer of each landing pad.

[0029]

[0033] The method may also optionally include filling holes for the vertical word lines with a filler material (306) and / or removing sacrificial material from the horizontal word line layer. FIG. 4F shows how contact holes may be temporarily filled according to some embodiments. A deposition process may be used to fill the holes 436 with a filler material 440, such as silicon. In contrast to conventional techniques, the filler material 440 may fill the holes 436 through multiple sacrificial layers 416 and / or insulating layers 414, all of the sacrificial layers 416 and / or insulating layers 414, down to or below the surface of the substrate 438.

[0030]

[0034] 4G shows a removal process for the sacrificial layer 416, according to some embodiments. For example, a wet etching process may be used to remove a silicon nitride material used as the sacrificial layer 416. The voids 442 remaining after removing the sacrificial layer 416 may later be filled with a metal layer to form the horizontal word lines of the memory elements of the structure 400. Thus, the sacrificial layer removal process may leave behind the insulating layer 414, the liner 420, the filler material 440, and the gap filler material 430.

[0031]

[0035] The method may also optionally include forming a barrier layer (308) in the voids left after removing the sacrificial material from the horizontal word lines. FIG. 4H illustrates forming a barrier layer 444 for the horizontal word lines, according to some embodiments. The surface of the fill material 440 may be exposed inside the voids 442 left after removing the sacrificial layer 416. The barrier layer is then formed on the vertical sidewalls of the fill material exposed in the voids left after removing the sacrificial material. The barrier layer 444 may serve to separate the area inside the voids 442 from the contact holes that will be filled with the fill material 440. As described below, the barrier layer 444 may later separate the conductive horizontal word lines from the conductive vertical word lines along the depth of the contact holes under the contact pads.

[0032]

[0036] A number of different processes can be used to form the barrier layer. In some embodiments, a silicon oxidation process can be used. For example, during the oxidation process, a silicon oxide layer can be formed on the exposed silicon of the fill material 440 in these voids 442. Thus, the oxidation process can form a barrier layer 444 inside each void 442 adjacent to the fill material 440.

[0033]

[0037] Some embodiments may replace the silicon oxidation process described above with an ALD process to form a barrier layer 444 in the voids 442 adjacent to the fill material 440. Instead of oxidizing the silicon of the fill material 440, the ALD process may progressively deposit an oxide layer to form the barrier layer 444 in each of the voids 442. This is useful because the oxidation process may also affect the equivalent oxide thickness (EOT) of a device defined by the MANOS stack. Furthermore, the ALD process can be used to deposit not only oxides of silicon, but also numerous other dielectrics that may have more advantageous selectivity in the remainder of the device integration process. The ALD process may also be used to precisely control the thickness of the barrier layer 444.

[0034]

[0038] The barrier layer 444 may be relatively thin compared to other dimensions in the 3D NAND structure. For example, the barrier layer 444 may be less than or about 20 Å, less than or about 30 Å, less than or about 40 Å, less than or about 50 Å, less than or about 60 Å, less than or about 70 Å, less than or about 80 Å, less than or about 90 Å, less than or about 100 Å, less than or about 110 Å, less than or about 120 Å, less than or about 130 Å, or less than 140 Å, depending on the size of the structure 400. or about 140 Å, less than or about 150 Å, less than or about 160 Å, less than or about 170 Å, less than or about 180 Å, less than or about 190 Å, less than or about 200 Å, less than or about 225 Å, less than or about 250 Å, less than or about 275 Å, less than or about 300 Å, less than or about 350 Å, less than or about 400 Å, etc. For example, barrier layer 444 can be about 100 Å to about 150 Å thick, with barrier layer 444 extending into voids 442. In various embodiments, the barrier layer can be between about 50 Å and about 100 Å or greater, between about 50 Å and about 150 Å or greater, between about 50 Å and about 200 Å or greater, between about 100 Å and about 200 Å or greater, between about 150 Å and about 200 Å or greater, between about 150 Å and about 250 Å or greater, etc.

[0035]

[0039] FIG. 4I illustrates wordline deposition according to some embodiments. For example, some embodiments may first form an aluminum oxide layer (e.g., a high-k layer) within the void 442. The aluminum oxide may be deposited using an ALD process to cover any exposed surfaces within the void 442. For example, the aluminum oxide layer may have a thickness of about 2 nm to about 3 nm. Note that the aluminum oxide layer is not explicitly shown in FIG. 4I due to its relatively small size. Next, a deposition process may be used to deposit horizontal wordline layer 450 within the void 442. The horizontal wordline layer may be formed using any conductive material or metal, such as tungsten, molybdenum, or other similar conductive materials.

[0036]

[0040] Method 300 may optionally further include removing the fill material and filling the holes with a conductive material (310). FIG. 4J illustrates removing fill material 440 according to some embodiments. The purpose of fill material 440 is to provide a surface for the barrier layer 444 described above. For example, fill material 440 may provide a surface for growing silicon oxide of barrier layer 444 using the oxidation process described above. Alternatively, fill material 440 may provide a surface for forming an oxide using the ALD process described above. Thus, after barrier layer 444 is formed and horizontal word line layer 450 is formed, fill material 440 may be removed. As shown, this may re-expose contact hole 436.

[0037]

[0041] 4K illustrates removing the liner 420, according to some embodiments. For example, an etching process may be used to remove a doped silicon oxide material that may be used for the liner 420. In some embodiments, an aluminum oxide layer formed between the horizontal word line layer 450 and the liner 420 may also be removed. Removing the aluminum oxide layer may expose a void 452 between the top horizontal word line layer and the contact hole 436. For example, a two-step etch may be used to first remove the doped silicon oxide of the liner 420, and then remove the aluminum oxide layer in a second step.

[0038]

[0042] 4L illustrates forming vertical wordlines according to some embodiments. For example, some embodiments may first deposit a titanium nitride liner and then fill contact holes 436 with a metal or other conductive material to form vertical wordlines 456. This process may also fill voids 452 with a metal or other conductive material to form conductive liner 454, which replaces liner 420. Conductive liner 454 may include tungsten, molybdenum, titanium, or other similar materials.

[0039]

[0043] In some embodiments, the conductive liner 454 may be formed simultaneously with the vertical word lines 456. Thus, the same material may be used to form both the conductive liner 454 and the vertical word lines 456. This material may be the same or different from the conductive material used to form the horizontal word line layer 450. More generally, the horizontal word line layer 450 may be formed from a first conductive material and the conductive liner 454 may be formed from a second conductive material. The first conductive material may be the same as the second conductive material, or the first material may be different from the second conductive material.

[0040]

[0044] Note that the conductive material of the vertical word lines 456 may be in electrical contact only with the conductive liner 454, which contacts the top horizontal word line layer, instead of the liner 420. Thus, the vertical word lines 456, the conductive liner 454, and the top horizontal word line layer may be referred to as being conductively connected to one another. For example, this conductive connection may include a resistance of less than 5 Ω. In other embodiments, this conductive connection may include a resistance of less than about 10 Ω, less than about 20 Ω, less than about 50 Ω, or less than about 100 Ω, depending on the embodiment. This conductive connection may also include direct contact between these layers without a significant intervening layer of insulating material.

[0041]

[0045] As in conventional 3D NAND structures, vertical word lines 456 are insulated from other horizontal word lines while only conductively contacting the topmost metal layer as horizontal word lines. However, now the connection passes through conductive liner 454 instead of liner 420. Gap 428 prevents conductive liner 454 from contacting any of the horizontal word line layers 450 above the intended horizontal word line. Additionally, because the metal of vertical word lines 456 extends downward through structure 400, barrier layer 444 formed on the fill material prevents vertical word lines 456 from contacting any of the underlying metal layers. Figure 5 shows a diagram of the 3D NAND structure after this process is completed.

[0042]

[0046] As used herein, the terms "about" or "approximately" or "substantially" can be interpreted as being within the range expected by one of ordinary skill in the art in light of the present specification.

[0043]

[0047] In the above description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments. However, it will be apparent that some embodiments may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form.

[0044]

[0048] The above description provides exemplary embodiments only and is not intended to limit the scope, applicability, or configuration of the present disclosure. Rather, the foregoing description of various embodiments provides an enabling disclosure for implementing at least one embodiment. It should be understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope of some embodiments, as set forth in the appended claims.

[0045]

[0049] Specific details have been given in the above description to provide a thorough understanding of the embodiments. However, it will be understood that the embodiments may be practiced without these specific details. For example, circuits, systems, networks, processes, and other components may be shown as components in block diagram form so as not to obscure the embodiments in unnecessary detail. In other instances, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail so as not to obscure the embodiments.

[0046]

[0050] Also, it should be noted that particular embodiments have been described as a process, which is depicted as a flowchart, flow diagram, data flow diagram, structure diagram, or block diagram. While a flowchart may describe steps as a sequential process, many of the steps may be performed in parallel or simultaneously. Moreover, the order of steps may be rearranged. A process terminates when a step is completed, but there may be additional steps not included in the diagram. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc. When a process corresponds to a function, its termination may correspond to a return of the function to a calling function or a main function.

[0047]

[0051] The term "computer-readable medium" includes, but is not limited to, portable or fixed storage devices, optical storage devices, wireless channels, and various other media capable of storing, containing, or carrying one or more instructions and / or data. A code segment or machine-executable instruction may represent a procedure, a function, a subprogram, a program, a routine, a subroutine, a module, a software package, a class, or any combination of instructions, data structures, or program statements. A code segment may be connected to another code segment or a hardware circuit by passing information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc. may be passed, forwarded, or transmitted via any suitable means including memory sharing, message passing, token passing, network transmission, etc.

[0048]

[0052] Furthermore, the embodiments may be implemented by hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented by software, firmware, middleware, or microcode, the program code or code segments to perform the necessary tasks may be stored in a machine-readable medium. One or more processors may perform the necessary tasks.

[0049]

[0053] While features have been described in the foregoing specification with reference to specific embodiments thereof, it should be recognized that not all embodiments are limited thereto. Various features and aspects of some embodiments may be used individually or together. Moreover, embodiments may be utilized in any number of environments and applications other than those described herein without departing from the broader spirit and scope of the specification. Accordingly, the specification and drawings should be regarded as illustrative rather than restrictive.

[0050]

[0054] Furthermore, for purposes of explanation, the methods have been described in a particular order. It should be understood that in alternative embodiments, the methods may be performed in an order different from that described. It should also be understood that the methods described above may be performed by hardware components or embodied in sequences of machine-executable instructions, which may be used to cause a machine, such as a general-purpose or special-purpose processor, or a logic circuit programmed with the instructions, to perform the method. These machine-executable instructions may be stored on one or more machine-readable media, such as a CD-ROM or other type of optical disk, a floppy diskette, ROM, RAM, EPROM, EEPROM, a magnetic or optical card, flash memory, or other type of machine-readable medium suitable for storing electronic instructions. Alternatively, the methods may be implemented by a combination of hardware and software.

Claims

1. 1. A three-dimensional (3D) NAND memory structure, comprising: a plurality of material layers arranged in a vertical stack including alternating horizontal insulating layers and horizontal word line layers, the plurality of material layers being etched to form landing pads; vertical word lines extending through one or more of the horizontal word line layers underlying the landing pads, a vertical word line, the vertical word line conductively connected to a topmost horizontal word line in the plurality of alternating material layers and insulated from the one or more horizontal word lines through which the vertical word line passes below the topmost horizontal word line; 1. A 3D NAND memory structure comprising:

2. 10. The 3D NAND memory structure of claim 1, further comprising an oxide barrier layer insulating the one or more horizontal word lines from the vertical word lines.

3. 3. The 3D NAND memory structure of claim 2, wherein the barrier layer is disposed between the vertical word line and the top horizontal word line at the landing pad.

4. 10. The 3D NAND memory structure of claim 1, further comprising a conductive liner on said top horizontal word line at said landing pad that conductively contacts said top horizontal word line and said vertical word line.

5. 10. The 3D NAND memory structure of claim 1, wherein the vertical word lines extend down to a substrate beneath the plurality of layers of material.

6. 10. The 3D NAND memory structure of claim 1, wherein the vertical word lines extend downward into a substrate beneath the plurality of layers of material.

7. 10. The 3D NAND memory structure of claim 1, wherein the vertical word lines contact the horizontal insulating layer.

8. 1. A method for fabricating a three-dimensional (3D) NAND memory structure, the method comprising: forming a plurality of material layers arranged in a vertical stack including alternating horizontal insulating layers and horizontal word line layers, the plurality of material layers being etched to form landing pads; etching holes for vertical word lines extending through one or more of the horizontal word line layers underlying the landing pads; A method comprising:

9. filling the holes for the vertical word lines with a fill material; removing sacrificial material from the horizontal word line layer; The method of claim 8 further comprising:

10. 10. The method of claim 9, further comprising forming a barrier layer in voids left after removing the sacrificial material from the horizontal word lines, the barrier layer being formed on vertical sidewalls of the fill material exposed in the voids left after removing the sacrificial material.

11. The method of claim 10 , wherein forming the barrier layer comprises forming an oxide layer on the vertical sidewalls of the fill material using an ALD process.

12. The method of claim 10, wherein the barrier layer is between 100 and 150 Å thick.

13. filling the voids left after removing the sacrificial material from the horizontal word lines with a first conductive material; removing the fill material from the holes for the vertical word lines; filling the holes for the vertical word lines with a second conductive material, the barrier layer insulating the second conductive material from the first conductive material for the one or more horizontal word lines underlying the landing pad; The method of claim 10 further comprising:

14. 1. A three-dimensional (3D) NAND memory structure, comprising: a plurality of material layers arranged in a vertical stack including alternating horizontal insulating layers and horizontal word line layers, the plurality of material layers being etched to form landing pads; a liner formed on the uppermost horizontal word line at the landing pad, the liner defining a gap between the liner and a vertical sidewall adjacent to the landing pad; 1. A 3D NAND memory structure comprising:

15. 15. The 3D NAND memory structure of claim 14, wherein the liner comprises an insulating liner formed of a material different from a sacrificial material forming the horizontal word line layer.

16. 15. The 3D NAND memory structure of claim 14, wherein the liner comprises a conductive liner comprising a first conductive material in conductive contact with a second conductive material forming the top horizontal word line at the landing pad.

17. 15. The 3D NAND memory structure of claim 14, further comprising a barrier layer between the horizontal word line layer and the vertical word lines, insulating the horizontal word line layer from the vertical word lines.

18. 15. The 3D NAND memory structure of claim 14, wherein the liner exposes vertical sidewalls of the plurality of material layers adjacent the landing pad.

19. 15. The 3D NAND memory structure of claim 14, wherein the gap is between about 50 nm and about 100 nm in width.

20. The 3D NAND memory structure of claim 14 , wherein the gap exposes a portion of the top horizontal word line at the landing pad.

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