Display device

Abstract

The display device includes light-emitting elements disposed in a display region on a substrate, a pad section disposed in the pad region on the substrate and including a plurality of output pads, a driver chip, and control signal wiring. The driver chip faces the substrate, includes a base section overlapping the pad region and including dummy bump regions, output bump regions positioned between the dummy bump regions, and a data output region positioned between the dummy bump regions, a plurality of dummy bumps attached to a bottom surface of the base section and overlapping the dummy bump regions and the output bump regions, a plurality of output bumps attached to the bottom surface of the base section and overlapping the output bump regions and connected in parallel to each other via transistors, and a plurality of detection bumps attached to the bottom surface of the base section, each electrically connected to one of the output bumps and overlapping the output bump regions. The control signal wiring is electrically connected to the output bumps via the transistors.

Description

[Technical Field]

[0001] The present invention relates to a display device. [Background technology]

[0002] With the development of information technology, the importance of display devices, which are a connection medium between users and information, is becoming more prominent, and the use of display devices such as liquid crystal displays (LCDs), organic light emitting display devices (OLEDs), and plasma display devices is increasing. Summary of the Invention [Problem to be solved by the invention]

[0003] SUMMARY OF THE INVENTION An object of the present invention is to provide a display device with reduced defects through redundancy.

[0004] However, the object of the present invention is not limited to this, and various extensions are possible without departing from the spirit and scope of the present invention. [Means for solving the problem]

[0005] According to an embodiment of the present invention, a display device includes a substrate including a display area and a non-display area including a pad area located on a periphery of the display area and adjacent to one side of the display area, a light emitting element disposed in the display area on the substrate, a pad section disposed in the pad area on the substrate and including a plurality of output pads, a base section facing the substrate and overlapping the pad area, the pad section including a dummy bump area, an output bump area located between the dummy bump areas, and a data output area located between the dummy bump areas, a plurality of dummy bumps attached to a bottom surface of the base and overlapping the dummy bump areas and the output bump areas, a plurality of output bumps attached to the bottom surface of the base and overlapping the output bump areas and connected in parallel to each other via transistors, and a plurality of detection bumps attached to the bottom surface of the base, each electrically connected to one of the output bumps and overlapping the output bump areas, and the control signal wiring is electrically connected to the output bumps via the transistors.

[0006] The control signal wiring further includes a first connection wiring that is electrically connected to the output bumps located in a first row and electrically connects the output bumps located in a second row and the control signal wiring, and a second connection wiring that electrically connects the output bumps located in a third row and the control signal wiring.

[0007] The transistors further include a first transistor arranged in the non-display area and coupled to the control signal wiring, a second transistor arranged in the non-display area and coupled to the first connecting wiring, and a third transistor arranged in the non-display area and coupled to the second connecting wiring.

[0008] Each of the first to third transistors is a switching transistor.

[0009] The control signal wiring, the first connection wiring, and the second connection wiring are arranged in the same layer.

[0010] In the output bump area, the dummy bumps are arranged in the nth row (where n is a natural number), the detection bumps are arranged in the n+1th row adjacent to the nth row, and the output bumps are arranged in the n+2th row adjacent to the n+1th row.

[0011] The dummy bumps, the detection bumps, and the output bumps are arranged in three rows.

[0012] In the output bump region, the number of the dummy bumps is greater than the number of the detection bumps and greater than the number of the output bumps.

[0013] In the output bump region, the detection bumps are arranged in the (5n-4)th and (5n-1)th columns of a first row and a second row adjacent to the first row, respectively (where n is a natural number); The dummy bumps are arranged in the 5n-th column of each of the first row and the second row and in a third row adjacent to the second row, and the output bumps are arranged in the 5n-3-th column and the 5n-2-th column of each of the first row and the second row.

[0014] In the output bump area, the detection bumps are arranged in columns 5n-4 and 5n-1 of the first row (where n is a natural number) and in columns 5n-3 and 5n-2 of the third row, the dummy bumps are arranged in column 5n of the first row and in columns 5n-4, 5n-1, and 5n of the second and third rows adjacent to the first row, respectively, and the output bumps are arranged in columns 5n-3 and 5n-2 of the first and second rows, respectively.

[0015] In the output bump area, the detection bumps are arranged in the 5n-4th and 5n-1st columns of a first row and a second row adjacent to the first row (where n is a natural number), the dummy bumps are arranged in the 5nth column of each of the first row and the second row, and the output bumps are arranged in the 5n-3rd and 5n-2nd columns of each of the first row and the second row.

[0016] In the output bump area, the detection bumps are arranged in columns 5n-4 and 5n-1 of the first row (where n is a natural number), the dummy bumps are arranged in columns 5n of the first row and a second row adjacent to the first row, and the output bumps are arranged in columns 5n-3 and 5n-2 of the first row.

[0017] In the output bump area, the detection bumps are arranged in columns 5n-3 and 5n-2 of the second row (where n is a natural number), the dummy bumps are arranged in columns 5n-4, 5n-1, and 5n of the first row and the second row adjacent to the second row, respectively, and the output bumps are arranged in columns 5n-3 and 5n-2 of the second row.

[0018] In the output bump area, the detection bumps are arranged in the 5n-2th column of each of a first row and a second row adjacent to the first row (where n is a natural number), the dummy bumps are arranged in the 5n-4th column, the 5n-1st column, and the 5nth column of each of the first row and the second row, and the output bumps are arranged in the 5n-3th column of each of the first row and the second row.

[0019] A high voltage is applied to each of the dummy bumps.

[0020] Each of the dummy bumps is in a floating state, and a ground voltage is applied to each of the dummy bumps.

[0021] The driver chip further includes a plurality of second output bumps attached to a bottom surface of the base portion, overlapping the data output region, and receiving a data voltage.

[0022] The display device further includes fan-out wiring electrically connected to each of the second output bumps to provide the data voltage to the light emitting element.

[0023] A control signal is applied to some of the output bumps, and other of the output bumps are in a floating state.

[0024] The sense pad measures the waveform of the control signal applied to the output bump.

[0025] A voltage is applied to some of the output bumps, and other of the output bumps are in a floating state.

[0026] The sense pad measures the magnitude of the voltage applied to the first output pad.

[0027] The first output bump, the detection bump, and the dummy bump are arranged corresponding to the output pads, respectively.

[0028] To achieve the above object, a display device according to the present invention includes a substrate including a display area and a pad area, a light-emitting element disposed in the display area on the substrate, a pad section disposed in the pad area on the substrate and including a plurality of output pads, a base section facing the substrate and overlapping the pad area, a plurality of output bumps attached to a bottom surface of the base section, connected in parallel to each other via transistors, some of which receive a control signal or a voltage, and a plurality of detection bumps attached to the bottom surface of the base section, electrically connected to each of the output bumps, at least one of which measures the waveform of the control signal or the magnitude of the voltage. The control signal wiring is electrically connected to the output bumps via the transistors.

[0029] The control signal wiring further includes a first connection wiring that is electrically connected to the output bumps located in a first row and electrically connects the output bumps located in a second row and the control signal wiring, and a second connection wiring that electrically connects the output bumps located in a third row and the control signal wiring.

[0030] The output bumps are arranged corresponding to the output pads, respectively, and the detection bumps are arranged corresponding to the output pads, respectively. [Effects of the Invention]

[0031] In the display device according to the present invention, all output bumps of the driver chips to which a control signal or voltage is applied are connected in parallel via connection wiring and control signal wiring. In addition, detection bumps electrically connected to the output bumps can measure the waveform or voltage of the control signal applied to the output bumps to detect whether the driver chip is defective. Therefore, if a defect occurs in the driver chip, the time it takes for the defect to occur can be delayed.

[0032] However, the effects of the present invention are not limited to this, and can be expanded in various ways without departing from the spirit and scope of the present invention. [Brief explanation of the drawings]

[0033] [Figure 1] FIG. 1 is a plan view showing a display device according to an embodiment of the present invention. [Figure 2] FIG. 2 is a cross-sectional view taken along line II' in FIG. [Figure 3] FIG. 3 is an enlarged cross-sectional view of region B in FIG. [Figure 4] FIG. 4 is an enlarged plan view showing an example of region A in FIG. [Figure 5] FIG. 5 is a block diagram of the driver chip for explaining a method for detecting defects in the driver chips of FIGS. [Figure 6] FIG. 6 is a plan view for explaining an example of a method for detecting defects in the driving chip of FIG. [Figure 7] FIG. 7 is a plan view for explaining an example of a method for detecting defects in the driving chip of FIG. [Figure 8] FIG. 8 is a plan view for explaining an example of a method for detecting defects in the driving chip of FIG. [Figure 9]FIG. 9 is a plan view for explaining another example of the defect detection method for the driver chip of FIG. [Figure 10] FIG. 10 is a plan view for explaining another example of the defect detection method for the driver chip of FIG. [Figure 11] FIG. 11 is a plan view for explaining another example of the defect detection method for the driver chip of FIG. [Figure 12] FIG. 12 is an enlarged plan view showing another example of the region A in FIG. [Figure 13] FIG. 13 is an enlarged plan view showing another example of the region A in FIG. [Figure 14] FIG. 14 is an enlarged plan view showing another example of the region A in FIG. [Figure 15] FIG. 15 is an enlarged plan view showing another example of the region A in FIG. [Figure 16] FIG. 16 is an enlarged plan view showing another example of the region A in FIG. [Figure 17] FIG. 17 is an enlarged plan view showing another example of the region A in FIG. [Figure 18] FIG. 18 is an enlarged plan view showing another example of the region A in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0034] Hereinafter, a display device according to an embodiment of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals are used to denote the same elements in the drawings, and redundant description of the same elements will be omitted.

[0035] Fig. 1 is a plan view showing a display device according to an embodiment of the present invention, and Fig. 2 is a cross-sectional view taken along line II' in Fig. 1.

[0036] As shown in Figures 1 and 2, a display device (DD) according to one embodiment of the present invention includes a display panel (DP), a pad part (PDP), a driver chip (IC), a circuit board (CB), and an anisotropic conductive film (ACF).

[0037] The display panel (DP) includes a substrate (SUB), a display section (DSP) disposed in a display area (DA) on the substrate (SUB), and an encapsulation layer (ENC) disposed on the display section (DSP) and surrounding the display section (DSP). The components of the display panel (DP) will be described in detail later.

[0038] The substrate (SUB) includes a display area (DA) and a non-display area (NDA). The non-display area (NDA) is located around the display area (DA). For example, the non-display area (NDA) surrounds or partially surrounds the display area (DA). The display area (DA) is an area that displays an image by generating light or adjusting the transmittance of light provided from an external light source. The non-display area (NDA) is an area that does not display an image.

[0039] The non-display area (NDA) includes a bending area (BA) and a pad area (PA). The bending area (BA) is located between the display area (DA) and the pad area (PA) in a plan view. A portion of the substrate (SUB) overlapping the bending area (BA) is bent based on a bending axis extending in a first direction (DR1). The pad area (PA) has a shape extending along one side of the display device (DD). For example, the pad area (PA) has a shape extending along the first direction (DR1) parallel to the top surface of the substrate (SUB).

[0040] A plurality of pixels (PX) are arranged in a display area (DA) on a substrate (SUB). Each pixel (PX) includes a drive element and a light-emitting element electrically connected to the drive element. Each pixel (PX) generates light in response to a drive signal. The pixels (PX) are arranged in a matrix in the display area (DA) as a whole. The pixels (PX) are components included in a display unit (DSP).

[0041] In the non-display area (NDA) on the substrate (SUB), drivers for driving the pixels (PX) are arranged. For example, a scan driver (SDV), an emission driver (EDV), and a driver chip (IC) are arranged in the non-display area (NDA) on the substrate (SUB).

[0042] In the display area (DA) on the substrate (SUB), data lines (DL), scan lines (SL), light-emitting control lines (EML), and drive voltage lines (PL) connected to the pixels (PX) are arranged. In the non-display area (NDA) on the substrate (SUB), first control signal lines (CSL1) connected to the scan driver (SDV), second control signal lines (CSL2) connected to the light-emitting driver (EDV), and fan-out lines (FL) connected to the pixels (PX) are arranged.

[0043] The scan lines (SL) are electrically connected to the scan driver (SDV) and extend in a first direction (DR1). The scan lines (SL) receive scan signals from the scan driver (SDV) and provide the scan signals to the pixels (PX).

[0044] The light emitting control line (EML) is electrically connected to the light emitting driver (EDV) and extends along a first direction (DR1). The light emitting control line (EML) receives a light emitting signal from the light emitting driver (EDV) and provides the light emitting signal to the pixel (PX). For example, an activation period of the light emitting signal corresponds to a light emitting period of the display device (DD), and an inactivation period of the light emitting signal corresponds to a non-light emitting period of the display device (DD).

[0045] The data wiring (DL) is electrically connected to the driver chip (IC) via the fan-out wiring (FL) and extends along a second direction (DR2) intersecting the first direction (DR1). That is, the data wiring (DL) is connected to the fan-out wiring (FL). The fan-out wiring (FL) is disposed in the non-display area (NDA) adjacent to the lower end of the display area (DA). The fan-out wiring (FL) receives a data voltage from the driver chip (IC) and provides the data voltage to the data wiring (DL). The data wiring (DL) provides the data voltage to the pixel (PX).

[0046] The driving voltage wiring (PL) is electrically connected to the driving chip (IC) and extends along the second direction (DR2). The driving voltage wiring (PL) receives a driving voltage from the driving chip (IC) and provides the driving voltage to the pixels (PX). For example, the driving voltage is a high power supply voltage for driving the pixels (PX).

[0047] The first control signal line (CSL1) is electrically connected to the driver chip (IC), and receives a first control signal from the driver chip (IC) and provides the first control signal to the scan driver (SDV).

[0048] The second control signal line (CSL2) is electrically connected to the driving chip (IC), and receives a second control signal from the driving chip (IC) and provides the second control signal to the light emitting driver (EDV).

[0049] The driver chip (IC) generates the first control signal, the second control signal, the drive voltage, and the data voltage. The scan driver (SDV) receives the first control signal from the driver chip (IC) and generates the scan signal based on the first control signal. The light emitting driver (EDV) receives the second control signal from the driver chip (IC) and generates the light emitting control signal based on the second control signal.

[0050] A pad section (PDP) is disposed in a pad area (PA) on the substrate (SUB). The pad section (PDP) includes an input pad (IPD) and an output pad (OPD). As shown in FIG. 4, a plurality of input pads (IPDs) and output pads (OPDs) are provided. Each of the input pads (IPDs) and output pads (OPDs) includes a metal, a transparent conductive material, or the like. For example, each of the input pads (IPDs) and output pads (OPDs) includes a metal such as gold (Au), silver (Ag), aluminum (Al), copper (Cu), or the like, and a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), or the like. These may be used alone or in combination with each other. In one embodiment, each of the input pads (IPDs) and output pads (OPDs) has a multi-layer structure including ITO / Ag / ITO.

[0051] The input pad (IPD) transmits voltages, control signals, etc. provided to the circuit board (CB) to the driver chip (IC). That is, the voltages, control signals, etc. output from the circuit board (CB) are provided to the driver chip (IC) through the input pad (IPD).

[0052] The output pad (OPD) receives voltages, control signals, etc. provided by the driver chip (IC). That is, the voltages, control signals, etc. output from the driver chip (IC) are provided to the pixels (PX), scan driver (SDV), and emission driver (EDV) through the output pad (OPD).

[0053] A driving chip (IC) is disposed in a pad area (PA) on the substrate (SUB). The driving chip (IC) controls signals, voltages, etc. provided to the pixels (PX). In one embodiment, when the substrate (SUB) includes glass, the driving chip (IC) has a chip-on-glass (COG) structure in which it is disposed directly on the substrate (SUB). In another embodiment, when the substrate (SUB) includes a transparent resin substrate, the driving chip (IC) may have a chip-on-plastic (COP) structure in which it is disposed directly on the substrate (SUB). However, the present invention is not limited thereto. A flexible film is disposed in the pad area (PA) on the substrate (SUB), and the driving chip (IC) may have a chip-on-film (COF) structure in which it is disposed directly on the flexible film.

[0054] The driver chip (IC) includes a base portion (BS) facing the substrate (SUB) and a bump portion (BP) attached to the bottom surface of the base portion (BS). The bump portion (BP) includes input bumps (IBP) and output bump groups (OBG). As shown in FIG. 4, a plurality of input bumps (IBP) and output bump groups (OBG) are provided. The input bumps (IBP) overlap the input pads (IPD), and the output bump groups (OBG) overlap the output pads (OPD). For example, the input bumps (IBP) and the output bump groups (OBG) each include a metal such as copper or gold. These may be used alone or in combination. The base portion (BS) may also include a plastic such as polyimide.

[0055] The input bumps (IBP) receive voltages and control signals provided by the circuit board (CB), and the output bump groups (OBG) output voltages provided to the pixels (PX), control signals provided to the scan driver (SDV), and control signals provided to the emission driver (EDV).

[0056] An anisotropic conductive film (ACF) is disposed in a pad area (PA) between a substrate (SUB) and a driver chip (IC). The anisotropic conductive film (ACF) bonds the pad portion (PDP) and the driver chip (IC). Thus, the anisotropic conductive film (ACF) electrically connects the substrate (SUB) and the driver chip (IC). In one embodiment, the anisotropic conductive film (ACF) includes an adhesive layer (AL) and a plurality of conductive particles (CP) arranged in the adhesive layer (AL).

[0057] The adhesive layer (AL) includes an insulating polymeric material such as an epoxy resin, an acrylic resin, a phenolic resin, a melamine resin, a diallyl phthalate resin, a urea resin, a polyimide resin, a polystyrene resin, a polyurethane resin, a polyethylene resin, or a polyvinyl acetate resin, which may be used alone or in combination with each other.

[0058] The conductive particles (CP) are disposed between the pad portion (PDP) and the bump portion (BP). Specifically, the conductive particles (CP) are disposed between the input pad (IPD) and the input bump (IBP) and between the output pad (OPD) and the output bump group (OBG). Thus, the conductive particles (CP) electrically connect the substrate (SUB) and the driver chip (IC). In one embodiment, each of the conductive particles (CP) includes a core including an insulating polymer material and a conductive film surrounding the core and including a conductive metal material.

[0059] A circuit board (CB) is disposed in a pad area (PA) on a substrate (SUB). Specifically, the circuit board (CB) partially overlaps the pad area (PA). That is, a first portion of the circuit board (CB) overlaps the pad area (PA), and a second portion of the circuit board (CB) excluding the first portion does not overlap the pad area (PA). The circuit board (CB) is bonded to the substrate (SUB) via an anisotropic conductive film (ACF). This electrically connects the circuit board (CB) to the display panel (DP).

[0060] The pixels (PX) receive voltages, control signals, etc. from a circuit board (CB). In one embodiment, the circuit board (CB) includes a printed circuit board (PCB), a flexible printed circuit board (FPCB), or a flexible flat cable (FFC).

[0061] 1, the scan driver (SDV) is arranged in the non-display area (NDA) adjacent to the left side of the display area (DA), and the emission driver (EDV) is arranged in the non-display area (NDA) adjacent to the right side of the display area (DA), but the present invention is not limited thereto. For example, the gate driver (GDV) and the emission driver (EDV) may be arranged at other positions in the non-display area (NDA).

[0062] In this specification, a first direction (DR1) and a second direction (DR2) intersecting the first direction (DR1) are defined as a plane. For example, the second direction (DR2) is perpendicular to the first direction (DR1).

[0063] FIG. 3 is an enlarged cross-sectional view of region B in FIG.

[0064] 2 and 3, a display panel (DP) of a display device (DD) according to an embodiment of the present invention includes a substrate (SUB), a display section (DSP) disposed on the substrate (SUB), and an encapsulation layer (ENC) disposed on the display section (DSP). The display section (DSP) includes a buffer layer (BUF), a transistor (TR), a first insulating layer (IL1), a second insulating layer (IL2), a third insulating layer (IL3), a pixel defining layer (PDL), and a light-emitting element (LED). The transistor (TR) includes an active pattern (ACT), a gate electrode (GAT), a source electrode (SE), and a drain electrode (DE). The light-emitting element (LED) includes an anode electrode (ADE), an emitting layer (EL), and a cathode electrode (CTE).

[0065] The substrate (SUB) includes a transparent material or an opaque material. The substrate (SUB) is made of a transparent resin substrate. An example of a transparent resin substrate used as the substrate (SUB) is a polyimide substrate. In such a case, the polyimide substrate includes a first polyimide layer, a barrier film layer, a second polyimide layer, etc. In other embodiments, the substrate (SUB) may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate, a soda-lime glass substrate, a non-alkali glass substrate, etc. These may be used alone or in combination with each other.

[0066] A buffer layer (BUF) is disposed on the substrate (SUB). The buffer layer (BUF) prevents metal atoms and impurities from diffusing from the substrate (SUB) into the transistor (TR). The buffer layer (BUF) can also improve the flatness of the surface of the substrate (SUB) if the surface of the substrate (SUB) is uneven. For example, the buffer layer (BUF) may include an inorganic material such as silicon oxide, silicon nitride, silicon nitride, etc. These may be used alone or in combination with each other.

[0067] An active pattern (ACT) is disposed on the buffer layer (BUF). The active pattern (ACT) includes a metal oxide semiconductor, an inorganic semiconductor (e.g., amorphous silicon, polysilicon), or an organic semiconductor. The active pattern (ACT) includes a source region, a drain region, and a channel region located between the source region and the drain region.

[0068] The metal oxide semiconductors include binary compounds (ABx), ternary compounds (ABxCy), and quaternary compounds (ABxCyDz) containing indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), magnesium (Mg), etc. For example, the metal oxide semiconductors include zinc oxide (ZnOx), gallium oxide (GaOx), tin oxide (SnOx), indium oxide (InOx), indium gallium oxide (IGO), indium zinc oxide (IZO), indium tin oxide (ITO), indium zinc tin oxide (IZTO), indium gallium zinc oxide (IGZO), etc. These may be used alone or in combination with each other.

[0069] A first insulating layer (IL1) is disposed on the buffer layer (BUF). The first insulating layer (IL1) fully covers the active pattern (ACT), does not create a step around the active pattern (ACT), and has a substantially flat upper surface. Alternatively, the first insulating layer (IL1) can be disposed to cover the active pattern (ACT) and follow the profile of the active pattern (ACT) with a uniform thickness. For example, the first insulating layer (IL1) can include an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon carbide (SiCx), silicon oxynitride (SiOxNy), silicon oxycarbide (SiOxCy), etc. These can be used alone or in combination with each other.

[0070] A gate electrode (GAT) is disposed on the first insulating layer (IL1). The gate electrode (GAT) overlaps the channel region of the active pattern (ACT). The gate electrode (GAT) includes a metal, an alloy metal nitride, a conductive metal oxide, a transparent conductive material, etc. Examples of the metal include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), and scandium (Sc). Examples of the conductive metal oxide include indium tin oxide and indium zinc oxide. Examples of the metal nitride include aluminum nitride (AlNx), tungsten nitride (WNx), and chromium nitride (CrNx). These may be used alone or in combination with each other.

[0071] A second insulating layer (IL2) is disposed on the first insulating layer (IL1). The second insulating layer (IL2) fully covers the gate electrodes (GAT), does not create a step around the gate electrodes (GAT), and has a substantially flat upper surface. Alternatively, the second insulating layer (IL2) can be disposed to cover the gate electrodes (GAT) and follow the respective profiles of the gate electrodes (GAT) with a uniform thickness. For example, the second insulating layer (IL2) can include an inorganic material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, etc. These can be used alone or in combination with each other.

[0072] A source electrode (SE) and a drain electrode (DE) are disposed on the interlayer insulating layer (ILD). The source electrode (SE) is connected to the source region of the active pattern (ACT) through a contact hole that penetrates a first portion of the first insulating layer (IL1) and the second insulating layer (IL2). The drain electrode (DE) is connected to the drain region of the active pattern (ACT) through a contact hole that penetrates a second portion of the first insulating layer (IL1) and the second insulating layer (IL2). For example, each of the source electrode (SE) and the drain electrode (DE) may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like, which may be used alone or in combination with each other.

[0073] As a result, a transistor (TR) including an active pattern (ACT), a gate electrode (GAT), a source electrode (SE), and a drain electrode (DE) is disposed in the display area (DA) on the substrate (SUB).

[0074] A third insulating layer (IL3) is disposed on the second insulating layer (IL2). The third insulating layer (IL3) fully covers the source electrode (SE) and the drain electrode (DE). The third insulating layer (IL3) includes an inorganic material or an organic material. For example, the third insulating layer (IL3) includes an organic material such as a phenolic resin, an acrylic resin, a polyimide resin, a polyamide resin, a siloxane resin, an epoxy resin, etc. These may be used alone or in combination with each other.

[0075] An anode electrode (ADE) is disposed on the third insulating layer (IL3). The anode electrode (ADE) is connected to the drain electrode (DE) of the transistor (TR) through a contact hole penetrating the third insulating layer (IL3). For example, the anode electrode (ADE) may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. In one embodiment, the anode electrode (ADE) has a stacked structure including ITO / Ag / ITO.

[0076] A pixel defining layer (PDL) is disposed on the third insulating layer (IL3). The pixel defining layer (PDL) covers both sides of the anode electrode (ADE). The pixel defining layer (PDL) may be made of an organic material or may include an organic material. For example, the pixel defining layer (PDL) may include an organic material such as an epoxy resin or a siloxane resin. These may be used alone or in combination with each other. In another embodiment, the pixel defining layer (PDL) may further include a light-shielding material such as a black pigment or a black dye.

[0077] The light-emitting layer (EL) is disposed on the anode electrode (ADE). The light-emitting layer (EL) includes an organic material that emits light of a predetermined color. For example, the light-emitting layer (EL) includes an organic material that emits red light, green light, or blue light.

[0078] The cathode electrode (CTE) is disposed on the light-emitting layer (EL) and the pixel-defining layer (PDL). For example, the cathode electrode (CTE) may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0079] As a result, a light emitting element (LED) including an anode electrode (ADE), a light emitting layer (EL), and a cathode electrode (CTE) is disposed in a display area (DA) on the substrate (SUB).

[0080] An encapsulation layer (ENC) is disposed on the cathode electrode (CTE). The encapsulation layer (ENC) prevents impurities, moisture, and air from penetrating into the light emitting device (LED). The encapsulation layer (ENC) includes at least one inorganic layer and at least one organic layer. For example, the inorganic layer includes silicon oxide, silicon nitride, silicon oxynitride, etc. These may be used alone or in combination with each other. The organic layer includes a polymeric cured material such as polyacrylate.

[0081] FIG. 4 is an enlarged plan view showing an example of region A in FIG.

[0082] 1, 2, and 4, a display device (DD) according to an embodiment of the present invention includes a substrate (SUB), a pad part (PDP), first and second control signal wirings (CSL1, CSL2), first and second connection wirings (CL1, CL2), first to third signal wirings (SL1, SL2, SL3), first to third transistors (T1, T2, T3), and a driver chip (IC). Here, the driver chip (IC) includes a base part (BS) facing the substrate (SUB) and a bump part (BP) attached to the bottom surface of the base part (BS).

[0083] In one embodiment, when viewed from above, the pad part (PDP), the bump part (BP), the first to third transistors (T1, T2, T3), the first and second connection wirings (CL1, CL2), the first to third signal wirings (SL1, SL2, SL3), and the first and second control signal wirings (CSL1, CSL2) are arranged symmetrically with respect to a virtual line (VL) passing through the center of the driver chip (IC). The components located on the left side of the virtual line (VL) will be described below.

[0084] The base portion (BS) is divided into a first region (1A) and a second region (2A). Each of the first region (1A) and the second region (2A) extends along a first direction (DR1). The first region (1A) is adjacent to the circuit board (CB), and the second region (2A) is adjacent to the display region (DA).

[0085] The pad section (PDP) includes a plurality of input pads (IPD) and a plurality of output pads (OPD). The bump section (BP) includes a plurality of input bumps (IBP) and a plurality of output bump groups (OBG). Here, each of the output bump groups (OBG) includes a first output bump (OBP1), a second output bump (OBP2), a detection bump (DTB), and a dummy bump (DB).

[0086] The input pads (IPD) overlap the first region (1A) of the driver chip (IC). For example, the input pads (IPD) have the same shape as each other. The input pads (IPD) are repeatedly arranged along the first direction (DR1).

[0087] The output pads (OPD) overlap the second region (2A) of the base portion (BS). For example, the output pads (OPD) have the same shape as one another. The output pads (OPD) are repeatedly arranged along the first direction (DR1) and the second direction (DR2). In one embodiment, the output pads (OPD) are repeatedly arranged along the first direction (DR1) in a first row (1R) of the second region (2A), repeatedly arranged along the first direction (DR1) in a second row (2R) adjacent to the first row (1R) of the second region (2A), and repeatedly arranged along the first direction (DR1) in a third row (3R) adjacent to the second row (2R) of the second region (2A). That is, the output pads (OPD) are arranged in three rows in the second region (2A). Due to the large number of pixels (PX) controlled by the driving chip (IC), the number of output pads (OPD) is greater than the number of input pads (IPD).

[0088] Each of the input bumps (IBP) is arranged corresponding to each of the input pads (IPD). That is, each of the input bumps (IBP) at least partially overlaps each of the input pads (IPD). In other words, the input bumps (IBP) overlap the first region (1A) of the base portion (BS) and are repeatedly arranged along the first direction (DR1). Each of the input bumps (IBP) is electrically connected to each of the input pads (IPD). For example, the input bumps (IBP) have the same shape as each other.

[0089] The second region (2A) of the base portion (BS) includes a dummy bump region (DMA), an output bump region (OBA), and a data output region (DTA). Each of the dummy bump regions (DMA) is located to the right and left of the output bump region (OBA). That is, each of the output bump regions (OBA) is located between the dummy bump regions (DMA). The center of the data output region (DTA) coincides with the imaginary line (VL).

[0090] Each of the first output bumps (OBP1) is arranged corresponding to each of the output pads (OPD). That is, each of the first output bumps (OBP1) at least partially overlaps each of the output pads (OPD). In other words, the first output bumps (OBP1) are arranged in three rows in the second region (2A). Specifically, the first output bumps (OBP1) overlap each of the output bump regions (OBA) and are repeatedly arranged along the first direction (DR1) and the second direction (DR2). In the output bump region (OBA), each of the first output bumps (OBP1) is electrically connected to each of the output pads (OPD).

[0091] When the display device (DD) is in a driving state, a control signal is applied to at least one first output bump (OBP1), and the control signal is provided to the first control signal line (CSL1) via the output pad (OPD) corresponding to the at least one first output bump (OBP1). For example, when the control signal is applied only to the first output bump (OBP1) located in the first row (1R), the first output bumps (OBP1) located in the second row (2R) and the third row (3R) are in a floating state. In contrast, when the display device (DD) is in a non-driving state, a voltage is applied to at least one first output bump (OBP1).

[0092] Each of the second output bumps (OBP2) is arranged corresponding to a corresponding one of the output pads (OPD). That is, each of the second output bumps (OBP2) at least partially overlaps with a corresponding one of the output pads (OPD). In other words, the second output bumps (OBP2) are arranged in three rows in the second region (2A). Specifically, the second output bumps (OBP2) overlap the data output region (DTA) and are repeatedly arranged along the first direction (DR1) and the second direction (DR2). In the data output region (DTA), each of the second output bumps (OBP2) is electrically connected to a corresponding one of the output pads (OPD). A data voltage is applied to the second output bumps (OBP2), and the data voltage is provided to the fan-out wiring (FL) via the output pads (OPD) corresponding to the second output bumps (OBP2).

[0093] Each of the dummy bumps (DB) is arranged corresponding to a corresponding output pad (OPD). That is, each of the dummy bumps (DB) at least partially overlaps a corresponding output pad (OPD). In other words, the dummy bumps (DB) are arranged in three rows in the second region (2A). In one embodiment, some of the dummy bumps (DB) overlap the dummy bump regions (DMA) and are repeatedly arranged along the first direction (DR1) and the second direction (DR2), and other parts of the dummy bumps (DB) overlap the output bump regions (OBA) and are repeatedly arranged along the first direction (DR1) and the second direction (DR2). The dummy bumps (DB) may not be electrically connected to the output pads (OPD) corresponding to the dummy bumps (DB).

[0094] The dummy bumps (DB) minimize the potential difference between adjacent first output bumps (OBP1). In one embodiment, a high voltage is applied to the dummy bumps (DB). In another embodiment, the dummy bumps (DB) may be in a floating state. In another embodiment, a ground voltage may be applied to the dummy bumps (DB).

[0095] Each of the detection bumps (DTB) is arranged corresponding to each of the output pads (OPD). That is, each of the detection bumps (DTB) at least partially overlaps each of the output pads (OPD). In other words, the detection bumps (DTB) are arranged in three rows in the second region (2A). Specifically, the detection bumps (DTB) overlap the output bump region (OBA) and are repeatedly arranged along the first direction (DR1) and the second direction (DR2). In the output bump region (OBA), each of the detection bumps (DTB) is electrically connected to each of the output pads (OPD).

[0096] In one embodiment, the output pads (OPD) corresponding to the detection bumps (DTB) are connected to the output pads (OPD) corresponding to the first output bumps (OBP1), so that each of the detection bumps (DTB) is electrically connected to each of the first output bumps (OBP1) located in the same row (e.g., the first row (1R), the second row (2R), or the third row (3R)).

[0097] When the display device (DD) is in the driving state, the detection bump (DTB) measures the waveform of the control signal applied to the first output bump (OBP1) to detect whether the driver chip (IC) is defective. On the other hand, when the display device (DD) is in the non-driving state, the detection bump (DTB) measures the magnitude of the voltage applied to the first output bump (OBP1) to detect whether the driver chip (IC) is defective. A driver chip (IC) defect refers to the lifting or corrosion of the driver chip (IC) in a high-temperature, high-humidity environment or a general user environment. This will be described in more detail below.

[0098] In one embodiment, only dummy bumps (DB) are arranged in the dummy bump area (DMA), and only second output bumps (OBP2) are arranged in the data output area (DTA).

[0099] In the output bump area (OBA), first output bumps (OBP1), dummy bumps (DB), and detection bumps (DTB) are arranged. In one embodiment, in the output bump area (OBA), the dummy bumps (DB) are arranged in an n-th row, the detection bumps (DTB) are arranged in an n+1-th row adjacent to the n-th row, and the first output bumps (OBP1) are arranged in an n+2-th row adjacent to the n+1-th row (where n is a natural number).

[0100] The fan-out wiring (FL) is connected to the output pads (OPD) located in the first row (1R) in the data output area (DTA), respectively, so that the fan-out wiring (FL) is electrically connected to the second output bumps (OBP2) located in the first row (1R) in the data output area (DTA).

[0101] The first control signal wiring (CSL1) is connected to each of the output pads (OPD) located in the first row (1R) in the output bump area (OBA), thereby electrically connecting the first control signal wiring (CSL1) to each of the first output bumps (OBP1) located in the first row (1R) in the output bump area (OBA).

[0102] The first connection wiring (CL1) is connected to the first control signal wiring (CSL1) and the output pads (OPD) located in the second row (2R) in the output bump area (OBA), respectively, so that the first connection wiring (CL1) is electrically connected to the first control signal wiring (CSL1) and the first output bumps (OBP1) located in the second row (2R) in the output bump area (OBA).

[0103] The second connection wiring (CL2) is connected to the first control signal wiring (CSL1) and the output pads (OPD) located in the third row (3R) in the output bump area (OBA), respectively, so that the second connection wiring (CL2) is electrically connected to the first control signal wiring (CSL1) and the first output bumps (OBP1) located in the third row (3R) in the output bump area (OBA).

[0104] That is, in the output bump area (OBA), the first output bump (OBP1) located in the first row (1R), the first output bump (OBP1) located in the second row (2R), and the first output bump (OBP1) located in the third row (3R) are connected in parallel via the first connection wiring (CL1), the second connection wiring (CL2), and the first control signal wiring (CSL1).

[0105] The first transistor (T1) is disposed in the non-display area (NDA) on the substrate (SUB). The first transistor (T1) includes a first electrode, a second electrode, and a gate electrode. The first electrode of the first transistor (T1) is connected to a first control signal wiring (CSL1). The second electrode of the first transistor (T1) is connected to a second electrode of the second transistor (T2). The gate electrode of the first transistor (T1) is connected to a first signal wiring (SL1). A first signal is applied to the gate electrode of the first transistor (T1) via the first signal wiring (SL1).

[0106] The second transistor (T2) is disposed in the non-display area (NDA) on the substrate (SUB). The second transistor (T2) includes a first electrode, a second electrode, and a gate electrode. The first electrode of the second transistor (T2) is connected to the first connection wiring (CL1). The second electrode of the second transistor (T2) is connected to the second electrode of the third transistor (T3). The gate electrode of the second transistor (T2) is connected to the second signal wiring (SL2). A second signal is applied to the gate electrode of the second transistor (T2) via the second signal wiring (SL2).

[0107] The third transistor (T3) is disposed in the non-display area (NDA) on the substrate (SUB). The third transistor (T3) includes a first electrode, a second electrode, and a gate electrode. The first electrode of the third transistor (T3) is connected to the second connection wiring (CL2). The second electrode of the third transistor (T3) is connected to the second electrode of the second transistor (T2). The gate electrode of the third transistor (T3) is connected to the third signal wiring (SL3). A third signal is applied to the gate electrode of the third transistor (T3) via the third signal wiring (SL3).

[0108] In one embodiment, each of the first to third transistors (T1, T2, T3) is a switching transistor.

[0109] In one embodiment, the first control signal wiring (CSL1), the second control signal wiring (CSL2), the first connection wiring (CL1), the second connection wiring (CL2), the first signal wiring (SL1), the second signal wiring (SL2), and the third signal wiring (SL3) are arranged in the same layer on the substrate (SUB).

[0110] In a display device (DD) according to an embodiment of the present invention, all first output bumps (OBP1) of a driver chip (IC) to which a control signal or voltage is applied are connected in parallel via first and second connection lines (CL1, CL2) and a control signal line (e.g., a first control signal line (CSL1) or a second control signal line (CSL2)). In addition, a detection bump (DTB) electrically connected to the first output bump (OBP1) measures the waveform of the control signal or the magnitude of the voltage applied to the first output bump (OBP1) to detect whether the driver chip (IC) is defective. This delays the time it takes for the driver chip (IC) to become defective when a defect occurs in the driver chip (IC).

[0111] Fig. 5 is a block diagram of a driver chip for explaining a defect detection method for the driver chips of Fig. 1 and Fig. 4. Figs. 6 to 8 are plan views for explaining an example of a defect detection method for the driver chip of Fig. 5. Figs. 9 to 11 are plan views for explaining an example of a defect detection method for the driver chip of Fig. 5.

[0112] 5 to 11, the driver chip (IC) includes a first fault detection unit (DDP1), a second fault detection unit (DDP2), a third fault detection unit (DDP3), a first signal inverter (SI1), and a second signal inverter (SI2). Each of the first to third fault detection units (DDP1, DDP2, and DDP3) includes a control signal generation unit (CSG), a voltage generation unit (VG), a waveform measurement unit (WM), and a voltage measurement unit (VM). Here, each of the control signal generation unit (CSG), the voltage generation unit (VG), the waveform measurement unit (WM), the voltage measurement unit (VM), and the first and second signal inverters (SI1 and SI2) is a software configuration of the driver chip (IC).

[0113] The first defect detection unit (DDP1) is configured to detect defects that occur in the driver chip (IC) portion corresponding to the first row (1R), the second defect detection unit (DDP2) is configured to detect defects that occur in the driver chip (IC) portion corresponding to the second row (2R), and the third defect detection unit (DDP3) is configured to detect defects that occur in the driver chip (IC) portion corresponding to the third row (3R).

[0114] The driver chip (IC) detects whether the driver chip (IC) is defective through the control signal or voltage applied to the first output bump (OBP1). First, a case where the display device (DD) is in the driving state will be described as an example. When the display device (DD) is in the driving state, the control signal generator (CSG) generates a control signal (CS) and the voltage generator (VG) does not generate a voltage.

[0115] 6, a control signal (CS) generated by the control signal generator (CSG) of the first defect detector (DDP1) is applied to a first output bump (OBP1) located in a first row (1R), and the first output bumps (OBP1) located in the second row (2R) and the third row (3R) are in a floating state (FLOATING) (S10). In this case, a first transistor (T1) is turned on by the first signal provided by a first signal wiring (SL1), a second transistor (T2) is turned off by the second signal provided by a second signal wiring (SL2), and a third transistor (T3) is turned off by the third signal provided by a third signal wiring (SL3). Here, the first signal has a high level, and the second signal and the third signal each have a low level.

[0116] The control signal (CS) applied to the first output bump (OBP1) located in the first row (1R) is provided to the detection bump (DTB) located in the first row (1R). The waveform measurement unit (WM) of the first defect detection unit (DDP1) then measures the waveform of the control signal (CS) provided to the detection bump (DTB) based on the second signal (S2). For example, if the peak value of the control signal (CS) provided to the detection bump (DTB) is smaller than the peak value of the control signal (CS) applied to the first output bump (OBP1) by a predetermined value, the driver chip (IC) corresponding to the first row (1R) is determined to be defective. Alternatively, if the peak-to-peak interval of the control signal (CS) provided to the detection bump (DTB) is greater than or equal to a predetermined value, the driver chip (IC) corresponding to the first row (1R) is determined to be defective.

[0117] If the driver chip (IC) portion corresponding to the first row (1R) is determined to be normal, the waveform measurement unit (WM) of the first fault detection unit (DDP1) provides a first on signal (SON1) to the control signal generation unit (CSG) of the first fault detection unit (DDP1), and the control signal generation unit (CSG) of the first fault detection unit (DDP1) generates a control signal (CS), and the above process is repeated. If the driver chip (IC) portion corresponding to the first row (1R) is determined to be defective, the waveform measurement unit (WM) of the first fault detection unit (DDP1) provides a first off signal (SOFF1) to the first signal inverter (SI1) and the control signal generation unit (CSG) of the second fault detection unit (DDP2). The control signal generation unit (CSG) of the first fault detection unit (DDP1), receiving the first off signal (SOFF1), does not generate a control signal (CS). That is, the first output bump (OBP1) located in the first row (1R) is in a floating state. The first signal inverter (SI1) converts the first off signal (SOFF1) into a second on signal (SON2). The second on signal (SON2) is provided to the control signal generator (CSG) of the second failure detector (DDP2).

[0118] 7, when the part of the driver chip (IC) corresponding to the first row (1R) is determined to be defective, the first output bumps (OBP1) located in the first row (1R) and the third row (3R) are in a floating state (FLOATING), and the control signal (CS) generated by the control signal generator (CSG) of the second defect detection unit (DDP2) based on the second on signal (SON2) is applied to the first output bump (OBP1) located in the second row (2R) (S20). In this case, the first transistor (T1) is turned off by the first signal provided by the first signal wiring (SL1), the second transistor (T2) is turned on by the second signal provided by the second signal wiring (SL2), and the third transistor (T3) is turned off by the third signal provided by the third signal wiring (SL3). Here, the second signal has a high level, and the first signal and the third signal each have a low level.

[0119] The control signal (CS) applied to the first output bump (OBP1) located in the second row (2R) is provided to the detection bump (DTB) located in the second row (2R). Then, the waveform measurement unit (WM) of the second defect detection unit (DDP2) measures the waveform of the control signal (CS) provided to the detection bump (DTB) based on the second signal (S2).

[0120] If the driver chip (IC) portion corresponding to the second row (2R) is determined to be normal, the waveform measurement unit (WM) of the second fault detection unit (DDP2) provides a second on signal (SON2) to the control signal generation unit (CSG) of the second fault detection unit (DDP2), which then generates the control signal (CS), and the above process is repeated. If the driver chip (IC) portion corresponding to the second row (2R) is determined to be defective, the waveform measurement unit (WM) of the second fault detection unit (DDP2) provides a second off signal (SOFF2) to the second signal inverter (SI2) and the control signal generation unit (CSG) of the third fault detection unit (DDP3). The control signal generation unit (CSG) of the second fault detection unit (DDP2), receiving the second off signal (SOFF2), does not generate the control signal (CS). That is, the first output bump (OBP1) located in the second row (2R) is in a floating state. The second signal inverter (SI2) converts the second off signal (SOFF2) into a third on signal (SON3). The third on signal (SON3) is provided to the control signal generator (CSG) of the third failure detector (DDP3).

[0121] When the part of the driver chip (IC) corresponding to the second row (2R) is determined to be defective, as shown in FIG. 8, the first output bumps (OBP1) located in the first row (1R) and the second row (2R) are in a floating state, and the control signal (CS) generated by the control signal generator (CSG) of the third defect detection unit (DDP3) based on the third on signal (SON3) is applied to the first output bump (OBP1) located in the third row (3R) (S30). In this case, the first transistor (T1) is turned off by the first signal provided by the first signal wiring (SL1), the second transistor (T2) is turned off by the second signal provided by the second signal wiring (SL2), and the third transistor (T3) is turned on by the third signal provided by the third signal wiring (SL3). Here, the third signal has a high level, and each of the first signal and the second signal has a low level.

[0122] The third defect detector (DDP3) detects whether the driver chip (IC) is defective in the same manner as the first and second defect detectors (DDP1, DDP2), and therefore, a description thereof will be omitted.

[0123] Finally, a control signal (CS) is applied to the first output bump (OBP1) located in the row corresponding to the part of the driver chip (IC) determined to be normal, and the control signal (CS) is provided to the scan driver (e.g., the scan driver (SDV) in FIG. 1) (or the light-emitting driver (EDV) in FIG. 1) via the first control signal wiring (CSL1) (or the second control signal wiring (CSL2) in FIG. 4).

[0124] However, the present invention is not limited to this, and there are various procedures for floating the first output bumps (OBP1) and applying the control signal (CS) to the first output bumps (OBP1). For example, as shown in Figure 9, the control signal (CS) is applied to each of the first to third rows (1R, 2R, 3R) (S10'). Here, if the part of the driver chip (IC) corresponding to the first row (1R) is determined to be defective, as shown in Figure 10, the first output bumps (OBP1) located in the first row (1R) are in a floating state, and the control signal (CS) is applied to the first output bumps (OBP1) located in the second row (2R) and the third row (3R) (S20'). Here, if the part of the driver chip (IC) corresponding to the second row (2R) is determined to be defective, as shown in Figure 11, the first output bumps (OBP1) located in each of the first row (1R) and the second row (2R) are in a floating state, and a control signal (CS) is applied to the first output bump (OBP1) located in the third row (3R) (S30').

[0125] The following description will be given taking the case where the display device (DD) is in the non-driving state as an example. When the display device (DD) is in the non-driving state, the control signal generator (CSG) does not generate a control signal (CS), and the voltage generator (VG) generates the voltage based on the first signal (S1). When the display device (DD) is in the non-driving state, the method of detecting a defect in the driver chip (IC) is substantially the same as the method of detecting a defect in the driver chip (IC) when the display device (DD) is in the driving state, except that the magnitude of the voltage is measured to detect a defect in the driver chip (IC). Therefore, a duplicated description will be omitted.

[0126] The voltage applied to the first output bump (OBP1) located in the first row (1R) is provided to the detection bump (DTB). Then, the voltage measurement unit (VM) of the first failure detection unit (DDP1) measures the magnitude of the voltage applied to the detection bump (DTB) based on the first signal (S1). For example, if the magnitude of the voltage applied to the detection bump (DTB) is reduced by a predetermined value from the magnitude of the voltage applied to the first output bump (OBP1), the voltage measurement unit (VM) determines that the portion of the driver chip (IC) corresponding to the first row (1R) is defective. The methods of detecting driver chip (IC) defects in the second failure detection unit (DDP2) and the third failure detection unit (DDP3) are substantially the same as the method of detecting driver chip (IC) defects in the first failure detection unit (DDP1).

[0127] Figures 12 to 18 are enlarged plan views showing other examples of region A in Figure 1. In the following, descriptions that overlap with those described in Figure 4 will be omitted or simplified.

[0128] Although Figures 12 to 18 do not show the switching transistors connected to the wiring (e.g., the first control signal wiring (CSL1), the second control signal wiring (CSL2), the first connection wiring (CL1), the second connection wiring (CL2), and the connection wiring (CL)), the switching transistors are connected to each of the wirings. Therefore, a description thereof will be omitted.

[0129] As shown in FIG. 12, the first output bumps (OBP1), dummy bumps (DB), and detection bumps (DTB) are arranged in the output bump area (OBA).

[0130] In one embodiment, the number of dummy bumps (DB) arranged in the output bump area (OBA) in Fig. 12 is greater than the number of dummy bumps (DB) arranged in the output bump area (OBA) in Fig. 4. That is, the number of dummy bumps (DB) located between the first output bumps (OBP1) is increased. In other words, the number of dummy bumps (DB) in the output bump area (OBA) is greater than the number of first output bumps (OBP1) and greater than the number of detection bumps (DTB).

[0131] As shown in Figure 13, the output bump area (OBA) has first output bumps (OBP1), dummy bumps (DB), and detection bumps (DTB). In one embodiment, the detection bumps (DTB) are arranged in the 5n-4th and 5n-1th columns of the first row (1R) and the second row (2R) in the output bump area (OBA). The dummy bumps (DB) are arranged in the 5n-th column of the first row (1R) and the second row (2R) in the output bump area (OBA), and in the third row (3R). The first output bumps (OBP1) are arranged in the 5n-3th and 5n-2nd columns of the first row (1R) and the second row (2R) in the output bump area (OBA), where n is a natural number.

[0132] Each of the detection bumps (DTB) is electrically connected to a corresponding one of the first output bumps (OBP1). The first output bumps (OBP1) located in the first row (1R) are connected to the first control signal wiring (CSL1) (or the second control signal wiring (CSL2)), and the second output bumps (OBP2) located in the second row (2R) are connected to the first control signal wiring (CSL1) via the first and second connection wirings (CL1, CL2). That is, the first output bumps (OBP1) are connected in parallel via the first connection wiring (CL1), the second connection wiring (CL2), and the first control signal wiring (CSL1) (or the second control signal wiring (CSL2)).

[0133] 14, the output bump area (OBA) has first output bumps (OBP1), dummy bumps (DB), and detection bumps (DTB). In one embodiment, the detection bumps (DTB) are arranged in the 5n-4th and 5n-1th columns of the first row (1R) and in the 5n-3rd and 5n-2nd columns of the third row (3R) in the output bump area (OBA). The dummy bumps (DB) are arranged in the 5n-4th column of the first row (1R) and in the 5n-4th, 5n-1st, and 5nth columns of the second row (2R) and the third row (3R) in the output bump area (OBA). In the output bump area (OBA), the first output bumps (OBP1) are arranged in the 5n-3 column and the 5n-2 column of each of the first row (1R) and the second row (2R) (where n is a natural number).

[0134] Each of the detection bumps (DTB) is electrically connected to a corresponding one of the first output bumps (OBP1). The first output bumps (OBP1) located in the first row (1R) are connected to the first control signal wiring (CSL1) (or the second control signal wiring (CSL2)), and the first output bumps (OBP1) located in the second row (2R) are connected to the first control signal wiring (CSL1) via the first and second connection wirings (CL1, CL2). That is, the first output bumps (OBP1) are connected in parallel via the first connection wiring (CL1), the second connection wiring (CL2), and the first control signal wiring (CSL1) (or the second control signal wiring (CSL2)).

[0135] 15, 16, 17, and 18, the output pads (OPD) are arranged only in the first row (1R) and the second row (2R). Also, the first output bump (OBP1), the second output bump (OBP2), the dummy bump (DB), and the detection bump (DTB) of each output bump group (OBG) are arranged only in the first row (1R) and the second row (2R). That is, the first output bump (OBP1), the second output bump (OBP2), the dummy bump (DB), and the detection bump (DTB) are arranged only in two rows.

[0136] Referring again to FIG. 15 , the output bump area (OBA) is provided with a first output bump (OBP1), a dummy bump (DB), and a detection bump (DTB). In one embodiment, the detection bump (DTB) is arranged in the 5n-4th and 5n-1th columns of each of the first row (1R) and the second row (2R) in the output bump area (OBA). The dummy bump (DB) is arranged in the 5n-th column of each of the first row (1R) and the second row (2R) in the output bump area (OBA). The first output bump (OBP1) is arranged in the 5n-3th and 5n-2nd columns of each of the first row (1R) and the second row (2R) in the output bump area (OBA), where n is a natural number.

[0137] Each of the detection bumps (DTB) is electrically connected to a corresponding one of the first output bumps (OBP1). The first output bumps (OBP1) located in the first row (1R) are connected to the first control signal wiring (CSL1) (or the second control signal wiring (CSL2)), and the first output bumps (OBP1) located in the second row (2R) are connected to the first control signal wiring (CSL1) (or the second control signal wiring (CSL2)) via the first and second connection wirings (CL1, CL2). That is, the first output bumps (OBP1) are connected in parallel via the first connection wiring (CL1), the second connection wiring (CL2), and the first control signal wiring (CSL1) (or the second control signal wiring (CSL2)).

[0138] Referring again to FIG. 16, the output bump area (OBA) is provided with a first output bump (OBP1), a dummy bump (DB), and a detection bump (DTB). In one embodiment, the detection bump (DTB) is arranged in the first row (1R) and in the 5n-4th and 5n-1th columns in the output bump area (OBA). The dummy bump (DB) is arranged in the first row (1R) and in the 5n-1st column in the output bump area (OBA), and in the second row (2R). The first output bump (OBP1) is arranged in the first row (1R) and in the 5n-3rd and 5n-2nd columns (where n is a natural number) in the output bump area (OBA).

[0139] Each of the detection bumps (DTB) is electrically connected to a corresponding one of the first output bumps (OBP1). Each of the first output bumps (OBP1) is electrically connected to a first control signal wiring (CSL1) (or a second control signal wiring (CSL2)), and adjacent first control signal wirings (CSL1) are connected via bridge wirings (BL). That is, the first output bumps (OBP1) are connected in parallel via the first control signal wirings (CSL1) and the bridge wirings (BL).

[0140] Referring again to FIG. 17 , the output bump area (OBA) is provided with a first output bump (OBP1), a dummy bump (DB), and a detection bump (DTB). In one embodiment, the detection bump (DTB) is arranged in the second row (2R) and the 5n-3 column and the 5n-2 column in the output bump area (OBA). The dummy bump (DB) is arranged in the first row (1R) and the second row (2R) and the 5n-4 column, the 5n-1 column, and the 5n column in the output bump area (OBA). The first output bump (OBP1) is arranged in the first row (1R) and the 5n-3 column and the 5n-2 column (where n is a natural number) in the output bump area (OBA).

[0141] Each of the detection bumps (DTB) is electrically connected to a respective one of the first output bumps (OBP1). Also, each of the first output bumps (OBP1) is electrically connected to a first control signal wiring (CSL1) (or a second control signal wiring (CSL2)), and adjacent first control signal wirings (CSL1) are connected via a bridge wiring (BL). That is, the first output bumps (OBP1) are connected in parallel via the first control signal wiring (CSL1) (or the second control signal wiring (CSL2)) and the bridge wiring (BL).

[0142] Referring again to FIG. 18 , the output bump area (OBA) is provided with a first output bump (OBP1), a dummy bump (DB), and a detection bump (DTB). In one embodiment, the detection bump (DTB) is arranged in the 5n-2 column of each of the first row (1R) and the second row (2R) in the output bump area (OBA). The dummy bump (DB) is arranged in the 5n-4 column, the 5n-1 column, and the 5n column of each of the first row (1R) and the second row (2R) in the output bump area (OBA). The first output bump (OBP1) is arranged in the 5n-3 column of each of the first row (1R) and the second row (2R) in the output bump area (OBA), where n is a natural number.

[0143] Each of the detection bumps (DTB) is electrically connected to a corresponding one of the first output bumps (OBP1). The first output bumps (OBP1) located in the first row (1R) are electrically connected to the first control signal wiring (CSL1) (or the second control signal wiring (CSL2)), and the first output bumps (OBP1) located in the second row (2R) are electrically connected to the first control signal wiring (CSL1) (or the second control signal wiring (CSL2)) via the connection wiring (CL). That is, the first output bumps (OBP1) are connected in parallel via the connection wiring (CL) and the first control signal wiring (CSL1) (or the second control signal wiring (CSL2)).

[0144] Although the present invention has been described with reference to exemplary embodiments, those skilled in the art will recognize that various modifications and variations can be made thereto without departing from the spirit and scope of the invention as set forth in the following claims. [Industrial Applicability]

[0145] The present invention can be applied to various display devices equipped with a display device, such as high-resolution smartphones, mobile phones, smart pads, smart watches, tablet PCs, vehicle navigation systems, televisions, computer monitors, and notebook computers. [Explanation of symbols]

[0146] DD:Display device SUB: Substrate DA:Display area PA: Pad area NDA: Hidden area LED: Light-emitting element IC: Driver chip BS: Base section OPD: Output Pad OBP1, OBP2: First and second output bumps DB: Dummy Bump 2R DTB: Detection Bump OBA: Output Bump Area DMA: Dummy bump area DTA: Data output area T1, T2, T3: first to third transistors CSL1, CSL2: First and second control signal wiring CL1, CL2: First and second connection wiring SL1, SL2, SL3: First to third signal wirings

Claims

1. a substrate including a display area and a non-display area including a pad area located around the display area and adjacent to one side of the display area; a light-emitting element disposed in the display region on the substrate; a pad section disposed in the pad region on the substrate and including a plurality of output pads; a base portion facing the substrate, overlapping the pad area, and including dummy bump areas, output bump areas positioned between the dummy bump areas, and data output areas positioned between the dummy bump areas; a plurality of dummy bumps attached to a bottom surface of the base portion and overlapping the dummy bump region and the output bump region; a plurality of output bumps attached to a bottom surface of the base portion, overlapping the output bump regions, and connected in parallel to each other via transistors; a driver chip attached to a bottom surface of the base portion, the driver chip including a plurality of detection bumps, each of which is electrically connected to one of the output bumps and overlaps the output bump area; and a control signal wiring electrically connected to the output bump via the transistor.

2. the control signal wiring is electrically connected to the output bumps located in a first row; a first connection wiring that electrically connects the output bumps located in a second row to the control signal wiring; 2. The display device according to claim 1, further comprising a second connection wiring that electrically connects the output bumps located in the third row to the control signal wiring.

3. The transistor is a first transistor disposed in the non-display area and connected to the control signal wiring; a second transistor disposed in the non-display area and connected to the first connection wiring; 3. The display device according to claim 2, further comprising a third transistor disposed in the non-display area and connected to the second connection wiring.

4. 4. The display device according to claim 3, wherein each of the first to third transistors is a switching transistor.

5. 3. The display device according to claim 2, wherein the control signal wiring, the first connection wiring, and the second connection wiring are arranged in the same layer.

6. In the output bump region, the dummy bumps are arranged in an n-th row (where n is a natural number), the detection bumps are arranged in an (n+1)th row adjacent to the nth row, The display device of claim 1 , wherein the output bumps are arranged in an (n+2)th column adjacent to the (n+1)th column.

7. 7. The display device according to claim 6, wherein the dummy bumps, the detection bumps, and the output bumps are arranged in three rows.

8. 2. The display device according to claim 1, wherein the number of the dummy bumps in the output bump region is greater than the number of the detection bumps and greater than the number of the output bumps.

9. In the output bump region, the detection bumps are arranged in the (5n-4)th and (5n-1)th columns of a first row and a second row adjacent to the first row, respectively (where n is a natural number); the dummy bumps are arranged in the 5n-th column of each of the first row and the second row and in a third row adjacent to the second row; 2. The display device according to claim 1, wherein the output bumps are arranged in the (5n-3)th and (5n-2)th columns of the first and second rows, respectively.

10. In the output bump region, the detection bumps are arranged in a first row, a column (5n-4) and a column (5n-1) (where n is a natural number), and in a third row, a column (5n-3) and a column (5n-2); the dummy bumps are arranged in a 5n-th column of the first row, and in a 5n-4th column, a 5n-1th column, and a 5n-th column of each of a second row and a third row adjacent to the first row; 2. The display device according to claim 1, wherein the output bumps are arranged in the (5n-3)th and (5n-2)th columns of the first and second rows, respectively.

11. In the output bump region, the detection bumps are arranged in the (5n-4)th and (5n-1)th columns of a first row and a second row adjacent to the first row, respectively (where n is a natural number); the dummy bump is arranged in the 5n-th column of each of the first row and the second row, 2. The display device according to claim 1, wherein the output bumps are arranged in the (5n-3)th and (5n-2)th columns of the first and second rows, respectively.

12. In the output bump region, the detection bumps are arranged in a first row and in columns (5n-4 and 5n-1), where n is a natural number; the dummy bumps are arranged in the 5nth column of the first row and in a second row adjacent to the first row; 2. The display device according to claim 1, wherein the output bumps are arranged in the (5n-3)th and (5n-2)th columns of the first row.

13. In the output bump region, the detection bumps are arranged in columns (5n-3) and (5n-2) of a second row (where n is a natural number); the dummy bumps are arranged in the (5n-4)th column, the (5n-1)th column, and the (5n)th column of each of the first row and the second row adjacent to the second row; 2. The display device according to claim 1, wherein the output bumps are arranged in the second row and in the (5n-3)th and (5n-2)th columns.

14. In the output bump region, the detection bumps are arranged in a first row and a second row adjacent to the first row in a (5n-2)th column (where n is a natural number); the dummy bumps are arranged in the (5n-4)th column, the (5n-1)th column, and the (5n)th column of each of the first row and the second row; 2. The display device according to claim 1, wherein the output bump is arranged in the (5n-3)th column of each of the first row and the second row.

15. 2. The display device according to claim 1, wherein a high voltage is applied to each of the dummy bumps.

16. 2. The display device of claim 1, wherein each of the dummy bumps is in a floating state and a ground voltage is applied to each of the dummy bumps.

17. The display device of claim 1 , wherein the driver chip further comprises a plurality of second output bumps attached to a bottom surface of the base, overlapping the data output region, and receiving a data voltage.

18. 18. The display device of claim 17, further comprising fan-out wiring electrically connected to each of the second output bumps to provide the data voltage to the light emitting element.

19. 2. The display device according to claim 1, wherein a control signal is applied to some of the output bumps, and other of the output bumps are in a floating state.

20. 20. The display device of claim 19, wherein the detection bump measures the waveform of the control signal applied to the output bump.

21. 2. The display device according to claim 1, wherein a voltage is applied to some of the output bumps, and other of the output bumps are in a floating state.

22. 22. The display device of claim 21, wherein the detection bump measures the magnitude of the voltage applied to the output pad.

23. 2. The display device according to claim 1, wherein the output bumps, the detection bumps, and the dummy bumps are arranged corresponding to the output pads, respectively.

24. a substrate including a display area and a pad area; a light-emitting element disposed in the display region on the substrate; a pad section disposed in the pad region on the substrate and including a plurality of output pads; a base portion facing the substrate and overlapping the pad region; a plurality of output bumps attached to a bottom surface of the base portion, connected in parallel to each other via transistors, and some of which receive a control signal or voltage; a driver chip attached to a bottom surface of the base portion and including a plurality of detection bumps electrically connected to each of the output bumps, at least one of which measures the waveform of the control signal or the magnitude of the voltage; and a control signal wiring electrically connected to the output bump via the transistor.

25. the control signal wiring is electrically connected to the output bumps located in a first row; a first connection wiring that electrically connects the output bumps located in a second row to the control signal wiring; 25. The display device according to claim 24, further comprising a second connection wiring that electrically connects the output bumps located in a third row to the control signal wiring.

26. 25. The display device according to claim 24, wherein each of the output bumps is disposed corresponding to each of the output pads, and each of the detection bumps is disposed corresponding to each of the output pads.

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