Semiconductor substrate patterning

Abstract

A method for forming a semiconductor device includes receiving a substrate in a processing chamber, the substrate including a first patterned layer including a metal-based material, and trimming the first patterned layer to form a second patterned layer by a gas etching process, the gas etching process including exposing the first patterned layer to a non-ionized gas including a halogen compound.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Patent Application No. 17 / 888,972, filed August 16, 2022, which is incorporated herein by reference.

[0002] The present invention relates generally to methods for manufacturing semiconductor devices, and more particularly, in certain embodiments, to patterning semiconductor substrates. [Background technology]

[0003] An integrated circuit (IC) is a network of electronic circuit components in a monolithic structure that includes a stack of patterned layers in a semiconductor substrate. ICs are fabricated by processing the substrate through a series of patterning levels, where a layer is deposited and patterned by photolithographic techniques at each level. This process involves printing a pattern of actinic radiation onto a photoresist-coated surface and transferring the printed pattern to lower layers by using the patterned resist as a mask for pattern-transfer etching.

[0004] With each new technology node, minimum feature design rules are scaled to double component packing density and lower the unit cost of integrated circuits. As a result, the number of pattern levels with nano-sized features has steadily increased. Even though minimum-pitch features at the 10-nm node can be printed using common 193-nm optics assisted by multiple patterning techniques, the increasing number of masks and masking steps required for multiple patterning remains a cost-limiting factor for further scaling. At sub-10-nm nodes, the critical pattern level may switch to shorter-wavelength 13.5-nm extreme ultraviolet (EUV) lithography. However, the successful implementation of EUV in mass production requires not only printing higher-resolution minimum-pitch features but also controlling line edge roughness (LER) and local critical dimension uniformity (LCDU) to less than approximately 1 to 3 nm. Therefore, method innovations to improve LER and LCDU are desirable. Summary of the Invention [Means for solving the problem]

[0005] A method of forming a semiconductor device, the method comprising: receiving a substrate in a processing chamber, the substrate including a first patterned layer including a metal-based material; and trimming the first patterned layer to form a second patterned layer by a gas etching process, the gas etching process comprising exposing the first patterned layer to a non-ionized gas including a halogen compound.

[0006] A method for patterning a semiconductor substrate includes receiving the substrate in a processing chamber, the substrate including a lithography stack over a layer to be patterned, the stack including a patterned metal-based resist (MBR) layer and an underlayer below the MBR layer; and flowing a non-ionized gas over the substrate, the gas including a halogen compound, wherein the flowing of the gas causes the MBR layer to chemically react with the halogen compound.

[0007] A method for forming a semiconductor device includes the steps of forming a metal-based resist (MBR) layer over a semiconductor substrate; patterning the MBR layer using a photolithography process to form a patterned MBR layer, where the patterned MBR layer includes lines having a first linewidth; exposing the patterned MBR layer to a flow of a non-ionized gas containing a halogen compound to change the linewidth of the lines from the first linewidth to a second linewidth, where the second linewidth is smaller than the first linewidth; and patterning a layer to be patterned after exposing the patterned MBR layer to the flow of the non-ionized gas containing a halogen compound, where patterning the layer to be patterned includes performing a pattern transfer etching process using the patterned MBR layer as an etching mask.

[0008] For a fuller understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions which should be read in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0009] [Figure 1A] 1A-1C illustrate methods of patterning a semiconductor substrate according to some embodiments with cross-sectional views of a semiconductor device at various intermediate stages of fabrication. [Figure 1B] 1A-1C illustrate methods of patterning a semiconductor substrate according to some embodiments with cross-sectional views of a semiconductor device at various intermediate stages of fabrication. [Figure 1C]1A-1C illustrate methods of patterning a semiconductor substrate according to some embodiments with cross-sectional views of a semiconductor device at various intermediate stages of fabrication. [Figure 1D] 1A-1C illustrate methods of patterning a semiconductor substrate according to some embodiments with cross-sectional views of a semiconductor device at various intermediate stages of fabrication. [Figure 1E] 1A-1C illustrate methods of patterning a semiconductor substrate according to some embodiments with cross-sectional views of a semiconductor device at various intermediate stages of fabrication. [Figure 1F] 1A-1C illustrate methods of patterning a semiconductor substrate according to some embodiments with cross-sectional views of a semiconductor device at various intermediate stages of fabrication. [Figure 1G] 1A-1C illustrate methods of patterning a semiconductor substrate according to some embodiments with cross-sectional views of a semiconductor device at various intermediate stages of fabrication. [Figure 2] 1 shows a flowchart of a method for patterning the semiconductor substrate shown in FIGS. 1A to 1G. [Figure 3] 1 illustrates a flowchart of a method for forming a semiconductor device, including a method for selecting a first process time before forming the semiconductor device, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0010] The present invention relates to a method for patterning a layer of a semiconductor substrate. A first layer is formed and patterned using photolithography, e.g., extreme ultraviolet (EUV) lithography, to form a first patterned layer. Generally, in photolithography, a photosensitive (resist) layer is formed on a substrate and exposed to a pattern of actinic radiation. For example, a radiation source for EUV lithography is radiation emitted in a narrow band around 13.5 nm from a laser-produced plasma (LPP) containing tin vaporized by a carbon dioxide laser. The exposed resist is then developed to transfer the radiation pattern into the resist, forming a first patterned layer. In the example described in this disclosure, the first patterned layer is a metal-based layer, e.g., a metal-based resist (MBR) layer. Using the method of the present invention, the first patterned layer is processed to form a second patterned layer. The second patterned layer can then be used as a masking layer in a first pattern-transfer etch to transfer the pattern into a layer of the substrate. The use of the embodiments described in the present disclosure provides the advantage of forming patterns in a patterned layer that have a low number of bridging and line-breaking defects for features such as arrays of lines designed at the minimum pitch of sub-10 nm technology nodes, and that have low line edge roughness (LER) values ​​relative to their line width W.

[0011] The term line refers to a feature that is shaped like a thin rectangle in plan view. The edge of a line refers to one of the two sides along the length dimension of the rectangle, with the length being the longer dimension. The position E of an edge is defined here as the distance of the edge from a reference line passing through the center of the feature along its length. Ideally, an edge would be perfectly straight, with E being a constant equal to W / 2. In practice, edges have roughness, i.e., E varies with the average value E when measured at various positions along its length. av = W / 2. The LER value is often three times the standard deviation of E (3σ ε) is a measure of the magnitude of this random variation in edge position. There is similar random variation at the edge of the top opening along the length of a patterned trench, which can be quantified by a similarly defined LER value for that trench. Random variation along the perimeter of a patterned hole or pillar, such as a contact hole or silicon pillar, is typically quantified by measuring the local critical dimension uniformity (LCDU) in the array of holes / pillars, where the critical dimension (CD) is the width of the hole / pillar.

[0012] Generally, LER degrades electrical behavior and, in severe cases, can even result in physical line breaks and bridging defects in densely packed features, such as arrays of lines with minimum pitch. For example, as the roughness of resist lines used as an etch mask when patterning sacrificial gates in a replacement metal gate (RMG) process flow increases, the unwanted leakage current of transistors increases. As another example, consider a patterned resist layer used as a mask for etching trenches in the interlayer dielectric (ILD) between adjacent interconnect levels. Typically, rectangular trenches with nearly vertical sidewalls are formed where rectangular openings are patterned in the resist (assuming a positive resist). The trenches are then filled with metal, and the excess metal is etched back to form inlaid metal lines. Random variations in the position of the edges of the openings in the resist layer are transferred to the respective trench sidewalls by the etching process. When the trenches are filled with metal, the roughness of the trench sidewalls translates into line width roughness (LWR) of the respective metal interconnect lines, which increases parasitic resistance and reduces the electromigration lifetime of the metal lines. For these and other similar reasons, it is beneficial to use patterning methods that offer the advantage of low LER, such as the embodiments described in this disclosure.

[0013] As mentioned in the background section, minimum feature sizes are constantly being scaled to smaller dimensions. Clearly, the smaller the linewidth in an IC design, the greater the impact of LER on IC performance and reliability. 13.5-nm EUV lithography can replace the current 193-nm deep ultraviolet (DUV) lithography for patterning higher-resolution features at the limiting patterning level in the sub-10-nm node. However, controlling LER in EUV resist lines is complicated by stochastic effects associated with high EUV photon energy.

[0014] The 14.3 times higher energy of EUV photons compared to 193 nm DUV photons (92 eV vs. 6.4 eV) allows for a fixed exposure dose, e.g., 15 mJ / cm, typically used to expose photoresists. 2 This means that the number of photons incident on the resist for EUV is 1 / 14.3 times that for DUV. The 1:14.3 ratio refers to the average number of photons, and the local number of photons varies randomly from position to position. In other words, after the resist is exposed to a radiation pattern containing a line, 2 The number of photon hits in a spot of 15 mJ / cm is a random variable whose value varies with the position of the spot along its length. 2 For an average exposure of 1 nm 2 A spot receives an average of 10 photon hits from exposure to 13.5 nm EUV radiation, compared to 143 photon hits for 193 nm DUV radiation. The spatial variation in photon number corresponds to the spatial variation in exposure dose, which is the number of photons multiplied by the photon energy. The smaller the average number of photons, the greater the magnitude of the random variation in exposure dose from one location to another relative to the average exposure dose.

[0015] Photon number fluctuations (often called shot noise) are mathematically modeled as a Poisson process, where the mean value of the random numbers (μ n ) is its variance (σ n 2 ) The rate of change of random numbers is generally equal to σ n / μn For a Poisson process, σ n / μ n =√(μ n ) -1 Therefore, as expected, resist exposure with EUV radiation has higher spatial variation compared to that with DUV radiation, since the ratio of EUV to DUV photons is 1:14.3 for the same exposure dose. This theoretically means that the percentage variation of the local exposure dose is √14.3, i.e., 3.8 times larger for EUV lithography compared to DUV lithography.

[0016] Other undesirable resist stochastic effects include those related to the random nature of photon absorption and the associated photochemical reactions. For example, the fraction of incident photons absorbed by the resist varies randomly with spatial position. Also, the trajectories of the cascade of photoelectrons and secondary electrons that interact with the resist after a photon absorption event and chemically alter the polymer structure are random, a phenomenon known as random walk. Similar to the fluctuations in the number of incident photons, the impact of these stochastic processes on resist exposure is worse for EUV compared to DUV.

[0017] Stochastic effects due to photon discreteness are the three-dimensional effect of a finite number of photons absorbed at random locations in a volume of resist. Therefore, random spatial variations in resist exposure not only increase the LER of the resist line but also increase the roughness of the top surface of the resist. A non-uniform top surface means random variations in resist thickness. The trend in resist thickness scaling is toward thinner resists to avoid deformation and even collapse of high-aspect-ratio resist features, despite the worsening shot noise caused by thinner resists due to the reduced average number of photons in the resist. For narrow line widths at the sub-10 nm node, resist thickness can be scaled down to avoid mechanical instability of high-aspect-ratio lines. Typically, a substrate can be coated with EUV resist with a thickness of approximately 20 nm to 40 nm, and in some cases as small as 15 nm. Thinning the resist thickness reduces the masking ability of the patterned resist layer to mask subsequent pattern-transfer etching. Thickness variations around the average value further exacerbate this situation. At certain random locations along the resist line, the resist thickness may be insufficient to mask the etchant for the entire duration of the etch, exposing the underlying layer to the etchant and resulting in a line break defect.

[0018] After the first patterned layer is formed in the developer, the substrate is processed to modify the first patterned layer to form a second patterned layer. A first pattern transfer etch is performed to pattern the underlying layer below the resist using the second patterned layer as a masking layer. Generally, the process includes performing an etching step to trim the first patterned layer. Trimming can serve two purposes: resist descumming and adjusting the resist line width to a smaller target CD. The trimmed resist is the second patterned layer.

[0019] If the descum etching process involves chemically and / or physically trimming the resist by interaction with high-energy particles, the resist material may be damaged. For example, if a plasma process is used, the resist may be damaged by high-energy ions and radicals in the plasma. The damage manifests as line break defects and severe LER. The enhanced roughness may be the result of resist notching caused by high-energy particles in the plasma colliding with the surface of the first patterned layer. Damaged resist lines due to notching along the edges may result in further line breaks during the first pattern transfer etch (typically a plasma etch process) using the second patterned layer as an etch mask. Such damage is avoided by using a resist descum / trim process in embodiments of the method of the present invention, described in more detail below.

[0020] In an embodiment of the present disclosure, a gas etching process using a non-ionized gas is performed to create the second patterned layer. As described in more detail below, the gas etching process used in the combined descum and trim etch is a chemical surface treatment that removes resist residue and reduces resist line widths without damaging the resist pattern. As described above, the first pattern transfer etch uses the second patterned layer (the layer remaining after trimming the first patterned layer) as an etch mask.

[0021] The term non-ionized gas does not mean that the gas is completely free of ions. It is understood that there is a very low ion density consistent with ambient temperature. In this disclosure, non-ionized gas refers to a gas state that is not a gas discharge plasma, in which the gas is in a weakly ionized state with an ion density that is many orders of magnitude higher than the thermal equilibrium density of ions in the respective non-ionized gas.

[0022] Resist trimming / descum gas etching using a non-ionized gas is utilized in the process flow of a method for patterning a semiconductor substrate. This process is described with reference to Figures 1A-1G, and a flow chart of the method is shown in Figure 2.

[0023] 1A shows a cross-sectional view of a semiconductor device 100 including a semiconductor substrate 102 on which a layer to be patterned 104 is formed. For concreteness, in this example, the layer to be patterned 104 is a titanium nitride (TiN) layer. In general, the layer to be patterned can be a dielectric layer (e.g., silicon oxide, silicon nitride, and carbon-doped oxide (CDO)), a metal layer (e.g., aluminum, titanium, and titanium nitride), or a semiconductor layer (e.g., amorphous silicon). The semiconductor substrate 102 can be a combination of various semiconductor, dielectric, and metal layers fabricated on a starting substrate. The starting substrate can be an elemental semiconductor (e.g., Si and Ge), a compound semiconductor (e.g., GaAs, GaN, InAs, InP, CdS, and ZnO), a semiconductor alloy (e.g., Ga x As 1-x , Ga x Al 1-x N, Si x Ge 1-x ), silicon-on-insulator (SOI), and others.

[0024] 1B, a lithography stack 110 is formed over the layer to be patterned 104. Typically, the lithography stack includes a sacrificial layer. A first layer 114 on top of the lithography stack 110 includes a metal-based material. In exemplary embodiments of the present disclosure, the first layer 114 is an MBR layer. In some embodiments, the first layer 114 can be formed using, for example, a spin-on process.

[0025] Although traditional organic chemically amplified resists (CARs) have been successfully fabricated using deep ultraviolet (DUV) lithography, they are unlikely to be used in high-volume manufacturing with extreme ultraviolet (EUV) lithography. The atoms (C, H, O, and N) in organic resists have small capture cross sections for EUV photons, resulting in low sensitivity of CARs to EUV radiation. Additionally, as known to those skilled in the art, the trade-off between resolution, linear error (LER), and sensitivity (RLS) inherent in organic CARs limits their RLS metrics. The trend toward thinner resists is also likely to be an insurmountable hurdle. Structural stability at high aspect ratios imposes an upper limit on resist thickness, while masking capability imposes a lower limit. The poor mechanical strength and poor etch resistance of organic CARs effectively eliminate a usable window for resist thickness at the sub-10 nm node, where minimum pitches are 30 nm or less.

[0026] Meanwhile, MBRs are a promising class of organic-inorganic hybrid resists. MBRs have a molecular structure that includes peripheral organic ligands bound to an inorganic core. The core comprises a metal nanoparticle or metal-oxo nanocluster. Generally, metal atoms have a much higher capture cross-section for EUV photons. By incorporating metals, MBRs offer higher sensitivity to EUV radiation, higher etch resistance, and higher mechanical strength, resulting in better structural stability. Therefore, MBRs are preferred for EUV lithography. The first layer 114 can be an MBR with a metal oxide core, such as oxides of hafnium, zirconium, titanium, tin, zinc, indium, and aluminum. The photoresist (e.g., first layer 114) in the present disclosure is a tin-based resist. In one embodiment, the thickness of the tin-based resist first layer 114 is approximately 22 nm; in various embodiments, this thickness can be 15 nm to 35 nm. The tin-oxo nanoclusters are smaller and more uniformly distributed, and therefore the tin-oxo nanocluster MBR may provide higher resolution and lower LER.

[0027] 1B, underlayer 112 is disposed below and adjacent to first layer 114. Underlayer 112 is typically used as a bottom anti-reflective coating (BARC) comprising a material selected to suppress undesired reflections and standing wave patterns due to interference between incident and reflected light. Underlayer 112 may include an organic BARC, a silicon-based anti-reflective coating (SiARC), a spin-on glass (SOG), or a silicon carbide (SiC) layer, etc. In some embodiments, underlayer 112 may be formed using, for example, a spin-on process.

[0028] The lithography stack 110 may optionally include a hard mask layer 106 and a planarization layer 108, as shown in the cross-sectional view shown in FIG. 1B.

[0029] The material of the hard mask layer 106 is selected to be resistant to an etchant used to remove portions of the layer to be patterned 104. In the example shown in FIG. 1B, if the layer to be patterned 104 includes TiN, the hard mask layer 106 may include tetraethyl orthosilicate (TEOS). In some embodiments, the layer to be patterned 104 and the hard mask layer 106 may be formed using, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or plasma-enhanced CVD (PECVD) processes.

[0030] In various embodiments, the planarization layer 108 is x H y It may be an organic planarization layer (OPL), such as a polymer or amorphous carbon layer, and may be formed, for example, using a spin-on process. Generally, the planarization layer 108 has a sufficiently low viscosity so that the top surface of the planarization layer 108 forms a substantially flat surface.

[0031] FIG. 1C illustrates a cross-sectional view of semiconductor device 100 after first layer 114 has been patterned using photolithography, e.g., EUV lithography, to form first patterned layer 116. In this example, first layer 114 is an MBR layer, and first patterned layer 116 is a patterned MBR layer. First patterned layer 116 may be formed by exposing first layer 114 to a pattern of actinic radiation, which in this example is 13.5 nm EUV radiation. The exposed resist is then developed to form first patterned layer 116. Specifically, in this example, the resist is a positive resist. Thus, the developer removes the exposed portions of first layer 114, forming opening 115. In one embodiment, first patterned layer 116 may have a thickness of approximately 9 nm (compared to 22 nm of the tin-based photoresist formed on the substrate to form first layer 114). In various embodiments, the thickness of the first patterned layer 116 can be between 6 nm and 15 nm.

[0032] Densely packed features in a patterned layer (e.g., first patterned layer 116) can have random bridging and line break defects. A bridging defect is a defect in which the expected separation between two closely spaced features (e.g., two adjacent lines) is broken, for example, by random deviations in the edges of the two features. A line break defect occurs, for example, when the continuity of a narrow feature (e.g., a thin line) is disrupted due to random deviations in the edges of the opposite sides of the feature. Naturally, there is a trade-off between bridging and line breaks when selecting process parameters (e.g., radiation exposure time). For example, in an array of lines with a fixed pitch, a longer exposure time may reduce the probability of bridging, but at the expense of an increased probability of line breaks. Bridging between closely spaced lines can also be caused by resist residue or resist scum, such as bridging defect 118 in first patterned layer 116 shown in FIG. 1C. Process parameters can be optimized to suppress line breaks during process development, and a descum / trim etch is performed on the first patterned layer 116 to eliminate bridging defects and provide a process window for manufacturability.

[0033] FIG. 1D shows a cross-sectional view of semiconductor device 100 after first patterned layer 116 has been trimmed using a descum etch process to form second patterned layer 120, which includes trimmed resist lines 117 and a chemisorbed layer 122 on its surface, as described in more detail below. The descum etch process used in this exemplary embodiment is a gaseous etching process that typically involves exposing first patterned layer 116 to a gas containing a gaseous halogen compound diluted with an inert diluent gas. In one embodiment, the halogen compound is hydrogen bromide (HBr). In other embodiments, the halogen compound may be BCl, Cl, I, F, or HF. In one embodiment, the HBr gas is diluted with argon (Ar). In some other embodiments, the diluent gas may be some other inert gas, such as helium or nitrogen, or a combination of inert gases.

[0034] The gas etching process may be performed by loading the substrate into a processing chamber and flowing a gas mixture comprising a process gas (i.e., a halogen compound) and a dilution gas (i.e., an inert gas) over the substrate and through the chamber for a selected processing time. Flowing the gas exposes the first patterned layer 116 to the halogen compound for the selected processing time. During the processing time, the halogen compound may chemically interact with the metal of the first patterned layer 116. In one embodiment where the first patterned layer 116 comprises an MBR (e.g., a tin-based MBR) and the halogen compound is HBr, the chemical interaction occurs via the addition of a volatile metal bromide, such as tin bromide (SnBr x), which can be removed from the processing chamber by the gas flow. The chemical reaction removes not only the resist scum (e.g., bridging defect 118 in FIG. 1C ) but also portions of the resist features, thereby trimming the linewidth of the features and forming a descummed second patterned layer 120, as shown in FIG. 1D . For example, the first linewidth of a resist line in first patterned layer 116 is reduced to a second linewidth by this gas etching process, forming a narrower resist line in the same location in second patterned layer 120. Thus, the descum etch is also a trimming etch, which can be utilized to adjust the linewidth of the resist to a smaller target CD.

[0035] It should be noted that the chemical interaction is a surface interaction, and this surface treatment can further form a chemisorbed layer 122 on the surface of the MBR, as shown in Figure 1D. This reduces the linewidth reduction rate. As explained in more detail below, the linewidth reduction rate decreases monotonically with increasing process time.

[0036] The descum / trim etch process exposes the first patterned layer 116 to a non-ionized gas in thermal equilibrium at a controlled ambient temperature in the chamber. In other words, the gas (e.g., a gas mixture of HBr and Ar) is not in an excited state with a non-equilibrium distribution of high-energy particles. As explained above, harsh descum etching, such as plasma processing, can damage resist features because a gas discharge plasma is a weakly ionized gas in a non-equilibrium state with a large number of high-energy particles. A gas discharge plasma ignites by exciting a gas initially in thermal equilibrium at ambient temperature with an electromagnetic field, generating a collection of high-energy ions and radicals with an equivalent temperature typically more than an order of magnitude higher than ambient temperature. Because a damaged resist layer can cause increased line edge roughness (LER) and line break defects, an exemplary embodiment of the present disclosure uses a less aggressive gas etching process using a non-ionized gas to trim the first patterned layer 116 and form a second patterned layer 120 including a chemisorbed layer 122 formed on the surface of the trimmed resist features and MBR.

[0037] In some embodiments, before flowing the gas (e.g., a gas mixture of HBr process gas and Ar diluent gas), the substrate temperature is set to a selected ambient temperature of −10° C. or higher and 60° C. or lower and maintained constant during the descum / trim etch process. Experiments conducted by the inventors have shown that lowering the substrate temperature results in lower LER in the patterned lines etched by the first pattern transfer etch using the second patterned layer 120 as an etch mask. It should be noted that the adsorption rate typically increases with decreasing temperature. Therefore, the observed effect of temperature on LER indicates that the adsorption layer helps smooth the LER in the first patterned layer 116.

[0038] As previously described, the first patterned layer 116 is exposed to a gas mixture of HBr process gas and Ar diluent gas in a processing chamber for a selected process time to form the second patterned layer 120, as shown in FIG. 1D. In some embodiments, the processing chamber for the gas etch, descum etch, can be a gas-phase reaction chamber. In other embodiments, the substrate can be loaded into a plasma chamber, and the gas etch process can be performed in the plasma chamber before plasma ignition. An advantage of using a plasma chamber is that if the pattern transfer etch is a plasma process, such as reactive ion etching (RIE), and the second patterned layer 120 is an etch mask, subsequent pattern transfer etches can be performed in situ in the same plasma chamber.

[0039] In one embodiment, the flow of a gas mixture of HBr process gas and Ar diluent gas is controlled at 50 sccm for HBr and 500 sccm for Ar, the pressure in the processing chamber is controlled at 50 mTorr, and the selected process time is 10 seconds. In various embodiments, the selected flow rate of HBr can be between 8 sccm and 70 sccm, the selected flow rate of Ar can be between 300 sccm and 700 sccm, the pressure in the processing chamber can be controlled between 10 mTorr and 1 Torr, and the selected process time can be between 4 seconds and 15 seconds.

[0040] In FIG. 1E, a first pattern-transfer etch is performed using second patterned layer 120 as an etch mask to pattern underlayer 112. The first pattern-transfer etch removes exposed portions of underlayer 112, widening opening 115 and exposing the surface of the adjacent substrate below underlayer 112. The etching process may be, for example, an anisotropic RIE technique using appropriate etching chemistries. The etch reduces the thickness of the MBR in second patterned layer 120, as shown in FIG. 1E. However, patterned underlayer 112 may now be used as a masking layer for a subsequent second pattern-transfer etch.

[0041] As explained above, patterned underlayer 112 has an acceptably low defect density due to the use of an embodiment of the method of the present invention, in which a chemical surface treatment with a non-ionized gas containing a halogen compound is used as a gas etching process to trim first patterned layer 116 and remove resist scum to form second patterned layer 120. In various experiments conducted by the inventors, various materials, namely, SiARC, SOG, and SiC, were used to form underlayer 112. It was found that the pattern quality of patterned underlayer 112 (shown in FIG. 1E ) is not affected by the material used for underlayer 112.

[0042] FIG. 1F illustrates a cross-sectional view of semiconductor device 100 after a second pattern transfer etch has been performed. As shown in FIG. 1F, the second pattern transfer etch completes the patterning of lithography stack 110 to form patterned lithography stack 130. As shown in FIG. 1F, the second pattern transfer etch removes exposed portions of planarization layer 108 and hard mask layer 106, widening opening 115 and exposing the surface of layer to be patterned 104, now located adjacent to and below patterned hard mask layer 106. Typically, as shown in FIG. 1F, after the second pattern transfer etch, no second patterned layer 120, including trimmed resist lines 117, remains on the substrate, leaving behind chemisorption layer 122. Performing the second pattern transfer etch can include performing a series of appropriate etching steps using different etchants and process parameters, depending on the materials of planarization layer 108 and hard mask layer 106. Underlying layer 112 can be an etch mask during the second pattern transfer etch. Depending on the material selectivity of the etch process, a large portion of underlayer 112, or even the entire underlayer 112, may be lost during the second pattern-transfer etch, as shown in FIG. 1F.

[0043] In FIG. 1G, the layer to be patterned 104 is patterned using a third pattern-transfer etch using the patterned lithography stack 130 as an etch mask. In the exemplary embodiment shown in FIG. 1G, the layer to be patterned 104 is a TiN layer. A suitable third pattern-transfer etch process is used to remove tin from exposed portions of the layer to be patterned 104. The third pattern-transfer etch process may include, for example, a plasma etch process using chlorine chemistry to etch TiN. As shown in FIG. 1G, the remaining portions of the lithography stack 130, including the sacrificial layer, are typically stripped from the substrate after the third pattern-transfer etch is completed. However, in some embodiments, the etch process may be adjusted to retain a thin layer of the hard mask layer 106 on top of the patterned lines of the layer to be patterned 104. For example, in an embodiment in which the layer to be patterned 104 includes TiN and the hard mask layer 106 includes TEOS, a thin layer of TEOS may cover the top surface of the TiN lines.

[0044] In some embodiments, the first pattern transfer etch, the second pattern transfer etch, and the third pattern transfer etch are performed in-situ in a plasma chamber. In other embodiments, where the descum / trim gas etch is performed in a plasma chamber, the descum / trim etch, the first pattern transfer etch, the second pattern transfer etch, and the third pattern transfer etch may all be performed in-situ in the same plasma chamber.

[0045] It should be understood that in some embodiments, the process flows described above (with respect to Figures 1A-1G) may include additional process steps, for example, a resist bake may be performed on second patterned layer 120 before etching underlayer 112.

[0046] FIG. 2 shows a flowchart summarizing process flow 200, which was described above with respect to FIGS. 1A-1G. As shown in box 210 (and FIG. 1A), a delivered substrate has a layer to be patterned formed on a semiconductor substrate. In box 220 (and FIG. 1B), a lithography stack is formed on the layer to be patterned. Typically, the lithography stack includes a sacrificial layer. As shown in box 230 (and FIG. 1C), photolithography (e.g., EUV lithography) can be used to pattern the MBR layer of the lithography stack to form a first patterned layer. The first patterned layer can have resist scum that needs to be removed and features that may require trimming. In box 240 (and FIG. 1D), a descum / trimming etch is performed to form a second patterned layer, which is the patterned MBR layer after descum and trimming. The etching process is a chemical surface treatment using a non-ionized gas flow containing a halogen compound (e.g., a gas mixture of HBr and Ar). As shown in box 250, the second patterned layer is used as a masking layer to transfer the pattern to the lithography stack. A pattern transfer etch is performed to pattern the underlying layer (as shown in FIG. 1E). If the lithography stack includes an optional planarization and / or hard mask layer, the patterned underlying layer can be used as a masking layer to transfer the pattern to the remaining portion of the lithography stack (as shown in FIG. 1F). As shown in box 260 (and FIG. 1G), the patterned lithography stack is used as an etch mask to transfer the pattern to the layer to be patterned. After each pattern transfer etch is completed, the remaining portion of the lithography stack can be stripped, as shown in box 270 (and as seen in FIG. 1G).

[0047] FIG. 3 shows a flowchart of a method 300 for forming a semiconductor device. The method 300 includes performing a sequence 301 of process steps in a manufacturing process flow for producing a semiconductor device. Additionally, in the exemplary method 300, a first process time may be selected during process development using method 302 prior to performing sequence 301, as shown in the flowchart of FIG. 3. The first process time is then used to perform a process step (box 330) of step sequence 301, as indicated by the dashed arrow in FIG. 3.

[0048] In sequence 301, an MBR layer is formed (box 310), patterned (box 320), and the substrate is exposed to a gas to trim the pattern lines in the patterned MBR layer (box 330).

[0049] At box 310, an MBR layer is formed on the semiconductor substrate using, for example, a spin-on process, in which the substrate is spun at a high rotational speed and a liquid MBR can be poured onto the top surface of the spinning substrate and distributed evenly over the surface by centrifugal force.

[0050] The MBR is a photosensitive material, such as a tin-oxo nanocluster organic-inorganic hybrid resist, selected to have a high absorption coefficient for EUV radiation. As shown in box 320, the MBR layer can be patterned by exposing it to a pattern of EUV radiation and developing the exposed MBR layer with a suitable developer to form a patterned MBR layer. The patterned MBR layer includes lines having a first linewidth.

[0051] After forming the patterned MBR layer, a trim etch (box 330) can be performed to change the linewidth of the lines from a first linewidth to a second linewidth, where the second linewidth is smaller than the first linewidth. The trim etch is a gas etching process. Trimming is achieved by exposing the MBR layer to a gas for a fixed time, a selected first process time, selected a priori using method 302, described in more detail below. The gas includes a halogen compound that trims the patterned MBR layer and removes resist scum. As explained above, an aggressive trim / descum etch can cause increased LER and line break defects during a subsequent pattern transfer etch in which the patterned MBR layer is the masking layer. Therefore, the gas stream to which the substrate is exposed during the trim / descum etch includes a non-ionized gas. The gas chemically reacts with the MBR surface, forming a chemisorbed layer on the surface through self-limiting interactions.

[0052] After exposing the substrate to the halogen compound in the non-ionized gas, the trimmed MBR layer can be used as an etch mask in a pattern transfer etch process to pattern other layers in the lithography stack and layers to be patterned below the lithography stack, as shown in box 340. As explained above, pattern transfer can be achieved in several steps that may use different etch chemistries depending on the materials used in the lithography stack and the materials used to form the layers to be patterned.

[0053] Process sequence 301 may be part of a manufacturing process flow for manufacturing semiconductor devices. The first process time may be selected prior to manufacturing, i.e., during process development, using method 302, as the first process time may be used in a process step of the manufacturing flow (i.e., box 330 of sequence 301). Once the first process time is selected, semiconductor devices may be manufactured in mass production using a manufacturing process flow that includes process sequence 301.

[0054] Typically, process development involves conducting several experiments, where a set of test substrates associated with different process conditions are processed. In this context, process conditions refer to a set of values ​​selected for different factors for each experiment, e.g., using a design of experiments (DOE) method. Varying a factor can affect observable metrics of the process results. Measurements are performed on the test substrates to evaluate the metrics and obtain a response function for the metric with respect to the factor. The response function is then used to select process conditions that provide a manufacturable process. For example, the inventors processed test substrates using a sequence of process steps 301, varying several process parameters for the underlying material and the descum / trim etch process. In addition, for each underlying material, a reference substrate was included in which the descum / trim etch step was omitted. The process parameters of the descum / trim etch process that were varied included process time, HBr flow rate, Ar flow rate, substrate temperature, and gas pressure. The measured metrics were the average linewidth and LER of a line within a dense array of lines drawn at a fixed pitch, which may be the minimum pitch allowed by the design rules. Measurements can be performed on the pattern on the substrate at different points in the sequence of process steps. In one embodiment, measurements are performed at two points in the process flow. The first measurement is performed during a post-development inspection immediately after the patterned MBR layer is formed (box 320). The second measurement is performed during a post-etch inspection after the layer to be patterned is patterned (box 340), where the patterning includes a pattern transfer etch and the etch mask is the trimmed MBR layer formed after the exposure of the MBR layer to the gas containing the halogen compound (box 330) is complete.

[0055] As shown in the flowchart depicted in FIG. 3 , method 302 includes conducting experiments during process development, where a group of substrates are processed through a process sequence similar to process sequence 301. In processing the group of substrates, a corresponding group of process times is used during trimming / descum etching. Each substrate in the group of substrates is associated with a process time in the group of process times. The difference in process times causes lines in the patterned and trimmed MBR layer to have different line widths (i.e., different second line widths) in the different substrates. The second line widths on each wafer are measured, and the measured second line widths are plotted against the corresponding process times to obtain a graph of line width versus process time.

[0056] As explained above, due to the self-limiting nature of chemical interactions and the formation of a chemisorbed layer, it is recognized that a linewidth versus process time graph has a turning point where the linewidth passes through a minimum value at that process time. In other words, the linewidth initially decreases with increasing process time, but as the process time is increased, the linewidth passes through a minimum value and may begin to increase. The linewidth versus process time graph obtained from the measurements is used to select a first process time to produce the desired linewidth. Note that if the selected first process time is near the turning point, the process will converge to a region of the graph where the linewidth is not affected by process time. This provides the advantage of reducing linewidth variation during manufacturing.

[0057] The embodiments described above in this disclosure are suitable for patterning substrates to produce patterns with low LER. This method has been demonstrated by the inventors to form arrays of lines and spaces with dense pitches in the range of approximately 24 nm to 30 nm by patterning test substrates using metal-based photoresists and EUV lithography. [Example]

[0058] Example 1. A method of forming a semiconductor device, the method comprising: receiving a substrate in a processing chamber, the substrate comprising a first patterned layer comprising a metal-based material; and trimming the first patterned layer to form a second patterned layer by a gas etching process, the gas etching process comprising exposing the first patterned layer to a non-ionized gas comprising a halogen compound.

[0059] Example 2. The method of Example 1, further comprising, before forming the first layer, forming an underlayer over the substrate, and etching the underlayer using the second patterned layer as an etch mask to form a third patterned layer.

[0060] Example 3. The method of one of Examples 1 or 2, wherein the first patterned layer comprises an array of lines designed with a pitch that is a minimum pitch of a photolithography process used to form the first patterned layer.

[0061] Example 4. The method of one of Examples 1-3, wherein the first patterned layer is a metal-based resist (MBR).

[0062] Example 5. The method of one of Examples 1-4, wherein the gas etching process is a descum process, and the descum process reduces the number of defects due to resist residue.

[0063] Example 6. The method of one of Examples 1-5, wherein the first patterned layer is a tin-based resist.

[0064] Example 7. The method of one of Examples 1-6, wherein the first patterned layer is formed using an extreme ultraviolet (EUV) lithography process.

[0065] Example 8 The method of one of Examples 1-7, wherein the halogen compound is hydrogen bromide.

[0066] Example 9. The method of one of Examples 1-8, wherein exposing the first patterned layer to a gas comprising a halogen compound comprises flowing a gas comprising a halogen compound into a processing chamber and exposing the first patterned layer to the halogen compound for a selected process time.

[0067] Example 10. A method for patterning a semiconductor substrate, the method comprising: receiving the substrate in a processing chamber, the substrate including a lithography stack over a layer to be patterned, the stack including a patterned metal-based resist (MBR) layer and an underlayer below the MBR layer; and flowing a non-ionized gas over the substrate, the gas including a halogen compound, wherein flowing the gas causes the MBR layer to chemically react with the halogen compound.

[0068] Example 11. The method of Example 10, further comprising the steps of: setting the temperature of the substrate to a selected ambient temperature before flowing the gas, the selected ambient temperature being greater than or equal to -10°C and less than or equal to 60°C; and controlling the temperature of the substrate while flowing the gas.

[0069] Example 12 The method of one of Examples 10 or 11, wherein the halogen compound is hydrogen bromide.

[0070] Example 13. The method of one of Examples 10-12, wherein the underlayer comprises a silicon-based antireflective coating (SiARC), a spin-on glass (SOG), or silicon carbide.

[0071] Example 14. The method of any one of Examples 10-13, wherein the lithographic stack includes a planarization layer below the underlayer, and the planarization layer includes an organic planarization layer (OPL) or an amorphous carbon layer.

[0072] Example 15. The method of any one of Examples 10-14, wherein the lithographic stack includes a hard mask layer disposed between the underlayer and the layer to be patterned.

[0073] Example 16. The method of one of Examples 10 to 15, further comprising the step of patterning the lithography stack to form a patterned lithography stack after flowing gas onto the substrate, wherein the step of patterning the lithography stack comprises performing a pattern transfer etching process using the patterned MBR layer as an etching mask, wherein the pattern transfer etching process transfers the pattern of the patterned MBR layer to the lithography stack; and after patterning the lithography stack, patterning the layer to be patterned, wherein the patterning the layer to be patterned comprises performing a pattern transfer etching process using the patterned lithography stack as an etching mask.

[0074] Example 17. A method for forming a semiconductor device, the method comprising: forming a metal-based resist (MBR) layer on a semiconductor substrate; patterning the MBR layer using a photolithography process to form a patterned MBR layer, wherein the patterned MBR layer includes lines having a first linewidth; exposing the patterned MBR layer to a flow of non-ionized gas comprising a halogen compound to change the linewidth of the lines from the first linewidth to a second linewidth, wherein the second linewidth is smaller than the first linewidth; and patterning a layer to be patterned after exposing the patterned MBR layer to the flow of non-ionized gas comprising a halogen compound, wherein the layer to be patterned is patterned using a pattern transfer etching process using the patterned MBR layer as an etching mask.

[0075] Example 18 The method of Example 17, wherein the halogen compound is hydrogen bromide.

[0076] Example 19. The method of one of Examples 17 or 18, wherein the exposing step includes exposing the patterned MBR layer to a flow of a non-ionized gas for a first processing time, and the method further includes, before forming the semiconductor device, the steps of: obtaining a linewidth versus process time graph, the steps including processing a group of substrates using a corresponding set of process times, each substrate being associated with a corresponding process time; and for each substrate, measuring the linewidth of the line; and plotting the measured linewidths and the corresponding set of process times to obtain a linewidth versus process time graph; and selecting a first process time from the obtained linewidth versus process time graph, the first process time being selected to produce a desired linewidth in the linewidth versus process time graph.

[0077] Example 20. The method of one of Examples 17-19, wherein a chemisorbed layer is formed on the surface of the patterned MBR layer by exposing the patterned MBR layer to a stream of non-ionized gas.

[0078] While the present invention has been described with reference to exemplary embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the exemplary embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art upon reference to this description. It is therefore intended that the appended claims cover any such modifications or embodiments.

Claims

1. 1. A method of forming a semiconductor device, comprising: receiving a substrate in a processing chamber, the substrate including a first patterned layer including a metal-based material; trimming the first patterned layer to form a second patterned layer by a gas etching process, the gas etching process comprising exposing the first patterned layer to a non-ionized gas comprising a halogen compound; A method comprising:

2. forming an underlayer over the substrate prior to forming the first patterned layer; etching the underlying layer using the second patterned layer as an etch mask to form a third patterned layer; The method of claim 1 further comprising:

3. 3. The method of claim 2, wherein the first patterned layer comprises an array of lines designed with a pitch that is a minimum pitch of a photolithography process used to form the first patterned layer.

4. 10. The method of claim 1, wherein the first patterned layer is a metal-based resist (MBR).

5. 5. The method of claim 4, wherein the gas etching process is a descum process, and the descum process reduces the number of defects due to resist residue.

6. The method of claim 1 , wherein the first patterned layer is a tin-based resist.

7. The method of claim 1 , wherein the first patterned layer is formed using an extreme ultraviolet (EUV) lithography process.

8. 2. The method of claim 1, wherein the halogen compound is hydrogen bromide.

9. The step of exposing the first patterned layer to a gas comprising a halogen compound comprises: flowing the gas containing the halogen compound into the processing chamber; exposing the first patterned layer to the halogen compound for a selected process time; The method of claim 1 , comprising:

10. 1. A method for patterning a semiconductor substrate, comprising: receiving a substrate into a processing chamber, the substrate including a lithography stack over a layer to be patterned, the lithography stack including a patterned metal-based resist layer (MBR layer) and an underlayer below the MBR layer; flowing a non-ionized gas over the substrate, the non-ionized gas including a halogen compound, and the flowing of the non-ionized gas causes the MBR layer to chemically react with the halogen compound; A method comprising:

11. setting the temperature of the substrate to a selected ambient temperature before flowing the non-ionized gas, the selected ambient temperature being greater than or equal to -10°C and less than or equal to 60°C; controlling the temperature of the substrate while flowing the non-ionized gas; The method of claim 10 further comprising:

12. 11. The method of claim 10, wherein the halogen compound is hydrogen bromide.

13. The method of claim 10 , wherein the underlayer comprises a silicon-based anti-reflective coating (SiARC), a spin-on glass (SOG), or silicon carbide.

14. 11. The method of claim 10, wherein the lithographic stack includes a planarization layer below the underlayer, the planarization layer comprising an organic planarization layer (OPL) or an amorphous carbon layer.

15. The method of claim 10 , wherein the lithographic stack includes a hard mask layer disposed between the underlying layer and the layer to be patterned.

16. After flowing the non-ionized gas over the substrate, patterning the lithography stack to form a patterned lithography stack, the step of patterning the lithography stack comprising: performing a pattern transfer etching process using the patterned MBR layer as an etching mask, the pattern transfer etching process transferring the pattern of the patterned MBR layer to the lithography stack; patterning the layer to be patterned after patterning the lithography stack, wherein the patterning of the layer to be patterned comprises performing a pattern transfer etching process using the patterned lithography stack as an etching mask; The method of claim 10, comprising:

17. 1. A method of forming a semiconductor device, comprising: forming a metal-based resist layer (MBR layer) on a semiconductor substrate; patterning the MBR layer using a photolithography process to form a patterned MBR layer, the patterned MBR layer including lines having a first line width; exposing the patterned MBR layer to a flow of non-ionized gas containing a halogen compound to change the line width of the lines from the first line width to a second line width, the second line width being smaller than the first line width; exposing the patterned MBR layer to a flow of non-ionized gas containing a halogen compound, and then patterning the layer to be patterned, the patterning comprising performing a pattern transfer etching process using the patterned MBR layer as an etching mask; A method comprising:

18. 18. The method of claim 17, wherein the halogen compound comprises hydrogen bromide.

19. the exposing step includes exposing the patterned MBR layer to the flow of the non-ionized gas for a first process time; obtaining a line width versus process time graph prior to forming the semiconductor device; processing a group of substrates using a corresponding group of process times, each substrate being associated with a corresponding process time; measuring the line width of the lines for each substrate; Plotting the measured line widths and corresponding process times to obtain a graph of line width versus process time; and selecting the first process time from the obtained line width versus process time graph, the first process time being selected to produce a desired line width in the line width versus process time graph; 20. The method of claim 17, comprising:

20. 18. The method of claim 17, wherein a chemisorbed layer is formed on the surface of the patterned MBR layer by exposing the patterned MBR layer to a flow of non-ionized gas.

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