2D Material Gate-All-Around Complementary FET Integration

Abstract

Complementary field-effect transistors (CFETs) are disclosed that are formed from stacked 2D-material transistors. The 2D-material transistors are formed from atomically thin semiconductors called transition metal dichalcogenides (TMDs). Stacked TMD transistors enable enhanced drive currents and lower switching capacitances, both of which are desirable.

Description

[Technical Field]

[0001]

[0001] The present disclosure relates generally to high performance devices, and more particularly, but not exclusively, to devices having 2D-material gate-all-around (GAA) complementary field effect transistor (CFET) integration. [Background technology]

[0002]

[0002] Integrated circuit technology has achieved great progress in increasing computing power by miniaturizing components such as semiconductor transistors. Semiconductor advancements have progressed from bulk substrate and planar CMOS, FinFET, nanowires or nanoribbons, FinFET 3D stacks, to nanowire or nanoribbon 3D stacks. Semiconductor technology is primarily based on silicon. However, fabrication of silicon-based transistors can be problematic with further scaling, for example, down to a few nanometers.

[0003]

[0003] Therefore, there is a need for systems, apparatus, and methods that overcome the shortcomings of conventional devices, including the methods, systems, and apparatus provided herein. Summary of the Invention

[0004] The following presents a simplified summary of one or more aspects and / or examples related to the apparatus and methods disclosed herein. As such, the following summary should not be considered an extensive overview of all contemplated aspects and / or examples, nor should it be considered to identify key or critical elements of all contemplated aspects and / or examples or to delineate the scope associated with any particular aspect and / or example. As such, the following summary is solely intended to present certain concepts related to one or more aspects and / or examples related to the apparatus and methods disclosed herein in a simplified form prior to the detailed description presented below.

[0005] An exemplary complementary field effect transistor (CFET) structure is disclosed. The CFET structure may include a lower source contact and a lower drain contact in an intermetal dielectric (IMD) layer. The CFET structure may also include a lower gate-all-around (GAA) gate region between the lower source and drain contacts in the IMD layer. The lower GAA gate region may be of a first conductivity type and may include one or more lower channel structures. Each lower channel structure may include a lower transition metal dichalcogenide (TMD) channel electrically coupled to the lower source and drain contacts. Each lower channel structure may also include first and second lower gate oxide layers on the lower and upper surfaces of the lower TMD channel, respectively. The CFET structure may further include upper source and drain contacts in the IMD layer above the lower source and drain contacts. The CFET structure may further include an upper GAA gate region in the IMD layer above the lower GAA gate region and between the upper source contact and the upper drain contact. The upper GAA gate region may be of a second conductivity type opposite the first conductivity type and may include one or more upper channel structures. Each upper channel structure may include an upper TMD channel electrically coupled to the upper source contact and the upper drain contact. Each upper channel structure may also include first and second upper gate oxide layers on the upper and lower surfaces of the upper TMD channel, respectively. The CFET structure may still further include common gates between the lower source contact and the lower drain contact in the IMD layer and between the upper source contact and the upper drain contact. The common gate may be configured to apply a common voltage to the lower and upper channel structures.

[0006] A method for fabricating a complementary field effect transistor (CFET) structure is disclosed. The method may include forming a lower source contact and a lower drain contact in an inter-metal dielectric (IMD) layer. The method may also include forming a lower gate-all-around (GAA) gate region between the lower source contact and the lower drain contact in the IMD layer. The lower GAA gate region may be of a first conductivity type and may include one or more lower channel structures. Each lower channel structure may include a lower transition metal dichalcogenide (TMD) channel electrically coupled to the lower source contact and the lower drain contact. Each lower channel structure may also include first and second lower gate oxide layers on lower and upper surfaces of the lower TMD channel, respectively. The method may further include forming upper source and upper drain contacts in the IMD layer above the lower source and lower drain contacts. The method may still include forming an upper GAA gate region in the IMD layer above the lower GAA gate region and between the upper source and upper drain contacts. The upper GAA gate region may be of a second conductivity type opposite the first conductivity type and may include one or more upper channel structures. Each upper channel structure may include an upper TMD channel electrically coupled to an upper source contact and an upper drain contact. Each upper channel structure may also include first and second upper gate oxide layers on upper and lower surfaces of the upper TMD channel, respectively. The method may still further include forming a common gate between the lower source contact and the lower drain contact, and between the upper source contact and the upper drain contact, in the IMD layer. The common gate may be configured to apply a common voltage to the lower channel structure and the upper channel structure.

[0007]

[0007] Other features and advantages associated with the apparatus and methods disclosed herein will become apparent to one skilled in the art based on the accompanying drawings and detailed description. [Brief explanation of the drawings]

[0008]

[0008] A more complete understanding of many of the aspects and attendant advantages of the present disclosure will be readily obtained by reference to the following detailed description, when considered in conjunction with the accompanying drawings, which are presented merely to illustrate and not to limit the disclosure, and in which: [Figure 1]

[0009] FIG. 1 illustrates an example of a CFET structure, according to one or more aspects of the present disclosure. [Figure 2A]

[0010] FIG. 2 is a detailed view of the lower GAA gate region of the exemplary CFET structure of FIG. 1. [Figure 2B]

[0011] FIG. 2 is a detailed view of the top GAA gate region of the exemplary CFET structure of FIG. 1. [Figure 3]

[0012] FIG. 1 illustrates an example of a CFET structure configured as NAND logic, in accordance with one or more aspects of the present disclosure. [Figure 4]

[0013] FIG. 1 illustrates an example of a CFET structure configured as NOR logic, in accordance with one or more aspects of the present disclosure. [Figure 5]

[0014] FIG. 1 illustrates another example of a CFET structure in accordance with one or more aspects of the present disclosure. [Figure 6A]

[0015] FIG. 6 is a detailed view of the lower GAA gate region of the exemplary CFET structure of FIG. 5. [Figure 6B]

[0016] FIG. 6 is a detailed view of the top GAA gate region of the exemplary CFET structure of FIG. 5. [Figure 7]

[0017] FIG. 1 illustrates an example of a CFET structure configured as NAND logic, in accordance with one or more aspects of the present disclosure. [Figure 8]

[0018] FIG. 1 illustrates an example of a CFET structure configured as NOR logic, in accordance with one or more aspects of the present disclosure. [Figure 9A]

[0019] 1A-1D illustrate example stages for fabricating a CFET in accordance with one or more embodiments of the present disclosure. [Figure 9B] 1A-1D illustrate example stages for fabricating a CFET in accordance with one or more embodiments of the present disclosure. [Figure 9C] 1A-1D illustrate example stages for fabricating a CFET in accordance with one or more embodiments of the present disclosure. [Figure 9D] 1A-1D illustrate example stages for fabricating a CFET in accordance with one or more embodiments of the present disclosure. [Figure 9E] 1A-1D illustrate example stages for fabricating a CFET in accordance with one or more embodiments of the present disclosure. [Figure 9F] 1A-1D illustrate example stages for fabricating a CFET in accordance with one or more embodiments of the present disclosure. [Figure 9G] 1A-1D illustrate example stages for fabricating a CFET in accordance with one or more embodiments of the present disclosure. [Figure 9H] 1A-1D illustrate example stages for fabricating a CFET in accordance with one or more embodiments of the present disclosure. [Figure 9I] 1A-1D illustrate example stages for fabricating a CFET in accordance with one or more embodiments of the present disclosure. [Figure 9J] 1A-1D illustrate example stages for fabricating a CFET in accordance with one or more embodiments of the present disclosure. [Figure 10A]

[0020] 1A-1D illustrate example stages for fabricating a CFET in accordance with one or more embodiments of the present disclosure. [Figure 10B] 1A-1D illustrate example stages for fabricating a CFET in accordance with one or more embodiments of the present disclosure. [Figure 10C] 1A-1D illustrate example stages for fabricating a CFET in accordance with one or more embodiments of the present disclosure. [Figure 10D] 1A-1D illustrate example stages for fabricating a CFET in accordance with one or more embodiments of the present disclosure. [Figure 10E] 1A-1D illustrate example stages for fabricating a CFET in accordance with one or more embodiments of the present disclosure. [Figure 10F] 1A-1D illustrate example stages for fabricating a CFET in accordance with one or more embodiments of the present disclosure. [Figure 10G]1A-1D illustrate example stages for fabricating a CFET in accordance with one or more embodiments of the present disclosure. [Figure 10H] 1A-1D illustrate example stages for fabricating a CFET in accordance with one or more embodiments of the present disclosure. [Figure 10I] 1A-1D illustrate example stages for fabricating a CFET in accordance with one or more embodiments of the present disclosure. [Figure 10J] 1A-1D illustrate example stages for fabricating a CFET in accordance with one or more embodiments of the present disclosure. [Figure 11]

[0021] 1 is a flowchart of an exemplary method for fabricating a CFET in accordance with one or more embodiments of the present disclosure. [Figure 12] 1 is a flowchart of an exemplary method for fabricating a CFET in accordance with one or more embodiments of the present disclosure. [Figure 13] 1 is a flowchart of an exemplary method for fabricating a CFET in accordance with one or more embodiments of the present disclosure. [Figure 14] 1 is a flowchart of an exemplary method for fabricating a CFET in accordance with one or more embodiments of the present disclosure. [Figure 15] 1 is a flowchart of an exemplary method for fabricating a CFET in accordance with one or more embodiments of the present disclosure. [Figure 16]

[0022] 1A-1C illustrate various electronic devices that may utilize one or more aspects of the present disclosure.

[0009]

[0023] Other objects and advantages associated with the aspects disclosed herein will become apparent to those skilled in the art based on the accompanying drawings and detailed description. According to common practice, features depicted by the drawings may not be drawn to scale. Accordingly, dimensions of depicted features may be arbitrarily increased or decreased for clarity. According to common practice, some of the drawings have been simplified for clarity. Thus, the drawings may not depict all components of a particular device or method. Moreover, like reference numerals refer to like features throughout the specification and figures. DETAILED DESCRIPTION OF THE INVENTION

[0010]

[0024] Aspects of the present disclosure are illustrated in the following description and related drawings directed to specific embodiments. Alternative aspects or embodiments may be devised without departing from the scope of the teachings herein. Additionally, well-known elements of the exemplary embodiments herein may not be described in detail or may be omitted so as not to obscure the relevant details of the teachings in the present disclosure.

[0011]

[0025] In some described exemplary implementations, instances are identified where portions of the structure and operation of various components may be derived from known conventional techniques and then configured in accordance with one or more exemplary embodiments. In such instances, some internal details of the structure and / or operation of known conventional components may be omitted to help avoid potentially obscuring the concepts illustrated in the exemplary embodiments disclosed herein.

[0012]

[0026] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0013]

[0027] As mentioned above, scaling transistors beyond FinFETs and nanowires to, for example, single-digit nanometers is a challenging task. In this regard, it has been proposed to fabricate transistors using two-dimensional (2D) materials. 2D-materials are also referred to as transition metal dichalcogenides (TMDs), which have the general molecular formula MX2, where "M" represents a transition metal element (e.g., titanium (Ti), molybdenum (Mo), tungsten (W), etc.) and "X" represents a chalcogen element (e.g., sulfur (S), selenium (Se), tellurium (Te), etc.). Thus, examples of TMDs include molybdenum disulfide (MoS2), tungsten disulfide (WS2), and tungsten diselenide (WSe2). It should be noted that there are well over 1500 possible different combinations of MX2 TMDs.

[0014]

[0028] In one or more embodiments, it is proposed to stack 2D TMDs to reach a 3D transistor configuration. Compared with transistors with a silicon (Si)-based channel between the source and drain, the technical advantages of 2D stacked TMDs as transistors include better drive current and lower switching capacitance. In short, 2D enables scaling, which leads to better performance and lower energy.

[0015]

[0029] 1 shows an example of a complementary field-effect transistor (CFET) structure 100 using a gate-all-around (GAA) TMD channel. In this case, the CFET structure 100 is configured as an inverter (NOT logic). However, as will be seen further below, the CFET structure may be configured for other purposes. It is anticipated that the proposed 3D GAA TMDS channel CFET integration may be a roadmap for future technology scaling below 1 nm.

[0016]

[0030] In FIG. 1 , the proposed CFET structure 100 can be formed within multiple inter-metal dielectric (IMD) layers, where 130 represents the main IMD layer, i.e., layer (x), 110 represents IMD (x−1), and 150 represents IMD layer (x+1). For ease of explanation, the main IMD layer 130 may be referred to simply as the “IMD layer.” As can be seen, IMD layers 110 and 150 may be below and above IMD layer 130, respectively. Thus, again for ease of explanation, layer 110 may be referred to as the “lower IMD layer” and layer 150 may be referred to as the “upper IMD layer.” Note that there may be other IMD layers below lower IMD layer 110 and / or above upper IMD layer 150.

[0017]

[0031] Before proceeding further, please also note that terms such as "upper," "lower," "left," "right," etc. are used for convenience of description and, therefore, unless expressly indicated otherwise, such terms are not meant to limit the aspects to any particular direction or orientation.

[0018]

[0032] A lower transistor and an upper transistor can be formed in the IMD layer 130. The lower transistor can include a lower source contact 132, a lower drain contact 134, and a lower GAA gate region 135, and the upper transistor can include an upper source contact 142, an upper drain contact 144, and an upper GAA gate region 145. In one embodiment, the lower GAA gate region 135 can be of a first conductivity type (e.g., P-type), and the upper GAA gate region 145 can be of a second conductivity type opposite the first conductivity type (e.g., N-type). Thus, the lower transistor and the upper transistor can form complementary transistors. Details of the lower GAA gate region 135 and the upper GAA gate region 145 will be described further below.

[0019]

[0033] The lower and upper source and drain contacts 132, 134, 142, 144 may be electrically conductive. In one embodiment, these contacts 132, 134, 142, 144 may be formed from materials including palladium (Pd), nickel (Ni), gold (Au), tungsten (W), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), bismuth (Bi), antimony (Sb), molybdenum (Mo), and ruthenium (Ru), among others. Each contact 132, 134, 142, 144 may be formed from any combination of such materials. Also, not all of the contacts 132, 134, 142, 144 need be the same. That is, each of the contacts 132, 134, 142, 144 may be formed from a material that is independent of the other contacts 132, 134, 142, 144.

[0020]

[0034] A common gate 139 and spacers 137 may be formed in the IMD layer 130. The common gate 139 may be between the lower source contact 132 and the lower drain contact 134, and between the upper source contact 142 and the upper drain contact 144. The common gate 139 may be conductive. For example, the common gate 139 may be formed from a metal such as tungsten (W) or titanium nitride (TiN), while the spacers 137 may be electrically insulating and may be formed from, for example, an oxide, silicon nitride, alumina oxide, or the like.

[0021]

[0035] For ease of reference, the spacer 137 to the left of the common gate 139 (between the upper source contact 142 and the common gate 139, and between the lower source contact 132 and the common gate 139) can be referred to as a source spacer. Conversely, the spacer 137 to the right of the common gate 1329 (between the upper drain contact 144 and the common gate 139, and between the lower drain contact 134 and the common gate 139) can be referred to as a drain spacer. In one aspect, the source spacer may contact any of the common gate 139, the lower source contact 132, and / or the upper source contact 142. Similarly, the drain spacer may contact any of the common gate 139, the lower drain contact 134, and / or the upper drain contact 144. In another aspect, the common gate 139 and / or the spacer 137 may span the entire height of the IMD layer 130, i.e., vertically from the top to the bottom of the IMD layer 130.

[0022]

[0036] FIG. 2A illustrates an exemplary embodiment of the lower GAA gate region 135. As can be seen, the lower GAA gate region 135 can include one or more lower channel structures 210 spaced apart from one another. Each lower channel structure 210 can include a lower TMD channel 212. In one aspect, the lower TMD channel 212 can be a 2D material as described above. For example, the lower TMD channel 212 can be formed from tungsten diselenide (WSe). The lower TMD channel 212 can be very thin. By way of example, the lower TMD channel 212 can be formed from one or two layers of 2D material (e.g., one or two layers of WSe). The thickness of the lower TMD channel 212 can be in the range of 1 to 2 nm. Additionally, adjacent lower TMD channels 212 can be spaced apart from one another by approximately 10 to 20 nm.

[0023]

[0037] The gate oxide layer 214 can be formed on both the bottom and top surfaces of the lower TMD channel 212. In one embodiment, the gate oxide layer 214 may be in physical contact with the bottom and / or top surfaces of the lower TMD channel 212. For ease of reference, the gate oxide layers 214 on the bottom and top surfaces of the lower TMD channel 212 can be referred to as the "first bottom gate oxide layer" and the "second bottom gate oxide layer," respectively. The first and / or second bottom gate oxide layers 214 can be high-k dielectric layers. Each gate oxide layer 214 can be a combination of hafnium oxide (HfO2) and aluminum oxide (Al2O3), or a combination of hafnium (Hf), HfO2, and Al2O3. The thickness of each gate oxide layer 214 can be in the range of 2 to 5 nm.

[0024]

[0038] Work function layers 216 can also be formed below and above the lower TMD channel 212, e.g., below the first lower gate oxide layer and above the second lower gate oxide layer. In one embodiment, the work function layers 216 may be in physical contact with the lower surface of the first lower gate oxide layer and / or the upper surface of the second lower gate oxide layer. For ease of reference, the work function layer 216 on the lower surface of the first lower gate oxide layer can be referred to as the "first lower work function layer," and the work function layer 216 on the upper surface of the second lower gate oxide layer can be referred to as the "second lower work function layer." The work function layers 216 can be formed from TiN, titanium alumina (TiAl), etc., or both metals. The thickness of each work function layer 216 can be in the range of 1 to 2 nm.

[0025]

[0039] In one embodiment, adjacent lower channel structures 210 may be spaced apart from one another by approximately 2-5 nm, which represents the thickness of the common gate 139 between adjacent lower channel structures 210 as seen in Figure 2A.

[0026]

[0040] FIG. 2B illustrates an exemplary embodiment of the upper GAA gate region 145. As can be seen, the upper GAA gate region 145 can include one or more upper channel structures 250 spaced apart from one another. Each upper channel structure 250 can include an upper TMD channel 252. The upper TMD channel 252 can also be a 2D material as described above. For example, the upper TMD channel 252 can be formed from molybdenum disulfide (MoS). The upper TMD channel 252 can be very thin. By way of example, the upper TMD channel 252 can be formed from one or two layers of a 2D material (e.g., one or two layers of MoS). The thickness of the upper TMD channel 252 can be in the range of 1 to 2 nm. Additionally, adjacent upper TMD channels 212 can be spaced apart from one another by approximately 10 to 20 nm.

[0027]

[0041] The gate oxide layer 254 can be formed on both the upper and lower surfaces of the upper TMD channel 252. In one embodiment, the gate oxide layer 254 may be in physical contact with the upper and / or lower surfaces of the upper TMD channel 252. For ease of reference, the gate oxide layers 254 on the lower and upper surfaces of the upper TMD channel 252 can be referred to as the "first upper gate oxide layer" and the "second upper gate oxide layer," respectively. The first and / or second upper gate oxide layers 254 can be high-k dielectric layers. Each gate oxide layer 254 can be a combination of hafnium oxide (HfO) and aluminum oxide (AlO), or a combination of hafnium (Hf), HfO, and AlO. The thickness of each gate oxide layer 254 can be in the range of 2 to 5 nm.

[0028]

[0042] Work function layers 256 can also be formed below and above the upper TMD channel 252, e.g., below the first upper gate oxide layer and above the second upper gate oxide layer. In one embodiment, the work function layers 256 may be in physical contact with the lower surface of the first upper gate oxide layer and / or the upper surface of the second upper gate oxide layer. For ease of reference, the work function layer 256 on the lower surface of the first upper gate oxide layer can be referred to as the "first upper work function layer," and the work function layer 256 on the upper surface of the second upper gate oxide layer can be referred to as the "second upper work function layer." The work function layers 256 can be formed from a metal such as TiN. The thickness of each work function layer 256 can be in the range of 1 to 2 nm.

[0029]

[0043] In one embodiment, adjacent upper channel structures 250 may be spaced apart from one another by approximately 2-5 nm, which represents the thickness of the common gate 139 between adjacent upper channel structures 250 as seen in Figure 2B.

[0030]

[0044] 1 , it should be noted that the lower TMD channel 212 (not numbered in FIG. 1 ) may be electrically coupled to the lower source contact 132 and the lower drain contact 134. For example, the lower TMD channel 212 may be in physical contact with the lower source contact 132 and the lower drain contact 134. Similarly, the upper TMD channel 252 (not numbered in FIG. 1 ) may be electrically coupled to the upper source contact 142 and the upper drain contact 144. For example, the upper TMD channel 252 may be in physical contact with the upper source contact 142 and the lower drain contact 144.

[0031]

[0045] The common gate 139 can be configured to apply a common voltage to the lower channel structure 210 and the upper channel structure 250 to induce a conductive path in the lower TMD channel 212 between the lower source contact 132 and the lower drain contact 134, and to induce a conductive path in the upper TMD channel 252 between the upper source contact 142 and the upper drain contact 144. In one embodiment, the top surfaces of the upper source contact 142, the spacer 137, the common gate 139, and the upper drain contact 144 can be planar with the top surface of the IMD layer 130.

[0032]

[0046] The CFET structure 100 may include a lower source terminal 112 and a lower drain terminal 114 in the lower IMD layer 110. The lower source terminal 112 and / or the lower drain terminal 114 may be formed from a conductive material such as highly doped silicon and a metal (e.g., copper (Cu)). The lower source terminal 112 and / or the lower drain terminal 114 may be exposed at a top surface of the lower IMD layer 110. For example, the top surfaces of the terminals 112, 114 and the lower IMD layer 110 may be planar. The lower source terminal 112 may be electrically coupled to a lower source contact 132, and the lower drain terminal 114 may be electrically coupled to a lower drain contact 134. For example, the lower source terminal 112 may be in physical contact with the lower source contact 132 and / or the lower drain terminal 114 may be in physical contact with the lower drain contact 134.

[0033]

[0047] The CFET structure 100 may include an upper source terminal 152, an upper drain terminal 154, and an upper gate terminal 156 in an upper IMD layer 150. The upper source terminal 152, the upper drain terminal 154, and / or the upper gate terminal 156 may be formed from a conductive material such as highly doped silicon and a metal (e.g., copper (Cu)). The upper source terminal 152, the upper drain terminal 154, and / or the upper gate terminal 156 may be exposed at a top surface of the upper IMD layer 150. For example, the top surfaces of the terminals 152, 154, 156 and the upper IMD layer 150 may be planar.

[0034]

[0048] The upper source terminal 152, the upper drain terminal 154, and the upper gate terminal 156 may be electrically coupled to the upper source contact 142, the upper drain contact 144, and the common gate 139. In one embodiment, a source via 153 may be formed in the upper IMD layer 150 to electrically couple the upper source terminal 152 to the upper source contact 142. Alternatively, or in addition, a drain via 155 may be formed in the upper IMD layer 150 to electrically couple the upper drain terminal 154 to the upper drain contact 144. Further, alternatively, or in addition, a drain via 155 may be formed in the upper IMD layer 150 to electrically couple the upper drain terminal 154 to the upper drain contact 144. If present, the lower surfaces of the source via 153, the drain via 155, and the gate via 157 may be planar with the lower surface of the upper IMD layer 150.

[0035]

[0049] In one embodiment, CFET structure 100 may include a lower protective layer 120 and an upper protective layer 160. Lower protective layer 120 may be between lower IMD layer 110 and IMD layer 130, and upper protective layer 160 may be on top of upper IMD layer 150. One or both of lower protective layer 120 and upper protective layer 160 may be formed from silicon carbonitride (SiCN).

[0036]

[0050] 1 includes tail vias 147 in the lower IMD layer 110 and in the IMD layer 130. In particular, tail via 147 electrically couples the lower drain terminal 114 to (e.g., may be in physical contact with) the upper drain terminal 154. In this configuration, the CFET structure can function as an inverter, i.e., NOT logic. That is, the Vout voltage (at drain terminals 114, 154) can be logically opposite to the voltage applied at gate 156.

[0037]

[0051] However, GAA TMDs may be configured with other CFET structures to perform other functions. FIG. 3 illustrates an exemplary CFET structure 300 configured to perform two-input NAND logic. As can be seen, CFET structure 300 is shown to include the components of the structure of FIG. 1 , namely, lower source terminal 112 and lower drain terminal 114 in lower IMD layer 110, source via 153, drain via 155, and gate via 157 in upper IMD layer 150, as well as upper source terminal 152, drain terminal 154, and gate terminal 156, lower source contact 132 and lower drain contact 134, upper source contact 142 and upper drain contact 144, lower GAA gate region 135 and upper GAA gate region 145, spacer 137, and common gate 139. It may be assumed that the description of these components provided with respect to FIG. 1 may also apply with respect to FIG. 3 .

[0038]

[0052] As can be seen, the CFET structure 300 may also include a second spacer 337, a second common gate 339, a second lower source contact 332, a second lower drain contact 334, a second lower GAA gate region 335, a second upper source contact 342, a second upper drain contact 344, and a second upper GAA gate region 345. The formation of the second contacts 332, 334, 342, 344 may be similar to that of the contacts 132, 134, 142, 144 (e.g., formed from any one or more of Pd, Ni, Au, W, Ta, TaN, Ti, TiN, Bi, Sb, Mo, Ru, among others).

[0039]

[0053] The second lower GAA gate region 335 and the upper GAA gate region 345 may also be similar to the lower GAA gate region 135 and the upper GAA gate region 145. That is, the second lower GAA gate region 335 may be of a first conductivity type, and the second upper GAA gate region 335 may be of a second conductivity type (see, for example, FIG. 2B). The second lower GAA gate region 335 may include one or more lower channel structures 210 (see FIG. 2A), and the second upper GAA gate region 345 may include one or more upper channel structures 250 (see FIG. 2B). For distinction, components related to the second lower GAA gate region 335 and the upper GAA gate region 345 are prefixed with "second." Thus, each second lower channel structure 210 in the second lower GAA gate region 335 may comprise a second lower TMD channel 212, 2-1 and 2-2 lower gate oxide layers 214, and 2-1 and 2-2 work function layers 216. Similarly, each second upper channel structure 250 in the second upper GAA gate region 345 may comprise a second upper TMD channel 252, 2-1 and 2-2 upper gate oxide layers 254, and 2-1 and 2-2 work function layers 256.

[0040]

[0054] A second lower source terminal 312 and a second lower drain terminal 314 may be formed in the lower IMD layer 110. The second lower source terminal 312 may be electrically coupled to a second lower source contact 332, and the second lower drain terminal 314 may be electrically coupled to a second lower drain contact 334.

[0041]

[0055] A second upper drain terminal 354 and a second upper gate terminal 356 can be formed in the upper IMD layer 150. The second upper drain terminal 354 can be electrically coupled to the second upper drain contact 344 (e.g., via a second drain via 355). The second upper gate terminal 356 can be electrically coupled to the second common gate 339 (e.g., via a second gate via 357). A second upper source terminal 352 can also be formed that is electrically coupled (e.g., via a second source via 353). However, in one aspect, the second source terminal 352 and the drain terminal 154 can be common, i.e., one and the same.

[0042]

[0056] Note that tail via 347 electrically couples second bottom drain terminal 314 to second top drain terminal 354. In this configuration, CFET structure 300 can perform NAND logic of inputs provided to top gate terminal 156 and second top gate terminal 356.

[0043]

[0057] 4 illustrates an exemplary CFET structure 400 configured to implement two-input NOR logic. As can be seen, CFET structure 400 is shown to include the components of the structure of FIG. 1 , namely, lower source terminal 112 and lower drain terminal 114 in lower IMD layer 110, source via 153, drain via 155, and gate via 157 in upper IMD layer 150, as well as upper source terminal 152, drain terminal 154, and gate terminal 156, lower source contact 132 and lower drain contact 134, upper source contact 142 and upper drain contact 144, lower GAA gate region 135 and upper GAA gate region 145, spacer 137, and common gate 139. It can be assumed that the description of these components provided with respect to FIG. 1 may also apply with respect to FIG. 4 .

[0044]

[0058] As can be seen, the CFET structure 400 may also include a third spacer 437, a third common gate 439, a third lower source contact 432, a third lower drain contact 434, a third lower GAA gate region 435, a third upper source contact 442, a third upper drain contact 444, and a third upper GAA gate region 445. The third contacts 432, 434, 442, 444 may be formed similarly to the contacts 132, 134, 142, 144 (e.g., formed from any one or more of Pd, Ni, Au, W, Ta, TaN, Ti, TiN, Bi, Sb, Mo, Ru, among others).

[0045]

[0059] The third lower GAA gate region 435 and the upper GAA gate region 445 may also be similar to the lower GAA gate region 135 and the upper GAA gate region 145. That is, the third lower GAA gate region 435 may be of a first conductivity type, and the third upper GAA gate region 445 may be of a second conductivity type (see, for example, FIG. 2B). The third lower GAA gate region 435 may include one or more lower channel structures 210 (see FIG. 2A), and the third upper GAA gate region 445 may include one or more upper channel structures 250 (see FIG. 2B). For distinction, components related to the third lower GAA gate region 435 and the upper GAA gate region 445 are prefixed with "third." Thus, each third lower channel structure 210 in the third lower GAA gate region 435 may comprise a third lower TMD channel 212, 3-1 and 3-2 gate oxide layers 214, and 3-1 and 3-2 work function layers 216. Similarly, each third upper channel structure 250 in the third upper GAA gate region 445 may comprise a third upper TMD channel 252, 3-1 and 3-2 gate oxide layers 254, and 3-1 and 3-1 work function layers 256.

[0046]

[0060] A third lower drain terminal 414 may be formed in the lower IMD layer 110 and electrically coupled to the third lower drain contact 434. A third lower source terminal 412 may also be formed. However, in one embodiment, the lower drain terminal and the third lower source terminal 412 may be common.

[0047]

[0061] A third upper source terminal 452, a third upper drain terminal 454, and a third upper gate terminal 456 may be formed in the upper IMD layer 150. The third upper source terminal 452 may be electrically coupled to the third upper source contact 442 (e.g., via a third source via 453). The third upper drain terminal 454 may be electrically coupled to the third upper drain contact 444 (e.g., via a third drain via 455). The third upper gate terminal 456 may be electrically coupled to the third common gate 439 (e.g., via a third gate via 457).

[0048]

[0062] Note that tail via 447 electrically couples third bottom drain terminal 414 to third top drain terminal 454. In this configuration, CFET structure 400 can perform NOR logic of inputs provided to top gate terminal 156 and third top gate terminal 456.

[0049]

[0063] Figure 5 shows another example of a CFET structure 500 according to one or more embodiments of the present disclosure. CFET structure 500 is very similar to CFET structure 100 of Figure 1 in that both contain many of the same elements. Like-numbered elements can be assumed to behave similarly in both structures. Therefore, differences between Figures 1 and 5 will now be described.

[0050]

[0064] One difference is that the illustrated CFET structure 500 may include a lower GAA gate region 535 and an upper GAA gate region 545 (instead of lower GAA gate region 135 and upper GAA gate region 145). Lower GAA gate region 535 may be of a first conductivity type, and upper GAA gate region 545 may be of a second conductivity type opposite the first conductivity type.

[0051]

[0065] As can be seen in FIG. 6A , the lower GAA gate region 535 can include one or more lower channel structures 610. Each lower channel structure 610 can include a lower TMD channel 612. The lower TMD channels 612 can be formed from a 2D material. In one embodiment, the lower TMD channels 612 can be formed from one of WSe2 and MoS2. The lower TMD channels 612 can be very thin. By way of example, the lower TMD channels 612 can be formed from one or two layers of 2D material. The thickness of the lower TMD channels 612 can be in the range of 1 to 2 nm. Additionally, adjacent lower TMD channels 612 can be spaced apart by approximately 10 to 20 nm.

[0052]

[0066] Each lower channel structure 610 may also include first and second lower gate oxide layers 614 (e.g., below and above the lower TMD channel 612). The first and second lower gate oxide layers 614 may be similar to the first and second lower gate oxide layers 214 of FIG. 2A. Each lower channel structure 610 may further include first and second lower work function layers 616. The first and second lower work function layers 616 may be similar to the first and second lower work function layers 216 of FIG. 2A.

[0053]

[0067] As can be seen in FIG. 6B , the upper GAA gate region 545 can include one or more upper channel structures 650. Each upper channel structure 650 can include an upper TMD channel 652. The upper TMD channel 652 can be formed from a 2D material. In one embodiment, the upper TMD channel 652 can be formed from the other of WSe2 and MoS2. The upper TMD channel 652 can be very thin. By way of example, the upper TMD channel 652 can be formed from one or two layers of 2D material. The thickness of the upper TMD channel 652 can be in the range of 1 to 2 nm. Adjacent upper TMD channels 652 can be spaced apart by approximately 10 to 20 nm.

[0054]

[0068] Each upper channel structure 650 may also include first and second upper gate oxide layers 654 (e.g., below and above the upper TMD channel 652). The first and second upper gate oxide layers 654 may be similar to the first and second upper gate oxide layers 214 of FIG. 2A. Each upper channel structure 650 may further include first and second upper work function layers 656. The first and second upper work function layers 656 may be similar to the first and second upper work function layers 216 of FIG. 2B.

[0055]

[0069] Referring back to FIG. 5 , another difference is that the CFET structure 500 may also include a lower inner source contact 531 and a lower outer drain contact 533. The lower inner source contact 531 may be between the lower source contact 132 and the lower GAA gate region 535, and the lower inner drain contact 533 may be between the lower GAA gate region 535 and the lower drain contact 134. The lower inner source contact 531 and the lower inner drain contact 533 may be conductive. In one aspect, the contacts 531, 533 may be formed from a material similar to that of the contacts 132, 134. The lower source contact 132 may be shifted to the left so that it is laterally outward of the upper source contact 142. Alternatively, or in addition, the lower drain contact 134 may be shifted to the right so that it is laterally outward of the upper drain contact 144.

[0056]

[0070] Note that the lower source contact 132 can be electrically coupled to the lower TMD channel 612 (not numbered in FIG. 5 ), for example, via a lower inner source contact 531. The lower drain contact 134 may also be electrically coupled to the lower TMD channel 612, for example, via a lower inner drain contact 533. In one embodiment, the lower inner source contact 531 may be in physical contact with the lower source contact 132 and the lower TMD channel 612. Alternatively, or in addition, the lower inner drain contact 533 may be in physical contact with the lower drain contact 134 and the lower TMD channel 612.

[0057]

[0071] As can be seen, the lower TMD channel 612 may extend into the lower inner source contact 531 and / or the lower inner drain contact 533. Alternatively, or in addition, the lower TMD channel 612 may also extend into the lower source contact 132 and / or the lower drain contact 134. Alternatively, or in addition, the upper TMD channel 652 (not numbered in FIG. 5 ) may extend into the upper source contact 142 and / or the upper drain contact 144. When the lower TMD channel 612 and / or the upper TMD channel 652 extend into the contacts 132, 531, 134, 532, 432, 434, the contact area is increased, which has the advantage of reducing the contact resistance.

[0058]

[0072] CFET structure 500 includes tail vias 147 in lower IMD layer 110 and in IMD layer 130. Thus, like CFET structure 100 (of FIG. 1), CFET structure 500 is also configured to implement NOT logic.

[0059]

[0073] FIG. 7 shows a CFET structure 700 configured to implement NAND logic, like CFET structure 300 (of FIG. 3). The following are some of the differences between FIG. 3 and FIG. 7. First, CFET structure 700 may include lower inner source contact 531, lower inner drain contact 533, second lower inner source contact 731, and second lower inner drain contact 733. Also, second lower TMD channel 612 (not numbered in FIG. 7) may extend into second lower inner source contact 731 and / or second lower inner drain contact 733, respectively. Furthermore, second upper TMD channel 616 (not numbered in FIG. 7) may extend into second upper source contact 342 and / or second upper drain contact 344, respectively. Note that CFET structure 700 may include second lower GAA gate region 735 and upper GAA gate region 745.

[0060]

[0074] FIG. 8 shows a CFET structure 800 configured to implement NOR logic, like CFET structure 400 (of FIG. 4). The following are some of the differences between FIG. 4 and FIG. 8. First, CFET structure 800 may include lower inner source contact 531, lower inner drain contact 533, third lower inner source contact 831, and third lower inner drain contact 833. Also, third lower TMD channel 612 (not numbered in FIG. 8) may extend into third lower inner source contact 831 and / or third lower inner drain contact 833, respectively. Furthermore, third upper TMD channel 616 (not numbered in FIG. 8) may extend into third upper source contact 442 and / or third upper drain contact 444, respectively. Note that CFET structure 800 may include third lower GAA gate region 835 and upper GAA gate region 845.

[0061]

[0075] 9A-9J illustrate example stages in fabricating a CFET structure, such as CFET structures 100, 300, 400, in accordance with one or more embodiments of the present disclosure.

[0062]

[0076] 9A shows a stage where fabrication begins with the back-end-of-line (BEOL) IMD layer (x-1), i.e., the lower IMD layer 110. A metal layer x-1 can now be deposited and patterned to form the lower source terminal 112 and the lower drain terminal 114. A lower protective layer 120 can be formed on the lower IMD layer 110 by depositing and patterning (e.g., polishing) a protective material (e.g., SiCn).

[0063]

[0077] FIG. 9B shows the step of depositing multiple oxide / HfO2 / 2D film (e.g., WSe2) layers for a first conductivity type transistor (e.g., P-type). The active and oxide films can be patterned in the gate region while preserving the 2D film material. A spacer material (e.g., SiN) can be deposited and etched to form spacers 137. Briefly, the lower TMD channel 212 and the (temporary) HfO2 layer 920 can be formed. Note that the spacers 137 are partial at this stage.

[0064]

[0078] 9C shows the stage where IMD oxide material can be deposited and planarized (e.g., by chemical mechanical polishing (CMP)) to form IMD layer 130. The gate area can be opened and the oxide in the gate area can be removed. IMD layer 130 is partial at this stage.

[0065]

[0079] 9D shows the step of removing the previous HfO2 layer 920. HfO2 / Al2O3 or Hf / HfO2 / Al2O3 can then be deposited (e.g., by atomic layer deposition (ALD)) to form the lower gate oxide layer 214. A lower work function layer 216 can be formed (e.g., by ALD deposition of TiN). Also, a common gate 139 can be formed (e.g., by depositing and polishing W). Note that the common gate 139 is partial at this stage.

[0066]

[0080] 9E shows the step of forming the lower GAA gate region 135. At this point, the IMD layer 130 and the lower protective layer 120 can be patterned, and a conductive material (e.g., Pd, Ni, Au, W, Ta, TaN, Ti, TiN, Bi, Sb, Mo, Ru, etc.) can be deposited in the patterned areas to form the lower source contact 132 and the lower drain contact 134. The deposited material can then be polished (e.g., by CMP).

[0067]

[0081] FIG. 9F shows the step of depositing multiple oxide / HfO2 / 2D film (e.g., MoS2) layers for a second conductivity type transistor (e.g., N-type). The active and oxide films can be patterned in the gate region while preserving the 2D film material. To further form the spacers 137, a spacer material (e.g., SiN) can be deposited and etched. Briefly, the upper TMD channel 252 and the (temporary) HfO2 layer 925 can be formed. Note that the spacers 137 can reach their full height at this stage.

[0068]

[0082] 9G shows the stage where more IMD oxide can be deposited and planarized (e.g., by CMP) to further form IMD layer 130. The gate area can be opened and the oxide in the gate area can be removed. IMD layer 130 can reach its full height at this stage.

[0069]

[0083] 9H shows the step of removing the previous HfO2 layer 925. HfO2 / Al2O3 or Hf / HfO2 / Al2O3 can then be deposited (e.g., by ALD) to form the upper gate oxide layer 254. An upper work function layer 256 can be formed (e.g., by ALD deposition of TiN). The common gate 139 can also be formed (e.g., by depositing and polishing W). Note that the common gate 139 can reach its full height at this stage.

[0070]

[0084] 9I shows the step of forming the upper GAA gate region 145. Areas for the upper source contact 142 and upper drain contact 144 can now be patterned in the IMD layer 130. The patterned areas can be deposited with a conductive material (e.g., Pd, Ni, Au, W, Ta, TaN, Ti, TiN, Bi, Sb, Mo, Ru, etc.) and polished (e.g., by CMP).

[0071]

[0085] 9J shows a stage where more IMD oxide layers can be deposited and patterned to form upper IMD layer 150. Metal layer x+1 can now be deposited and patterned to form upper source terminal 152, upper drain terminal 154, and upper gate terminal 156. Source via 153, drain via 155, and gate via 157 can also be formed. Furthermore, lower protective layer 120, IMD layer 130, and upper IMD layer 150 can be patterned, and a conductive material can be deposited in the patterned areas to form tail via 147. Upper protective layer 160 can be formed on upper IMD layer 150 by depositing and patterning (e.g., polishing) a protective material (e.g., SiCN).

[0072]

[0086] 10A-10J illustrate example stages in fabricating a CFET structure, such as CFET structures 500, 700, and 800, in accordance with one or more embodiments of the present disclosure.

[0073]

[0087] 10A shows a stage where fabrication begins with the back-end-of-line (BEOL) IMD layer (x-1), i.e., the lower IMD layer 110. Now, metal layer x-1 can be deposited and patterned to form the lower source terminal 112 and the lower drain terminal 114. The lower protective layer 120 can be formed on the lower IMD layer 110 by depositing and patterning (e.g., polishing) a protective material (e.g., SiCN).

[0074]

[0088] FIG. 10B illustrates the deposition of multiple oxide / HfO2 / 2D film (e.g., one of MoS2 and WSe2) layers for a first conductivity type transistor (e.g., P-type). The active and oxide films can be patterned in the gate region while retaining the 2D film material. A spacer material (e.g., SiN) can be deposited and etched to form spacers 137. Briefly, a lower TMD channel 612 and a (temporary) HfO2 layer 1020 can be formed. Note that the lower TMD channel 612 is wider than the lower TMD channel 212 (in FIG. 9B). For example, the lower TMD channel 612 may extend beyond the spacers 137. Also, note that the spacers 137 are partial at this stage.

[0075]

[0089] 10C shows the stage where IMD oxide material can be deposited and planarized (e.g., by CMP) to form IMD layer 130. The gate area can be opened and the oxide in the gate area can be removed. IMD layer 130 is partial at this stage.

[0076]

[0090] 10D shows the step of removing the previous HfO2 layer 1020. HfO2 / Al2O3 or Hf / HfO2 / Al2O3 can then be deposited (e.g., by ALD) to form the lower gate oxide layer 614. A lower work function layer 616 can be formed (e.g., by ALD deposition of TiN). Also, a common gate 139 can be formed (e.g., by depositing and polishing W). Note that the common gate 139 is partial at this stage.

[0077]

[0091] 10E illustrates the step of forming the lower GAA gate region 535. Here, the IMD layer 130 can be patterned and a conductive material (e.g., Pd, Ni, Au, W, Ta, TaN, Ti, TiN, Bi, Sb, Mo, Ru, etc.) can be deposited in the patterned regions to form the lower inner source contact 531 and the lower inner drain contact 533. The IMD layer 130 and the lower protective layer 120 can also be patterned and a conductive material (e.g., Pd, Ni, Au, W, Ta, TaN, Ti, TiN, Bi, Sb, Mo, Ru, etc.) can be deposited in the patterned regions to form the lower source contact 132 and the lower drain contact 134. The deposited materials for the inner source contact 531, the inner drain contact 533, and the lower source contact 132 and the lower drain contact 134 can be polished (e.g., by CMP).

[0078]

[0092] FIG. 10F shows the step of depositing multiple oxide / HfO2 / 2D film (e.g., MoS2) layers for a second conductivity type transistor (e.g., N-type). The active and oxide films can be patterned in the gate region while preserving the 2D film material. To further form the spacers 137, a spacer material (e.g., SiN) can be deposited and etched. Briefly, the upper TMD channel 652 and the (temporary) HfO2 layer 1025 can be formed. Note that the spacers 137 can reach their full height at this stage.

[0079]

[0093] 10G shows the stage where more IMD oxide can be deposited and planarized (e.g., by CMP) to further form IMD layer 130. The gate area can be opened and the oxide in the gate area can be removed. IMD layer 130 can reach its full height at this stage.

[0080]

[0094] FIG. 10H shows a step illustrating the removal of the previous HfO layer 1025. HfO / AlO or Hf / HfO / AlO can then be deposited (e.g., by ALD) to form the upper gate oxide layer 654. An upper work function layer 656 can be formed (e.g., by ALD deposition of TiN). A common gate 139 can also be formed (e.g., by depositing and polishing W). Note that the upper TMD channel 656 is wider than the upper TMD channel 216 (in FIG. 9H). For example, the upper TMD channel 656 may extend beyond the spacer 137. Note also that the common gate 139 can reach its full height at this stage.

[0081]

[0095] 10I illustrates the step of forming the upper GAA gate region 545. Areas for the upper source contact 142 and upper drain contact 144 can now be patterned in the IMD layer 130. The patterned areas can be deposited with a conductive material (e.g., Pd, Ni, Au, W, Ta, TaN, Ti, TiN, Bi, Sb, Mo, Ru, etc.) and polished (e.g., by CMP).

[0082]

[0096] 10J shows a stage where more IMD oxide layers can be deposited and patterned to form upper IMD layer 150. Now, metal layer x+1 can be deposited and patterned to form upper source terminal 152, upper drain terminal 154, and upper gate terminal 156. Source via 153, drain via 155, and gate via 157 can also be formed. Furthermore, lower protective layer 120, IMD layer 130, and upper IMD layer 150 can be patterned, and a conductive material can be deposited in the patterned areas to form tail via 147. Upper protective layer 160 can be formed on upper IMD layer 150 by depositing and patterning (e.g., polishing) a protective material (e.g., SiCN).

[0083]

[0097] 11 shows a flowchart of an exemplary method 1100 of fabricating a CFET structure (e.g., CFET structures 100, 300, 400, 500, 700, 800, etc.) according to one or more embodiments of the present disclosure. In block 1110, a lower source contact (e.g., lower source contact 132) and a lower drain contact (e.g., lower drain contact 134) may be formed in an inter-metal dielectric (IMD) layer (e.g., IMD layer 130). Block 1110 may correspond to the steps shown in FIGS. 9E and 10E.

[0084]

[0098] In block 1120, a lower gate-all-around (GAA) gate region (e.g., lower GAA gate region 135) may be formed in the IMD layer between the lower source contact and the lower drain contact (e.g., lower source contact 132 and lower drain contact 134). The lower GAA gate region may be of a first conductivity type (e.g., P-type) and may include one or more lower channel structures (e.g., lower channel structures 210, 610). Each lower channel structure may include a lower transition metal dichalcogenide (TMD) channel (e.g., lower TMD channel 212, 612). The lower TMD channel may be electrically coupled to the lower source contact and the lower drain contact. The lower TMD channel may also include first and second lower gate oxide layers (e.g., lower gate oxide layers 214, 614) on the lower and upper surfaces of the lower TMD channel, respectively. The lower channel structure may further include first and second lower work function layers (e.g., lower work function layers 216, 616) on the lower surface of the first lower gate oxide layer and on the upper surface of the second lower gate oxide layer, respectively. Block 1120 may correspond to the steps shown in Figures 9B-9E and 10B-10E.

[0085]

[0099] In block 1130, an upper source contact (e.g., upper source contact 142) and an upper drain contact (e.g., upper drain contact 144) may be formed above the lower source contact and lower drain contact in the IMD layer. Block 1130 may correspond to the steps shown in Figures 9I and 10I.

[0086]

[0100] In block 1140, an upper gate-all-around (GAA) gate region (e.g., upper GAA gate region 145) may be formed in the IMD layer between the upper source contact and the upper drain contact. The upper GAA gate region may be of a second conductivity type (e.g., N-type) opposite the first conductivity type and may include one or more upper channel structures (e.g., upper channel structures 250, 650). Each upper channel structure may include an upper transition metal dichalcogenide (TMD) channel (e.g., upper TMD channel 252, 652). The upper TMD channel may be electrically coupled to the upper source contact and the upper drain contact. The upper TMD channel may also include first and second upper gate oxide layers (e.g., upper gate oxide layers 254, 654) on the lower and upper surfaces, respectively, of the upper TMD channel. The upper channel structure may further include first and second upper work function layers (e.g., upper work function layers 256, 656) on an upper surface of the first upper gate oxide layer and an upper surface of the second upper gate oxide layer, respectively. Block 1140 may correspond to the steps shown in Figures 9F-9I and 10F-10I.

[0087]

[0101] In block 1150, a common gate (e.g., common gate 139) can be formed in the IMD layer between the lower source and lower drain contacts and between the upper source and upper drain contacts. The common gate can be configured to apply a common voltage to the lower and upper channel structures to induce a conductive path in the lower TMD channel between the lower source and lower drain contacts and to induce a conductive path in the upper TMD channel between the upper source and upper drain contacts. Block 1150 can correspond to the steps shown in Figures 9D, 9H, 10D, and 10H.

[0088]

[0102] 12 shows a flowchart of an exemplary method 1200 of fabricating a CFET structure (e.g., CFET structures 100, 300, 400, 500, 700, 800, etc.) according to one or more embodiments of the present disclosure. FIG. 12 can be viewed as more comprehensive than FIG.

[0089]

[0103] Thus, blocks 1210 to 1250 may be similar to blocks 1110 to 1150. Therefore, a detailed description of blocks 1210 to 1250 will be omitted for the sake of brevity.

[0090]

[0104] In block 1255, a lower inner contact may be formed in the IMD layer. Figure 13 shows a flowchart of an exemplary process for performing block 1255. In block 1310, a lower inner source contact (e.g., lower inner source 531) may be formed between the lower outer source contact and the lower GAA gate region. Block 1310 may correspond to the step shown in Figure 10H.

[0091]

[0105] In block 1320, a lower inner drain contact (e.g., lower inner contact 533) can be formed between the lower GAA gate region and the lower outer drain contact. Block 1310 can also correspond to the step shown in FIG. 10H.

[0092]

[0106] Referring back to FIG. 12 , in block 1260, spacers may be formed in the IMD layer. FIG. 14 shows a flowchart of an exemplary process for performing block 1260. In block 1410, source spacers (e.g., left spacers 137, 537) may be formed between the lower source contact and the common gate and between the upper source contact and the common gate. The source spacers may extend from the upper surface of the IMD layer to the lower surface of the IMD layer. Block 1410 may correspond to the steps shown in FIGS. 9C, 9F, 10C, and 10F.

[0093]

[0107] In block 1420, drain spacers (e.g., right spacers 137, 537) may be formed between the lower drain contact and the common gate and between the upper drain contact and the common gate 139. The drain spacers may extend from the upper surface of the IMD layer to the lower surface of the IMD layer. Block 1420 may also correspond to the steps shown in Figures 9C, 9F, 10C, and 10F.

[0094]

[0108] Referring again to FIG. 12 , in block 1270, terminals may be formed in the upper and lower IMD layers (e.g., upper IMD layer 150, lower IMD layer 110). FIG. 15 shows a flowchart of an exemplary process for performing block 1270. In block 1510, a lower source terminal (e.g., lower source terminal 112) may be formed in the lower IMD layer. The lower source terminal may be electrically coupled to the lower source contact. The lower IMD layer may be on a lower surface of the IMD layer. Block 1510 may correspond to the steps shown in FIGS. 9A and 10A.

[0095]

[0109] In block 1520, a lower drain terminal (e.g., lower drain terminal 114) may be formed in the lower IMD layer. The lower drain terminal may be electrically coupled to the lower source contact. Block 1520 may correspond to the steps shown in FIGS. 9A and 10A.

[0096]

[0110] In block 1530, an upper source terminal (e.g., upper source terminal 152) may be formed in the upper IMD layer. The upper source terminal may be electrically coupled to the upper source contact. The upper IMD layer may be on a top surface of the IMD layer. Block 1530 may correspond to the steps shown in Figures 9J and 10J.

[0097]

[0111] In block 1535, a source via (e.g., source via 153) may be formed in the upper IMD layer. The source via may electrically couple the upper source terminal to the upper source contact. Block 1535 may correspond to the steps shown in Figures 9J and 10J.

[0098]

[0112] In block 1540, an upper drain terminal (e.g., upper drain terminal 154) may be formed in the upper IMD layer. The upper drain terminal may be electrically coupled to the upper drain contact. Block 1540 may correspond to the steps shown in FIGS. 9J and 10J.

[0099]

[0113] In block 1545, a drain via (e.g., drain via 155) may be formed in the upper IMD layer. The drain via may electrically couple the upper drain terminal to the upper drain contact. Block 1545 may correspond to the steps shown in Figures 9J and 10J.

[0100]

[0114] In block 1550, an upper gate terminal (e.g., upper gate terminal 156) may be formed in the upper IMD layer. The upper gate terminal may be electrically coupled to the common gate. Block 1550 may correspond to the steps shown in Figures 9J and 10J.

[0101]

[0115] In block 1545, a gate via (e.g., gate via 157) may be formed in the upper IMD layer. The gate via may electrically couple the upper gate terminal to the common gate. Block 1555 may correspond to the steps shown in Figures 9J and 10J.

[0102]

[0116] It will be understood that the foregoing manufacturing process and related discussion are provided merely as general illustrations of some of the aspects of the present disclosure and are not intended to limit the scope of the present disclosure or the appended claims. Furthermore, many details of the manufacturing process known to those skilled in the art may be omitted or combined in summary process sections to facilitate understanding of the various aspects disclosed without detailed description of each and every detail and / or every possible process variation. Furthermore, it will be understood that the illustrated configurations and descriptions are provided merely to aid in the explanation of the various aspects disclosed herein. For example, the number and location of inductors, metallization structures may have more or fewer conductive and insulating layers, cavity orientation, size, whether formed of multiple cavities, whether closed or open, and other aspects may have variations driven by specific application design features such as the number of antennas, antenna type, frequency range, power, etc. Therefore, the foregoing illustrative examples and associated figures should not be construed as limiting the various aspects disclosed and claimed herein.

[0103]

[0117] 16 illustrates various electronic devices 1600 that may be integrated with any of the aforementioned devices according to various aspects of the present disclosure. For example, a mobile phone device 1602, a laptop computer device 1604, and a stationary terminal device 1606 may each be generally considered user equipment (UE) and may include one or more CFET structures (e.g., CFET structures 100, 300, 400, 500, 700, 800) as described herein. The devices 1602, 1604, 1606 illustrated in FIG. 16 are merely exemplary. Other electronic devices may also include RF filters, including, but not limited to, a group of devices (e.g., electronic devices) including mobile devices, handheld personal communication systems (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, stationary data units such as meter reading equipment, communication devices, smartphones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented in automotive vehicles (e.g., autonomous vehicles), Internet of things (IoT) devices, or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0104]

[0118] The devices and functions disclosed above may be designed and configured into computer files (e.g., RTL, GDSII, GERBER, etc.) stored on a computer-readable medium. Some or all of such files may be provided to a manufacturer who produces devices based on such files. The resulting product may include semiconductor wafers that are later cut into semiconductor dies and packaged with antennas on glass devices. The antennas on glass devices may then be used in the devices described herein.

[0105]

[0119] Example implementations are described in the following numbered clauses.

[0106]

[0120] Clause 1: A complementary field effect transistor (CFET) structure, comprising: lower source and drain contacts in an inter-metal dielectric (IMD) layer; a lower gate-all-around (GAA) gate region between the lower source and drain contacts in the IMD layer, the lower GAA gate region being of a first conductivity type and comprising one or more lower channel structures, each lower channel structure comprising a lower transition metal dichalcogenide (TMD) channel electrically coupled to the lower source and drain contacts, and first and second lower gate oxide layers on a lower surface and an upper surface of the lower TMD channel, respectively; and upper source and drain contacts in the IMD layer above the lower source and drain contacts. an upper GAA gate region in the IMD layer above the lower GAA gate region and between the upper source contact and the upper drain contact, the upper GAA gate region being of a second conductivity type opposite the first conductivity type, the upper GAA gate region comprising one or more upper channel structures, each upper channel structure comprising an upper TMD channel electrically coupled to the upper source contact and the upper drain contact, and first and second upper gate oxide layers on upper and lower surfaces of the upper TMD channel, respectively; and a common gate between the lower source contact and the lower drain contact in the IMD layer and between the upper source contact and the upper drain contact, the common gate configured to apply a common voltage to the lower channel structure and the upper channel structure.

[0107]

[0121] Clause 2: The CFET of clause 1, wherein each lower channel structure further comprises a first lower work function layer on a lower surface of the first lower gate oxide layer and a second lower work function layer on an upper surface of the second lower gate oxide layer, and each upper channel structure further comprises a first upper work function layer on a lower surface of the first upper gate oxide layer and a second upper work function layer on an upper surface of the second upper gate oxide layer.

[0108]

[0122] Clause 3: The CFET of clause 2, wherein the first lower work function layer or the second lower work function layer, or both, is formed from one or both of titanium nitride (TiN) or titanium alumina (TiAl), or the first upper work function layer or the second upper work function layer, or both, is formed from one or both of TiN or TiAl.

[0109]

[0123] Clause 4: The CFET of any one of clauses 1 to 3, wherein the lower TMD channel is formed from tungsten diselenide (WSe2) and the upper TMD channel is formed from molybdenum disulfide (MoS2).

[0110]

[0124] Clause 5: The CFET of clause 4, wherein the lower TMD channel is formed from one or two layers of WSe2 and the upper TMD channel is formed from one or two layers of MoS2.

[0111]

[0125] Clause 6: The CFET of any one of clauses 1 to 5, wherein the common gate extends from an upper surface of the IMD layer to a lower surface of the IMD layer.

[0112]

[0126] Clause 7: The CFET of any one of clauses 1 to 6, wherein the common gate is formed from tungsten (W), titanium nitride (TiN), or both.

[0113]

[0127] Clause 8: The CFET of any one of clauses 1 to 7, further comprising: source spacers between the lower source contact and the common gate and between the upper source contact and the common gate, the source spacers extending from the upper surface to the lower surface of the IMD layer; and drain spacers between the lower drain contact and the common gate and between the upper drain contact and the common gate, the drain spacers extending from the upper surface to the lower surface of the IMD layer.

[0114]

[0128] Clause 9: The CFET of any one of clauses 1 to 8, wherein the first lower gate oxide layer or the second lower gate oxide layer or both are high-k dielectric layers, or the first upper gate oxide layer or the second upper gate oxide layer or both are high-k dielectric layers.

[0115]

[0129] Clause 10: The CFET of clause 9, wherein the first lower gate oxide layer or the second lower gate oxide layer or both are formed from a combination of hafnium oxide (HfO2) and aluminum oxide (Al2O3), or a combination of Hf, HfO2, and Al2O3, or the first upper gate oxide layer or the second upper gate oxide layer or both are formed from a combination of HfO2 and Al2O3, or a combination of Hf, HfO2, and Al2O3, or both.

[0116]

[0130] Clause 11: A CFET described in any one of clauses 1 to 10, further comprising a lower inner source contact between the lower source contact and the lower GAA gate region, and a lower inner drain contact between the lower GAA gate region and the lower drain contact.

[0117]

[0131] Clause 12: A CFET as described in clause 11, wherein the lower TMD channel extends into the lower inner source contact and / or the lower inner drain contact, or the upper TMD channel extends into the upper source contact and / or the upper drain contact, or both.

[0118]

[0132] Clause 13. The CFET of clause 11 or clause 12, wherein the lower TMD channel is formed from one of tungsten diselenide (WSe2) and molybdenum disulfide (MoS2), and the upper TMD channel is formed from the other of WSe2 and MoS2.

[0119]

[0133] Clause 14: The CFET of any one of clauses 1 to 13, further comprising: a lower source terminal electrically coupled to a lower source contact in the lower IMD layer on a lower surface of the IMD layer; a lower drain terminal electrically coupled to a lower drain contact in the lower IMD layer; an upper source terminal electrically coupled to an upper source contact in the upper IMD layer on an upper surface of the IMD layer; an upper drain terminal electrically coupled to an upper drain contact in the upper IMD layer; and an upper gate terminal electrically coupled to a common gate in the upper IMD layer.

[0120]

[0134] Clause 15: The CFET of clause 14, further comprising: a source via in the upper IMD layer between the upper source terminal and the upper source contact, electrically coupling the upper source terminal to the upper source contact; a drain via in the upper IMD layer between the upper drain terminal and the upper drain contact, electrically coupling the upper drain terminal to the upper drain contact; and a gate via in the upper IMD layer between the upper gate terminal and the common gate, electrically coupling the upper gate terminal to the common gate.

[0121]

[0135] Clause 16: A CFET as described in clause 14 or clause 15, further comprising tail vias in the IMD layer and in the upper IMD layer electrically coupling the lower drain terminal to the upper drain terminal, wherein the CFET structure is configured to function as an inverter.

[0122]

[0136] Clause 17: A second lower source contact and a second lower drain contact in the IMD layer; a second lower GAA gate region between the second lower source contact and the second lower drain contact in the IMD layer, the second lower GAA gate region being of a first conductivity type and comprising one or more second lower channel structures, each second lower channel structure electrically coupled to the second lower source contact and the second lower drain contact; and 2-1 and 2-2 lower gate oxide layers on a lower surface and an upper surface of the second lower TMD channel, respectively. a second upper source contact and a second upper drain contact above the second lower source contact and the second lower drain contact in the IMD layer; and a second upper GAA gate region in the IMD layer above the second lower GAA gate region and between the second upper source contact and the second upper drain contact, the second upper GAA gate region being of a second conductivity type and comprising one or more second upper channel structures, each second upper channel structure providing electrical connection to the second upper source contact and the second upper drain contact. a second upper GAA gate region, comprising a second upper TMD channel electrically coupled thereto and a second-1st and second-2nd upper gate oxide layer on the top and bottom surfaces of the second upper TMD channel, respectively; a second common gate between a second lower source contact and a second lower drain contact in the IMD layer and between the second upper source contact and the second upper drain contact, the second common gate configured to apply a second common voltage to the second lower channel structure and the second upper channel structure; 16. The CFET of claim 14 or 15, further comprising: a second lower drain terminal in the lower IMD layer electrically coupled to the second lower drain contact; a second upper drain terminal in the upper IMD layer electrically coupled to the second upper drain contact; and a tail via in the IMD layer and in the upper IMD layer electrically coupling the second lower drain terminal to the second upper drain terminal, wherein the upper drain terminal is also electrically coupled to the second upper source contact, and the CFET structure is configured to function as NAND logic.

[0123]

[0137] Clause 18: A third lower source contact and a third lower drain contact in the IMD layer; and a third lower GAA gate region between the third lower source contact and the third lower drain contact in the IMD layer, the third lower GAA gate region being of a first conductivity type and comprising one or more third lower channel structures, each third lower channel structure comprising a third lower TMD channel electrically coupled to the third lower source contact and the third lower drain contact, and third-1 and third-2 lower gate oxides on a lower surface and an upper surface of the third lower TMD channel, respectively. a third upper GAA gate region in the IMD layer between the third upper source contact and the third upper drain contact, the third upper GAA gate region being of the second conductivity type ... a third upper GAA gate region comprising a third upper TMD channel electrically coupled to the third gate oxide contact; third-1 and third-2 upper gate oxide layers on the top and bottom surfaces of the third upper TMD channel, respectively; a third common gate in the IMD layer between the third lower source contact and the third lower drain contact and between the third upper source contact and the third upper drain contact, the third common gate configured to apply a third common voltage to the third lower channel structure and the third upper channel structure; 16. The CFET of claim 14 or 15, further comprising: a third lower drain terminal electrically coupled to the third lower drain contact in the lower IMD layer; a third upper drain terminal electrically coupled to the third upper drain contact in the upper IMD layer; and tail vias in the IMD layer and in the upper IMD layer electrically coupling the third lower drain terminal to the third upper drain terminal, wherein the lower drain terminal is also electrically coupled to the third lower source contact, and the CFET structure is configured to function as NOR logic.

[0124]

[0138] Clause 19: The CFET of any one of clauses 14 to 18, further comprising a lower protective layer between the lower IMD layer and the IMD layer, and an upper protective layer on the upper IMD layer.

[0125]

[0139] Clause 20: The CFET of any one of clauses 1 to 19, wherein the lower source contact is formed from palladium (Pd), nickel (Ni), gold (Au), tungsten (W), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), bismuth (Bi), antimony (Sb), molybdenum (Mo), ruthenium (Ru), or any combination thereof; and / or the lower drain contact is formed from Pd, Ni, Au, W, Ta, TaN, Ti, TiN, Bi, Sb, Mo, Ru, or any combination thereof; and / or the upper source contact is formed from Pd, Ni, Au, W, Ta, TaN, Ti, TiN, Bi, Sb, Mo, Ru, or any combination thereof; and / or the upper drain contact is formed from Pd, Ni, Au, W, Ta, TaN, Ti, TiN, Bi, Sb, Mo, Ru, or any combination thereof.

[0126]

[0140] Clause 21: A CFET structure described in any one of clauses 1 to 20, wherein the CFET structure is incorporated into an apparatus selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a stationary terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, and a device in an automotive vehicle.

[0127]

[0141] Clause 22: A method of fabricating a complementary field effect transistor (CFET) structure, comprising: forming a lower source contact and a lower drain contact in an inter-metal dielectric (IMD) layer; forming a lower gate-all-around (GAA) gate region between the lower source contact and the lower drain contact in the IMD layer, the lower GAA gate region being of a first conductivity type and comprising one or more lower channel structures, each lower channel structure comprising a lower transition metal dichalcogenide (TMD) channel electrically coupled to the lower source contact and the lower drain contact, and first and second lower gate oxide layers on lower and upper surfaces of the lower TMD channel, respectively; and forming an upper source contact and an upper drain contact in the IMD layer above the lower source contact and the lower drain contact. forming a contact in the IMD layer above the lower GAA gate region and between the upper source contact and the upper drain contact, the upper GAA gate region being of a second conductivity type opposite the first conductivity type and comprising one or more upper channel structures, each upper channel structure comprising an upper TMD channel electrically coupled to the upper source contact and the upper drain contact, and first and second upper gate oxide layers on upper and lower surfaces of the upper TMD channel, respectively; and forming a common gate in the IMD layer between the lower source contact and the lower drain contact and between the upper source contact and the upper drain contact, the common gate being configured to apply a common voltage to the lower channel structure and the upper channel structure.

[0128]

[0142] Clause 23: The method of clause 22, wherein each lower channel structure further comprises a first lower work function layer on a lower surface of the first lower gate oxide layer and a second lower work function layer on an upper surface of the second lower gate oxide layer, and each upper channel structure further comprises a first upper work function layer on a lower surface of the first upper gate oxide layer and a second upper work function layer on an upper surface of the second upper gate oxide layer.

[0129]

[0143] Clause 24: The method of clause 22 or clause 23, wherein the lower TMD channel is formed from tungsten diselenide (WSe2) and the upper TMD channel is formed from molybdenum disulfide (MoS2).

[0130]

[0144] Clause 25: The method of any one of clauses 22 to 24, wherein the common gate is formed from tungsten (W), titanium nitride (TiN), or both.

[0131]

[0145] Clause 26: The method of any one of clauses 22 to 25, further comprising forming spacers in the IMD layer, wherein forming the spacers comprises forming source spacers between the lower source contact and the common gate and between the upper source contact and the common gate, the source spacers extending from the upper surface of the IMD layer to the lower surface of the IMD layer, and forming drain spacers between the lower drain contact and the common gate and between the upper drain contact and the common gate, the drain spacers extending from the upper surface of the IMD layer to the lower surface of the IMD layer.

[0132]

[0146] Clause 27: A method according to any one of clauses 22 to 26, further comprising forming a lower inner contact in the IMD layer, wherein forming the lower inner contact comprises forming a lower inner source contact between the lower source contact and the lower GAA gate region, and forming a lower inner drain contact between the lower GAA gate region and the lower drain contact.

[0133]

[0147] Clause 28: The method of clause 27, wherein the lower TMD channel extends into the lower inner source contact and / or the lower inner drain contact, or the upper TMD channel extends into the upper source contact and / or the upper drain contact, or both.

[0134]

[0148] Clause 29: The method of any one of Clauses 22 to 28, further comprising forming terminals in the upper IMD layer and the lower IMD layer, wherein forming the terminals comprises: forming a lower source terminal in the lower IMD layer on a lower surface of the IMD layer, the lower source terminal being electrically coupled to the lower source contact; forming a lower drain terminal in the lower IMD layer, the lower drain terminal being electrically coupled to the lower drain contact; forming an upper source terminal in the upper IMD layer on an upper surface of the IMD layer, the upper source terminal being electrically coupled to the upper source contact; forming an upper drain terminal in the upper IMD layer, the upper drain terminal being electrically coupled to the upper drain contact; and forming an upper gate terminal in the upper IMD layer, the upper gate terminal being electrically coupled to the common gate.

[0135]

[0149] Clause 30: The method of clause 29, wherein forming the terminals further includes forming a source via in the upper IMD layer between the upper source terminal and the upper source contact, electrically coupling the upper source terminal to the upper source contact; forming a drain via in the upper IMD layer between the upper drain terminal and the upper drain contact, electrically coupling the upper drain terminal to the upper drain contact; and forming a gate via in the upper IMD layer between the upper gate terminal and the common gate, electrically coupling the upper gate terminal to the common gate.

[0136]

[0150] As used herein, terms such as “user equipment” (or “UE”), “user device,” “user terminal,” “client device,” “communication device,” “wireless device,” “wireless communication device,” “handheld device,” “mobile device,” “mobile terminal,” “mobile station,” “handset,” “access terminal,” “subscriber device,” “subscriber terminal,” “subscriber station,” “terminal,” etc., and variations thereof, may interchangeably refer to any suitable mobile or fixed device capable of receiving wireless communication and / or navigation signals. These terms include, but are not limited to, music players, video players, entertainment units, navigation devices, communication devices, smartphones, personal digital assistants, stationary terminals, tablet computers, computers, wearable devices, laptop computers, servers, automotive devices in automotive vehicles, and / or other types of portable electronic devices typically carried by a person and / or having communication capabilities (e.g., wireless, cellular, infrared, short-range radio, etc.). These terms are also intended to include a device that communicates with another device capable of receiving wireless communication and / or navigation signals, such as by a short-range wireless connection, an infrared connection, a wireline connection, or other connection, regardless of whether the satellite signal reception, assistance data reception, and / or position-related processing is performed on the device itself or on another device. Furthermore, these terms are intended to include all devices, including wireless and wireline communication devices, that can communicate with a core network via a radio access network (RAN), and through which the UE can connect to external networks, such as the Internet, and to other UEs. Of course, other mechanisms for connecting to a core network and / or the Internet are also possible for a UE, such as via a wired access network, a wireless local area network (WLAN) (e.g., based on IEEE 802.11, etc.), etc.A UE may be embodied by any of several types of devices, including, but not limited to, a printed circuit (PC) card, a compact flash device, an external or internal modem, a wireless or wireline telephone, a smartphone, a tablet, a tracking device, an asset tag, etc. A communication link over which a UE can transmit signals to a RAN is called an uplink channel (e.g., a reverse traffic channel, a reverse control channel, an access channel, etc.). A communication link over which a RAN can send signals to a UE is called a downlink channel or a forward link channel (e.g., a paging channel, a control channel, a broadcast channel, a forward traffic channel, etc.). As used herein, the term traffic channel (TCH) may refer to either an uplink / reverse traffic channel or a downlink / forward traffic channel.

[0137]

[0151] Wireless communication between electronic devices can be based on various technologies, such as code division multiple access (CDMA), W-CDMA, time division multiple access (TDMA), frequency division multiple access (FDMA), Orthogonal Frequency Division Multiplexing (OFDM), Global System for Mobile Communications (GSM), 3GPP Long Term Evolution (LTE), 5G New Radio, Bluetooth (BT), Bluetooth Low Energy (BLE), IEEE 802.11 (WiFi), and IEEE 802.15.4 (Zigbee / Thread), or other protocols that may be used in wireless or data communication networks. Bluetooth Low Energy (also known as Bluetooth LE, BLE, and Bluetooth Smart) is a wireless personal area networking technology designed and marketed by the Bluetooth Special Interest Group that aims to significantly reduce power consumption and cost while maintaining a similar communication range. BLE was integrated into the main Bluetooth standard in 2010 with the adoption of Bluetooth Core Specification Version 4.0 and updated in Bluetooth 5.

[0138]

[0152] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any detail described herein as "exemplary" should not be construed as advantageous over other examples. Likewise, the term "example" does not imply that all examples include the discussed features, advantages, or modes of operation. Furthermore, particular features and / or structures may be combined with one or more other features and / or structures. Moreover, at least a portion of the apparatus described herein may be configured to perform at least a portion of the methods described herein.

[0139]

[0153] It should be noted that the terms "connected" and "coupled," or any variation thereof, mean any direct or indirect connection or coupling between elements unless the connection is expressly disclosed as being directly connected, and may encompass the presence of intermediate elements between two elements that are "connected" or "coupled" together through intermediate elements.

[0140]

[0154] Any reference herein to an element using a designation such as "first," "second," etc. is not intended to limit the quantity and / or order of those elements. Rather, these designations are used as a convenient method of distinguishing between two or more elements and / or instances of an element. Also, unless otherwise stated, a set of elements can include one or more elements.

[0141]

[0155] Those skilled in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0142]

[0156] Nothing described or illustrated in this application is intended to publicly disclose any element, act, feature, benefit, advantage, or equivalent, whether or not that element, act, feature, benefit, advantage, or equivalent is claimed.

[0143]

[0157] In the above detailed description, it can be seen that different features are grouped together in the examples. This method of disclosure should not be interpreted as a claimed example having more features than are expressly recited in each claim. Rather, the disclosure may include fewer features than all of the individual disclosed examples. Accordingly, the following claims should be considered incorporated into this description as if each claim could stand alone as a separate example. While each claim can stand alone as a separate example, it should be noted that a dependent claim may refer to one or specific combinations with one or more claims within its scope, while other examples may also encompass or include a combination of that dependent claim with the subject matter of any other dependent claim, or with any feature of another dependent claim and an independent claim. Such combinations are suggested herein unless it is expressly stated that a specific combination is not intended. Furthermore, it is also intended that features of a claim may be included in any other independent claim, even if that claim is not directly dependent on that independent claim.

[0144]

[0158] It is further noted that the methods, systems, and apparatuses disclosed in this description or claims may be implemented by a device comprising means for performing each act and / or function of the disclosed method.

[0145]

[0159] Furthermore, in some instances, an individual act may be subdivided into or include one or more sub-acts, which may be included in and part of the disclosure of the individual act.

[0146]

[0160] While the above disclosure sets forth illustrative examples of the present disclosure, it should be noted that various modifications and variations can be made herein without departing from the scope of the present disclosure, as defined by the appended claims. The functions and / or acts of the method claims according to the examples of the present disclosure described herein need not be performed in any particular order. Additionally, well-known elements may not be described in detail or may be omitted so as not to obscure the relevant details of the aspects and examples disclosed herein. Furthermore, although elements of the present disclosure may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

Claims

1. A complementary field-effect transistor (CFET) structure, Lower source contact and lower drain contact within the intermetallic dielectric (IMD) layer, The lower gate all-around (GAA) gate region between the lower source contact and the lower drain contact within the IMD layer, which is of a first conductivity type and comprises one or more lower channel structures, each lower channel structure being A lower transition metal dichalcogenide (TMD) channel electrically coupled to the lower source contact and the lower drain contact, A lower GAA gate region comprising a first and second lower gate oxide layer on the lower surface and upper surface of the lower TMD channel, respectively, Within the IMD layer, the upper source contact and upper drain contact are located above the lower source contact and the lower drain contact. The upper GAA gate region in the IMD layer, above the lower GAA gate region, between the upper source contact and the upper drain contact, having a second conductivity type opposite to the first conductivity type, and comprising one or more upper channel structures, each upper channel structure being An upper TMD channel electrically coupled to the upper source contact and the upper drain contact, An upper GAA gate region comprising a first and second upper gate oxide layer on the lower and upper surfaces of the upper TMD channel, respectively, A CFET structure comprising a common gate between the lower source contact and the lower drain contact within the IMD layer, and between the upper source contact and the upper drain contact, the common gate configured to apply a common voltage to the lower channel structure and the upper channel structure.

2. Each lower channel structure is, The first lower work function layer on the lower surface of the first lower gate oxide layer, The present invention further comprises a second lower work function layer on the upper surface of the second lower gate oxide layer, Each upper channel structure is, The first upper work function layer on the lower surface of the first upper gate oxide layer, The present invention further comprises a second upper work function layer on the upper surface of the second upper gate oxide layer, The first lower work function layer or the second lower work function layer or both are formed from titanium nitride (TiN) or titanium alumina (TiAl), or The first upper work function layer or the second upper work function layer or both are formed from either TiN or TiAl, or both. The CFET structure according to claim 1.

3. The lower TMD channel is tungsten diselenide (WSe ２ ) is formed from, and the upper TMD channel is molybdenum disulfide (MoS ２ ) is formed from, The lower TMD channel is formed from one or two layers of WSe 2, The CFET structure according to claim 1, wherein the upper TMD channel is formed from one or two layers of MoS2.

4. The CFET structure according to claim 1, wherein the common gate extends from the upper surface of the IMD layer to the lower surface of the IMD layer.

5. The CFET structure according to claim 1, wherein the common gate is formed from tungsten (W), titanium nitride (TiN), or both.

6. A source spacer between the lower source contact and the common gate, and between the upper source contact and the common gate, the source spacer extending from the upper surface to the lower surface of the IMD layer, The system further comprises drain spacers between the lower drain contact and the common gate, and between the upper drain contact and the common gate, the drain spacers extending from the upper surface to the lower surface of the IMD layer. The CFET structure according to claim 1.

7. The first lower gate oxide layer or the second lower gate oxide layer or both are high-k dielectric layers, The first upper gate oxide layer or the second upper gate oxide layer or both are high-k dielectric layers, or both are The first lower gate oxide layer or the second lower gate oxide layer or both are formed from a combination of hafnium oxide (HfO₂) and aluminum oxide (Al₂O₃), or a combination of Hf, HfO₂, and Al₂O₃, The first upper gate oxide layer or the second upper gate oxide layer or both are formed from a combination of HfO₂ and Al₂O₃, or from a combination of Hf, HfO₂ and Al₂O₃, or both. The CFET structure according to claim 1.

8. The lower inner source contact between the lower source contact and the lower GAA gate region, The system further comprises a lower inner drain contact between the lower GAA gate region and the lower drain contact, The CFET structure according to claim 1.

9. The lower TMD channel extends into the lower inner source contact and / or the lower inner drain contact, or The upper TMD channel extends into the upper source contact and / or the upper drain contact, or both. Or, The lower TMD channel is formed from one of tungsten diselenide (WSe2) and molybdenum disulfide (MoS2). The upper TMD channel is formed from the other of WSe 2 and MoS 2. The CFET structure according to claim 8.

10. A lower source terminal electrically coupled to the lower source contact within the lower IMD layer on the lower surface of the IMD layer, A lower drain terminal in the lower IMD layer that is electrically coupled to the lower drain contact, An upper source terminal electrically coupled to the upper source contact within the upper IMD layer on the upper surface of the IMD layer, An upper drain terminal electrically coupled to the upper drain contact within the upper IMD layer, The upper IMD layer further comprises an upper gate terminal electrically coupled to the common gate, The CFET structure according to claim 1.

11. Within the upper IMD layer, there is a source via between the upper source terminal and the upper source contact, which electrically couples the upper source terminal to the upper source contact, Within the upper IMD layer, there is a drain via between the upper drain terminal and the upper drain contact, which electrically couples the upper drain terminal to the upper drain contact. The upper IMD layer further comprises a gate via between the upper gate terminal and the common gate, which electrically couples the upper gate terminal to the common gate, and / or The IMD layer and the upper IMD layer further include tail vias that electrically connect the lower drain terminal to the upper drain terminal, The CFET structure is configured to function as an inverter. The CFET structure according to claim 10.

12. The second lower source contact and the second lower drain contact within the IMD layer, A second lower GAA gate region between the second lower source contact and the second lower drain contact within the IMD layer, comprising the first conductivity type and comprising one or more second lower channel structures, each second lower channel structure being A second lower TMD channel electrically coupled to the second lower source contact and the second lower drain contact, A second lower GAA gate region comprising a second-first and second-second lower gate oxide layer on the lower and upper surfaces of the second lower TMD channel, respectively, A second upper source contact and a second upper drain contact located above the second lower source contact and the second lower drain contact within the IMD layer, A second upper GAA gate region in the IMD layer, above the second lower GAA gate region, between the second upper source contact and the second upper drain contact, which is of the second conductivity type and comprises one or more second upper channel structures, each second upper channel structure being A second upper TMD channel electrically coupled to the second upper source contact and the second upper drain contact, A second upper GAA gate region comprising a second-first and second-second upper gate oxide layer on the upper and lower surfaces of the second upper TMD channel, respectively, A second common gate between the second lower source contact and the second lower drain contact within the IMD layer, and between the second upper source contact and the second upper drain contact, the second common gate configured to apply a second common voltage to the second lower channel structure and the second upper channel structure, A second lower drain terminal in the lower IMD layer, electrically coupled to the second lower drain contact, A second upper drain terminal in the upper IMD layer, electrically coupled to the second upper drain contact, The device further comprises tail vias in the IMD layer and the upper IMD layer that electrically couple the second lower drain terminal to the second upper drain terminal. The upper drain terminal is also electrically coupled to the second upper source contact. The CFET structure is configured to function as NAND logic. The CFET structure according to claim 10.

13. The third lower source contact and the third lower drain contact within the IMD layer, A third lower GAA gate region between the third lower source contact and the third lower drain contact in the IMD layer, which is of the first conductivity type and comprises one or more third lower channel structures, each third lower channel structure being A third lower TMD channel electrically coupled to the third lower source contact and the third lower drain contact, A third lower GAA gate region comprising a third lower gate oxide layer, the lower surface and upper surface of the third lower TMD channel, respectively, and A third upper source contact and a third upper drain contact located above the third lower source contact and the third lower drain contact within the IMD layer, A third upper GAA gate region in the IMD layer, above the third lower GAA gate region, between the third upper source contact and the third upper drain contact, which is of the second conductivity type and comprises one or more third upper channel structures, each third upper channel structure being A third upper TMD channel electrically coupled to the third upper source contact and the third upper drain contact, A third upper GAA gate region comprising a third upper gate oxide layer, the upper surface and the lower surface of the third upper TMD channel, respectively, and A third common gate between the third lower source contact and the third lower drain contact within the IMD layer, and between the third upper source contact and the third upper drain contact, the third common gate configured to apply a third common voltage to the third lower channel structure and the third upper channel structure, A third lower drain terminal in the lower IMD layer, electrically coupled to the third lower drain contact, A third upper drain terminal in the upper IMD layer, electrically coupled to the third upper drain contact, The device further comprises tail vias in the IMD layer and the upper IMD layer that electrically couple the third lower drain terminal to the third upper drain terminal. The lower drain terminal is also electrically coupled to the third lower source contact. The CFET structure is configured to function as NOR logic. The CFET structure according to claim 10.

14. The lower IMD layer and the lower protective layer between the IMD layer, The above further comprises an upper protective layer on the upper IMD layer, The CFET structure according to claim 10.

15. A method for manufacturing a complementary field-effect transistor (CFET) structure, Forming a lower source contact and a lower drain contact within an intermetallic dielectric (IMD) layer, The lower gate all-around (GAA) gate region between the lower source contact and the lower drain contact within the IMD layer, which is of a first conductivity type and comprises one or more lower channel structures, each lower channel structure being A lower transition metal dichalcogenide (TMD) channel electrically coupled to the lower source contact and the lower drain contact, A lower GAA gate region is formed, comprising a first and a second lower gate oxide layer on the lower surface and upper surface of the lower TMD channel, respectively. An upper source contact and an upper drain contact are formed above the lower source contact and the lower drain contact within the IMD layer. Within the IMD layer, above the lower GAA gate region, between the upper source contact and the upper drain contact, there is an upper GAA gate region which is a second conductivity type opposite to the first conductivity type, and comprises one or more upper channel structures, each upper channel structure being An upper TMD channel electrically coupled to the upper source contact and the upper drain contact, An upper GAA gate region is formed, comprising a first and a second upper gate oxide layer on the upper and lower surfaces of the upper TMD channel, respectively. A method comprising forming a common gate between the lower source contact and the lower drain contact within the IMD layer, and between the upper source contact and the upper drain contact, the common gate being configured to apply a common voltage to the lower channel structure and the upper channel structure.

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