Wafer carrier assembly with improved temperature uniformity

Abstract

The wafer carrier includes a base including a generally flat bottom surface and an upper surface including a plurality of platforms extending thereover. The wafer carrier includes a thermal cover defining a plurality of pockets. The thermal cover is configured to be coupled to the base by at least one fastener, and the plurality of pockets are arranged such that each pocket of the plurality of pockets aligns with a corresponding platform of the plurality of platforms when the thermal cover is supported by the plurality of first pedestals extending from the upper surface of the base. A plurality of second pedestals are arranged along the plurality of platforms for supporting one or more wafers, each platform including at least one second pedestal extending from the upper surface of the platform for supporting one wafer.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Patent Application No. 63 / 409,557, filed September 23, 2022, which is expressly incorporated herein by reference in its entirety.

[0002] The present disclosure relates generally to semiconductor manufacturing technology, and more particularly to a wafer carrier assembly for a chemical vapor deposition (CVD) reactor having a contoured base and base pedestal that supports a wafer to improve thermal uniformity management during the CVD process. [Background technology]

[0003] Certain processes for manufacturing semiconductors can require complex processes for growing epitaxial layers to create multilayer semiconductor structures for use in the fabrication of high-performance devices such as light-emitting diodes (LEDs), laser diodes, photodetectors, power electronics, and field-effect transistors. In this process, the epitaxial layers are grown via a common process called chemical vapor deposition (CVD). One type of CVD process is called metal-organic chemical vapor deposition (MOCVD). In MOCVD, reactant gases are introduced into a sealed reactor chamber in a controlled environment, allowing the reactor gases to deposit on a substrate (commonly called a wafer) and grow a thin epitaxial layer. Examples of current product lines of such manufacturing equipment include the TurboDisc®, MaxBright®, and EPIK® family of MOCVD systems, and the PROPEL® Power GaN MOCVD system, all manufactured by Veeco Instruments Inc., Plainplay, New York, USA.

[0004] During epitaxial layer growth, several process parameters, such as temperature, pressure, and gas flow rates, are controlled to achieve the desired epitaxial layer quality. Different layers are grown using different materials and process parameters. For example, devices formed from compound semiconductors, such as III-V semiconductors, are typically formed by growing a series of distinct layers. In this process, the wafer is exposed to a combination of reactive gases, typically comprising a metal-organic compound formed using an alkyl source containing a Group III metal, such as gallium, indium, aluminum, and combinations thereof, and a hydride source containing a Group V element, such as NH3, AsH3, or PH3, or an organometallic AN Sb, such as tetramethylantimony. Typically, the alkyl and hydride sources are combined with a carrier gas, such as N2 and / or H2, that does not significantly participate in the reaction. In these processes, the alkyl and hydride sources flow over the surface of the wafer and react with each other to form compounds of the general formula In X Ga y AlzN A A SB P C Sb D where x+y+z is equal to about 1, A+B+C+D is equal to about 1, and x, y, z, A, B, C, and D can each be between 0 and 1. In other processes, commonly referred to as "halide" or "chloride" processes, the Group III metal source is the metal or a volatile halide of the metal, most commonly a chloride such as GaCl. In still other processes, bismuth is used in place of some or all of the other Group III metals.

[0005] Suitable substrates for the reaction may be in the form of wafers having metallic, semiconducting, and / or insulating properties. In some processes, the wafers may be formed from sapphire, aluminum oxide, silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), indium phosphide (InP), indium arsenide (InAs), gallium phosphide (GaP), aluminum nitride (AIN), silicon dioxide (SiO2), etc.

[0006] In a CVD process chamber, one or more wafers are placed in a tray, commonly called a wafer carrier, so that the top surface of each wafer is exposed and uniformly exposed to the atmosphere within the reactor chamber for deposition of semiconductor material. The wafer carrier typically rotates at a rotational speed on the order of about 50 to 1500 RPM or higher. As the wafer carrier rotates, reactant gases are introduced into the chamber from a gas distribution device located upstream of the wafer carrier. The flowing gases preferably flow laminarly downstream toward the wafer carrier and wafer. One such example of a CVD process chamber is disclosed in U.S. Pat. No. 10,570,510, which is expressly incorporated herein by reference in its entirety. The wafer carrier includes a carrier element, commonly called a susceptor, platen, or base, having a pocket for the semiconductor wafer, typically formed from a single bulk material such as graphite or silicon carbide. In various embodiments, the wafer carrier may include a cover restraint disposed on the susceptor or platen or base to define a pocket and help retain the wafer within the pocket. Various configurations and shapes of susceptor / platen / base and cover restraints have been developed for processing, as disclosed, for example, in U.S. Pat. No. 8,888,919, which is incorporated herein by reference in its entirety. The '919 patent also describes and illustrates a conventional chemical vapor deposition apparatus that can be used with the wafer carriers described herein.

[0007] During a CVD process, the wafer carrier is maintained at a desired elevated temperature, often by a heating element positioned below the wafer carrier. Heat is then transferred from the heating element to the bottom surface of the wafer carrier and flows upward through the wafer carrier to one or more wafers. Depending on the process, the temperature of the wafer carrier is maintained between approximately 450°C and 1200°C. However, reactive gases are introduced into the chamber by a gas distribution system at a much lower temperature, typically below 200°C, to prevent premature reaction of the gases.

[0008] In such environments, it is generally desirable to maintain a highly uniform deposition rate for the material(s) being epitaxially grown. The more uniform the thickness of the constituent layers on the wafer or within the wafer, the less waste or usable product is produced. In conventional chemical vapor deposition systems incorporating a thermal cover, heat is transferred directly from the susceptor / platen / base to the wafer substrate, with reduced heat transfer to the cover. In a typical system, there is a temperature difference of approximately 30°C between the wafer and the substrate itself, and the temperature within the wafer can vary by approximately 3-4°C; however, even these small variations can affect wafer uniformity.

[0009] Therefore, it is desirable to optimize the temperature uniformity of the wafer carrier and reduce or eliminate areas of the wafer carrier that are outside the desired temperature profile. Summary of the Invention

[0010] One deficiency in conventional wafer carrier designs is the presence of a low-temperature cold ring region along the periphery of the wafer. Conventional wafer carrier designs support the wafer on a thermal cover, such as by placing the wafer on a ledge or protrusion that is part of the thermal cover. In these designs, the outer edge of the wafer rests on the thermal cover and is suspended above the (platform) base of the wafer carrier. The outer edge of the wafer resting on the thermal cover has a lower temperature than the inner portion of the wafer, thus leading to a non-uniform temperature profile. The wafer carrier described herein overcomes this deficiency by providing a pedestal support mechanism that is directly associated with the wafer carrier base rather than supporting the wafer on the thermal cover, thus eliminating contact between the wafer and the thermal cover.

[0011] Another deficiency of conventional wafer carriers is the potential for thermal hot spots to exist between the central thermal cover and the wafer. Generally, the greater the open space between the center of the thermal cover and the wafer, the greater the likelihood of thermal hot spots and the magnitude of the thermal hot spots. A temperature rise (hot spot) between the inner edge of the wafer at the center of the thermal cover adversely affects the inner surface (inner portion) of the wafer closest to the center of the wafer carrier and thermal cover. As a result of these hot spots, the wafer has a non-uniform temperature profile. Optionally, in certain embodiments, the wafer carriers described herein are constructed to reduce and / or eliminate thermal hot spots on the center of the thermal cover and between the wafers by modifying the top surface of the base of the wafer carrier. More specifically, a sloped central recessed region can be incorporated into the top surface of the base, as described herein.

[0012] Thus, in one embodiment, a wafer carrier for use in a system for growing epitaxial layers on one or more wafers by chemical vapor deposition (CVD) is described and illustrated herein. The wafer carrier includes a base including a substantially flat bottom surface and a top surface substantially parallel to the bottom surface. The top surface further includes a plurality of first pedestals and a plurality of platforms extending above the top surface of the base. The wafer carrier includes a thermal cover defining a plurality of pockets. The thermal cover is configured to be coupled to the base by at least one fastener, and the plurality of pockets are arranged such that each pocket of the plurality of pockets aligns with a corresponding platform of the plurality of platforms when the thermal cover is supported by the plurality of first pedestals. A plurality of second pedestals are arranged along the plurality of platforms for supporting one or more wafers, and each platform includes at least one second pedestal extending from the top surface of the platform for supporting one wafer.

[0013] The subject matter herein can be more fully understood in consideration of the following detailed description of various embodiments in connection with the accompanying drawings. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a perspective view of a wafer carrier according to an embodiment. [Figure 2] 2 is a perspective view of the wafer carrier of FIG. 1 with the thermal cover removed. [Figure 3] FIG. 2 is a detailed view of the central region of the wafer carrier of FIG. [Figure 4] FIG. 10 is a perspective view of a wafer carrier according to another embodiment. [Figure 5] FIG. 5 is an exploded perspective view of the wafer carrier of FIG. [Figure 6] 5 is a perspective view of the wafer carrier of FIG. 4, showing two of the segmented thermal cover pieces removed. [Figure 7] FIG. 10 is an enlarged partial view of the overlapping edges of the segmented thermal cover parts. [Figure 8] 1 is an enlarged partial cross-sectional view of a central section of a wafer carrier showing modifications to dissipate and / or eliminate hot spotting in the center of the wafer carrier. [Figure 9] FIG. 2 is an enlarged partial cross-sectional view of a pedestal wafer support mechanism of a wafer carrier. Detailed Description of the Drawings

[0015] While various embodiments are susceptible to various modifications and alternative forms, details thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that it is not intended to limit the claimed invention to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the subject matter defined by the claims.

[0016] The embodiments described herein offer several improvements, some or all of which may be applicable, individually or in combination, to different embodiments, each of which is described in further detail below.

[0017] Throughout this application, several terms known to those skilled in the art of chemical vapor deposition and similar systems are used. These terms may, in some cases, differ from their plain and ordinary meaning in common parlance. As used throughout this application, the following terms are defined as follows:

[0018] The base is a structure disposed within the reactor to receive precursor gases. The base can have various pockets defined therein upon which wafers are grown. In embodiments, substrates are disposed within each of the pockets upon which wafers are grown via epitaxial growth within the reactor chamber.

[0019] During wafer growth, the base is typically heated and rotated along with the rest of the wafer carrier assembly. Heating provides energy to promote reaction of precursor gases entering the substrate within the wafer carrier assembly, and rotating the wafer carrier assembly promotes growth uniformity across the wafer.

[0020] The thermal cover is a structure that can be connected to the base and typically covers portions of the base other than the pockets, allowing precursor gases access to those pockets (and / or the wafer and base that may be disposed therein).

[0021] Pedestal and platform have similar meanings in everyday usage, but are defined herein to refer to different structures / regions of a wafer carrier assembly. As used herein, platform refers to a raised portion that is relatively large compared to a pedestal. The platform is positioned below the wafer or substrate and defines a height relative to portions of the base that are not below the wafer or substrate, and defines a height relative to portions of the base that are not below the wafer or substrate. On the other hand, a pedestal supports a component (e.g., substrate, thermal cover, etc.) but is small enough to provide sufficient mechanical support without promoting significant levels of heat transfer. The pedestal may extend upward from the platform.

[0022] Throughout this application, references to directions may be made. When one component is referred to as being "above" or "below" another component, this refers to the general orientation in which such a system is used. In a typical deposition system, a showerhead or other sprayer for precursor chemicals is located at the gravitational top of the reactor chamber. Accordingly, the wafer carrier assembly has a thermal cover on top of it. The heater is typically located below the base or, in some embodiments, within the base of the wafer carrier assembly. While this directional language is used to refer to a typical system, it should be understood that alternative chemical vapor deposition or other epitaxial growth systems may be arranged differently. Accordingly, these directions are used for purposes of illustrating the drawings and general implementations and should not be construed as limiting the embodiments described herein.

[0023] As previously mentioned, in a typical chemical vapor deposition process, multiple wafers are held on a component commonly referred to as a wafer carrier, so that the top surface of each wafer is exposed at the top surface of the wafer carrier. The wafer carrier is then placed in a reaction chamber and maintained at a desired temperature while a gas mixture flows over the surface of the wafer carrier. It is important to maintain uniform conditions at all points on the top surfaces of the various wafers on the carrier during the process. Small variations in the composition of the reactive gases and the temperature of the wafer surfaces can cause undesirable variations in the properties of the resulting semiconductor devices.

[0024] Wafer carriers are often described by the number of wafers they can hold and the size of each wafer. For example, a 3×8 inch wafer carrier, such as the exemplary one shown in FIG. 1, is designed to hold three wafers, each 8 inches in diameter. FIGS. 4-7 show an exemplary 15×4 inch wafer carrier holding 15 wafers, each 4 inches in diameter. It will be appreciated that fewer wafers on a wafer carrier means less density, which translates into empty spaces between individual wafers, as described herein. It will be understood that the teachings of the present application can be implemented in wafer carriers of different sizes than those described above.

[0025] 1-3 are perspective views of a wafer carrier 100 according to an exemplary embodiment. It will be understood that the wafer carrier 100 can also be considered a wafer carrier assembly because it is formed from several parts / components attached to one another. The wafer carrier 100 includes a main body, commonly referred to as a base 110, and a thermal cover 200. The wafer carrier 100 includes several pockets 112, each of which corresponds to an opening defined by the thermal cover 200. Thus, the pockets 112 are open along the top surface of the wafer carrier 100 and are arranged circumferentially around the wafer carrier 100, with each such pocket configured to removably receive a disk-shaped wafer 10 (FIG. 9) and retain such wafer 10 during an MOCVD process (or other semiconductor manufacturing process) as described below. Each wafer 10 is formed from a suitable wafer material, including, but not limited to, sapphire, silicon carbide, silicon, or other crystalline substrate material. Typically, each wafer 10 has a thickness that is small compared to the dimensions of its major surface. Each wafer 10 may be placed on or adjacent to the wafer carrier 100 with its top surface facing upward, so that the top surface of the wafer 10 is exposed and accessible at the top surface of the wafer carrier 100. The wafer 10 may be flush or nearly flush with the top surface of the wafer carrier 100.

[0026] The thermal cover 200 may be a single piece, as shown in Figure 1, or may have multiple overlapping segments, as shown in Figures 4-7. This segmented design is described in more detail below and is more commonly found in larger sized wafer carriers.

[0027] Although not shown, each of the pockets 112 may have flats. As is known, flats may be used in chemical vapor deposition systems to lock a wafer (not shown) in the corresponding pocket 112 from rotation during epitaxial growth. Additionally, as shown in Figures 6 and 7, each pocket may, in certain embodiments, include tabs for supporting the wafer.

[0028] The thermal cover 200 is coupled to the base 110 using conventional techniques, such as the use of fasteners. For example, the surface of the thermal cover 200 includes a plurality of holes 202; in the illustrated embodiment, the thermal cover 200 includes nine holes 202. As described in more detail below, the holes 202 are small openings through which fastening pins can pass. Additionally, screws can be used to fasten the thermal cover 200 to the base 110.

[0029] In certain embodiments, pins may be used in combination with screws to achieve the desired level of restraint. Not all of the various implementations of this fastening arrangement are shown herein, and it should be understood that while the outer restraint is often a screw, the radially inner restraint can be either an angled pin or a screw to achieve the desired result. Some embodiments have a "pinless" look, using a backside screw to keep the thermal cover fastened to the inside. In various embodiments, by entering from the backside, heat transfer to the topside can be minimized or eliminated using either screws or pins. Any combination of properly placed restraints using pins and screws can be effective in preventing deformation of the thermal cover 200, which can result in temperature non-uniformities.

[0030] 3 shows the pins 135 that connect the thermal cover 200 to the base 110. The pins 135 may be angled to prevent the thermal cover 200 from being lifted off the base 110.

[0031] The 3x8 inch wafer carrier can use pins and screws, while the 15x4 inch carrier does not require pins.

[0032] Typically, during epitaxial growth of a substrate in a CVD system, the wafer carrier 100 is placed in a reactor chamber and heated from below, i.e., from the side opposite the pocket 112. The chamber is typically under vacuum, and some gases introduced from one or more sources are directed toward the wafer carrier 100, thereby flowing across its top surface. The gases may include a purge gas and one or more precursor gases that react when heated to deposit the desired material in the pocket 112.

[0033] During a typical CVD process, it is desirable to have growth occur in pocket 112 in a uniform, predictable, and consistent manner from run to run. It is also desirable to reduce the amount of system time required to produce each wafer 10, either by increasing run speed or by reducing system downtime. For example, if unwanted material deposition occurs in unwanted locations, system downtime may be required for cleaning.

[0034] The thermal cover 200 can introduce other variables that adversely affect the ability to create uniform, predictable, and consistent deposition across the pocket 112. For example, if the surface of the wafer 10 located above the pocket 112 is significantly hotter or colder than the surrounding thermal cover 200, as is the case with conventional single-piece wafer carriers, the gas flowing across the surface of the wafer carrier 100 can exhibit temperature gradients, resulting in uneven deposition. In contrast, as described herein, the thermal cover can prevent such temperature differences or can be used to adjust temperature differences as needed by adjusting thermal gaps between its components / portions.

[0035] Similarly, the thermal cover 200 can prevent physical obstructions to the flow of precursor gases, which can affect the quality of epitaxial growth in the pockets 112. Rotating the wafer carrier during deposition generally improves uniformity and maintains uniformity between the various pockets 112 therein. However, deformation of the thermal cover 200 can affect the spacing between parts of the wafer carrier 100, which in turn affects the heat transfer characteristics throughout the device and can affect the height of the fluid layer. It will be appreciated that the fluid boundary layer can also affect the growth rate, and in particular, small variations in affecting the fluid boundary layer can affect the growth rate uniformity. When these properties are affected by unwanted deformations, different areas may be hotter or colder, which can affect the deposition rate and pattern. These patterns are generally undesirable because they result in uneven deposition and thickness. Therefore, it is beneficial to control deformation of the thermal cover 200 to maintain a substantially flat, uniform surface that is not significantly cambered / bowled or curved / bumped relative to a plane that represents an ideal, flat, uniform surface. The flatness of the cover may also be non-planar due to film stresses from deposited materials on its surface.

[0036] As discussed herein, non-uniform temperature profiles are a problem, and the wafer carriers disclosed herein are constructed to provide a more uniform temperature profile and overcome the localized non-uniform temperature profiles associated with conventional wafer carriers. More specifically, conventional wafer carrier designs are susceptible to the following deficiencies: 1) thermal "hot spots" on the thermal cover in the center and between the wafers, and 2) low temperature "cold ring" regions along the periphery of the wafer. These problems combine to reduce overall wavelength uniformity and device yield, and therefore the present wafer carriers provide improved overall wafer temperature and wavelength uniformity.

[0037] Internal thermal hot spots One deficiency of conventional wafer carriers is the potential for thermal hot spots to exist between the central thermal cover and the wafer. Generally, the greater the amount of open space between the center of the thermal cover and the wafer, the greater the likelihood of thermal spotting and the magnitude of the thermal spotting. The elevated temperature (hot spot) between the inner edge of the wafer at the center of the thermal cover adversely affects the inner surface (inner portion) of the wafer closest to the center of the wafer carrier and thermal cover. As a result of these hot spots, the wafer has a non-uniform temperature profile.

[0038] The wafer carriers described herein are constructed to reduce and / or eliminate thermal hot spots on the center of the thermal cover and between the wafers by modifying the top surface of the wafer carrier's base. Referring now to FIGS. 2, 3, and 8, the top surface of the wafer carrier's base 110 is modified in a manner that reduces and / or eliminates thermal hot spotting between the center of the thermal cover 200 and the wafer 100. Specifically, the top surface of the base 110 surrounding the center of the wafer carrier 100 is modified to include localized features that dissipate thermal hot spotting within the cover center and between the wafers 100. This modification is in the form of a reduced-thickness region of the base 110 surrounding the centers of the wafer carrier 100 and thermal cover 200, outside of the area where the platform is formed. This modification is implemented to reduce the temperature of the cover in the center of the wafer carrier 100.

[0039] The modification involves removing material from the top surface of the base 110 to further adjust the temperature of the cover in its central region. The removal of base material results in the formation of a sloped central recessed region 115 in the base 110. FIG. 2 shows the base 110 without the thermal cover 200 and indicates the location of the sloped central recessed region 115. As shown, the sloped central recessed region 115 is formed around the center of the base 110 and is formed in the region between the wafer-receiving regions of the base 110. In the embodiment shown in FIG. 2, there are three wafer-receiving regions; therefore, the sloped central recessed region 115 can be described as including three spokes extending radially outward from the center. As best shown in FIG. 3, there may be a mounting feature within the sloped central recessed region 115, such as openings that allow the passage of mounting hardware, such as pins and / or screws, to couple the thermal cover 200 to the base 110. Additionally, other support features may be provided within the sloped central recessed region 115. For example, a larger pedestal 201 may be provided directly at the center of the wafer carrier, as shown in FIGS. 3 and 8.

[0040] The interface between the sloped central recessed region 115 and the surrounding flat portion of the substrate 110 is defined by an outer edge or shoulder or step 119. In the illustrated embodiment of Figure 2, there are three steps 119 as a result of the tri-spoke structure of the sloped central recessed region 115.

[0041] 8, the sloped central recessed region 115 can be described in terms of a dimension B and a dimension C. Dimension B is the distance between the top surface of the base 110 and the thermal cover 200. It will be understood that this dimension B is not constant along the length / width (dimension C) of the sloped central recessed region 115, given that the sloped central recessed region 115 is defined by a sloped (angled) surface. The sloped central recessed region 115 slopes downward toward the center of the wafer carrier 100, resulting in dimension B increasing toward the center.

[0042] The slope of the sloped central recessed region 115 can be expressed in terms of an angle. For example, in one embodiment for a first type of wafer carrier, the angle is 0.41826 arc seconds, and in another embodiment for a different type of wafer, the angle is 0.55330 arc seconds. It will be understood that these values ​​are merely exemplary, and many other slope angles may be used. Specifically, the slope of the sloped central recessed region 115 is determined by the temperature profile of the wafer carrier design. As previously mentioned, the greater the free space within the wafer carrier, the greater the slope angle; for certain more crowded wafer carrier designs, such as a 15×4 inch wafer carrier, it may not be necessary to include this feature; thus, there may be no additional need for provisioning and it may not be necessary to provide and incorporate the sloped central recessed region 115 in the wafer carrier. Therefore, this heat dissipation feature is optional for certain wafer carrier designs and can be eliminated or not included in certain wafer carriers that do not benefit from such a feature.

[0043] 8 represents the gap between the thermal cover 200 and the base of the base 110. This gap A increases the gap between the cover and the base at the center of the thermal cover, reducing the temperature of the cover.

[0044] In one example, dimension A = 0.2 mm to 2 mm, dimension B = 0.3 mm to 2 mm, and dimension C = 0 to 65 mm. For wafer carriers that do not include this optional heat dissipation mechanism, C = 0. It will be understood that the above values ​​are for illustrative purposes only and are not intended to limit the scope of the present invention.

[0045] Pedestal wafer support mechanism As mentioned above, another deficiency in conventional wafer carrier designs is the presence of a cold ring region along the periphery of the wafer. Conventional wafer carrier designs support the wafer on a thermal cover, such as by placing the wafer on a ledge or protrusion that is part of the thermal cover. In these designs, the outer edge of the wafer rests on the thermal cover and is suspended above the base of the wafer carrier. The outer edge of the wafer resting on the thermal cover is cooler than the inner portion of the wafer, thus leading to a non-uniform temperature profile.

[0046] The wafer carrier described herein overcomes this deficiency by providing a pedestal support mechanism associated with the wafer carrier base rather than supporting the wafer on a thermal cover.

[0047] 9, a pedestal support mechanism for supporting a wafer 10 according to the present disclosure is shown. The platform of the base 110 of the wafer carrier 100 includes one or more first pedestals 130 disposed along the top surface of the base 110 and one or more second pedestals 140 also disposed along the top surface of the platform of the base 110. The one or more second pedestals 140 are disposed within a pocket of the wafer carrier 100, and the one or more first pedestals 130 are disposed radially outward from the one or more second pedestals 140. While the term "pedestal" is used to describe each of the structures identified as 130, 140, it will be understood that these may also be described as support tabs, etc.

[0048] 9 can be thought of as having a first region in which one or more first pedestals 130 are recessed relative to a second region (defined by a platform) in which one or more second pedestals 140 are disposed. A wall 150 is disposed between the one first region and the one second region. The wall 150 is formed perpendicular to the upper surface of the first region and the upper surface of the second region (i.e., the wall 150 extends from the upper surface of the base to the upper surface of the platform).

[0049] The one or more first pedestals 130 are located radially outward from the wall 150 and are constructed to support the thermal cover 200. In one embodiment, each of the one or more first pedestals 130 includes a plurality of separate pedestals (pads) upon which the thermal cover 200 rests, although other constructions are possible.

[0050] As described in more detail below, the one or more second pedestals 140 provide a surface upon which the wafer 10 rests within the pocket. In one embodiment, each of the one or more second pedestals 140 comprises a single, continuous, annular pedestal upon which the wafer 10 rests. In another embodiment, each of the one or more second pedestals 140 comprises a plurality of separate tabs that are circumferentially spaced from one another, thus defining a discontinuous surface upon which the wafer 10 rests.

[0051] As described above, the thermal cover 200 includes a pocket in which the wafer 10 is placed. The thermal cover 200 is constructed taking into account the contour of the platform of the base 110. For example, the pocket of the thermal cover 200 is defined by an inner edge of the thermal cover 200 having a contour complementary to the platform shape. More specifically, the inner edge of the thermal cover 200 defining one pocket includes a first inner edge 205 and a second inner edge (inner peripheral edge) 207 located on the first inner edge 205. The first inner edge 205 is located radially outward from the second inner edge 207. The first inner edge 205 is parallel to the wall 150. In the illustrated embodiment, the first and second inner edges 205, 207 are formed non-parallel. A first bottom edge 209 is located between the first inner edge 205 and the second inner edge 207. The first bottom edge 209 is formed perpendicular to the first inner edge 205 and intersects with the second inner edge 207 such that the angle between the second inner edge 207 and the first bottom edge 209 is other than 90 degrees.

[0052] Additionally, the top surface of the thermal cover 200 may include an angled section 240 surrounding each pocket. As shown, the angled section 240 slopes downward toward the pocket. The angled or sloped section 240 intersects with the second inner edge 207. The angled section 240 has an annular shape and surrounds the opening of the pocket. The width of the angled section 240 may be selected based on several factors discussed herein. The angled section 240 promotes smooth gas flow into and out of the pocket, particularly around the outer edge of the wafer.

[0053] 9, the thermal cover 200 partially overhangs (overlaps) a raised platform from which the one or more second pedestals 140 project upwardly. Specifically, an inner portion of the first bottom edge 209 and the second inner edge 207 are positioned above the raised platform but radially outward from the one or more second pedestals 140.

[0054] The second inner edge 207 provides a lateral mechanical restraint for the wafer 10. In other words, the second inner edge 207 prevents unwanted movement of the wafer 10 within the pocket and prevents the wafer 10 from flying off the one or more second pedestals 140.

[0055] As previously mentioned, in contrast to conventional wafer carrier designs, the one or more second pedestals 140 support the outer edge of the wafer 10. This design prevents the outer edge of the wafer from losing heat to the cooler thermal cover 200, eliminating an undesirable low temperature "cold ring" region along the periphery of the wafer.

[0056] FIG. 9 includes labels for specific dimensions that define the structure and features of the wafer carrier 100. For example, dimension A is the distance (gap) between the thermal cover 200 and the top surface of the platform in the recessed area where the one or more first pedestals 130 are located. This dimension A is selected to equalize the average wafer and cover top surface temperatures. Dimension B is the distance between the wafer 10 and the top surface of the platform below the wafer 10. This dimension B prevents a bowed wafer from contacting the platform during the manufacturing process. Dimensions C and D are the distance (gap) between the thermal cover 200 and the platform of the base 110. Dimension C is the distance between the first inner edge 205 and the wall 150, and dimension D is the distance between the first bottom edge 209 and the top surface of the raised platform of the base 110. These dimensions C and D are calibrated to optimize the wafer edge temperature. Dimension E is the width of the angled section 240 at the inner edge of the thermal cover 200 that defines the pocket. Dimension F is the height of the second inner edge 207. Dimensions E and F are designed to provide smooth gas flow around the edge of the wafer.

[0057] In one example, dimension A = 0.2 mm to 2 mm, dimension B = 0.2 mm to 0.4 mm, dimension C = 0.5 mm to 1.5 mm, dimension D = 0.2 mm to 0.5 mm, dimension E = 1 mm to 3 mm, and dimension F = 0.5 mm to 2 mm. For wafer carriers that do not include this optional heat dissipation feature, C = 0. It will be understood that the above values ​​are for illustrative purposes only and are not intended to limit the scope of the present invention.

[0058] It will be understood that the pedestal wafer support mechanism shown in Figure 9 can be incorporated into the wafer carrier 100 of Figures 1-3, and the wafer carriers of Figures 4-7 described below, as well as within other wafer carrier designs. It will further be understood that the pedestal wafer support mechanism of Figure 9 can be used in combination with the sloped central recessed region 115, or can be used without such a mechanism. As previously mentioned, the inclusion of the sloped central recessed region 115 is optional and depends on the characteristics of the wafer carrier, such as the size and the number and spacing of wafers.

[0059] 4-7 are perspective views of another exemplary embodiment of a wafer carrier 300, specifically a 15x4 inch design. For wafer carriers of this size, the thermal cover is most often a multi-piece (segmented) structure.

[0060] Wafer carrier 300 includes base 110 and includes the pedestal wafer support mechanism of Figure 9. However, it does not include the sloped central recessed region 115 of Figure 7 because it does not include the same degree of central open space as wafer carrier 100 of Figures 1-3.

[0061] It will be appreciated that the wafer carrier 300 may also be considered a wafer carrier assembly, as it is formed from several parts / components that are attached to one another. The wafer carrier 100 includes a body, e.g., a base 110, and a thermal cover 310. The wafer carrier 100 includes several pockets 312, each of which corresponds to an opening defined by the thermal cover 310. Thus, the pockets 312 are open along the top surface of the wafer carrier 100 and are arranged circumferentially around the wafer carrier 100, with each such pocket being configured to removably receive a disk-shaped wafer 10 (FIG. 9) and to retain such a wafer 10 during an MOCVD process (or other semiconductor manufacturing process) as described below.

[0062] The thermal cover 310 is defined by multiple thermal cover components (segments), generally designated 320, which engage with one another to define the assembled thermal cover 310. In Figures 4-7, there are five thermal cover components 320 arranged around the center of the wafer carrier. The illustrated thermal cover components 320 are generally the same size, but there are differences. For example, an interlocking mechanism may be provided to join the thermal cover components together. As shown in Figure 7, a first side edge of each thermal cover component 320 includes a first locking mechanism, generally designated 325, while an opposite second side edge of the thermal cover component 320 includes a second locking mechanism, generally designated 325. The first and second locking mechanisms are complementary to one another and define an overlapping structure when adjacent thermal cover components 320 are mated together. For example, the first and second locking mechanisms may be male / female components. 7, the first locking mechanism 325 is a female part and the second locking mechanism 327 is a male part. When two adjacent thermal cover parts 320 are mated together, the male second locking mechanism 327 sits within the stepped first locking mechanism 325, providing a seal through an overlapping configuration.

[0063] Example - CVD equipment and processing conditions A conventional chemical vapor deposition apparatus includes a reaction chamber having a gas inlet manifold located at one end of the chamber. The end of the chamber having the gas inlet manifold is referred to herein as the "top" end of the chamber. This end of the chamber is typically, but not necessarily, located at the top of the chamber in a normal gravity reference frame. Thus, as used herein, a downward direction refers to a direction away from the gas inlet manifold, and an upward direction refers to a direction within the chamber toward the gas inlet manifold, regardless of whether these directions are aligned with the upward and downward directions of gravity.

[0064] A spindle is positioned within the chamber to rotate about a vertical central axis. The spindle's central axis extends above and below the reaction chamber. The spindle is attached to the chamber by a conventional rotary feedthrough device incorporating bearings and seals to allow the spindle to rotate about the central axis while maintaining a seal between the spindle and the chamber's base plate. The spindle is connected to a rotary drive mechanism, such as an electric motor drive, which is arranged to rotate the spindle about the central axis. The spindle can also include an internal coolant passage extending generally axially of the spindle within the gas passage. The internal coolant passage can be connected to a coolant source, such that fluid coolant can be circulated through the coolant passage by the source and returned to the coolant source. A wafer carrier (e.g., wafer carrier 100, 300) is attached to the spindle such that the central axis of the wafer carrier coincides with the axis of the spindle.

[0065] The wafer carrier is maintained at a desired elevated temperature by heating elements, such as electrical resistance heating elements, typically located beneath the bottom surface of the wafer carrier. These heating elements are maintained at a temperature higher than the desired temperature of the wafer surface, while the gas distribution elements are typically maintained at a temperature sufficiently below the desired reaction temperature to prevent premature reaction of the gases. Heat is thus transferred from the heating elements to the bottom surface of the wafer carrier and flows upward through the wafer carrier to the individual wafers.

[0066] During operation, the spindle typically rotates at a rotational speed of 400-800 revolutions per minute, with 500 RPM being typical for certain MOCVD processes. In some embodiments, a typical deposition range is 25-100 Torr, typically under a H2 atmosphere. Small amounts of N2 can be added to the total flow rate, but these are typically less than 5%. Typically, the wafer is maintained at a temperature on the order of 500-750°C during material deposition. It will be understood that the above values ​​pertain to AsP deposition; other materials may be deposited at higher or lower pressure ranges and / or higher or lower temperature ranges. It will be understood that the aforementioned parameters are merely illustrative of one particular embodiment and may vary depending on the exact processing operation being performed.

[0067] In one embodiment, the thermal cover can be formed from graphite and the base can also be formed from graphite. However, other materials can be used as described herein. For example, the thermal cover and / or base can be formed from SiC or coated with a SiC coating.

[0068] It should be understood that like numerals in the drawings represent like elements throughout the several drawings, and that not all components and / or steps described with reference to the drawings are required for all embodiments or configurations.

[0069] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprise" and / or "comprising," as used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0070] Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of "including," "comprising," "having," "containing," "involving," and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof, as well as additional items.

[0071] The above subject matter is provided by way of example only and should not be construed as limiting. Various modifications and changes to the subject matter described herein can be made without following the illustrated and described embodiments and applications and without departing from the true spirit and scope of the invention as set forth in the following claims.

Claims

1. 1. A wafer carrier for use in a system for growing epitaxial layers on one or more wafers by chemical vapor deposition (CVD), comprising: a base including a generally flat bottom surface and a top surface generally parallel to the bottom surface, the top surface of the base including a plurality of first pedestals and a plurality of platforms extending above the top surface; a thermal cover defining a plurality of pockets, the thermal cover configured to be coupled to the base by at least one fastener, the plurality of pockets arranged such that each pocket of the plurality of pockets aligns with a corresponding one of the plurality of platforms when the thermal cover is supported by the plurality of first pedestals; Including, a plurality of second pedestals are disposed along the plurality of platforms for supporting the one or more wafers, each platform including at least one second pedestal extending from a top surface of the platform for supporting one wafer; The wafer carrier.

2. 2. The wafer carrier of claim 1, wherein each pocket includes one continuous second pedestal having an annular shape for supporting one wafer.

3. 2. The wafer carrier of claim 1, wherein each pocket includes a plurality of second pedestals in the form of discrete circumferentially arranged tabs for supporting one wafer.

4. 2. The wafer carrier of claim 1, wherein the plurality of first pedestals comprises a plurality of separate pads upon which the thermal cover rests.

5. 2. The wafer carrier of claim 1, wherein said plurality of first pedestals are positioned radially outward from said plurality of platforms including said plurality of second pedestals.

6. 6. The wafer carrier of claim 5, wherein said plurality of second pedestals are raised relative to said plurality of first pedestals.

7. The wafer carrier of claim 1 , wherein the thermal cover partially overlaps the plurality of platforms.

8. 2. The wafer carrier of claim 1, wherein each platform is defined by an outer wall extending upwardly from the upper surface of the base, the outer wall having a height greater than a height of each first pedestal.

9. The wafer carrier (1), wherein each platform includes an outer periphery region located radially outward from the at least one second pedestal of the platform, and the thermal cover overlaps the outer periphery region in each pocket.

10. 10. The wafer carrier of claim 9, wherein each pocket of the thermal cover is defined by an inner peripheral edge disposed radially outward from the at least one second pedestal to provide lateral mechanical restraint for the wafer within the pocket.

11. 11. The wafer carrier of claim 10, wherein the inner peripheral edge is angled other than 90 degrees relative to the flat upper surface of the platform.

12. 2. The wafer carrier of claim 1, wherein the upper surface of the thermal cover immediately surrounding each pocket is defined by a downwardly angled section that defines and circumferentially surrounds a pocket.

13. The wafer carrier of claim 1 , wherein the one or more wafers are not in direct contact with the thermal cover.

14. 2. The wafer carrier of claim 1, wherein a distance between the top surface of the platform and the thermal cover is 0.2 mm to 0.4 mm, a distance between the bottom surface of the thermal cover and the top surface of the base is 0.2 mm to 2 mm, and a distance between the thermal cover and the top surface of the platform is 0.2 mm to 0.5 mm.

15. 2. The wafer carrier of claim 1, wherein the top surface of the base includes a sloped central recessed area at the center of the base in the area between the platforms.

16. 16. The wafer carrier of claim 15, wherein a step is formed between the sloped central recessed region and a peripheral flat section of the top surface.

17. 16. The wafer carrier of claim 15, wherein the sloped central recessed area slopes downwardly toward a center point of the base.

18. 16. The wafer carrier of claim 15, wherein the angle of the sloped central recessed area is less than 1 degree.

19. 10. The wafer carrier of claim 1, wherein said thermal cover comprises a segmented thermal cover including a plurality of thermal cover parts that interlock with one another to form said thermal cover.

20. 1. A wafer carrier for use in a system for growing epitaxial layers on one or more wafers by chemical vapor deposition (CVD), comprising: a base including a generally flat bottom surface and a top surface generally parallel to the bottom surface, the top surface including a plurality of platforms extending above the top surface of the base; a thermal cover defining a plurality of pockets, the thermal cover configured to be coupled to the base by at least one fastener, the plurality of pockets arranged such that each pocket of the plurality of pockets aligns with a corresponding one of the plurality of platforms when the thermal cover is supported by a plurality of first pedestals of the base; Including, the base includes a plurality of second pedestals extending from upper surfaces of the plurality of platforms that support the one or more wafers so that the one or more wafers do not come into direct contact with the thermal cover during operation; The wafer carrier.

Images