Method for processing polycrystalline silicon carbide wafers

Abstract

The present invention relates to a method for processing a polycrystalline silicon carbide wafer, the method comprising: (R2) identifying the surface condition of the front side of the polycrystalline silicon carbide wafer; If the identified surface condition does not meet the predetermined specifications for bonding the polycrystalline silicon carbide wafer to the monocrystalline silicon carbide substrate with the front surface at the bonding interface (C), modifying the front surface condition by removing material from the front surface of the polycrystalline silicon carbide wafer (R3). Includes.

Description

[Technical Field]

[0001] The field of the invention is that of polycrystalline silicon carbide wafers intended to act as a support for a thin layer of monocrystalline silicon carbide.

[0002] Silicon carbide (SiC) is being increasingly widely used in power electronics applications, particularly to meet the expanding needs of electronic devices, such as electric vehicles. Power devices and integrated power systems based on single-crystal SiC can indeed manage much higher power densities than their conventional silicon counterparts, and do so with smaller active area sizes.

[0003] Nevertheless, substrates for the microelectronics industry made of single-crystal SiC remain expensive and difficult to supply in large sizes. Therefore, it is advantageous to resort to layer transfer solutions to generate composite structures comprising thin layers made of single-crystal SiC, typically on lower-cost support substrates. One well-known thin-layer transfer solution is the Smart Cut™ process. Such a process makes it possible to produce composite structures comprising a thin layer made of single-crystal SiC, obtained from a donor substrate made of single-crystal SiC (m-SiC), in contact with a recipient substrate made of polycrystalline SiC (p-SiC).

[0004] The receiving substrate is a p-SiC wafer obtained from a relatively thick slab of p-SiC (e.g., 0.6-3 mm thick). Deposition of p-SiC onto a growth substrate (e.g., a graphite substrate), typically by chemical vapor deposition at temperatures between 1100°C and 1400°C, allows the formation of a p-SiC slab. After removing the growth substrate, the p-SiC slab undergoes a process to form one or more wafers (wafering process), which includes various cleaning, etching, grinding, and polishing steps, allowing one or more p-SiC wafers to be obtained with the desired morphology (e.g., chamfered edges) and thickness. Sawing may also be performed during this process, especially if several wafers need to be produced from the same slab. The thickness of the polycrystalline SiC wafers thus produced is, according to SEMI standards, 350 μm ± 25 μm for 150 mm diameter substrates or 500 μm ± 25 μm for 200 mm diameter substrates.

[0005] The Smart-Cut™ process applied to SiC requires that a specific surface preparation be available before the donor substrate (mSiC) and the recipient substrate (pSiC) can be bonded together; the bonding can be performed, for example, using ADB (Atomic Diffusion Bonding) or SAB (Surface Activated Bonding) techniques. This surface preparation seeks to create a specific surface state, specified by roughness over a spatial frequency range extending from 5 x 5 μm to 150 x 150 μm.

[0006] However, this surface preparation does not appear to be completely repeatable, as a large number of p-SiC wafers prepared in this manner carry the risk of incomplete transfer of the m-SiC layer during the SmartCut™ process. Therefore, in practice, p-SiC wafers prepared in this manner are pre-sorted to remove p-SiC wafers that do not meet the required roughness specifications to meet the requirements of the bonding process. In addition to being found to have a high defect rate, p-SiC wafers are expensive and their production is energy-intensive. DISCLOSURE OF THE INVENTION

[0007] The objective of the present invention is to reduce the defect rate in order to lower the cost and environmental impact of the Smart-Cut™ process applied to SiC.

[0008] To this end, the present invention provides a method for processing a polycrystalline silicon carbide wafer, the method comprising: determining a surface roughness of a front surface of the polycrystalline silicon carbide wafer; if the determined surface roughness meets a predetermined specification for bonding of a polycrystalline silicon carbide wafer to a monocrystalline silicon carbide substrate with said front surface at the bonding interface, performing said bonding; If the determined surface roughness does not meet the specification, reducing the front surface roughness by removing a thickness of 3 μm to 10 μm of material from the front surface of the polycrystalline silicon carbide wafer and repeating the determination of the front surface roughness; and if the surface roughness determined by repeating the determining step meets the predetermined specification, performing the bonding.

[0009] The predetermined specifications, when met, correspond to predetermined criteria that, for example, are sufficient to obtain a perfect bond of a p-SiC wafer to an m-SiC substrate with the front surface at the bonding interface. Bonding is said to be perfect if the m-SiC substrate is bonded over its entire front surface, except for a peripheral ring less than 10 mm wide at all points, preferably less than 6 mm wide, and more preferably less than 5 mm wide. The bonding and material removal steps are options governed by the suitability or incompatibility of the specific surface roughness of the surfaces to be bonded. Thus, the method according to the invention makes it possible to identify, among a batch of wafers originating from one and the same wafering process, those polycrystalline silicon carbide wafers that pose a risk of incomplete transfer of the monocrystalline silicon carbide layer, so that these wafers can be corrected until the surface condition of the wafers allows for satisfactory bonding, without excluding a significant number of wafers.

[0010] Certain preferred, but non-limiting aspects of this method are as follows. Material removal is performed only on the front side, Removing material from the front surface includes grinding; Grinding includes a series of rough grinding and fine grinding. Rough grinding is performed with a grinding wheel having an abrasive grit size specified by a mesh size of less than 5000; Rough grinding removes material thickness less than 10 μm, Fine grinding is performed with a grinding wheel having an abrasive grit size specified by a mesh size of greater than 5000; Fine grinding removes material thicknesses of less than 3 μm, Removing material from the front surface after this grinding further includes polishing the front surface. The polishing is chemical polishing or chemical-mechanical polishing. Polishing removes a material thickness of less than 1 μm, The method further includes pre-forming polycrystalline silicon carbide wafers from the polycrystalline silicon carbide slab, the pre-forming including double-sided thinning (wafering) of the polycrystalline silicon carbide slab, the double-sided wafering including, for example, sequential rough grinding, coarse grinding, and fine grinding. The pre-forming further includes sawing, etching, and / or polishing the back surface and / or the front surface of the polycrystalline silicon carbide slab. Identifying the surface condition of the front side of the polycrystalline silicon carbide wafer includes measuring light scattering haze. The method further includes, if the surface roughness determined by repeating the determination of the surface roughness of the front surface does not meet specifications, further reducing the surface roughness of the front surface by removing material; The polycrystalline silicon carbide wafer is initially supplied with an initial thickness that falls within an interval of acceptable thickness, and after the front surface roughness has been reduced, has a final thickness that falls within the same interval of acceptable thickness.

[0011] The present invention is directed to a method for creating a batch of polycrystalline silicon carbide wafers, each having a final thickness that falls within an interval of acceptable thickness, the method comprising: providing a set of polycrystalline silicon carbide wafers, each having an initial thickness that falls within the same interval of acceptable thickness; For each wafer in this set, in turn: determining the surface roughness of the front side of the wafer; adding a wafer to the batch if the determined surface roughness meets a predetermined specification for bonding the wafer to a single crystal silicon carbide substrate with the front surface at the bonding interface; If the determined surface roughness does not meet the predetermined specification, reducing the front surface roughness by removing a thickness of 3 μm to 10 μm of material from the front surface of the polycrystalline silicon carbide wafer and repeating the determination of the front surface roughness; and if the determined surface roughness meets the predetermined specification by repeating the determining step, adding the wafer to the batch.

[0012] Finally, the invention applies to a method for producing a batch of multi-layer structures, each multi-layer structure comprising a thin layer of monocrystalline silicon carbide deposited on a polycrystalline silicon carbide wafer, the method comprising, for each wafer of the batch of polycrystalline silicon carbide wafers formed as described above, bonding a monocrystalline silicon carbide substrate to the front side of said polycrystalline silicon carbide wafer.

[0013] Other aspects, objects, advantages and features of the present invention will become more apparent from reading the following detailed description of preferred embodiments thereof, given by way of non-limiting example and made with reference to the accompanying drawings, in which: [Brief explanation of the drawings]

[0014] [Figure 1] 1A-1D illustrate various steps of a Smart-Cut™ process incorporating the treatment of p-SiC wafers according to the present invention. Detailed Disclosure of Specific Embodiments

[0015] The present invention relates to a method for processing p-SiC wafers intended to serve as supports for thin layers of m-SiC. This method can include the preliminary step of forming wafers from p-SiC slabs. To do this, the p-SiC slabs undergo a wafering process. This process can include, among other things, double-sided thinning of the slab and, optionally, flattening the slab to correct any curvature that may be present. Thinning can be performed by grinding. This grinding can include a series of coarse grindings to reduce the thickness to approximately 400 μm, rough grindings to reduce the thickness to approximately 360 μm, and fine grindings to remove the last few microns of material. The various grinding steps differ in the grit size of the grinding wheels used, which become progressively smaller throughout the series of grinding steps. The various grinding steps are performed on both the front and back surfaces of the polycrystalline silicon carbide slab.

[0016] In addition to grinding, the wafering process can include one or more steps of cleaning, etching, and / or polishing the front and / or back surfaces of the polycrystalline silicon carbide slabs. For example, polishing can include chemical mechanical polishing. Polishing reduces the surface roughness of the polycrystalline silicon carbide slabs and / or modifies the flatness of the polycrystalline silicon carbide slabs. Cleaning removes contamination.

[0017] Finally, the wafering process may include sawing, especially if several polycrystalline silicon carbide wafers are to be produced from one and the same polycrystalline silicon carbide slab.

[0018] For example, a p-SiC slab is prepared on graphite by CVD, which means that a step of exfoliating the graphite precedes double-sided thinning of said p-SiC slab.

[0019] The polycrystalline silicon carbide wafers obtained from the p-SiC slabs preferably have an initial thickness that falls within an acceptable or target thickness interval chosen such that, after the surface roughness of the front side of said polycrystalline silicon carbide wafer has been reduced by one or more successive removals of material as described below, the final thickness of the p-SiC wafer will still fall within the same interval of tolerances, the initial and final thicknesses referring to the average thickness of the p-SiC wafer before and after the removal of all material.

[0020] More specifically, the initial and final thicknesses of the polycrystalline silicon carbide wafer fall within intervals referred to as the initial and final thickness distributions of the polycrystalline silicon carbide wafer, respectively. The initial thickness distribution of the polycrystalline silicon carbide wafer is selected to fall within an acceptable thickness range, and the center of the initial thickness distribution is selected to be greater than the center of the acceptable thickness range, so that the final thickness distribution of the polycrystalline silicon carbide wafer also falls within the acceptable thickness range, where the center of each range refers to the average of the lower and upper limits of the range. For example, the center of the initial thickness distribution is 15 μm greater than the center of the acceptable thickness range.

[0021] Such an embodiment advantageously allows for obtaining polycrystalline silicon carbide wafers that meet thickness specifications despite one or more successive reductions in surface roughness due to material removal. The thickness specifications may correspond to thickness ranges accepted by semiconductor industry equipment. Alternatively or additionally, the thickness specifications may meet specifications commonly adopted in the semiconductor industry or may be specifically defined by semiconductor industry standards.

[0022] For example, the acceptable thickness interval is that defined by the SEMI standard for 150 mm diameter p-SiC slabs, i.e., 350 μm±25 μm. As a further example, the acceptable thickness interval is that commonly adopted by most of the semiconductor industry for 200 mm diameter p-SiC slabs, i.e., 500 μm±25 μm.

[0023] In that case, wafers obtained from a 150 mm diameter p-SiC slab may have an initial thickness that falls within an initial film thickness distribution offset toward 365 μm, e.g., an initial thickness of 365 μm±10 μm, and wafers obtained from a 200 mm diameter p-SiC slab may have an initial thickness that falls within an initial film thickness distribution offset toward 515 μm, e.g., an initial thickness of 515 μm±10 μm. This embodiment allows the final thickness of a 150 mm diameter p-SiC wafer to remain compliant with SEMI standards by having the final thickness fall within a final thickness distribution of 350 μm ± 25 μm, and allows the final thickness of a 200 mm diameter p-SiC wafer to remain compliant with specifications typically adopted by the semiconductor industry by having the final thickness fall within a final thickness distribution of 500 μm ± 25 μm, even though one or more steps are performed to modify the surface condition of the p-SiC wafer to ensure successful results of the Smart Cut™ process after the wafer is bonded to a substrate made of m-SiC in accordance with the invention described below.

[0024] Thus, as shown in FIG. 1 , the method according to the present invention can include a step R1 of providing a p-SiC wafer. Furthermore, the method according to the present invention includes a step (shown as R2 in FIG. 1 ) of characterizing the surface condition of the front surface of the p-SiC wafer, typically characterizing the roughness of this front surface. This characterization can include, in particular, a light scattering haze measurement. Such a haze measurement makes it possible to characterize the surface roughness of the front surface of the p-SiC wafer. This haze is obtained from a method using the optical reflectance characteristics of the surface to be characterized and corresponds to the light signal scattered by the surface due to the microroughness of the surface. The haze measurement can be performed, for example, using a KLA-Tencor Surfscan SP1 or SPA2 inspection system or a Lasertec SICA88 inspection system.

[0025] Next, the method according to the invention includes the step of determining whether the identified surface roughness meets predetermined specifications.

[0026] In a particular embodiment, the determined specifications are predetermined criteria that, when met, are sufficient to obtain a perfect bond of the p-SiC wafer to the m-SiC substrate with the front surface at the bonding interface. The bond is said to be perfect if the m-SiC substrate is bonded over the entire front surface except for a peripheral ring having a width of less than 10 mm at all points, preferably less than 6 mm, and more preferably even less than 5 mm. It should be remembered that in practice, the substrates generally have a chamfer around their edges, so that the bonding of the m-SiC substrate, and therefore the subsequent transfer of the thin layer of m-SiC, occurs over most of the surface of the p-SiC wafer but not over the peripheral annular portion extending from the edge of the wafer, the width of which depends, inter alia, on the shape of the chamfer.

[0027] The predetermined specification may relate to an indirect measurement of surface roughness. In embodiments where the determination of surface roughness may include haze measurement, the predetermined specification may be that the measured haze level must be below a predetermined threshold, in other words below a haze level limit previously determined as a guarantee of successful bonding, i.e., in particular a guarantee of perfect bonding as defined above.

[0028] If the determined surface roughness meets the predetermined specifications, the method according to the invention continues with bonding (denoted as C in FIG. 1 ) of the p-SiC wafer to the substrate made of m-SiC, for example using the ADB technique, where the front side of the p-SiC wafer is at the bonding interface. According to the Smart-Cut™ process, the m-SiC substrate is then delaminated along a weakened plane previously formed in the SiC substrate by ion implantation, in order to transfer a thin layer of m-SiC onto the p-SiC wafer, thereby forming a composite structure; this delamination (denoted as D in FIG. 1 ) is brought about by heat treatment, mechanical action, or a combination of these means. In this regard, FIG. 1 denotes the supply of the m-SiC substrate as D1 and uses D2 to denote the ion implantation used to weaken the m-SiC substrate. At the end of the detachment D and upon transfer of the thin layer of m-SiC onto the p-SiC wafer, on the one hand, finishing treatments (denoted as F in Fig. 1) are performed on the composite structure, and on the other hand, possible recycling R of the remainder of the m-SiC substrate is performed so that the m-SiC substrate can be reused.

[0029] If the surface condition of the front surface does not meet the predetermined specifications, the method according to the present invention includes a step (shown as R3 in FIG. 1 ) of reducing the surface roughness of the front surface of the p-SiC wafer by removing material from the front surface of the p-SiC wafer. Unlike previous double-sided thinning of p-SiC slabs, material removal can be performed only on the front surface.

[0030] This removal of material from the front surface removes a thickness of 3 μm to 10 μm. This can be achieved by grinding the front surface. As mentioned previously, grinding of the p-SiC wafer can now be performed only on the front surface, which is intended to be bonded to the m-SiC substrate. This front-only grinding is made possible by the fact that the double-sided grinding previously performed during the wafering process was able to balance the stresses between the front and rear surfaces.

[0031] Grinding can include a series of coarse and fine grinds. The coarse grinding can be performed with a grinding wheel having an abrasive grit size characterized by a mesh size of less than 5000. The coarse grinding preferably removes less than 10 μm of material thickness, for example, 5 μm.

[0032] Alternatively, fine grinding can be performed with a grinding wheel having an abrasive grit size characterized by a mesh size of more than 5000, for example, a mesh size of 8000 to 12000. The fine grinding preferably removes a material thickness of less than 3 μm.

[0033] In one possible embodiment, removing material from the front surface can further include polishing the front surface after grinding. This polishing can be chemical polishing or chemical-mechanical polishing. Preferably, the polishing removes a material thickness of less than 1 μm.

[0034] It will be appreciated that if this reduction in the surface roughness of the front surface intended to be bonded is to remove, for example, a 10 μm thickness of material, the p-SiC wafer will preferably initially have a thickness greater than that expected by the standard, for example a thickness of 365 μm, so that after modification the p-SiC wafer will have the 350 μm thickness expected by the standard, or alternatively the p-SiC wafer can be subjected to several surface condition modification operations while maintaining a final thickness above the lower limit of 325 μm expected by the standard.

[0035] Specifically, after a first modification of the surface roughness of the front surfaces intended to be bonded, the method includes iterative identification of the surface condition of the front surfaces, and if the surface condition identified by the iterative identification meets predetermined specifications, bonding is performed.

[0036] If the surface roughness determined by a particular iteration does not meet the predetermined specifications, the method can include further reducing the surface roughness of the front surface by removing material.

[0037] The method according to the present invention can include one or more further reductions of the surface roughness of the front surface by removal of material, each further reduction preceded by characterization of the surface condition. Each further removal of material is preferably identical to the initial removal of material. The initial removal of material and up to three further removals of material can generally be performed while maintaining a final thickness that complies with SEMI standards, where each removal removes 3-10 μm of material.

[0038] The method according to the invention can further be repeated to process a set of wafers all obtained from one and the same wafering process to create a batch of wafers each capable of being bonded to a monocrystalline substrate, despite the lack of reproducibility of the surface state of the wafers obtained from said wafering process. Thereby, the invention can be applied to a method for creating a batch of polycrystalline silicon carbide wafers, the method comprising: providing a set of polycrystalline silicon carbide wafers; For each wafer in this set, determining the surface roughness of the front side of the wafer; adding a wafer to the batch if the determined surface roughness meets a predetermined specification for bonding the wafer to a single crystal silicon carbide substrate with the front surface at the bonding interface; If the determined surface roughness does not meet the predetermined specification, reducing the front surface roughness by removing a thickness of 3 μm to 10 μm of material from the front surface of the polycrystalline silicon carbide wafer and repeating the determination of the front surface roughness; and then adding the wafer to the batch if the determined surface roughness meets the predetermined specification by repeating the determination step.

[0039] The wafers of the batch thus formed can then each be bonded to a single crystal SiC substrate.

[0040] Preferably, each polycrystalline silicon carbide wafer of the set of polycrystalline silicon carbide wafers is supplied with an initial thickness that falls within an interval of acceptable thickness and, after the front side surface roughness has been reduced, has a final thickness that falls within the same interval of acceptable thickness.

[0041] In other words, each polycrystalline silicon carbide wafer resulting from the method for creating a batch has a final thickness within the target range, and each polycrystalline silicon carbide wafer of the set of polycrystalline silicon carbide wafers is initially supplied with an initial thickness that falls within a narrow range that falls within the target range, the narrow range being centered at a value higher than the central value of the target range.

Claims

1. 1. A method for processing a polycrystalline silicon carbide wafer, the method comprising: (R2) determining the surface roughness of the front surface of the polycrystalline silicon carbide wafer; if the determined surface roughness satisfies a predetermined specification for bonding (C) the polycrystalline silicon carbide wafer to a monocrystalline silicon carbide substrate with the front surface at the bonding interface, performing the bonding; if the determined surface roughness does not meet the specification, reducing the surface roughness of the front surface by removing a thickness of 3 μm to 10 μm of material from the front surface of the polycrystalline silicon carbide wafer (R3) and repeating the determination of the surface roughness of the front surface; and if the surface roughness determined by repeating the determining step meets the predetermined specification, performing the bonding. A method comprising:

2. The method of claim 1 , wherein the removal of material is performed only on the front surface.

3. The method of claim 1 or 2, wherein the removal of material from the front surface comprises grinding.

4. The method of claim 3 , wherein the grinding comprises a series of coarse and fine grinds.

5. 5. The method of claim 4, wherein the coarse grinding is performed with a grinding wheel having an abrasive grit size specified by a mesh size of less than 5000.

6. 6. The method of claim 4 or 5, wherein the rough grinding removes a thickness of material less than 10 μm.

7. 7. The method according to any one of claims 4 to 6, wherein the fine grinding is carried out with a grinding wheel having an abrasive grit size specified by a mesh size of more than 5000.

8. A method according to any one of claims 4 to 7, wherein the fine grinding removes a material thickness of less than 3 μm.

9. The method of any one of claims 4 to 8, wherein said removing material from said front surface further comprises polishing said front surface after said grinding.

10. The method of claim 9 , wherein the polishing is chemical polishing or chemical-mechanical polishing.

11. 11. The method of claim 9 or 10, wherein the polishing removes a thickness of material less than 1 μm.

12. 12. The method of claim 1, further comprising pre-forming the polycrystalline silicon carbide wafers from a polycrystalline silicon carbide slab, the pre-forming comprising double-sided thinning (wafering) of the polycrystalline silicon carbide slab, the double-sided wafering comprising, for example, rough grinding, coarse grinding, and fine grinding, in that order.

13. The method of claim 12 , wherein the pre-forming further comprises sawing, etching, and / or polishing the rear surface and / or the front surface of the polycrystalline silicon carbide slab.

14. The method of any one of claims 1 to 13, wherein the characterization of the surface condition of the front surface of the polycrystalline silicon carbide wafer comprises a light scattering haze measurement.

15. 15. The method of any one of claims 1 to 14, comprising further reducing the surface roughness of the front surface by removing material if the surface roughness determined by repeating the determining of the surface roughness of the front surface does not meet the specification.

16. 16. The method of any one of claims 1 to 15, wherein the polycrystalline silicon carbide wafer is initially supplied with an initial thickness that falls within an interval of acceptable thickness and, after the surface roughness of the front side has been reduced, has a final thickness that falls within the same interval of acceptable thickness.

17. 1. A method for creating a batch of polycrystalline silicon carbide wafers, each having a final thickness that falls within an interval of acceptable thickness, the method comprising: providing a set of polycrystalline silicon carbide wafers, each having an initial thickness that falls within the same interval of acceptable thickness; For each of the wafers in the set, successively: determining the surface roughness of the front surface of the wafer (R2); adding the wafer to the batch if the determined surface roughness meets a predetermined specification for bonding (C) the wafer to a single crystal silicon carbide substrate with the front surface at the bonding interface; if the determined surface roughness does not meet the predetermined specification, reducing the surface roughness of the front surface by removing a thickness of 3 μm to 10 μm of material from the front surface of the polycrystalline silicon carbide wafer (R3) and repeating the determination of the surface roughness of the front surface; and if the surface roughness determined by repeating the determination step meets the predetermined specification, adding the wafer to the batch. A method comprising:

18. 20. The method for creating a batch of polycrystalline silicon carbide wafers of claim 17, wherein each silicon carbide wafer of the set of polycrystalline silicon carbide wafers is supplied with an initial thickness that falls within a narrow range that falls within the interval of acceptable thicknesses, the narrow range being centered at a value higher than a median value of the interval of acceptable thicknesses.

19. 19. A method for producing a batch of multi-layer structures, each multi-layer structure comprising a thin layer of monocrystalline silicon carbide deposited on a polycrystalline silicon carbide wafer, the method comprising, for each wafer of a batch of polycrystalline silicon carbide wafers formed according to one of claims 17 or 18, bonding a monocrystalline silicon carbide substrate to the front side of the polycrystalline silicon carbide wafer.

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