Vertical transport field effect transistor with backside gate contact

Abstract

A VTFET is on the wafer, and a backside power distribution network is on the backside of the wafer. A first backside contact is connected to a gate of the VTFET and a first portion of the backside power distribution network. The VTFET has a first width, the first width being a contacted poly pitch (CPP). The first backside contact may be at least a first width from the VTFET. The first backside contact may be twice the first width from the VTFET.

Description

[Technical Field]

[0001] [Background of the invention] The present invention relates generally to the field of semiconductor device manufacturing, and more particularly to a vertical-transport field-effect transistor (VTFET) having a gate connected to a backside power distribution network.

[0002] Semiconductor devices are fabricated by sequentially depositing insulating (dielectric), conductive, and semiconducting layers of material onto a semiconductor substrate and using lithography to pattern the various layers to form circuit components and elements therein. Generally, these semiconductor devices include multiple circuits that form an integrated circuit (IC) fabricated on the semiconductor substrate.

[0003] Backside power distribution networks are an emerging technology for providing power to circuitry on a wafer. Backside power distribution networks are formed on the backside of the wafer, as opposed to the frontside of the wafer where circuitry and interconnects are traditionally formed. A challenge with backside power distribution is connecting to contacts in the circuitry on the frontside of the wafer, as the backside power distribution network must traverse device layers to connect to contacts in the circuitry on the frontside.

[0004] VTFET devices allow current to flow vertically from the lower source / drain region to the upper source / drain region. In a VTFET device, the lower source / drain region is located closest to the wafer, the gate region is above the lower source / drain region, and the upper source / drain region is above the gate region. The lower source / drain region is located closest to the wafer on which the circuitry is formed, and the upper source / drain region is located furthest from the wafer on which the circuitry is formed. The gate region has a contact routed to the front side of the device and therefore must contact the backside power distribution network. Summary of the Invention

[0005] In a first embodiment, a vertical transport field effect transistor (VTFET) is on a wafer, and a backside power distribution network is on the backside of the wafer. In the first embodiment, a first backside contact is connected to a gate of the VTFET and a first portion of the backside power distribution network. In the first embodiment, the VTFET has a first width, and the first width is a contacted poly pitch (CPP). In the first embodiment, the first backside contact can be at least the first width from the VTFET. In the first embodiment, the first backside contact can be twice the first width from the VTFET.

[0006] In a first embodiment, the backside power distribution network is selected from the group consisting of a clock signal and an input signal. In a first embodiment, a height of the first backside contact is the cell height of the VTFET. In a first embodiment, a frontside contact is connected to an upper source / drain region of the VTFET and a frontside interconnect. In the first embodiment, the frontside interconnect is selected from the group consisting of a local clock signal and an external input signal.

[0007] Embodiments of the present invention provide for any number of signals (e.g., clock, bus, I / O, power, ground, etc.) to be distributed or delivered to the source / drain / gate regions of VTFETs through a backside power delivery network. Embodiments of the present invention provide area efficiency by providing a single CPP to drive many gate regions of multiple devices with low resistance. Embodiments of the present invention provide full cell height contacts that reduce the resistance from the backside to the frontside contact or vice versa.

[0008] In a second embodiment, a plurality of vertical transport field effect transistors (VTFETs) are on a wafer. In a second embodiment, a backside power distribution network is on the backside of the wafer. In a second embodiment, a first backside contact is connected to a gate of each VTFET of the plurality of VTFETs and to a first portion of the backside power distribution network.

[0009] In a second embodiment, each VTFET of the plurality of VTFETs has a first width, and the first width is a contacted poly pitch (CPP). In a second embodiment, the first backside contact may be at least the first width from a first VTFET of the plurality of VTFETs. In a second embodiment, the first backside contact may be twice the first width from a first VTFET of the plurality of VTFETs. In a second embodiment, the first portion of the backside power distribution network is selected from the group consisting of a clock signal and an input signal. In a second embodiment, a height of the first backside contact is the cell height of a VTFET of the plurality of VTFETs. In a second embodiment, a frontside contact is connected to an upper source / drain region of the VTFET and a frontside interconnect. In a second embodiment, the frontside interconnect is selected from the group consisting of a local clock signal and an external input signal.

[0010] Embodiments of the present invention provide for any number of signals (e.g., clock, bus, I / O, power, ground, etc.) to be distributed or delivered to the source / drain / gate regions of the VTFETs through a backside power delivery network. Embodiments of the present invention provide area efficiency by providing a single CPP to drive many gate regions of multiple devices with low resistance. Embodiments of the present invention provide full cell height contacts that reduce the resistance from the backside to the frontside contact or vice versa. Embodiments of the present invention provide for the elimination of the RX, or active area, layer to further reduce resistance.

[0011] In a third embodiment, a first plurality of vertical transport field effect transistors (VTFETs) are in a first column on a wafer. In a third embodiment, a second plurality of VTFETs are in a second column on the wafer, the first column being vertically adjacent to the second column. In a third embodiment, a backside power distribution network is on the backside of the wafer. In a third embodiment, a first backside contact is between the first column and the second column. In a third embodiment, the first backside contact is connected to a gate of each VTFET in the first plurality of VTFETs and to a gate of each VTFET in the second plurality of VTFETs. In a third embodiment, a second backside contact is connected to the first backside contact and to the backside power distribution network.

[0012] In a third embodiment, at least one VTFET of the first plurality of VTFETs and the second plurality of VTFETs has a first width, the first width being a contacted poly pitch (CPP). In a third embodiment, a third plurality of VTFETs is in the first column, with at least the first width separating the first plurality of VTFETs and the third plurality of VTFETs. In a third embodiment, the first backside contact extends adjacent to the third plurality of VTFETs, and the first backside contact is connected to a gate of each VTFET of the third plurality of VTFETs.

[0013] In a third embodiment, a fourth plurality of VTFETs is in the second column, and the second plurality of VTFETs and the fourth plurality of VTFETs are spaced apart by at least the first width. In a third embodiment, the first backside contact extends adjacent to the fourth plurality of VTFETs, and the first backside contact is connected to a gate of each VTFET in the fourth plurality of VTFETs. In a third embodiment, the height of the second backside contact is the height of a VTFET cell of the first plurality of VTFETs and the second plurality of VTFETs. In a third embodiment, the backside power distribution network is selected from the group consisting of a clock signal and an input signal.

[0014] Embodiments of the present invention provide for any number of signals (e.g., clock, bus, I / O, power, ground, etc.) to be distributed or delivered to the source / drain / gate regions of the VTFETs through a backside power delivery network. Embodiments of the present invention provide area efficiency by providing a single CPP to drive many gate regions of multiple devices with low resistance. Embodiments of the present invention provide full cell height contacts that reduce the resistance from the backside to the frontside contact or vice versa. Embodiments of the present invention provide for the elimination of the RX, or active area, layer to further reduce resistance. [Brief explanation of the drawings]

[0015] The above and other aspects, features, and advantages of various embodiments of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings.

[0016] [Figure 1] 1 is a cross-sectional view of a VTFET semiconductor structure having front-side contacts for upper source / drain regions, lower source / drain regions, and a gate region according to a first embodiment of the present invention.

[0017] [Figure 2]1 is a cross-sectional view of a VTFET semiconductor structure having front-side contacts for upper source / drain and gate regions and back-side contacts for lower source / drain regions according to a first embodiment of the present invention. FIG.

[0018] [Figure 3] 1 is a cross-sectional view of a VTFET semiconductor structure having front-side contacts for the upper source / drain and back-side contacts for the lower source / drain and gate regions according to a first embodiment of the present invention;

[0019] [Figure 4A] 1 is a top view of a semiconductor structure including four VTFETs connected in parallel according to a first embodiment of the present invention; FIG.

[0020] [Figure 4B] FIG. 2 is a cross-sectional view of Section A of a semiconductor structure including four VTFETs connected in parallel according to a first embodiment of the present invention.

[0021] [Figure 5A] FIG. 2 is a top view of a semiconductor structure including four VTFETs connected in parallel, according to a second embodiment of the present invention.

[0022] [Figure 5B] FIG. 10 is a cross-sectional view of Section B of a semiconductor structure including four VTFETs connected in parallel according to a second embodiment of the present invention.

[0023] [Figure 6] 1 is a top view of a semiconductor structure having shared gate regions for multiple columns of semiconductor structures, according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0024] Embodiments of the present invention recognize that a vertical transport field effect transistor (VTFET) has vertical current flow. Embodiments of the present invention recognize that a VTFET includes lower and upper source / drain regions. Embodiments of the present invention recognize that the lower source / drain region is closer to the backside of the VTFET (closer to the wafer) and the upper source / drain region is closer to the front side of the VTFET (closer to the conventional interconnect wiring). Embodiments of the present invention recognize that the input will be toward one source / drain region and the output will be toward the other source / drain region, such that either the input or the output will be on the backside of the device and either the input or the output will be on the front side of the device. Embodiments of the present invention recognize that a fin region is between the upper and lower source / drain regions and that a gate region surrounds the fin region. Accordingly, embodiments of the present invention recognize that the gate region needs to be connected to the front and / or backside of the semiconductor device. Embodiments of the present invention recognize that in conventional VTFETs, the pitch (or width) between gates in adjacent devices in the same semiconductor layer is commonly known as the contacted gate pitch (CGP) or contact poly pitch (CPP).

[0025] Embodiments of the present invention provide for any number of signals (e.g., clock, bus, I / O, power, ground, etc.) to be distributed or provided to the source / drain / gate regions of the VTFETs through a backside power delivery network. Embodiments of the present invention provide area efficiency by providing a single CPP to drive many gate regions of multiple devices with low resistance. Embodiments of the present invention provide full cell height contacts that reduce resistance from the backside to the frontside contact or vice versa. Embodiments of the present invention provide for the elimination of the RX or active area layer to further reduce resistance. Embodiments of the present invention provide frontside wiring connected to frontside contacts connected to the upper source / drain regions. Embodiments of the present invention provide frontside wiring to be selected from the group consisting of a local clock signal and an external input signal.

[0026] Certain embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings, in which embodiments of the disclosure are shown. However, the present disclosure may be implemented in various ways and therefore should not be construed as limited to the embodiments disclosed herein. Reference will now be made in detail to embodiments of the invention, examples of which are illustrated in the accompanying drawings, in which like reference numerals refer to like elements throughout.

[0027] The following presents a summary to provide a basic understanding of one or more embodiments of the present disclosure. This summary is not intended to identify key or critical elements or to delineate the scope of particular embodiments or the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. Aspects of the invention are described in terms of given example architectures; however, it should be understood that other architectures, structures, substrate materials, process features, and steps may vary within the scope of aspects of the invention.

[0028] Detailed embodiments of the claimed structures and methods are disclosed herein. The method steps described below do not form a complete process flow for manufacturing integrated circuits, such as semiconductor devices. The embodiments may be practiced in conjunction with integrated circuit fabrication techniques currently used in the art for advanced semiconductor devices, and only commonly practiced process steps necessary to understand the described embodiments are included. The figures represent cross-sectional portions of portions of advanced semiconductor devices after fabrication and are not drawn to scale, but rather are drawn to illustrate features of the described embodiments. Specific structural and functional details disclosed herein should not be construed as limiting, but merely as representative principles for teaching those skilled in the art how to employ the disclosed methods and structures in various ways. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0029] When an element, such as a layer, region, or substrate, is referred to as being "on" or "over" another element, it is understood that it can be directly on the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. When an element is referred to as being "connected" or "coupled" to another element, it is understood that it can be directly connected or coupled to the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0030] For purposes of explanation, hereinafter, the terms "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and derivatives thereof, refer to the disclosed structures and methods as oriented within the depicted figures. The terms "overlying," "atop," "over," "on," "positioned on," or "positioned atop" mean that a first element is on a second element, and that intervening elements, such as interface structures, may be present between the first and second elements. The term "directly contacting" means that a first element and a second element are connected without any intermediate conductive, insulating, or semiconducting layer at the interface of the two elements.

[0031] In order to avoid obscuring the presentation of embodiments of the present invention, in the following detailed description, some of the processing steps, materials, or operations known in the art may be combined for purposes of presentation and illustration, and in some instances may not be described in detail. Additionally, for the sake of brevity and to maintain focus on the unique features of the elements of the present invention, descriptions of previously discussed materials, processes, and structures may not be repeated with respect to subsequent figures. In other instances, some known processing steps or operations may not be described. It should be understood that the following description instead focuses on the unique features or elements of various embodiments of the present invention.

[0032] This embodiment may include an integrated circuit chip design, which may be created in a graphical computer programming language and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive, e.g., in a storage access network). If the designer does not fabricate the chip or the photolithography masks used to fabricate the chip, the designer may transmit the resulting design directly or indirectly to such an entity by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., via the Internet). The stored design is then converted into an appropriate format (e.g., GDSII) for fabricating photolithography masks, which typically contain multiple copies of the intended chip design that will be formed on wafers. The photolithography masks are used to define areas of the wafer (and / or layers thereon) to be etched or otherwise processed.

[0033] The methods described herein can be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as bare die, or in packaged form. In the latter case, the chips are mounted in single-chip packages (such as plastic carriers with leads attached to a motherboard or other higher-level carrier) or multi-chip packages (such as ceramic carriers with either surface interconnects or buried interconnects, or both). In either case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product can be any product containing integrated circuit chips, ranging from toys and other low-end applications to sophisticated computer products with displays, keyboards or other input devices, and central processors.

[0034] It should also be understood that material compounds are described in terms of the listed elements, e.g., SiGe. These compounds include various ratios of elements within the compound, e.g., SiGe includes SiGe, where x is less than or equal to 1, etc. Other elements may also be included in the compound and still function according to the present principles. Compounds with additional elements will be referred to herein as alloys.

[0035] References herein to "one embodiment" or "an embodiment," as well as other variations thereof, mean that the particular features, structures, characteristics, and the like described in connection with the embodiment are included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment," and any other variations thereof, appearing in various places throughout this specification are not necessarily all referring to the same embodiment.

[0036] References herein to "one embodiment," "other embodiment," "another embodiment," "an embodiment," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes that particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with one embodiment, it is understood that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments, whether explicitly described or not.

[0037] It should be understood that the use of any of the following terms " / ," "and / or," and "at least one of" is intended to encompass the selection of only the first enumerated option (A), or the selection of only the second enumerated option (B), or the selection of both options (A and B), for example, "A / B," "A and / or B," and "at least one of A and B." As another example, "A, B, and / or C" and "at least one of A, B, and C" are intended to encompass the selection of only the first enumerated option (A), or the selection of only the second enumerated option (B), or the selection of only the third enumerated option (C), or the selection of only the first and second enumerated options (A and B), or the selection of only the first and third enumerated options (A and C), or the selection of only the second and third enumerated options (B and C), or the selection of all three options (A, B, and C). This may be expanded to include as many items as are listed, as would be readily apparent to one skilled in this and related arts.

[0038] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit example embodiments. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0039] Spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element or feature as depicted in the figures for ease of description. It will be understood that the spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in a figure were inverted, elements described as being "below" or "below" other elements or features would then be oriented "above" such other elements or features. Thus, the term "below" can encompass both an above and below orientation. A device may be otherwise oriented (rotated 90 degrees or at another orientation), and the spatially relative descriptors used herein may be interpreted accordingly. Also, when a layer is referred to as being "between" two layers, it should be understood that it may be the only layer between the two layers, or there may be one or more intervening layers.

[0040] Although terms such as "first," "second," and the like may be used herein to describe various elements, it should be understood that these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Thus, a first element discussed below may be referred to as a second element without departing from the scope of the present concepts.

[0041] Generally, the various processes used to form semiconductor chips fall into four general categories: film deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process that grows, coats, or otherwise transfers material onto a wafer. Available techniques include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and the more recent atomic layer deposition (ALD). Another deposition technique is plasma-enhanced chemical vapor deposition (PECVD), a process that uses energy in a plasma to induce reactions at the wafer surface that would otherwise require the higher temperatures associated with conventional CVD. High-energy ion bombardment during PECVD deposition can also improve the electrical and mechanical properties of the film.

[0042] Semiconductor lithography is the formation of three-dimensional relief images or patterns on semiconductor substrates for later transfer of the patterns to the substrate. In semiconductor lithography, the patterns are formed with photosensitive polymers called photoresists. The patterns created by lithography or photolithography are typically used to define or protect selected surfaces and portions of semiconductor structures during subsequent etching processes.

[0043] Removal is any process, such as etching or chemical-mechanical planarization (CMP), that removes material from a wafer. Examples of etching processes include either wet (e.g., chemical) or dry etching processes. One example of a removal or dry etching process is ion beam etching (IBE). Generally, IBE (or milling) refers to a dry plasma etching method that utilizes a remote broad-beam ion / plasma source to remove substrate material by physically inert and / or chemically reactive gas means. Similar to other dry plasma etching techniques, IBE offers advantages such as etch rate, anisotropy, selectivity, uniformity, aspect ratio, and minimal substrate damage. Another example of a dry etching process is reactive ion etching (RIE). Generally, RIE uses a highly chemically reactive plasma to remove material deposited on a wafer. High-energy ions from the RIE plasma bombard the wafer surface and react with and remove the surface material.

[0044] Deposition processes for metal liners and sacrificial materials include, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or gas cluster ion beam (GCIB) deposition. CVD is a deposition process in which deposition species are formed as a result of a chemical reaction between gaseous reactants at temperatures above room temperature (e.g., from about 25°C to about 900°C). A solid product of the reaction is deposited on a surface on which a film, coating, or layer of the solid product is to be formed. Variations on CVD processes include, but are not limited to, atmospheric pressure CVD (APCVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), and metal organic CVD (MOCVD), and combinations thereof may also be employed. In an alternative embodiment using PVD, the sputtering equipment may include a direct current diode system, radio frequency sputtering, magnetron sputtering, or ionized metal plasma sputtering. In an alternative embodiment using ALD, chemical precursors react with the surface of the material one at a time to deposit a thin film on the surface. In an alternative embodiment using GCIB deposition, high pressure gas is expanded in a vacuum and then allowed to condense into clusters, which can be ionized and directed onto a surface to provide highly anisotropic deposition.

[0045] It should be noted that the embodiments of the present invention described below are discussed with reference to a semiconductor structure consisting of four connected VTFETs. In alternative embodiments, the semiconductor structure may consist of any number of VTFETs in any organization / layout in parallel and / or series.

[0046] Vertical transport field-effect transistors (VTFETs) have become a viable device option for scaling semiconductor devices (e.g., complementary metal oxide semiconductor (CMOS) devices) to the 5-nanometer (nm) node and beyond. VTFET devices include one or more fin channels with source / drain regions at the ends of the fin channel on the top and bottom sides of the fin. Current flows vertically (e.g., perpendicular to the substrate) through the fin channel, e.g., from the bottom source / drain region to the top source / drain region. Vertical transport architecture devices are designed to address limitations of horizontal device architectures, e.g., in terms of density, performance, power consumption, and integration, by, e.g., decoupling gate length from contact gate pitch to provide density comparable to FinFETs at larger contacted poly pitches (CPPs) and lower middle-of-line (MOL) resistance.

[0047] In a first embodiment, Figure 1 shows VTFET 100 with contacts 114, 124, and 134 connected directly to the interconnection wiring and / or power distribution network (not shown) on the front side of VTFET 100. In a second embodiment, Figure 2 shows VTFET 200 with contacts 214 and 234 connected directly to the interconnection wiring and / or power distribution network (not shown) on the front side of VTFET 200, and contact 224 connected directly to the interconnection wiring and / or power distribution network (not shown) on the back side of VTFET 200. In a third embodiment, Figure 3 shows VTFET 300 with contact 314 connected directly to the interconnection wiring and / or power distribution network (not shown) on the front side of VTFET 300, and contacts 324 and 334 connected directly to the interconnection wiring and / or power distribution network (not shown) on the back side of VTFET 300.

[0048] 1 is a cross-sectional view of a VTFET 100 formed on a bulk substrate 102. The substrate 102 may be formed of any suitable semiconductor structure, including various silicon-containing materials, including but not limited to silicon (Si), silicon germanium (SiGe), silicon germanium carbide (SiGeC), silicon carbide (SiC), and multiple layers thereof. While silicon is the semiconductor material primarily used in wafer fabrication, alternative semiconductor materials, such as but not limited to germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), SiGe, cadmium telluride (CdTe), zinc selenide (ZnSe), and the like, may be employed as additional layers. In one exemplary embodiment, the substrate 102 is silicon.

[0049] VTFET 100 includes an STI region 104 made of a dielectric material such as silicon oxide or silicon oxynitride and formed by methods known in the art. For example, in one exemplary embodiment, STI region 104 is a shallow trench isolation oxide layer.

[0050] The VTFET 100 includes upper source / drain regions 110 and lower source / drain regions 120 on either end of a fin 130. In one embodiment, the upper source / drain region 110 is formed between dielectric layers 170. In one embodiment, the lower source / drain region 120 is formed in the substrate 102 between shallow trench isolation regions 104. The upper source / drain region 110 and the lower source / drain region 120 are formed, for example, by an epitaxial growth process. The epitaxially grown upper source / drain region 110 and lower source / drain region 120 may be in-situ doped, meaning that dopants are incorporated into the epitaxy film during the epitaxy process. Other alternative doping techniques may be used, including, but not limited to, ion implantation, gas phase doping, plasma doping, plasma immersion ion implantation, cluster doping, implant doping, liquid phase doping, solid phase doping, etc., and the dopants may include, for example, n-type dopants selected from the group of phosphorus (P), arsenic (As), and antimony (Sb), and p-type dopants selected from the group of boron (B), gallium (Ga), indium (In), and thallium (Tl), in various concentrations. For example, in a non-limiting example, dopant concentrations range from 1×10 18 / cm 3 From 1x10 21 / cm 3 According to one embodiment, the lower source / drain region 120 may be SiGe doped with boron in a p-type field-effect transistor (P-FET) or silicon doped with phosphorus in an n-type field-effect transistor (N-FET). It should be understood that the term "source / drain region" as used herein means that a given source / drain region may be either a source region or a drain region depending on the application.

[0051] Terms such as "epitaxial growth and / or deposition" and "epitaxially formed and / or grown" refer to the growth of a semiconductor material on a deposition surface of a semiconductor material, where the semiconductor material being grown has the same crystalline properties as the semiconductor material on the deposition surface. In an epitaxial deposition process, chemical reactants provided by source gases are controlled and system parameters are set so that the depositing atoms arrive at the deposition surface of a semiconductor substrate with sufficient energy to move around the surface and orient themselves relative to the crystalline arrangement of atoms on the deposition surface. Thus, the epitaxial semiconductor material has the same crystalline properties as the deposition surface on which it is formed. For example, epitaxial semiconductor material deposited on a {100} crystal plane will adopt a {100} orientation. In some embodiments, the epitaxial growth and / or deposition process is selective for formation on semiconductor surfaces and does not deposit material on dielectric surfaces, such as silicon dioxide or silicon nitride surfaces.

[0052] Examples of various epitaxial growth processes include, for example, rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). Temperatures for epitaxial deposition processes can range from 500°C to 900°C. Higher temperatures typically result in faster deposition, but faster deposition can result in crystalline defects and film cracking.

[0053] A number of different sources can be used in the epitaxial growth of compressively strained layers. In some embodiments, the gas source for deposition of the epitaxial semiconductor material includes a silicon-containing gas source, a germanium-containing gas source, or a combination thereof. For example, an epitaxial silicon layer can be deposited from a silicon gas source, including, but not limited to, silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, and combinations thereof. An epitaxial germanium layer can be deposited from a germanium gas source, including, but not limited to, germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. Epitaxial silicon-germanium alloy layers can be formed using a combination of these gas sources, although carrier gases such as hydrogen, nitrogen, helium, and argon may be used. After epi formation, a drive-in anneal can be applied to drive the dopants closer to the bottom of the fin channel.

[0054] In one embodiment, as used herein, "semiconductor fin" or fin 130 refers to a semiconductor material including a pair of parallel vertical sidewalls. As used herein, a surface is "vertical" if there is a vertical plane therefrom that is no more than three times the root-mean-square roughness of the surface. In one embodiment, each fin 130 has a height ranging from about 20 nm to about 200 nm and a width ranging from about 5 nm to about 30 nm. Other heights and / or widths smaller or larger than the ranges mentioned herein may also be used in this application. Each fin 130 is spaced apart from its nearest neighboring fin 130 by a pitch ranging from about 20 nm to about 100 nm; the pitch is measured from a point or reference plane on one semiconductor fin to the exact same point or reference plane on a neighboring semiconductor fin. Additionally, the fins 130 are generally oriented parallel to one another. While this application describes and illustrates a single fin 108, any number of fins with surrounding gate regions may be used, and the fins may be of any shape.

[0055] The fin 130 may be formed of any suitable semiconductor structure, including various silicon-containing materials, including, but not limited to, silicon (Si), silicon germanium (SiGe), silicon germanium carbide (SiGeC), silicon carbide (SiC), and multiple layers thereof. While silicon is the semiconductor material primarily used in wafer fabrication, alternative semiconductor materials, such as, but not limited to, germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), SiGe, cadmium telluride (CdTe), zinc selenide (ZnSe), and the like, may be employed as additional layers. In one exemplary embodiment, the fin 130 is silicon.

[0056] In one embodiment, a lower spacer layer 140 is formed over the STI regions 104 and the lower source / drain regions 120. In one embodiment, the lower spacer layer 140 is formed around the fin 130. Suitable materials for the lower spacer layer 140 include, for example, silicon boron nitride (SiBN), silicon boron carbonitride (SiBCN), silicon oxycarbonitride (SiOCN), SiN, and SiO x The lower spacer layer 140 may be deposited using directional deposition techniques such as high-density plasma (HDP) deposition and gas cluster ion beam (GCIB) deposition. Directional deposition deposits the spacer material preferably on exposed horizontal surfaces, but not on lateral sidewalls. Alternatively, the lower spacer layer 140 may be formed by overfilling the space with a dielectric material, followed by chemical mechanical planarization (CMP) and a dielectric recess.

[0057] In one embodiment, an upper spacer layer 160 is formed over the gate region between the fin 130 and the dielectric layer 170. In one embodiment, the upper spacer layer 160 is formed around the fin 130. Suitable materials for the upper spacer layer 160 include, for example, silicon boron nitride (SiBN), silicon boron carbonitride (SiBCN), silicon oxycarbonitride (SiOCN), SiN, and SiO x The lower spacer layer 140 may be deposited using directional deposition techniques such as high-density plasma (HDP) deposition and gas cluster ion beam (GCIB) deposition. Directional deposition deposits the spacer material preferably on exposed horizontal surfaces, but not on lateral sidewalls. Alternatively, the upper spacer layer 160 may be formed by overfilling the space with a dielectric material, followed by chemical mechanical planarization (CMP) and a dielectric recess.

[0058] A gate region is formed on the lower spacer layer 140 and around the fin 130. In an exemplary embodiment, the gate region is deposited on the lower spacer layer 140 and around the fin 130 using, for example, ALD, CVD, RFCVD, plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), or molecular layer deposition (MLD). The gate region may include a gate dielectric layer 150 and a gate conductor layer 132. The gate dielectric layer 150 may be formed of a high-k dielectric material. Examples of high-k materials include, but are not limited to, metal oxides such as HfO, hafnium silicon oxide (Hf-Si-O), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminate (LaAlO), zirconium oxide (ZrO), zirconium silicate, zirconium silicon oxynitride, tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanate, barium titanate, strontium titanate, yttrium oxide (YO), aluminum oxide (AlO), lead scandium tantalate, and lead zinc niobate. High-k materials may further include dopants such as lanthanum (La), aluminum (Al), and magnesium (Mg). The gate conductor layer 132 may include a metal gate or a work function metal (WFM). The WFM for the gate conductor layer may be titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbon (TiAlC), combinations of Ti and Al alloys, a stack including a barrier layer (e.g., TiN, TaN, etc.) followed by one or more of the aforementioned WFM materials, etc. It should be understood that a variety of other materials may be used for the gate conductor layer 132 as desired.

[0059] In one embodiment, the dielectric layer 170 is made of, for example, silicon dioxide (SiO xThe dielectric layer 170 may be composed of a low-κ dielectric layer, such as silicon dioxide, silicon dioxide, silicon dioxide (SiO 2 ), ...

[0060] In one embodiment, the upper source / drain region 110, the lower source / drain region 120, and the gate region are connected to interconnect wiring and / or a power distribution network (not shown) via contacts 114, 124, and 134, respectively. In one embodiment, as shown in FIG. 1 , contacts 114, 124, and 134 are formed to directly connect to interconnect wiring and / or a power distribution network (not shown) on the front side of VTFET 100. In one embodiment, contacts 114, 124, and 134 may comprise any suitable conductive material, such as, for example, copper, aluminum, tungsten, cobalt, or alloys thereof. Examples of deposition techniques that may be used include, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). In some cases, electroplating techniques may be used to form contacts 114, 124, and 134.

[0061] In a second embodiment, FIG. 2 shows VTFET 200 with contacts 214 and 234 directly connected to interconnect wiring and / or a power distribution network (not shown) on the front side of VTFET 200, and contact 224 directly connected to interconnect wiring and / or a power distribution network (not shown) on the back side of VTFET 200. In the second embodiment, VTFET 200 shares substantially similar features to those described above with reference to VTFET 100. For example, upper source / drain region 210 is substantially similar to upper source / drain region 110. It should be noted that while a substrate similar to substrate 102 shown in FIG. 1 is not shown in FIG. 2, it is known to those skilled in the art that VTFET 200 would be formed on a substrate similar to substrate 102 shown in FIG. 1.

[0062] In the second embodiment, the orientation of the contacts in VTFET 200 is the primary difference compared to VTFET 100. In the second embodiment, contacts 214 and 234 are directly connected to the interconnect wiring and / or power distribution network (not shown) on the front side of VTFET 200, and contact 224 is directly connected to the interconnect wiring and / or power distribution network (not shown) on the back side of VTFET 200.

[0063] In a third embodiment, FIG. 3 illustrates VTFET 300 having contact 314 directly connected to interconnect wiring and / or a power distribution network (not shown) on the front side of VTFET 300, and contacts 324 and 334 directly connected to interconnect wiring and / or a power distribution network (not shown) on the back side of VTFET 300. In the third embodiment, VTFET 300 shares substantially similar features to those described above with reference to VTFET 100 and VTFET 200. For example, upper source / drain region 310 is substantially similar to upper source / drain region 110 and upper source / drain region 210. It should be noted that while a substrate similar to substrate 102 shown in FIG. 1 is not shown in FIG. 3, it is known to those skilled in the art that VTFET 300 would be formed on a substrate similar to substrate 102 shown in FIG. 1.

[0064] In the third embodiment, the orientation of the contacts in VTFET 300 is the primary difference compared to VTFET 100 and VTFET 200. In the third embodiment, contact 314 is directly connected to the interconnect wiring and / or power distribution network (not shown) on the front side of VTFET 300, and contacts 324 and 334 are directly connected to the interconnect wiring and / or power distribution network (not shown) on the back side of VTFET 300.

[0065] FIG. 4A shows a top view of a semiconductor structure 400A including four VTFETs connected in parallel according to a first embodiment of the present invention. In other words, a shared input is provided to the first VTFET, the second VTFET, the third VTFET, and the fourth VTFET, and a shared output extends from the first VTFET, the second VTFET, the third VTFET, and the fourth VTFET. As shown in FIG. 4A, the first VTFET includes a shared lower source / drain region 420A, a fin 430A, and an upper source / drain region (not shown). As shown in FIG. 4A, the second VTFET includes a shared lower source / drain region 420A, a fin 432A, and an upper source / drain region (not shown). As shown in FIG. 4A, the third VTFET includes a shared lower source / drain region 420A, a fin 434A, and an upper source / drain region (not shown). As shown in FIG. 4A , the fourth VTFET includes a shared lower source / drain region 420A, a fin 436A, and an upper source / drain region (not shown). As explained, the upper source / drain region of each VTFET is not shown for clarity. Note that in a preferred embodiment, the shared lower source / drain region 420A may be connected to a backside power distribution network (not shown). In an alternative embodiment, the shared lower source / drain region 420A may be connected to a frontside power distribution network (not shown). In an embodiment, the shared lower source / drain region 420A may be any number of separate lower source / drain regions connected by a shared bottom contact that connects to a frontside or backside power distribution network (not shown). In an embodiment, the first VTFET, the second VTFET, the third VTFET, and the fourth VTFET each have an upper source / drain region (not shown) connected to a shared topside contact 480A. In an embodiment, the shared topside contact 480A is connected to a frontside or backside power distribution network (not shown). In an alternative embodiment, each upper source / drain region (not shown) may be connected to a separate front side contact (not shown), with each separate front side contact being connected to a front side or back side power supply network (not shown).In one embodiment, as shown here, shared front side contact 480A extends to the left edge of gate region 440A and to the right edge of gate region 446A. In alternative embodiments, as known in the art, shared front side contact 480A can extend any horizontal distance, so long as shared front side contact 480A is at least electrically connected to the upper source / drain regions described below.

[0066] As shown in FIG. 4A , in one embodiment, the first VTFET includes a gate region 440A that surrounds at least a portion of fin 430A. In one embodiment, the second VTFET includes a gate region 442A that surrounds at least a portion of fin 432A. In one embodiment, semiconductor structure 400A includes a shared gate region 472 connected to both gate region 440A and gate region 442A. In one embodiment, shared gate region 472 is connected to gate contact 474, which is connected to shared gate contact 481. In an alternative embodiment, shared gate region 472 may not be present, and both gate region 440A and gate region 442A may have their own gate contacts (not shown) connected to shared gate contact 481. In one embodiment, the third VTFET includes a gate region 444A that surrounds at least a portion of fin 434A. In one embodiment, the fourth VTFET includes a gate region 446A that surrounds at least a portion of fin 436A. In one embodiment, semiconductor structure 400A includes a shared gate region 476 connected to both gate region 444A and gate region 446A. In one embodiment, shared gate region 476 is connected to gate contact 478, which is connected to shared gate contact 481. In an alternative embodiment, shared gate region 476 may not be present, and both gate region 444A and gate region 446A may have their own gate contacts (not shown) connected to shared gate contact 481. In another alternative embodiment, a single shared gate contact (not shown) may be connected to gate regions 440A, 442A, 444A, and 446A, and a single shared gate contact (not shown) is connected to shared gate contact 481. In one embodiment, gate contact 481 may be of any size or shape to connect to gate regions 440A, 442A, 444A, and 446A, and / or any configuration of shared gate regions.For example, shared gate contact 481 may extend to only the fourth VTFET and connect to a gate contact (not shown) adjacent to the fourth VTFET, which connects to gate regions 440A, 442A, 444A, and 446A.

[0067] In one embodiment, shared gate contact 481 is connected to shared gate contact 483. For simplicity, shared gate contact 481 and shared gate contact 483 are shown as two separate gate contacts; however, note that in some embodiments, they may be a single shared gate contact. In one embodiment, shared gate contact 483 extends to backside contact 482A. In one embodiment, backside contact 482A is connected to a backside power delivery network (not shown). In one embodiment, the center of backside contact 482A is approximately 1 CPP from the center of the adjacent fourth VTFET. In one embodiment, as known in the art, shared gate contact 481 may be any shape (i.e., length, width, height) as long as shared gate contact 481 is electrically connected to the gate regions discussed above.

[0068] FIG. 4B shows a cross-sectional view of section A of a semiconductor structure 400B including four VTFETs connected in parallel according to a first embodiment of the present invention. As shown in FIG. 4B, a first VTFET includes a shared lower source / drain region 420B, a fin 430B, an upper source / drain region 410B, and a gate region 440B surrounding a portion of fin 430B. As shown in FIG. 4B, a second VTFET includes a shared lower source / drain region 420B, a fin 432B, an upper source / drain region 412B, and a gate region 442B surrounding a portion of fin 432B. As shown in FIG. 4B, a third VTFET includes a shared lower source / drain region 420B, a fin 434B, an upper source / drain region 414B, and a gate region 444B surrounding a portion of fin 434B. As shown in FIG. 4B , the fourth VTFET includes a shared lower source / drain region 420B, a fin 436B, an upper source / drain region 416B, and a gate region 446B surrounding a portion of the fin 436B. Note that in alternative embodiments, each VTFET, or any combination of VTFETs, may have individual / separate lower source / drain regions connected to a shared lower contact (not shown). In one embodiment, the shared lower source / drain region 420B is connected to a backside contact 490, which may be connected to a backside power distribution network (not shown). In one embodiment, a backside contact 482B is connected to gate regions 440B, 442B, 444B, and 446B via a structure not shown in Cross Section A. In one embodiment, the backside contact 482B connects to a backside power distribution network (not shown). In one embodiment, the shared gate contact 481 may connect to the backside contact 482B at any vertical point of the backside contact 482B. In one embodiment, when the backside contact 482B is formed from the front side, the backside, or a combination of the two, the backside contact 482B may connect to the shared gate contact 481 at the middle, top, or any portion of the backside contact 482B.

[0069] FIG. 5A shows a top view of a semiconductor structure 500A including four VTFETs connected in parallel according to a second embodiment of the present invention. In other words, a shared input is provided to the first VTFET, the second VTFET, the third VTFET, and the fourth VTFET, and a shared output extends from the first VTFET, the second VTFET, the third VTFET, and the fourth VTFET. As shown in FIG. 5A, the first VTFET includes a shared lower source / drain region 520A, a fin 530A, and an upper source / drain region (not shown). As shown in FIG. 5A, the second VTFET includes a shared lower source / drain region 520A, a fin 532A, and an upper source / drain region (not shown). As shown in FIG. 5A, the third VTFET includes a shared lower source / drain region 520A, a fin 534A, and an upper source / drain region (not shown). As shown in FIG. 5A , the fourth VTFET includes a shared lower source / drain region 520A, a fin 536A, and an upper source / drain region (not shown). As explained, the upper source / drain region of each VTFET is not shown for clarity. Note that in a preferred embodiment, the shared lower source / drain region 520A may be connected to a backside power distribution network (not shown). In an alternative embodiment, the shared lower source / drain region 520A may be connected to a frontside power distribution network (not shown). In an embodiment, the shared lower source / drain region 520A may be any number of separate lower source / drain regions connected by a shared bottom contact that connects to a frontside or backside power distribution network (not shown). In an embodiment, the first VTFET, the second VTFET, the third VTFET, and the fourth VTFET each have an upper source / drain region (not shown) connected to a shared topside contact 580A. In an embodiment, the shared topside contact 580A is connected to a frontside or backside power distribution network (not shown). In an alternative embodiment, each upper source / drain region (not shown) may be connected to a separate front side contact (not shown), with each separate front side contact being connected to a front side or back side power supply network (not shown).In one embodiment, as shown here, shared front side contact 580A extends to the left edge of gate region 540A and the right edge of gate region 546A. In alternative embodiments, as known in the art, shared front side contact 580A can extend any horizontal distance, so long as shared front side contact 580A is at least electrically connected to the upper source / drain regions described below.

[0070] As shown in FIG. 5A , in one embodiment, the first VTFET includes a gate region 540A that surrounds at least a portion of fin 530A. In one embodiment, the second VTFET includes a gate region 542A that surrounds at least a portion of fin 532A. In one embodiment, semiconductor structure 500A includes a shared gate region 572 connected to both gate region 540A and gate region 542A. In one embodiment, shared gate region 572 is connected to gate contact 574, which is connected to shared gate contact 581. In an alternative embodiment, shared gate region 572 may not be present, and both gate region 540A and gate region 542A may have their own gate contacts (not shown) connected to shared gate contact 581. In one embodiment, the third VTFET includes a gate region 544A that surrounds at least a portion of fin 534A. In one embodiment, the fourth VTFET includes a gate region 546A that surrounds at least a portion of fin 536A. In one embodiment, semiconductor structure 500A includes a shared gate region 576 connected to both gate region 544A and gate region 546A. In one embodiment, shared gate region 576 is connected to gate contact 578, which is connected to shared gate contact 581. In an alternative embodiment, shared gate region 576 may not be present, and both gate region 544A and gate region 546A may have their own gate contacts (not shown) connected to shared gate contact 581. In another alternative embodiment, a single shared gate contact (not shown) may be connected to gate regions 540A, 542A, 544A, and 546A, and a single shared gate contact (not shown) is connected to shared gate contact 581. In an embodiment, gate contact 581 may be of any size or shape to connect to gate regions 540A, 542A, 544A, and 546A, and / or any configuration of shared gate regions.For example, shared gate contact 581 may extend only to the fourth VTFET and connect to a gate contact (not shown) adjacent to the fourth VTFET, which connects to gate regions 540A, 542A, 544A, and 546A.

[0071] In one embodiment, shared gate contact 581 is connected to shared gate contact 582A. For simplicity, shared gate contact 581 and shared gate contact 582A are shown as two separate gate contacts; however, note that in some embodiments, they may be a single shared gate contact. In one embodiment, shared gate contact 582A extends to RX layer 584A. In one embodiment, RX layer 584A may extend to connect to any other semiconductor device (not shown). In one embodiment, RX layer 584A connects to backside contact 586. In one embodiment, backside contact 586 is connected to a backside power delivery network (not shown). In one embodiment, the center of shared gate contact 582A is approximately 1 CPP from the center of the adjacent fourth VTFET. In one embodiment, as known in the art, shared gate contact 581 may be any shape (i.e., length, width, height) as long as it is electrically connected to the gate regions discussed above.

[0072] FIG. 5B shows a cross-sectional view of section B of a semiconductor structure 500B including four VTFETs connected in parallel according to a second embodiment of the present invention. As shown in FIG. 5B, a first VTFET includes a shared lower source / drain region 520B, a fin 530B, an upper source / drain region 510B, and a gate region 540B surrounding a portion of fin 530B. As shown in FIG. 5B, a second VTFET includes a shared lower source / drain region 520B, a fin 532B, an upper source / drain region 512B, and a gate region 542B surrounding a portion of fin 532B. As shown in FIG. 5B, a third VTFET includes a shared lower source / drain region 520B, a fin 534B, an upper source / drain region 514B, and a gate region 544B surrounding a portion of fin 534B. As shown in FIG. 5B , the fourth VTFET includes a shared lower source / drain region 520B, a fin 536B, an upper source / drain region 516B, and a gate region 546B surrounding a portion of the fin 536B. Note that in alternative embodiments, each VTFET, or any combination of VTFETs, may have individual / separate lower source / drain regions connected to a shared lower contact (not shown). In one embodiment, the shared lower source / drain region 520B is connected to a backside contact 590, which may be connected to a backside power distribution network (not shown). In one embodiment, a backside contact 582B is connected to gate regions 540B, 542B, 544B, and 546B via a structure not shown in Cross Section B. In one embodiment, the backside contact 582B connects to an RX layer 584B. As discussed above, in one embodiment, the RX layer 584A may extend to connect to any other semiconductor device (not shown). In one embodiment, the RX layer 584A connects to a backside contact 586. In one embodiment, the backside contact 586 connects to a backside power distribution network (not shown). In one embodiment, the shared gate contact 581 can connect to the backside contact 582B at any vertical point of the backside contact 582B.In one embodiment, when the backside contact 582B is formed from the front side, the backside, or a combination of the two, the backside contact 582B may connect to the shared gate contact 581 at the middle, top, or any portion of the backside contact 582B.

[0073] 6 illustrates a top view of a semiconductor structure having a shared gate region for multiple columns of semiconductor structures, according to one embodiment of the present invention. As shown in FIG. 6, in one embodiment, semiconductor structure 600 includes a first column 602 of parallel-connected VTFETs 620, 622, 624, and 626. In one embodiment, semiconductor structure 600 includes a second column 612 of parallel-connected VTFETs 630, 632, 634, and 636. In one embodiment, semiconductor structure 600 includes a third column 604 of parallel-connected VTFETs 640, 642, 644, and 646. In one embodiment, semiconductor structure 600 includes a fourth column 614 of parallel-connected VTFETs 650, 652, 654, and 656. In other words, each group of four parallel-connected VTFETs includes a shared input (source / drain region or contact region) and a shared output (source / drain region or contact region). VTFETs 620, 622, 624, 626, 630, 632, 634, 636, 640, 642, 644, 646, 650, 652, 654, and 656 are similar to and include similar features as VTFET structures described herein. As noted above, it should be noted that semiconductor structure 600 represents a single structure and layout of a VTFET circuit and is not intended to limit embodiments of the present invention to this structure and layout. In an embodiment, any other structure and layout of a VTFET circuit, including, but not limited to, other field effect transistors, not shown, may be included. Note that source / drain region contacts are not included to facilitate discussion of FIG. 6 .

[0074] In one embodiment, the VTFETs in the first column 602 and the VTFETs in the third column 604 include a first gate region 606. In one embodiment, the VTFETs in the third column 612 and the VTFETs in the fourth column 614 include a second gate region 616. In one embodiment, the first gate region 606 includes a first gate contact 660. In one embodiment, the first gate contact 660 is connected to the gate region of each VTFET found in the first column 602 and the third column 604. In one embodiment, the second gate region 616 includes a second gate contact 662. In one embodiment, the second gate contact 662 is connected to the gate region of each VTFET found in the second column 612 and the fourth column 614. In one embodiment, the first gate contact 660 and the second gate contact 662 are connected to a shared gate contact 664. In one embodiment, the shared gate contact 664 includes one or more backside gate contacts (not shown) connected to a backside power distribution network (not shown). In one embodiment, the center of the shared gate contact 664 is 1 CPP from the center of the fins of the VTFETs 626, 630, 646, and 650.

[0075] In one embodiment, as described above, the front side contacts may extend any horizontal distance, so long as the front side is at least electrically connected to the upper source / drain regions described above.

[0076] The description of various embodiments of the present invention has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein have been selected to best explain the principles, practical applications, or technical improvements of the embodiments over technologies found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. Vertical transport field effect transistors (VTFETs) on wafers; a backside power supply network on the backside of the wafer; and a first backside contact, wherein the first backside contact is connected to a gate of the VTFET and a first portion of the backside power delivery network; A semiconductor device comprising:

2. the VTFET has a first width, the first width being a contacted poly pitch (CPP); and the first backside contact is the first width; The semiconductor device of claim 1 .

3. the VTFET has a first width, the first width being a contacted poly pitch (CPP); and the first backside contact is twice the first width; The semiconductor device of claim 1 .

4. 10. The semiconductor device of claim 1, wherein the backside power delivery network is selected from the group consisting of a clock signal and an input signal.

5. The semiconductor device of claim 1 , wherein a height of the first backside contact is a cell height of the VTFET.

6. 10. The semiconductor device of claim 1, further comprising a front-side contact, the front-side contact connected to an upper source / drain region of the VTFET and to a front-side interconnect.

7. The semiconductor device according to claim 6 , wherein the front side wiring is selected from the group consisting of a local clock signal and an external input signal.

8. a plurality of vertical transport field effect transistors (VTFETs) on the wafer; a backside power supply network on the backside of the wafer; and a first backside contact, wherein the first backside contact is connected to a gate of each VTFET of the plurality of VTFETs and to a first portion of the backside power delivery network; A semiconductor device comprising:

9. each VTFET of the plurality of VTFETs has a first width, the first width being a contacted poly pitch (CPP); the first backside contact is the first width; The semiconductor device of claim 8.

10. a VTFET of the plurality of VTFETs has a first width, the first width being a contacted poly pitch (CPP); the first backside contact is twice the first width; The semiconductor device of claim 8 further comprising:

11. 9. The semiconductor device of claim 8, wherein the first portion of the backside power delivery network is selected from the group consisting of a clock signal and an input signal.

12. 9. The semiconductor device of claim 8, wherein a height of the first backside contact is a cell height of each VTFET of the plurality of VTFETs.

13. 9. The semiconductor device of claim 8, further comprising a front-side contact, the front-side contact connected to upper source / drain regions of the plurality of VTFETs and to front-side wiring.

14. 9. The semiconductor device according to claim 8, wherein the front side wiring is selected from the group consisting of a local clock signal and an external input signal.

15. a first plurality of vertical transport field effect transistors (VTFETs) in a first column on the wafer; a second plurality of VTFETs in a second column on the wafer, wherein the first column is vertically adjacent to the second column; a backside power supply network on the backside of the wafer; a first backside contact between the first column and the second column, wherein the first backside contact is connected to a gate of each VTFET of the first plurality of VTFETs and a gate of each VTFET of the second plurality of VTFETs; and a second backside contact, wherein the second backside contact is connected to the first backside contact and to the backside power supply network; A semiconductor device comprising:

16. at least one VTFET of the first plurality of VTFETs and the second plurality of VTFETs has a first width, the first width being a contacted poly pitch (CPP); 16. The semiconductor device of claim 15.

17. further comprising a third plurality of VTFETs in the first column, the first plurality of VTFETs and the third plurality of VTFETs being spaced apart by at least the first width; and the first backside contact extends adjacent to the third plurality of VTFETs, the first backside contact being connected to a gate of each VTFET of the third plurality of VTFETs.

17. The semiconductor device of claim 16.

18. further comprising a fourth plurality of VTFETs in the second column, the second plurality of VTFETs and the fourth plurality of VTFETs being spaced apart by at least the first width; and the first backside contact extends adjacent to the fourth plurality of VTFETs, the first backside contact being connected to a gate of each VTFET in the fourth plurality of VTFETs.

18. The semiconductor device of claim 17.

19. 16. The semiconductor device of claim 15, wherein a height of the second backside contact is a height of each VTFET cell of the first and second plurality of VTFETs.

20. 16. The semiconductor device of claim 15, wherein the backside power delivery network is selected from the group consisting of a clock signal and an input signal.

Images