Molecular layer deposition carbon masks for direct selective deposition of silicon-containing materials

Abstract

An embodiment of the present technology relates to a semiconductor processing method that includes providing a structured semiconductor substrate that includes a trench having a bottom surface and a top surface, the method further including depositing a portion of a silicon-containing material on the bottom surface of the trench during at least one deposition cycle, each deposition cycle including depositing a portion of the silicon-containing material on the bottom surface and the top surface of the trench, depositing a carbon-containing mask layer on the silicon-containing material on the bottom surface of the trench, where the carbon-containing mask layer is not formed on the top surface of the trench, removing the portion of the silicon-containing material from the top surface of the trench, and removing the carbon-containing mask layer from the silicon-containing material on the bottom surface of the trench, where the deposited silicon-containing material remains on the bottom surface of the trench.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of and priority to U.S. patent application Ser. No. 17 / 954,565, filed Sep. 28, 2022, entitled "MOLECULAR LAYER DEPOSITION CARBON MASKS FOR DIRECT SELECTIVE DEPOSITION OF SILICON-CONTAINING MATERIALS," the entire contents of which are incorporated herein by reference.

[0002] TECHNICAL FIELD

[0002] The present technology relates to semiconductor manufacturing methods for depositing silicon-containing materials into trenches, steps, and other structures of semiconductor-containing components. [Background technology]

[0003]

[0003] In the fabrication of microelectronic devices, many applications require void-free filling of narrow trenches with aspect ratios (AR) exceeding 10:1. One application is shallow trench isolation (STI). In this application, films must be of high quality throughout the trench (e.g., wet etch rate ratios less than 2) and have very low leakage. One method that has been used successfully in the past is flowable CVD, in which oligomers are carefully formed in the gas phase, which condense on the surface and then "flow" into the trench. The deposited films have been of very poor quality, requiring processing steps such as water vapor annealing and UV curing.

[0004] As feature dimensions shrink and aspect ratios increase, post-deposition curing methods for deposited flowable films become more difficult, resulting in films with varying composition throughout the filled trench.

[0005]

[0005] Silicon-containing materials, such as amorphous silicon, have been widely used in semiconductor manufacturing processes as sacrificial layers because they offer good etch selectivity over other films (e.g., silicon oxide, amorphous carbon, etc.). With the shrinking critical dimensions (CDs) in semiconductor manufacturing, filling high-aspect-ratio gaps has become increasingly important in advanced wafer fabrication. Current metal replacement gate processes involve furnace-deposited polycrystalline silicon or amorphous silicon dummy gates. Due to the nature of the deposition process, a seam forms in the center of the Si dummy gate. This seam can open during post-deposition processing, potentially causing structural damage.

[0006]

[0006] In conventional plasma-enhanced chemical vapor deposition (PECVD) of amorphous silicon (a-Si), a "mushroom-shaped" film forms at the top of narrow trenches because the plasma cannot penetrate deep trenches, resulting in pinching-off of the narrow trench from the top and the formation of voids at the bottom of the trench.

[0007]

[0007] Conventional thermal CVD / furnace processes can grow a-Si by thermally decomposing silicon precursors (e.g., silane, disilane). Due to insufficient precursor supply or the presence of decomposition by-products at the bottom of the trench, the deposition rate at the top of the trench is higher than that at the bottom. As a result, narrow seams or voids are observed within the trench.

[0008] Therefore, there is a need for a method for gap filling in high aspect ratio structures that can provide seam-free film growth.

[0009] The nature and advantages of the present invention may be further understood by reference to the remaining portions of the specification and drawings, in which the same reference numerals are used throughout the several views to refer to like components. In some instances, a sub-label may be associated with the reference numeral and, following a hyphen, may indicate one of multiple similar components. When a reference numeral is made without specifying an existing sub-label, it is intended to refer to all such multiple similar components. Summary of the Invention

[0010]

[0012] An embodiment of the present technology includes a semiconductor processing method. The method includes providing a structured semiconductor substrate including a bottom surface and an upper surface laterally adjacent to the bottom surface. The method further includes depositing a portion of a silicon-containing material on the bottom surface of the trench during at least one deposition cycle, each deposition cycle including depositing a portion of the silicon-containing material on the bottom and upper surfaces of the trench. The cycle also includes depositing a carbon-containing mask layer on the silicon-containing material on the bottom surface of the trench, with no carbon-containing mask layer formed on the upper surface of the trench. The cycle further includes removing a portion of the silicon-containing material from the upper surface of the trench. The cycle also includes removing the carbon-containing mask layer from the silicon-containing material on the bottom surface of the trench, leaving the deposited silicon-containing material on the bottom surface of the trench.

[0011]

[0013] In a further embodiment, depositing a portion of the silicon-containing material on the bottom and top surfaces of the trench includes treating the deposited silicon-containing material with argon, helium, and hydrogen ions, the ions accelerating in a direction perpendicular to the structured semiconductor substrate. In a further embodiment, depositing the carbon-containing mask layer includes depositing a first portion of a carbon-containing layer on the portion of the silicon-containing material on the bottom surface of the trench, the first portion of the carbon layer being deposited from a first carbon-containing deposition precursor having a first reactive moiety. The first carbon-containing deposition precursor is removed from the substrate processing region in contact with the structured semiconductor substrate, and a second portion of the carbon-containing layer is deposited on the first portion of the carbon-containing layer. The second portion of the carbon-containing layer is deposited from a second carbon-containing deposition precursor including a second reactive moiety operable to react with the first reactive moiety on the first carbon-containing deposition precursor. The deposited first and second portions of the carbon-containing layer are annealed to form the carbon-containing mask layer. In further embodiments, the first reactive moiety on the first carbon-containing deposition precursor comprises an aldehyde-containing moiety, and the second reactive moiety on the second carbon-containing deposition precursor comprises an amine-containing moiety. In yet additional embodiments, removing the carbon-containing mask layer comprises heating the carbon-containing mask layer in an oxygen-containing atmosphere. In more embodiments, the at least one deposition cycle comprises about five or more deposition cycles. In even more embodiments, the trench is characterized by a depth-to-width aspect ratio of about 3:1 or greater. In even more embodiments, the silicon-containing material is amorphous silicon or silicon nitride.

[0012]

[0014] Additional embodiments of the present technology include further semiconductor processing methods. The method includes providing a structured semiconductor substrate including a trench having a bottom surface, a top surface, and sidewall surfaces adjacent to the bottom and top surfaces. The method further includes depositing a first portion of a silicon-containing layer over the trench, the first portion of the silicon-containing layer being characterized by a bottom thickness at the bottom surface of the trench greater than a sidewall thickness at the sidewall surfaces of the trench. The method further includes forming a carbon-containing mask layer over the first portion of the silicon-containing layer at the bottom surface of the trench. The method further includes removing at least a portion of the first portion of the silicon-containing layer from the top surface and sidewall surfaces of the trench, wherein the carbon-containing mask layer prevents removal of the first portion of the silicon-containing layer from the bottom surface of the trench. The method further includes removing the carbon-containing mask layer from the bottom surface of the trench and forming a second portion of the silicon-containing layer over the trench.

[0013]

[0015] In a further embodiment, depositing a first portion of the silicon-containing layer on the trench includes generating a deposition plasma in a plasma deposition chamber containing a structured semiconductor substrate, the deposition plasma being generated from a deposition precursor comprising a silicon-containing precursor, argon, helium, and molecular hydrogen. The first portion of the silicon-containing layer is deposited on the trench from species formed in the deposition plasma in the deposition chamber. In a further embodiment, the deposition plasma is generated by supplying RF power to the deposition precursor at a power level of about 500 watts or less. In a further embodiment, removing at least a portion of the first portion of the silicon-containing layer from the top surface and sidewall surface of the trench includes contacting the first portion of the silicon-containing layer with an etching plasma, the etching plasma comprising hydrogen ions. In yet a further embodiment, the etching plasma is generated by supplying RF power to the etching precursor at a power level of about 1500 watts or more. In more embodiments, the first and second portions of the silicon-containing layer comprise amorphous silicon or silicon nitride.

[0014]

[0016] Further embodiments of the present technology include a semiconductor structure including a structured semiconductor substrate including a trench having a bottom surface, a top surface, and sidewall surfaces adjacent to the bottom surface and the top surface. The semiconductor structure includes a silicon-containing material positioned within the trench, the silicon-containing material including at least one of amorphous silicon and silicon nitride and characterized by a refractive index of about 3.0 or greater. The semiconductor structure is also characterized in that the top surface of the trench is free of the silicon-containing material.

[0015]

[0017] In yet many embodiments, the trench is characterized by a depth-to-width aspect ratio of about 3:1 or greater. In yet many embodiments, the trench has a bottom width of about 10 nm or less. In additional embodiments, the structured semiconductor substrate comprises polycrystalline silicon or crystalline silicon. In further embodiments, the silicon-containing material positioned within the trench is characterized by less than 1 wt. % carbon. In further embodiments, the silicon-containing material positioned within the trench is free of voids or seams.

[0016]

[0018] The present technique offers several advantages over conventional methods for depositing silicon-containing materials within narrow, high-aspect ratio trenches in structured semiconductor substrates. In embodiments, the present technique can deposit silicon-containing materials directionally onto the bottom surface of the trench without accumulating material on the sidewalls and top surface of the trench. In further embodiments, a selectively deposited carbon-containing mask formed on the silicon-containing material at the bottom surface of the trench protects the removal of that material during a selective removal step that removes material from the sidewalls and top surface of the trench. The combination of directional deposition and selective removal of the mask-protected silicon-containing material results in rapid deposition of high-quality, void-free silicon-containing materials within the trench. These and other embodiments, along with their many advantages and features, are described in more detail below and in the accompanying drawings. [Brief explanation of the drawings]

[0017] [Figure 1] 1 shows a flowchart including selected steps of an exemplary method for filling trenches in a structured substrate, in accordance with an embodiment of the present technique. [Figure 2] 1A-1D show simplified cross-sectional views of manufacturing stages for an exemplary structured structure, according to an embodiment of the present technique. DETAILED DESCRIPTION OF THE INVENTION

[0018]

[0019] Advances in semiconductor manufacturing technology are shrinking the distance between adjacent structural features on patterned semiconductor substrates to 10 nanometers (nm) or less. As this distance continues to shrink, trenches formed between the structural features become increasingly difficult to uniformly fill with dielectric material. This difficulty arises, in part, because the trench's width decreases faster than its height (i.e., depth), thereby increasing the trench's depth-to-width aspect ratio. As the trench aspect ratio increases at these small nanometer dimensions, it becomes increasingly difficult to form a deep layer of dielectric material at the bottom of the trench before it is blocked by material at the top of the trench. This results in the formation of voids or seams near the center of the dielectric space, which can adversely affect the performance of adjacent semiconductor components.

[0019]

[0020] Techniques have been developed to address the gap-filling problem of dielectric materials. These include using flowable dielectric precursors that allow the dielectric to fill the trench from the bottom up, similar to pouring liquid into a glass. These techniques have been successful in filling small, high-aspect-ratio trenches with silicon-containing dielectrics characterized by high carbon and oxygen content. In embodiments, a remote plasma is used to generate a flowable silicon-, carbon-, and oxygen-containing deposition precursor that flows into the trench and hardens to form silicon oxide and silicon-, carbon-, and oxygen-containing dielectric materials. Unfortunately, these flowable deposition techniques have not been successful in filling these trenches with silicon-containing dielectrics that contain little or no oxygen and carbon, such as amorphous silicon and silicon nitride.

[0020]

[0021] Additional techniques have been developed to address the gap-filling problem of silicon-containing materials that contain little or no oxygen and carbon. These techniques involve directly and selectively filling the bottom of the trench with silicon-containing material while reducing the amount of material formed on the sidewalls and top of the trench. In embodiments, the direct selective filling technique also involves removing some of the silicon-containing material from the top and sidewall surfaces while reducing the amount of material removed from the bottom. By repeating these selective filling and removal cycles multiple times, the silicon-containing material can fill the trench from the bottom up without forming voids or seams in the material.

[0021]

[0022] Direct selective fill techniques have been successful in providing high-quality, void- and seam-free deposition of low-carbon and low-oxygen silicon-containing materials within trenches. However, they have suffered from reduced process efficiency and consequently reduced wafer throughput due to the partial removal of material from the bottom of the trench during each material removal cycle. This technique addresses this issue by forming a carbon-containing mask layer on the silicon-containing material deposited on the bottom of the trench before the removal portion of the cycle removes the silicon-containing material from the sidewalls and top surface of the trench. The carbon-containing mask layer is selectively formed on the silicon-containing material deposited on the bottom of the trench by molecular layer deposition (MLD), which uses at least two different deposition precursors containing different reactive moieties that react with each other upon contact to form the carbon-containing layer. After selectively removing the silicon-containing material from the sidewalls and top surface of the trench, the carbon-containing mask layer is removed to provide the deposited silicon-containing material at the bottom of the trench for the next selective deposition and removal cycle. The incorporation of the carbon-containing mask layer improves the efficiency of the deposition process of silicon-containing materials within the trench.

[0022]

[0023] FIG. 1 illustrates a flowchart including selected steps in a method 100 for depositing silicon-containing material into trenches in a structured semiconductor substrate 200 in accordance with embodiments of the present technology. Method 100 may or may not include one or more steps prior to the start of the method, including front-end processing, deposition, etching, polishing, cleaning, or any other steps that may be performed before the described steps. The method may also include optional steps that may or may not be particularly relevant to some embodiments of methods in accordance with the present technology. Method 100 describes steps for forming embodiments of trenches filled with silicon-containing material in a structured semiconductor substrate, a portion of which is illustrated in the simplified schematic diagram of structure 200 in FIG. 2D . The cross-sectional view of structure 200 in FIG. 2D is a split-open cross-section. FIG. 2D illustrates only a partial schematic view with limited detail. In further embodiments not illustrated, the exemplary structure may include additional layers, regions, and materials having aspects as illustrated, as well as alternative structural and material aspects that may still benefit from any of the aspects of the present technology.

[0023]

[0024] Method 100 includes providing a structured substrate 202 in step 105. In embodiments, structured substrate 202, as shown in FIG. 2A, may include any material, such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, as well as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. In additional embodiments, the structured substrate may include a semiconductor wafer. In further embodiments, structured substrate 202 may be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, e-beam cure, and / or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in the present disclosure, any of the disclosed film processing steps may also be performed on an underlying layer formed on a structured substrate, as disclosed in more detail below, and the term "surface" is intended to include such an underlying layer, as the context indicates. Thus, for example, if a film / layer or partial film / layer is deposited on the bottom surface of a trench in a structured substrate, the exposed surface of the newly deposited film / layer would be the bottom surface.

[0024]

[0025] In the embodiment of structured substrate 202 shown in FIG. 2A, the structured substrate includes, for illustrative purposes, two features in the form of trenches 204a-b. Those skilled in the art will appreciate that additional features are possible. The feature shapes may be any suitable shape, including, but not limited to, additional trenches and cylindrical vias, among other features. The term "feature" as used in this regard refers to an intentional surface irregularity. Suitable examples of features include, but are not limited to, a trench (also called a gap) having a top-surface forming peak laterally adjacent to the bottom surface, and a sidewall surface positioned vertically between the top and bottom surfaces of the trench. In further embodiments, the bottom surface may be characterized by a width of about 20 nm or less, about 15 nm or less, about 12.5 nm or less, about 10 nm or less, about 9 nm or less, about 8 nm or less, about 7 nm or less, about 6 nm or less, or less than about 5 nm. In further embodiments, the aspect ratio (i.e., the ratio of trench depth to trench width) may be characterized as about 1:1 or greater, about 2:1 or greater, about 3:1 or greater, about 4:1 or greater, about 5:1 or greater, about 6:1 or greater, about 7:1 or greater, about 8:1 or greater, about 9:1 or greater, about 10:1 or greater, about 15:1 or greater, about 20:1 or greater, about 25:1 or greater, about 30:1 or greater, about 35:1 or greater, about 40:1 or greater, or greater.

[0025]

[0026] Method 100 also includes depositing a first portion of a silicon-containing material on structured substrate 202 in step 110. In an embodiment, depositing the first portion of the silicon-containing material includes depositing a first upper portion of silicon-containing material 206a-b on the top surfaces of trenches 204a-b and a first bottom portion of silicon-containing material 208a-b on the bottom surfaces of trenches 204a-b, as shown in FIG. 2B . In an embodiment, the first portion of the silicon-containing material may be deposited by a plasma-enhanced chemical vapor deposition (PECVD) process or a plasma-enhanced atomic layer deposition (PEALD) process. In additional embodiments, deposition step 110 may include a PECVD process including a first pulsed high frequency radio frequency (HFRF) plasma. In an embodiment, the first pulsed HFRF plasma may include multiple first HFRF pulses. The use of ordinal numbers such as “first,” “second,” etc., is used to identify different processes or components and does not imply a particular order of steps or use. In a further embodiment, the high frequency radio frequency plasma includes high frequency on / off pulsed power. When on, the power can be supplied at a frequency such as radio frequency. Pulse frequency and radio frequency refer to different aspects of the power used to generate the plasma and can be controlled independently.

[0026]

[0027] In further embodiments, the silicon-containing material may include at least one of amorphous silicon or silicon nitride, among other silicon-containing materials. In further embodiments, the silicon-containing material may consist essentially of silicon nitride. In further embodiments, the silicon-containing material may consist essentially of amorphous silicon. As used in this manner, the term "consists essentially of" means that the silicon-containing material is, on an atomic basis, about 90%, 93%, 95%, 98%, or 99% or more amorphous silicon or silicon nitride (or another species as described). In some embodiments, the silicon-containing material includes amorphous silicon and silicon nitride. In more embodiments, the silicon-containing material includes substantially only amorphous silicon. As used in this manner, the term "substantially only amorphous silicon" means that the silicon-containing material is about 90%, 93%, 95%, 98%, or 99% or more amorphous silicon.

[0027]

[0028] In more embodiments, the silicon-containing material may contain little or no oxygen or carbon. In embodiments, the silicon-containing material may be characterized by an oxygen molar percentage of about 5 mol% or less, about 4 mol% or less, about 3 mol% or less, about 2 mol% or less, about 1 mol% or less, or less. In additional embodiments, the silicon-containing material may be characterized by a carbon molar percentage of about 5 mol% or less, about 4 mol% or less, about 3 mol% or less, about 2 mol% or less, about 1 mol% or less, or less.

[0028]

[0029] In further embodiments, a first portion of silicon-containing material is selectively deposited on the structured substrate 202. In embodiments, the first portion of silicon-containing material is deposited at different rates on the top, bottom, and sidewalls of the trenches 204a-b. In additional embodiments, the deposited first portion of silicon-containing material is characterized by a bottom film thickness on the bottom surfaces of the trenches 204a-b that is greater than a top film thickness on the top surfaces of the trenches 204a-b. In more embodiments, the deposited first portion of silicon-containing material is characterized by a top film thickness on the sidewall surfaces of the trenches 204a-b that is greater than a sidewall film thickness.

[0029]

[0030] In more embodiments, the first portion of the silicon-containing material is formed non-conformally on the structured substrate 202. As used herein, the terms "non-conformal" or "non-conformally" refer to a layer that adheres to and unevenly covers an exposed surface with a thickness variation of more than 10% relative to the average thickness of the film. For example, a film with an average thickness of 100 Å will have a thickness variation of more than 10 Å. This thickness variation includes edges, corners, sides, and bottoms of recesses. In some embodiments, the variation is 10% or more, 15% or more, 20% or more, 25% or more, 30% or more, 35% or more, 40% or more, 45% or more, 50% or more, 55% or more, 60% or more, 65% or more, 70% or more, 75% or more, 80% or more, 85% or more, or 90% or more. In some embodiments, the film deposited on the sidewalls of the trench is thinner than the thickness of the film deposited on the bottom of the trench or the surface on which the trench is formed, In some embodiments, the average thickness of the film deposited on the sidewalls is 90% or less, 80% or less, 70% or less, 60% or less, 50% or less, 40% or less, 30% or less, or 20% or less of the average thickness at the bottom and / or top of the trench.

[0030]

[0031] In yet many embodiments, the first portion of silicon-containing material is deposited to an average thickness within the range of 1 nm to 100 nm, 1 nm to 80 nm, 1 nm to 50 nm, 10 nm to 100 nm, 10 nm to 80 nm, 10 nm to 50 nm, 20 nm to 100 nm, 20 nm to 80 nm, or 20 nm to 50 nm before deposition is stopped. In additional embodiments, the first portion of silicon-containing material is deposited to an average thickness within the range of 5 nm to 100 nm, 5 nm to 80 nm, 5 nm to 40 nm, 5 nm to 30 nm, or 10 nm to 30 nm.

[0031]

[0032] In embodiments, the process parameters used to deposit the first portion of the silicon-containing material can affect the film thickness on the top, sidewall, and bottom surfaces of trenches 204a-b. For example, the particular precursor and / or reactive species, plasma conditions, and temperature, among other process parameters, can affect the thickness of the deposition on different trench surfaces. In further embodiments, the thickness at the top surface is greater than the thickness at the sidewall surfaces of trenches 204a-b. In further embodiments, the thickness at the bottom surface of the trench is greater than the thickness at the sidewalls and top surfaces of trenches 204a-b.

[0032]

[0033] In embodiments, the substrate structure 202 is exposed to one or more process gases and / or conditions that form a first portion of a silicon-containing material. In additional embodiments, the process gases are flowed into a processing region of the processing chamber, and a pulsed HFRF plasma is formed from the process gases to deposit the first portion of the silicon-containing material. In some embodiments, the process gases include a silicon precursor and a carrier gas, and the carrier gas is ignited into a plasma by HFRF power.

[0033]

[0034] In more embodiments, the first pulsed HFRF plasma is a conductively coupled plasma (CCP) or an inductively coupled plasma (ICP). In even more embodiments, the first pulsed HFRF plasma is a direct plasma or a remote plasma. In even more embodiments, each of the multiple first HFRF pulses is independently generated at a first power within the range of 0 W to 500 W, 50 W to 500 W, 50 W to 400 W, 50 W to 300 W, 50 W to 200 W, 50 W to 100 W, 100 W to 500 W, 100 W to 400 W, 100 W to 300 W, 100 W to 200 W, 200 W to 500 W, 200 W to 400 W, or 200 W to 300 W. In some embodiments, the minimum first plasma power is greater than 0 W. In some embodiments, all of the first pulses have the same power. In some embodiments, the individual pulse power of the first HFRF plasma varies.

[0034]

[0035] In embodiments, the plurality of first HFRF plasma pulses have a first duty cycle in the range of 1% to 50%, 1% to 45%, 1% to 40%, 1% to 35%, 1% to 30%, 1% to 25%, 1% to 20%, 1% to 15%, 1% to 10%, 5% to 50%, 5% to 45%, 5% to 40%, 5% to 35%, 5% to 30%, 5% to 25%, 5% to 20%, 5% to 15%, 5% to 10%, 10% to 50%, 10% to 45%, 10% to 40%, 10% to 35%, 10% to 30%, 10% to 25%, 10% to 20%, or 10% to 15%. In additional embodiments, each of the plasma pulses in the deposition process has the same duty cycle. In some embodiments, the duty cycle varies during the deposition process.

[0035]

[0036] In further embodiments, each of the plurality of first HFRF plasma pulses independently has a pulse width within the ranges of 5 milliseconds to 50 microseconds, 4 milliseconds to 50 microseconds, 3 milliseconds to 50 microseconds, 2 milliseconds to 50 microseconds, 1 millisecond to 50 microseconds, 800 microseconds to 50 microseconds, 500 microseconds to 50 microseconds, 200 microseconds to 50 microseconds, 5 milliseconds to 100 microseconds, 4 milliseconds to 100 microseconds, 3 milliseconds to 100 microseconds, 2 milliseconds to 100 microseconds, 1 millisecond to 100 microseconds, 800 microseconds to 100 microseconds, 500 microseconds to 100 microseconds, and 200 microseconds to 100 microseconds. In embodiments, each pulse width is the same during the deposition process. In some embodiments, the pulse width varies during the deposition process.

[0036]

[0037] In one or more embodiments, each of the plurality of first HFRF plasma pulses independently has a first pulse frequency in the range of 0.1 kHz to 20 kHz, 0.1 kHz to 15 kHz, 0.1 kHz to 10 kHz, 0.1 kHz to 5 kHz, 0.5 kHz to 20 kHz, 0.5 kHz to 15 kHz, 0.5 kHz to 10 kHz, 0.5 kHz to 5 kHz, 1 kHz to 20 kHz, 1 kHz to 15 kHz, 1 kHz to 10 kHz, 1 kHz to 5 kHz, 2 kHz to 20 kHz, 2 kHz to 15 kHz, 2 kHz to 10 kHz, or 2 kHz to 5 kHz. In embodiments, the pulse frequency remains the same during the deposition process. In additional embodiments, the pulse frequency varies during the deposition process.

[0037]

[0038] In one or more embodiments, the plurality of first HFRF pulses have a first radio frequency in the range of 5 MHz to 20 MHz, 5 MHz to 15 MHz, 5 MHz to 10 MHz, 10 MHz to 20 MHz, or 10 MHz to 15 MHz. In one or more embodiments, the plurality of first HFRF pulses have a first radio frequency of 13.56 MHz. In some embodiments, the radio frequency of the pulses remains the same throughout the deposition process. In some embodiments, the radio frequency of the pulses varies during the deposition process. In one or more embodiments, each of the plurality of first HFRF pulses independently has a first radio frequency in the range of 5 MHz to 20 MHz, 5 MHz to 15 MHz, 5 MHz to 10 MHz, 10 MHz to 20 MHz, or 10 MHz to 15 MHz. In one or more embodiments, each of the plurality of first HFRF pulses independently has a first radio frequency of 13.56 MHz.

[0038]

[0039] In embodiments, each of the plurality of first HFRF pulses has a first duty cycle in the range of 1% to 50%, 1% to 45%, 1% to 40%, 1% to 35%, 1% to 30%, 1% to 25%, 1% to 20%, 1% to 15%, 1% to 10%, 5% to 50%, 5% to 45%, 5% to 40%, 5% to 35%, 5% to 30%, 5% to 25%, 5% to 20%, 5% to 15%, 5% to 10%, 10% to 50%, 10% to 45%, 10% to 40%, 10% to 35%, 10% to 30%, 10% to 25%, 10% to 20%, or 10% to 15%. In some embodiments, the duty cycle of the pulses remains the same throughout the deposition process. In some embodiments, the duty cycle of the pulses varies during the deposition process. The deposition process can be carried out at any suitable substrate temperature. In some embodiments, the substrate is heated to a temperature between 15°C and 250°C, between 15°C and 225°C, between 15°C and 200°C, between 15°C and 175°C, between 15°C and 150°C, between 15°C and 125°C, between 15°C and 100°C, between 25°C and 250°C, between 25°C and 225°C, between 25°C and 200°C, between 25°C and 175°C, between 25°C and 150°C, between 25°C and 125°C, between 25°C and 100°C. The temperature is maintained within the range of 100°C, 50°C to 250°C, 50°C to 225°C, 50°C to 200°C, 50°C to 175°C, 50°C to 150°C, 50°C to 125°C, 50°C to 100°C, 75°C to 250°C, 75°C to 225°C, 75°C to 200°C, 75°C to 175°C, 75°C to 150°C, 75°C to 125°C, or 75°C to 100°C.

[0039]

[0040] In additional embodiments, the film deposition process may include flowing one or more of a first carrier gas, a precursor, or a first reactant onto the substrate surface. In some embodiments, the carrier gas includes, but is not limited to, argon (Ar), helium (He), H, or N. In some embodiments, the carrier gas includes or consists essentially of helium (He). In some embodiments, the carrier gas includes argon (Ar). In one or more embodiments, the precursor includes, but is not limited to, silane, disilane, dichlorosilane (DCS), trisilane, or tetrasilane. In some embodiments, the precursor gas includes silane (SiH). In some embodiments, the precursor gas includes, or consists essentially of disilane (SiH). In some embodiments, the precursor gas is heated in a hot can to increase its vapor pressure and delivered to the chamber using a carrier gas. In some embodiments, the first reactant gas includes H.

[0040]

[0041] In more embodiments, each of the first carrier gas, precursor gas, or first reactant gas is 40 sccm to 10,000 sccm, 40 sccm to 5,000 sccm, 40 sccm to 2,000 sccm, 40 sccm to 1,000 sccm, 40 sccm to 500 sccm, 40 sccm to 100 sccm, 100 sccm to 10,000 sccm, 100 sccm to 5,000 sccm, 100 sccm to 2,000 sccm, 100 sccm to 100 The gases are independently flowed onto the substrate surface at flow rates within the ranges of 0 sccm, 100 sccm to 500 sccm, 250 sccm to 10,000 sccm, 250 sccm to 5,000 sccm, 250 sccm to 2,000 sccm, 250 sccm to 1,000 sccm, 250 sccm to 500 sccm, 500 sccm to 10,000 sccm, 500 sccm to 5,000 sccm, 500 sccm to 2,000 sccm, or 500 sccm to 1,000 sccm.

[0041]

[0042] In embodiments, the first part of the silicon-containing material deposited during the deposition process is a continuous film.As used herein, the term "continuous" refers to a layer that covers the entire exposed surface, without gaps or bare spots that expose the material underneath the deposited layer.A continuous film may have gaps or bare spots that have a surface area of ​​less than about 1% of the total surface area of ​​the film.

[0042]

[0043] In some embodiments, after the deposition step 110 but before any additional steps, the structured substrate 202 may be subjected to a purge and / or vacuum treatment. In some embodiments, a purge gas, such as argon, is introduced into the processing chamber to purge the reaction zone or otherwise remove any residual reactive compounds or by-products from the reaction zone between the deposition step 110 and any additional steps. In some embodiments, the purge gas is continuously flowed into the processing chamber throughout the method 100. In some embodiments, a negative pressure is applied in the processing chamber between the deposition step and any additional steps to remove any residual reactive compounds or by-products from the deposition region of the chamber. In some embodiments, a negative pressure is continuously applied in the processing chamber throughout the method 100. In some embodiments, a purge and / or vacuum treatment is applied before any post-processing step.

[0043]

[0044] The method 100 also includes depositing a carbon-containing mask layer 210 on the first portion of the silicon-containing material in step 115. In an embodiment, the deposition of the carbon-containing mask layer 210 can include molecular layer deposition (MLD) of a carbon layer on the first portion of the silicon-containing material, as shown in FIG. 2C. In an additional embodiment, the MLD-C deposition can include flowing a first deposition precursor into a substrate processing region including a structured substrate 202 having a first portion of the silicon-containing material. In a further embodiment, the first precursor can be a carbon-containing precursor having at least two reactive groups capable of forming bonds with groups attached to a surface of a substrate in the substrate processing region. The molecules of the first precursor react with the surface groups, forming bonds that connect the first precursor molecules to the substrate surface. The reaction between the first precursor molecules and the groups on the substrate surface continues until most or all of the surface groups are bonded to the reactive groups on the first precursor molecules. A first portion of a compound layer of the deposition precursor is formed, preventing further reaction between the first precursor molecules in the first precursor effluent and the substrate.

[0044]

[0045] In additional embodiments, the rate of formation of the first portion of the compound layer can depend not only on the temperature of the substrate but also on the temperature of the deposition precursor flowing into the substrate processing region. Exemplary substrate temperatures during the formation process can be about 50°C or higher, about 60°C or higher, about 70°C or higher, about 80°C or higher, about 90°C or higher, about 100°C or higher, about 110°C or higher, about 120°C or higher, about 130°C or higher, about 140°C or higher, about 150°C or higher, or higher. In some embodiments, maintaining a high substrate temperature (e.g., about 100°C or higher) can increase the number of available nucleation sites along the substrate, which can improve formation and reduce void formation by increasing coverage at each location.

[0045]

[0046] In more embodiments, the first deposition precursor can be delivered at any number of temperatures to effectively increase ligand formation across the substrate and improve initial formation and coverage across the substrate. The first deposition precursor can be delivered at a temperature of about 80°C or higher, about 90°C or higher, about 100°C or higher, or about 110°C or higher. Increasing the deposition of the first precursor can result in a greater number of deposition moieties, potentially resulting in a more seamless growth of material on the substrate. This can also allow the second deposition precursor to be delivered at a lower temperature than the first. In some embodiments, the reaction between the second deposition precursor and the first deposition precursor occurs more readily than the reaction between the first deposition precursor and the substrate, and therefore, delivering the first deposition precursor at a higher temperature can ensure sufficient formation across the substrate. The second deposition precursor can then be reacted with the reactive groups of the first deposition precursor at a lower temperature. For example, the second deposition precursor may be provided at a temperature of about 100°C or less, and may be provided at a temperature of about 90°C or less, about 80°C or less, about 70°C or less, about 60°C or less, about 50°C or less, about 40°C or less, or lower.

[0046]

[0047] In embodiments, the formation rate of the first portion of the compound layer may also depend on the pressure of the first deposition precursor effluent in the substrate processing region. Exemplary effluent pressures in the substrate processing region may be in the range of about 1 mTorr to about 500 Torr. Additional exemplary ranges include 1 Torr to about 20 Torr, 5 Torr to 15 Torr, and 9 Torr to 12 Torr, among other exemplary ranges.

[0047]

[0048] In further embodiments, the first deposition precursor effluent can remain in the substrate processing region for a period of time to substantially or completely form the first portion of the compound layer. To grow the material, precursors can be supplied in alternating pulses. In some embodiments, the pulse time of either or both of the first and second deposition precursors can be about 0.5 seconds or more, about 1 second or more, about 2 seconds or more, about 3 seconds or more, about 4 seconds or more, about 5 seconds or more, about 10 seconds or more, about 20 seconds or more, about 40 seconds or more, about 60 seconds or more, about 80 seconds or more, about 100 seconds or more, or more. In some embodiments, the first deposition precursor can be pulsed for a longer period of time than the second deposition precursor. Similar to the temperature described above, increasing the residence time of the first deposition precursor can improve adhesion across the substrate. The second deposition precursor can be more reactive with the ligands of the first deposition precursor, thus reducing the pulse time and potentially increasing throughput. For example, in some embodiments, the second precursor may be pulsed for about 90% or less of the time that the first precursor is pulsed, the second precursor may also be pulsed for about 80% or less of the time that the first precursor is pulsed, about 70% or less of the time that the first precursor is pulsed, about 60% or less of the time that the first precursor is pulsed, about 50% or less of the time that the first precursor is pulsed, about 40% or less of the time that the first precursor is pulsed, about 30% or less of the time that the first precursor is pulsed, or less.

[0048]

[0049] In additional embodiments, the first deposition precursor effluent can be purged or removed from the substrate processing region following the formation of the first portion of the compound layer. The effluent can be removed by pumping it out of the substrate deposition region for a time ranging from about 10 seconds to about 100 seconds. Additional exemplary time ranges can include about 20 seconds to about 50 seconds, and 25 seconds to about 45 seconds, among other exemplary time ranges. However, in some embodiments, longer purge times can begin to remove reactive moieties and reduce uniform formation. Thus, in some embodiments, purging can be performed for about 60 seconds or less, about 50 seconds or less, about 40 seconds or less, about 30 seconds or less, or less. In some embodiments, a purge gas can be introduced into the substrate processing region to aid in species removal. Exemplary purge gases include helium and nitrogen, among other purge gases.

[0049]

[0050] In embodiments, the first deposition precursor may be characterized by a first formula including: Y1-R1-Y2, where R1 comprises one or more of an alkyl group, an aromatic group, or a cycloalkyl group, and Y1 and Y2 independently comprise a hydroxide group, an aldehyde group, a ketone group, an acid group, an amino group, an isocyanate group, a thiocyanate group, or an acyl chloride group. In more embodiments, exemplary first deposition precursors can include terephthalaldehyde and 1,4-phenylenediisocyanate, among other first deposition precursors.

[0050]

[0051] After removing the first deposition precursor effluent, a second deposition precursor can be introduced to the structured substrate. In embodiments, the second precursor can be a carbon-containing precursor having at least two reactive groups capable of forming bonds with the unreacted reactive groups of the first deposition precursor that formed the first portion of the compound layer. The second precursor molecules react with the unreacted reactive groups of the first deposition precursor to form bonds linking the second precursor molecules to the first precursor molecules. The reaction between the second precursor molecules and the first precursor molecules continues until most or all of the unreacted reactive groups on the first precursor molecules react with the second precursor molecules. A second portion of the compound layer of the deposition precursor is formed, preventing further reaction between the second precursor molecules in the second precursor effluent and the first portion of the compound layer.

[0051]

[0052] In additional embodiments, the rate of formation of the second portion of the compound layer can also depend on the pressure of the second deposition precursor effluent in the substrate processing region. Exemplary effluent pressures in the substrate processing region can be in the range of about 1 Torr to about 20 Torr. Additional exemplary ranges include 5 Torr to 15 Torr, and 9 Torr to 12 Torr, among other exemplary ranges.

[0052]

[0053] In further embodiments, the second deposition precursor effluent may be purged or removed from the substrate processing region following formation of the second portion of the compound layer. The effluent may be removed by pumping it out of the substrate deposition region for a time ranging from about 10 seconds to about 100 seconds. Additional exemplary time ranges may include about 20 seconds to about 50 seconds, and 25 seconds to about 45 seconds, among other exemplary time ranges. In some embodiments, a purge gas may be introduced into the substrate processing region to aid in the removal of the effluent. Exemplary purge gases include helium and nitrogen, among other purge gases.

[0053]

[0054] In embodiments, the second deposition precursor may be characterized by a second formula including: Z1-R2-Z2, where R2 comprises one or more of an alkyl group, an aromatic group, and a cycloalkyl group, and Z1 and Z2 independently comprise a hydroxyl group, an aldehyde group, a ketone group, an acid group, an amino group, an isocyanate group, a thiocyanate group, or an acyl chloride group. In additional embodiments, an exemplary second deposition precursor can include ethylenediamine.

[0054]

[0055] In some embodiments, following one or more cycles of forming a compound layer (e.g., following formation of a first portion and a second portion of a compound layer), it may be determined whether a target thickness of deposited carbon-containing material on the substrate has been reached. If the target thickness of deposited carbon-containing material has not been reached, another cycle of forming the first portion and the second portion of the compound layer is performed. If the target thickness of deposited carbon-containing material has been reached, another cycle of forming another compound layer is not initiated. An exemplary number of cycles for compound layer formation may include 1 to 2000 cycles. Additional exemplary ranges of cycle numbers may include 50 to 1000 cycles and 100 to 750 cycles, among other exemplary ranges. An exemplary range of target thickness at which further cycles of forming a compound layer are discontinued includes about 10 nm to about 500 nm. Additional exemplary thickness ranges may include about 50 nm to about 300 nm and 100 nm to about 200 nm, among other exemplary thickness ranges.

[0055]

[0056] In further embodiments, the deposited carbon-containing layer on the substrate can be annealed to form the carbon-containing mask layer 210. Exemplary annealing can include thermal annealing of the deposited carbon-containing material, which consists of one or more successive compound layers. An exemplary temperature range for the thermal anneal can include about 100°C to about 600°C. Additional exemplary temperature ranges can include about 200°C to about 500°C and about 300°C to about 450°C, among other temperature ranges. Exemplary times for the thermal anneal can include ranges from about 1 minute to about 120 minutes, from about 10 minutes to about 60 minutes, and from about 20 minutes to about 40 minutes, among other exemplary time ranges.

[0056]

[0057] The method 100 further includes selectively removing a first portion of the silicon-containing material in step 120. In an embodiment, the removing step etches a greater thickness of the silicon-containing material on the sidewall surfaces of the trenches 204a-b than on the top surfaces thereof. In a further embodiment, the carbon-containing mask layer 210 prevents the deposited first portion of the silicon-containing material on the bottom surfaces of the trenches 204a-b from being removed during the removing step 120, as shown in FIG. 2D.

[0057]

[0058] Without being bound to a particular process theory, it is believed that the directional plasma treatment preferentially modifies a first portion of the silicon-containing material on the top and bottom surfaces of the trenches 204a-b relative to the material deposited on the sidewall surfaces. The modified silicon-containing material on the top and bottom surfaces appears to be more etch-resistant. This results in a higher etch rate on the sidewalls than on the top surface. Meanwhile, the silicon-containing material on the bottom surface experiences a zero etch rate due to the presence of the carbon-containing mask layer 210.

[0058]

[0059] In additional embodiments, the removing step 120 removes substantially all of the first portion of the silicon-containing material from the sidewall surfaces of the trenches 204a-b, leaving a portion of the top surface. In some embodiments, removing substantially all of the sidewall material means that at least about 95%, 98%, or 99% of the surface area of ​​the sidewalls has been etched. In some embodiments, removing substantially all of the sidewall material includes a nucleation delay for a subsequent deposition process.

[0059]

[0060] In one or more embodiments, the etching process 120 includes exposing the substrate surface to one or more of a second carrier gas or a second reactive gas. In some embodiments, the second carrier gas includes one or more of argon (Ar), helium (He), or nitrogen (N). In some embodiments, the second reactive gas includes one or more of Cl, H, NF, or HCl. In some embodiments, the second reactive gas includes or consists essentially of H. In some embodiments, the second carrier gas or the second reactant gas each has a flow rate of 40 sccm to 10,000 sccm, 40 sccm to 5,000 sccm, 40 sccm to 2,000 sccm, 40 sccm to 1,000 sccm, 40 sccm to 500 sccm, 40 sccm to 100 sccm, 100 sccm to 10,000 sccm, 100 sccm to 5,000 sccm, 100 sccm to 2,000 sccm, 100 sccm to 1,000 sccm. cm, 100 sccm to 500 sccm, 250 sccm to 10,000 sccm, 250 sccm to 5,000 sccm, 250 sccm to 2,000 sccm, 250 sccm to 1,000 sccm, 250 sccm to 500 sccm, 500 sccm to 10,000 sccm, 500 sccm to 5,000 sccm, 500 sccm to 2,000 sccm, or 500 sccm to 1,000 sccm.

[0060]

[0061] In one or more embodiments, the removal step 120 may include removing the structured substrate 202 at temperatures ranging from 15°C to 250°C, 15°C to 225°C, 15°C to 200°C, 15°C to 175°C, 15°C to 150°C, 15°C to 125°C, 15°C to 100°C, 25°C to 250°C, 25°C to 225°C, 25°C to 200°C, 25°C to 175°C, 25°C to 150°C, 25°C to 12 ... The etching step 120 may include maintaining a temperature within the range of 5°C to 100°C, 50°C to 250°C, 50°C to 225°C, 50°C to 200°C, 50°C to 175°C, 50°C to 150°C, 50°C to 125°C, 50°C to 100°C, 75°C to 250°C, 75°C to 225°C, 75°C to 200°C, 75°C to 175°C, 75°C to 150°C, 75°C to 125°C, or 75°C to 100°C. In some embodiments, the structured substrate 202 is maintained at the same temperature during the deposition step 110 and the removal step 120. In some embodiments, the structured substrate 202 is maintained at different temperatures (ΔT > 10°C) during the deposition step 110 and the removal step 120.

[0061]

[0062] In one or more embodiments, the removal step 120 may include removing the reaction region containing the structured substrate 202 from a pressure of 0.1 Torr to 12 Torr, 0.5 Torr to 12 Torr, 1 Torr to 12 Torr, 2 Torr to 12 Torr, 3 Torr to 12 Torr, 4 Torr to 12 Torr, 0.1 Torr to 10 Torr, 0.5 Torr to 10 Torr, 1 Torr to 10 Torr, 2 Torr to 10 Torr, 3 Torr to 10 Torr, orr, 4 Torr to 10 Torr, 0.1 Torr to 8 Torr, 0.5 Torr to 8 Torr, 1 Torr to 8 Torr, 2 Torr to 8 Torr, 3 Torr to 8 Torr, 4 Torr to 8 Torr, 0.1 Torr to 5 Torr, 0.5 Torr to 5 Torr, 1 Torr to 5 Torr, 2 Torr to 5 Torr, 3 Torr to 5 Torr, or 4 Torr to 5 Torr.

[0062]

[0063] In some embodiments, the removal process 120 includes an etching plasma. In some embodiments, the etching plasma is a conductively coupled plasma (CCP) or an inductively coupled plasma (ICP). In some embodiments, the etching plasma is a direct plasma or a remote plasma. In some embodiments, the etching plasma operates at a power in the range of 0 W to 500 W, 50 W to 500 W, 50 W to 400 W, 50 W to 300 W, 50 W to 200 W, 50 W to 100 W, 100 W to 500 W, 100 W to 400 W, 100 W to 300 W, 100 W to 200 W, 200 W to 500 W, 200 W to 400 W, or 200 W to 300 W. In some embodiments, the minimum power of the plasma is greater than 0 W.

[0063]

[0064] In some embodiments, the removal step 120 is performed at a continuous power level. In some embodiments, the etching process is performed with second HFRF plasma pulses. In some embodiments, each of the plurality of second HFRF plasma pulses is independently generated at a second power in the range of 0 W to 500 W, 50 W to 500 W, 50 W to 400 W, 50 W to 300 W, 50 W to 200 W, 50 W to 100 W, 100 W to 500 W, 100 W to 400 W, 100 W to 300 W, 100 W to 200 W, 200 W to 500 W, 200 W to 400 W, or 200 W to 300 W. In some embodiments, the minimum second plasma power is greater than 0 W. In some embodiments, the power of the pulses remains the same throughout the etching process. In some embodiments, the power of the pulses varies throughout the etching process.

[0064]

[0065] In one or more embodiments, the plurality of second HFRF plasma pulses have a duty cycle in the range of 1% to 50%, 1% to 45%, 1% to 40%, 1% to 35%, 1% to 30%, 1% to 25%, 1% to 20%, 1% to 15%, 1% to 10%, 5% to 50%, 5% to 45%, 5% to 40%, 5% to 35%, 5% to 30%, 5% to 25%, 5% to 20%, 5% to 15%, 5% to 10%, 10% to 50%, 10% to 45%, 10% to 40%, 10% to 35%, 10% to 30%, 10% to 25%, 10% to 20%, or 10% to 15%. In some embodiments, the duty cycle of the pulses remains the same throughout the etching process. In some embodiments, the duty cycle of the pulses varies during the etching process.

[0065]

[0066] In one or more embodiments, each of the plurality of second HFRF plasma pulses has a pulse width in the range of 5 milliseconds to 50 microseconds, 4 milliseconds to 50 microseconds, 3 milliseconds to 50 microseconds, 2 milliseconds to 50 microseconds, 1 millisecond to 50 microseconds, 800 microseconds to 50 microseconds, 500 microseconds to 50 microseconds, 200 microseconds to 50 microseconds, 5 milliseconds to 100 microseconds, 4 milliseconds to 100 microseconds, 3 milliseconds to 100 microseconds, 2 milliseconds to 100 microseconds, 1 millisecond to 100 microseconds, 800 microseconds to 100 microseconds, 500 microseconds to 100 microseconds, and 200 microseconds to 100 microseconds. In some embodiments, the pulse width of the pulses remains the same throughout the etching process. In some embodiments, the pulse width of the pulses varies throughout the etching process.

[0066]

[0067] In one or more embodiments, each of the plurality of second HFRF plasma pulses independently has a pulse frequency in the range of 0.1 kHz to 20 kHz, 0.1 kHz to 15 kHz, 0.1 kHz to 10 kHz, 0.1 kHz to 5 kHz, 0.5 kHz to 20 kHz, 0.5 kHz to 15 kHz, 0.5 kHz to 10 kHz, 0.5 kHz to 5 kHz, 1 kHz to 20 kHz, 1 kHz to 15 kHz, 1 kHz to 10 kHz, 1 kHz to 5 kHz, 2 kHz to 20 kHz, 2 kHz to 15 kHz, 2 kHz to 10 kHz, or 2 kHz to 5 kHz. In some embodiments, the frequency of the pulses remains the same during the ablation process 120. In some embodiments, the frequency of the pulses varies during the ablation process 120.

[0067]

[0068] In one or more embodiments, the plurality of second HFRF pulses have a second radio frequency in the range of 5 MHz to 20 MHz, 5 MHz to 15 MHz, 5 MHz to 10 MHz, 10 MHz to 20 MHz, or 10 MHz to 15 MHz. In one or more embodiments, the plurality of second HFRF pulses have a second radio frequency of 13.56 MHz. In some embodiments, the radio frequency of the pulses remains the same throughout the etching process. In some embodiments, the radio frequency of the pulses varies throughout the etching process. In one or more embodiments, each of the plurality of second HFRF pulses independently has a second radio frequency in the range of 5 MHz to 20 MHz, 5 MHz to 15 MHz, 5 MHz to 10 MHz, 10 MHz to 20 MHz, or 10 MHz to 15 MHz. In one or more embodiments, each of the plurality of second HFRF pulses independently has a second radio frequency of 13.56 MHz.

[0068]

[0069] Method 100 also includes removing carbon-containing mask layer 210 in step 125. In embodiments, mask removal step 125 may include heating mask layer 210 in an oxidizing atmosphere to convert the mask material to carbon dioxide, water vapor, and ash. In further embodiments, the oxidizing atmosphere may include atomic oxygen, molecular oxygen (O), among other oxygen-containing gases. In additional embodiments, an oxidizing compound may be used to generate an oxidizing plasma in contact with mask layer 210. In more embodiments, removal step 125 may include raising the temperature of mask layer 210 to 100° C. or higher, 110° C. or higher, 125° C. or higher, 150° C. or higher, 175° C. or higher, 200° C. or higher, 225° C. or higher, 250° C. or higher, 300° C. or higher, or higher.

[0069]

[0070] Method 100 further includes a determining step 130 after completing the cycles of depositing and etching a portion of the silicon-containing material and removing the carbon-containing mask layer, as described in steps 105-125 above. In embodiments, the determining step evaluates whether trenches 204a-b are sufficiently filled with the silicon-containing material. In some embodiments, method 100 can stop once the trenches are sufficiently filled (e.g., completely filled), as shown in step 135 of FIG. 1 . In additional embodiments, structured substrate 202 can be exposed to a post-gap-fill process. On the other hand, if the trenches are not sufficiently filled, method 100 initiates another cycle of depositing a portion of the silicon-containing material, as described in step 110. In embodiments, method 100 can include about 2 or more cycles, about 3 or more cycles, about 4 or more cycles, about 5 or more cycles, about 6 or more cycles, about 7 or more cycles, about 8 or more cycles, about 9 or more cycles, about 10 or more cycles, about 15 or more cycles, about 20 or more cycles, about 25 or more cycles, or more.

[0070]

[0071] The present technique enables the deposition of silicon-containing materials, such as amorphous silicon and silicon nitride, in high-aspect-ratio features, such as trenches, in structured substrates. The use of a selectively deposited MLD carbon mask layer to protect selected portions of the silicon-containing material during removal steps of other portions of the material improves the deposition efficiency of the method. In embodiments, the method may be characterized by an increase in deposition efficiency, as measured by reduced deposition time, of about 5% or more, about 10% or more, about 15% or more, about 20% or more, about 25% or more.

[0071]

[0072] While several embodiments have been described, those skilled in the art will recognize that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the invention. Moreover, in order to avoid unnecessarily obscuring the present invention, many well-known processes and elements have not been described. Therefore, the above description should not be construed as limiting the scope of the invention.

[0072]

[0073] Where a range of values ​​is provided, it is understood that each intervening value between the upper and lower limits of that range is also expressly disclosed, to the tenth of the unit of the lower limit, unless the context clearly indicates otherwise. Each narrower range between any stated or intervening value in a stated range and any other stated or intervening value in that stated range is encompassed. The upper and lower limits of these narrower ranges may individually be included or excluded within the range, and each range where either limit is included in the narrower range, where neither limit is included in the narrower range, or where both limits are included in the narrower range, is also encompassed within the scope of the invention, subject to any explicitly excluded limit in the stated range. When the stated range includes one or both limits, ranges excluding either or both of those included limits are also included.

[0073]

[0074] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, a reference to "a process" includes a plurality of such processes, and a reference to "the pixel structure" includes a reference to one or more pixel structures and equivalents thereof known to those skilled in the art.

[0074]

[0075] Also, the words "comprise / comprising" and "include / including / includes", when used in this specification and the claims that follow, are intended to specify the presence of stated features, integer values, components, or steps, but do not exclude the presence or addition of one or more other features, integer values, components, steps, acts, or groups.

Claims

1. 1. A semiconductor processing method comprising: providing a structured semiconductor substrate including a trench having a bottom surface and an upper surface laterally adjacent the bottom surface; depositing a portion of a silicon-containing material on the bottom surface of the trench during at least one deposition cycle; each deposition cycle comprising: depositing said portion of said silicon-containing material on said bottom surface and said top surface of said trench; depositing a carbon-containing mask layer on the silicon-containing material on the bottom surface of the trench, the carbon-containing mask layer not being formed on the top surface of the trench; removing the portion of the silicon-containing material from the top surface of the trench; and removing the carbon-containing mask layer from the silicon-containing material on the bottom surface of the trench, leaving the deposited silicon-containing material on the bottom surface of the trench; A semiconductor processing method comprising:

2. 2. The semiconductor processing method of claim 1, wherein said depositing said portion of said silicon-containing material on said bottom surface and said top surface of said trench comprises treating said deposited silicon-containing material with argon, helium, and hydrogen ions, said ions being accelerated in a direction perpendicular to said structured semiconductor substrate.

3. depositing the carbon-containing mask layer depositing a first portion of a carbon-containing layer over the portion of the silicon-containing material on the bottom surface of the trench, the first portion of the carbon layer being deposited from a first carbon-containing deposition precursor having a first reactive moiety; removing the first carbon-containing deposition precursor from a substrate processing region contacting the structured semiconductor substrate; depositing a second portion of the carbon-containing layer on the first portion of the carbon-containing layer, the second portion of the carbon-containing layer being deposited from a second carbon-containing deposition precursor including a second reactive moiety operable to react with the first reactive moiety on the first carbon-containing deposition precursor; annealing the deposited first and second portions of the carbon-containing layer to form the carbon-containing mask layer; 10. The semiconductor processing method of claim 1, comprising:

4. 4. The semiconductor processing method of claim 3, wherein the first reactive moiety comprises an aldehyde-containing moiety and the second reactive moiety comprises an amine-containing moiety.

5. 10. The semiconductor processing method of claim 1, wherein said removing said carbon-containing mask layer comprises heating said carbon-containing mask layer in an oxygen-containing atmosphere.

6. The semiconductor processing method of claim 1 , wherein the at least one deposition cycle comprises about 5 or more deposition cycles.

7. 10. The semiconductor processing method of claim 1, wherein said trench has a depth to width aspect ratio of about 3:1 or greater.

8. 8. The semiconductor processing method of claim 7, wherein the silicon-containing material comprises amorphous silicon or silicon nitride.

9. 1. A semiconductor processing method comprising: providing a structured semiconductor substrate including a trench having a bottom surface, a top surface, and sidewall surfaces adjacent to the bottom surface and the top surface; depositing a first portion of a silicon-containing layer over the trench, the first portion of the silicon-containing layer having a bottom thickness at the bottom surface of the trench that is greater than a sidewall thickness at the sidewall surfaces of the trench; forming a carbon-containing mask layer over the first portion of the silicon-containing layer on the bottom surface of the trench; removing at least a portion of the first portion of the silicon-containing layer from the top surface and the sidewall surface of the trench, wherein the carbon-containing mask layer prevents removal of the first portion of the silicon-containing layer from the bottom surface of the trench; removing the carbon-containing mask layer from the bottom surface of the trench; forming a second portion of the silicon-containing layer over the trench; and A semiconductor processing method comprising:

10. said depositing said first portion of said silicon-containing layer over said trench; generating a deposition plasma in a plasma deposition chamber containing the structured semiconductor substrate, the deposition plasma being generated from a deposition precursor comprising a silicon-containing precursor, argon, helium, and molecular hydrogen; depositing the first portion of the silicon-containing layer onto the trench from species formed in the deposition plasma in the deposition chamber; 10. The semiconductor processing method of claim 9, comprising:

11. 10. The semiconductor processing method of claim 9, wherein the deposition plasma is generated by supplying RF power to the deposition precursor at a power level of about 500 watts or less.

12. 10. The semiconductor processing method of claim 9, wherein said removing at least a portion of said first portion of said silicon-containing layer from said top surface and said sidewall surface of said trench comprises contacting said first portion of said silicon-containing layer with an etching plasma, said etching plasma comprising hydrogen ions.

13. 10. The semiconductor processing method of claim 9, wherein the etching plasma is generated by supplying RF power to an etching precursor at a power level of about 1500 Watts or greater.

14. 10. The semiconductor processing method of claim 9, wherein the first portion and the second portion of the silicon-containing layer comprise amorphous silicon or silicon nitride.

15. 1. A semiconductor structure comprising: a structured semiconductor substrate including a trench having a bottom surface, a top surface, and sidewall surfaces adjacent to the bottom surface and the top surface; a silicon-containing material positioned within the trench, the silicon-containing material comprising at least one of amorphous silicon and silicon nitride and characterized by a refractive index of about 3.0 or greater; Including, The semiconductor structure, wherein the top surface of the trench is free of the silicon-containing material.

16. 16. The semiconductor structure of claim 15, wherein the trench has a depth-to-width aspect ratio of about 3:1 or greater.

17. 17. The semiconductor structure of claim 16, wherein the width of the bottom of the trench is about 10 nm or less.

18. 16. The semiconductor structure of claim 15, wherein the structured semiconductor substrate comprises polycrystalline silicon or crystalline silicon.

19. 16. The semiconductor structure of claim 15, wherein the silicon-containing material located within the trench is characterized by less than 1% carbon by weight.

20. 16. The semiconductor structure of claim 15, wherein the silicon-containing material located within the trench is free of voids or seams.

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